Blackfin updates for 2010.09

index 0a13c28..c8bec11 100644
@@ -29,6 +29,7 @@
 
 void board_reset(void) __attribute__((__weak__));
 void bfin_reset_or_hang(void) __attribute__((__noreturn__));
+void bfin_dump(struct pt_regs *reg);
 void bfin_panic(struct pt_regs *reg);
 void dump(struct pt_regs *regs);
 

167 lines not on this page · raw message

new file mode 100644
index 0000000..6cf6dd5
@@ -0,0 +1,34 @@
+/*
+ * functions for handling bootcount support
+ *
+ * Copyright (c) 2010 Analog Devices Inc.
+ *
+ * Licensed under the 2-clause BSD.
+ */
+
+/* This version uses one 32bit storage and combines the magic/count */
+
+#include <common.h>
+
+/* We abuse the EVT0 MMR for bootcount storage by default */
+#ifndef CONFIG_SYS_BOOTCOUNT_ADDR
+# define CONFIG_SYS_BOOTCOUNT_ADDR EVT0
+#endif
+
+#define MAGIC_MASK 0xffff0000
+#define COUNT_MASK 0x0000ffff
+
+void bootcount_store(ulong cnt)
+{
+	ulong magic = (BOOTCOUNT_MAGIC & MAGIC_MASK) | (cnt & COUNT_MASK);
+	bfin_write32(CONFIG_SYS_BOOTCOUNT_ADDR, magic);
+}
+
+ulong bootcount_load(void)
+{
+	ulong magic = bfin_read32(CONFIG_SYS_BOOTCOUNT_ADDR);
+	if ((magic & MAGIC_MASK) == (BOOTCOUNT_MAGIC & MAGIC_MASK))
+		return magic & COUNT_MASK;
+	else
+		return 0;
+}

index 5f80ad6..9453d5d 100644
@@ -675,7 +675,12 @@ void initcode(ADI_BOOT_DATA *bs)
 
 #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
 	serial_putc('I');
-	/* tell the bootrom where our entry point is */
+	/* Tell the bootrom where our entry point is so that it knows
+	 * where to jump to when finishing processing the LDR.  This
+	 * allows us to avoid small jump blocks in the LDR, and also
+	 * works around anomaly 05000389 (init address in external
+	 * memory causes bootrom to trigger external addressing IVHW).
+	 */
 	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
 		bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
 #endif

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index 0fd7e31..9358afa 100644
@@ -1,19 +1,28 @@
 /*
- * File: include/asm-blackfin/mach-bf527/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ * DO NOT EDIT THIS FILE
+ * This file is under version control at
+ *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
+ * and can be replaced with that version at any time
+ * DO NOT EDIT THIS FILE
  *
- * Copyright (C) 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
+ * Copyright 2004-2010 Analog Devices Inc.
+ * Licensed under the ADI BSD license.
+ *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  */
 
 /* This file should be up to date with:
- *  - Revision B, 08/12/2008; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision F, 03/03/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ *  - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
+ *  - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
  */
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
+/* We do not support old silicon - sorry */
+#if __SILICON_REVISION__ < 0
+# error will not work on BF526/BF527 silicon version
+#endif
+
 #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
 # define ANOMALY_BF526 1
 #else

@@ -25,10 +34,14 @@
 # define ANOMALY_BF527 0
 #endif
 
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
+#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
+#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
+#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
+
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
 #define ANOMALY_05000074 (1)
 /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
+#define ANOMALY_05000119 (1)
 /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
 #define ANOMALY_05000122 (1)
 /* False Hardware Error from an Access in the Shadow of a Conditional Branch */

@@ -40,167 +53,226 @@
 /* False Hardware Errors Caused by Fetches@the Boundary of Reserved Memory */
 #define ANOMALY_05000310 (1)
 /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
 /* Host DMA Boot Modes Are Not Functional */
 #define ANOMALY_05000330 (__SILICON_REVISION__ < 2)
 /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
 /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
 /* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
 /* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* USB Calibration Value to use */
 #define ANOMALY_05000346_value 0xE510
 /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
 /* Security Features Are Not Functional */
-#define ANOMALY_05000348 (ANOMALY_BF527 && __SILICON_REVISION__ < 1)
+#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
 /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (ANOMALY_BF526)
+#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
 /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
 /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
 /* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (ANOMALY_BF527 && __SILICON_REVISION__ == 1)
+#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
 /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
 #define ANOMALY_05000366 (1)
 /* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
 /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
 /* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
 /* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
 /* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
 /* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
 /* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
 /* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
 /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
 /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
 /* Log Buffer Not Functional */
-#define ANOMALY_05000394 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
 /* Hook Routine Not Functional */
-#define ANOMALY_05000395 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
 /* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
 /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
 /* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
 /* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
 /* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
 #define ANOMALY_05000405 (1)
 /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
 #define ANOMALY_05000408 (1)
 /* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
 /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000411 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Speculative Fetches Can Cause Undesired External FIFO Operations */
 #define ANOMALY_05000416 (1)
 /* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
 /* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
 #define ANOMALY_05000421 (1)
 /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
 /* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (ANOMALY_BF527 && __SILICON_REVISION__ < 2)
+#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
 /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
 #define ANOMALY_05000426 (1)
 /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
+#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
 /* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (ANOMALY_BF527 && __SILICON_REVISION__ > 1)
+#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
 /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
 #define ANOMALY_05000431 (1)
 /* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (ANOMALY_BF526)
+#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
+/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
+#define ANOMALY_05000434 (1)
 /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 ((ANOMALY_BF526 && __SILICON_REVISION__ < 1) || ANOMALY_BF527)
+#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (1)
+#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (1)
+#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
+#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
 /* IFLUSH Instruction@End of Hardware Loop Causes Infinite Stall */
 #define ANOMALY_05000443 (1)
 /* The WURESET Bit in the SYSCR Register is not Functional */
 #define ANOMALY_05000445 (1)
+/* USB DMA Mode 1 Short Packet Data Corruption */
+#define ANOMALY_05000450 (1)
 /* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
 #define ANOMALY_05000451 (1)
 /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (1)
+#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
 /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
 #define ANOMALY_05000456 (1)
 /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
 #define ANOMALY_05000457 (1)
+/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
+#define ANOMALY_05000460 (1)
+/* False Hardware Error when RETI Points to Invalid Memory */
+#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* USB Rx DMA hang */
+#define ANOMALY_05000465 (1)
+/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
+#define ANOMALY_05000466 (1)
+/* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
+#define ANOMALY_05000467 (1)
+/* PLL Latches Incorrect Settings During Reset */
+#define ANOMALY_05000469 (1)
+/* Incorrect Default MSEL Value in PLL_CTL */
+#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
+/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
+#define ANOMALY_05000473 (1)
+/* Possible Lockup Condition whem Modifying PLL from External Memory */
+#define ANOMALY_05000475 (1)
+/* TESTSET Instruction Cannot Be Interrupted */
+#define ANOMALY_05000477 (1)
+/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
+#define ANOMALY_05000481 (1)
+/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
+#define ANOMALY_05000483 (1)
+/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
+#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* IFLUSH sucks at life */
+#define ANOMALY_05000491 (1)
 
 /* Anomalies that don't exist on this proc */
+#define ANOMALY_05000099 (0)
+#define ANOMALY_05000120 (0)
 #define ANOMALY_05000125 (0)
+#define ANOMALY_05000149 (0)
 #define ANOMALY_05000158 (0)
 #define ANOMALY_05000171 (0)
+#define ANOMALY_05000179 (0)
+#define ANOMALY_05000182 (0)
 #define ANOMALY_05000183 (0)
+#define ANOMALY_05000189 (0)
 #define ANOMALY_05000198 (0)
+#define ANOMALY_05000202 (0)
+#define ANOMALY_05000215 (0)
+#define ANOMALY_05000219 (0)
+#define ANOMALY_05000220 (0)
 #define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
+#define ANOMALY_05000231 (0)
+#define ANOMALY_05000233 (0)
+#define ANOMALY_05000234 (0)
 #define ANOMALY_05000242 (0)
 #define ANOMALY_05000244 (0)
+#define ANOMALY_05000248 (0)
+#define ANOMALY_05000250 (0)
+#define ANOMALY_05000257 (0)
 #define ANOMALY_05000261 (0)
 #define ANOMALY_05000263 (0)
 #define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
+#define ANOMALY_05000274 (0)
 #define ANOMALY_05000278 (0)
+#define ANOMALY_05000281 (0)
+#define ANOMALY_05000283 (0)
 #define ANOMALY_05000285 (0)
+#define ANOMALY_05000287 (0)
+#define ANOMALY_05000301 (0)
 #define ANOMALY_05000305 (0)
 #define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000312 (0)
+#define ANOMALY_05000315 (0)
 #define ANOMALY_05000323 (0)
 #define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
+#define ANOMALY_05000400 (0)
+#define ANOMALY_05000402 (0)
 #define ANOMALY_05000412 (0)
 #define ANOMALY_05000447 (0)
 #define ANOMALY_05000448 (0)
+#define ANOMALY_05000474 (0)
 
 #endif

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index 2c8fd86..18dbdf7 100644
@@ -91,7 +91,9 @@ int irq_init(void)
 #else
 	bfin_write_SIC_IMASK(0);
 #endif
-	bfin_write_EVT2(evt_default);	/* NMI */
+	/* Set up a dummy NMI handler if needed.  */
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
+		bfin_write_EVT2(evt_nmi);	/* NMI */
 	bfin_write_EVT5(evt_default);	/* hardware error */
 	bfin_write_EVT6(evt_default);	/* core timer */
 	bfin_write_EVT7(evt_default);

index c8bec11..ba85e0b 100644
@@ -34,6 +34,7 @@ void bfin_panic(struct pt_regs *reg);
 void dump(struct pt_regs *regs);
 
 asmlinkage void trap(void);
+asmlinkage void evt_nmi(void);
 asmlinkage void evt_default(void);
 
 #endif

index 9453d5d..007f5ce 100644
@@ -101,6 +101,28 @@ static inline void serial_putc(char c)
 		continue;
 }
 
+__attribute__((always_inline)) static inline void
+program_nmi_handler(void)
+{
+	u32 tmp1, tmp2;
+
+	/* Older bootroms don't create a dummy NMI handler,
+	 * so make one ourselves ASAP in case it fires.
+	 */
+	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
+		return;
+
+	asm volatile (
+		"%0 = RETS;" /* Save current RETS */
+		"CALL 1f;"   /* Figure out current PC */
+		"RTN;"       /* The simple NMI handler */
+		"1:"
+		"%1 = RETS;" /* Load addr of NMI handler */
+		"RETS = %0;" /* Restore RETS */
+		"[%2] = %1;" /* Write NMI handler */
+		: "=r"(tmp1), "=r"(tmp2) : "ab"(EVT2)
+	);
+}
 
 /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
  * us a freq of 16MHz for SPI which should generally be

@@ -640,6 +662,9 @@ void initcode(ADI_BOOT_DATA *bs)
 {
 	ADI_BOOT_DATA bootstruct_scratch;
 
+	/* Setup NMI handler before anything else */
+	program_nmi_handler();
+
 	serial_init();
 
 	serial_putc('A');

index b5bebd4..d2ac7a5 100644
@@ -7,6 +7,7 @@
  */
 
 #include <common.h>
+#include <netdev.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -16,3 +17,10 @@ int checkboard(void)
 	printf("       Support: http://www.i-syst.com/\n");
 	return 0;
 }
+
+#ifdef CONFIG_DRIVER_AX88180
+int board_eth_init(bd_t *bis)
+{
+	return ax88180_initialize(bis);
+}
+#endif

index 2eef5ef..5601416 100644
@@ -58,6 +58,18 @@
 
 
 /*
+ * Network Settings
+ */
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_NET_MULTI
+#define CONFIG_DRIVER_AX88180	1
+#define AX88180_BASE		0x2c000000
+#define CONFIG_HOSTNAME		ibf-dsp561
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
  * Flash Settings
  */
 #define CONFIG_SYS_FLASH_CFI		/* The flash is CFI compatible */

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index 81eca83..1ffa239 100644
@@ -1,2 +1,6 @@
+#include "gpio.h"
 #include "mem_map.h"
+#include "portmux.h"
 #include "ports.h"
+
+#define CONFIG_BF52x 1	/* Linux glue */

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index 14c111f..c545b54 100644
@@ -1 +1,5 @@
+#include "gpio.h"
+#include "portmux.h"
 #include "ports.h"
+
+#define BF533_FAMILY 1	/* Linux glue */

new file mode 100644
index 0000000..e02416d
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2008 Analog Devices Inc.
+ * Licensed under the GPL-2 or later.
+ */
+
+
+#ifndef _MACH_GPIO_H_
+#define _MACH_GPIO_H_
+
+#define MAX_BLACKFIN_GPIOS 16
+
+#define GPIO_PF0	0
+#define GPIO_PF1	1
+#define GPIO_PF2	2
+#define GPIO_PF3	3
+#define GPIO_PF4	4
+#define GPIO_PF5	5
+#define GPIO_PF6	6
+#define GPIO_PF7	7
+#define GPIO_PF8	8
+#define GPIO_PF9	9
+#define GPIO_PF10	10
+#define GPIO_PF11	11
+#define GPIO_PF12	12
+#define GPIO_PF13	13
+#define GPIO_PF14	14
+#define GPIO_PF15	15
+
+#define PORT_F GPIO_PF0
+
+#endif /* _MACH_GPIO_H_ */

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index 14c111f..e210db9 100644
@@ -1 +1,5 @@
+#include "gpio.h"
+#include "portmux.h"
 #include "ports.h"
+
+#define BF537_FAMILY 1	/* Linux glue */

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index 81eca83..f1e69a7 100644
@@ -1,2 +1,6 @@
+#include "gpio.h"
 #include "mem_map.h"
+#include "portmux.h"
 #include "ports.h"
+
+#define CONFIG_BF54x 1	/* Linux glue */

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index 597dcec..08e37e5 100644
@@ -9,4 +9,8 @@
 #define bfin_write_WDOG_CTL(val) bfin_write_WDOGA_CTL(val)
 #define bfin_write_WDOG_STAT(val) bfin_write_WDOGA_STAT(val)
 
+#include "gpio.h"
+#include "portmux.h"
 #include "ports.h"
+
+#define BF561_FAMILY 1	/* Linux glue */

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index 6bc7208..952438e 100644

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deleted file mode 100644
index a4c1ec0..0000000
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc > 1) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTFIO();
-		printf("Port F data %04x (PF4:%i)\n", data, !!(data & PF4));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
-	"set/clear PF4 GPIO flash bank switch\n",
-	"<pf4> - set PF4 GPIO pin state\n");

deleted file mode 100644
index 52abe79..0000000
@@ -1,34 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc > 1) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTHIO();
-		printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(ph, 3, 0, do_ph,
-	"set/clear PH0 GPIO flash bank switch\n",
-	"<ph0> - set PH0 GPIO pin state\n");

deleted file mode 100644
index 14055c6..0000000
@@ -1,37 +0,0 @@
-/*
- * flash.c - helper commands for working with GPIO-assisted flash
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include "gpio_cfi_flash.h"
-
-int do_pf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	ulong faddr = CONFIG_SYS_FLASH_BASE;
-	ushort data;
-	ulong dflg;
-
-	if (argc == 3) {
-		dflg = simple_strtoul(argv[1], NULL, 16);
-		faddr |= (dflg << 21);
-		dflg = simple_strtoul(argv[2], NULL, 16);
-		faddr |= (dflg << 22);
-		gpio_cfi_flash_swizzle((void *)faddr);
-	} else {
-		data = bfin_read_PORTFIO();
-		printf("Port F data %04x (PF4:%i PF5:%i)\n", data,
-			!!(data & PF4), !!(data & PF5));
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(pf, 3, 0, do_pf,
-	"set/clear PF4/PF5 GPIO flash bank switch\n",
-	"<pf4> <pf5> - set PF4/PF5 GPIO pin state\n");

index 92ceb38..cba4ac0 100644
@@ -268,8 +268,6 @@
 #define CONFIG_RTC_BFIN
 #define CONFIG_UART_CONSOLE	0
 
-/* #define CONFIG_BF537_STAMP_LEDCMD	1 */
-
 /* Define if want to do post memory test */
 #undef CONFIG_POST
 #ifdef CONFIG_POST

index 1896cf5..fa1e694 100644
@@ -83,6 +83,7 @@
 # define CONFIG_CMD_CPLBINFO
 # define CONFIG_CMD_ELF
 # define CONFIG_ELF_SIMPLE_LOAD
+# define CONFIG_CMD_GPIO
 # define CONFIG_CMD_KGDB
 # define CONFIG_CMD_REGINFO
 # define CONFIG_CMD_STRINGS

index 711fa27..52aeb5c 100644
@@ -161,12 +161,6 @@
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
 /* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
 #define STATUS_LED_BIT 1

index 80c4884..d5e82ca 100644
@@ -231,12 +231,6 @@
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-#ifndef __ASSEMBLY__
-typedef unsigned int led_id_t;
-void __led_init(led_id_t mask, int state);
-void __led_set(led_id_t mask, int state);
-void __led_toggle(led_id_t mask);
-#endif
 /* use LED1 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
 #define STATUS_LED_BIT 1

index 9dbf01f..f213595 100644
@@ -346,9 +346,6 @@ void status_led_set  (int led, int state);
 #elif defined(CONFIG_NIOS2)
 /* XXX empty just to avoid the error */
 /************************************************************************/
-#elif defined(CONFIG_BLACKFIN)
-/* XXX empty just to avoid the error */
-/************************************************************************/
 #elif defined(CONFIG_V38B)
 
 # define STATUS_LED_BIT		0x0010			/* Timer7 GPIO */

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index 4abad08..fd10eae 100644
@@ -134,43 +134,6 @@ void show_boot_progress(int status)
 }
 #endif
 
-#ifdef CONFIG_STATUS_LED
-#include <status_led.h>
-
-static void set_led(int pf, int state)
-{
-	switch (state) {
-		case STATUS_LED_OFF:      bfin_write_FIO_FLAG_S(pf); break;
-		case STATUS_LED_BLINKING: bfin_write_FIO_FLAG_T(pf); break;
-		case STATUS_LED_ON:       bfin_write_FIO_FLAG_C(pf); break;
-	}
-}
-
-static void set_leds(led_id_t mask, int state)
-{
-	if (mask & 0x1) set_led(PF2, state);
-	if (mask & 0x2) set_led(PF3, state);
-	if (mask & 0x4) set_led(PF4, state);
-}
-
-void __led_init(led_id_t mask, int state)
-{
-	bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
-	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
-}
-
-void __led_set(led_id_t mask, int state)
-{
-	set_leds(mask, state);
-}
-
-void __led_toggle(led_id_t mask)
-{
-	set_leds(mask, STATUS_LED_BLINKING);
-}
-
-#endif
-
 #ifdef CONFIG_SMC91111
 int board_eth_init(bd_t *bis)
 {

index 52aeb5c..ecda216 100644
@@ -160,17 +160,19 @@
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
 #define CONFIG_BOARD_SPECIFIC_LED
 /* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF8
 #define STATUS_LED_STATE STATUS_LED_ON
 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
 /* use LED1 to indicate crash */
 #define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PG11
 #define STATUS_LED_STATE1 STATUS_LED_ON
 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PG12 */
 #endif
 
 

index d5e82ca..2ec9c42 100644
@@ -230,17 +230,19 @@
 /* define to enable run status via led */
 /* #define CONFIG_STATUS_LED */
 #ifdef CONFIG_STATUS_LED
+#define CONFIG_GPIO_LED
 #define CONFIG_BOARD_SPECIFIC_LED
-/* use LED1 to indicate booting/alive */
+/* use LED0 to indicate booting/alive */
 #define STATUS_LED_BOOT 0
-#define STATUS_LED_BIT 1
+#define STATUS_LED_BIT GPIO_PF2
 #define STATUS_LED_STATE STATUS_LED_ON
 #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
-/* use LED2 to indicate crash */
+/* use LED1 to indicate crash */
 #define STATUS_LED_CRASH 1
-#define STATUS_LED_BIT1 2
+#define STATUS_LED_BIT1 GPIO_PF3
 #define STATUS_LED_STATE1 STATUS_LED_ON
 #define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
+/* #define STATUS_LED_BIT2 GPIO_PF4 */
 #endif
 
 /* define to enable splash screen support */

index 3911be6..ec888d4 100644
@@ -46,11 +46,8 @@ int checkboard(void)
 void board_reset(void)
 {
 	/* workaround for weak pull ups on ssel */
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
-		bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~PF10);
-		bfin_write_PORTFIO_SET(PF10);
-		udelay(1);
-	}
+	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
+		bfin_reset_boot_spi_cs(GPIO_PF10);
 }
 
 #ifdef CONFIG_BFIN_MAC

index 7167680..f8ccc07 100644
@@ -8,12 +8,13 @@
 
 #include <common.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include "gpio_cfi_flash.h"
 
-#define GPIO_PIN_1  PH9
+#define GPIO_PIN_1  GPIO_PH9
 #define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2  PG11
+#define GPIO_PIN_2  GPIO_PG11
 #define GPIO_MASK_2 (1 << 22)
 #define GPIO_MASK   (GPIO_MASK_1 | GPIO_MASK_2)
 

@@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr)
 {
 	unsigned long addr = (unsigned long)vaddr;
 
-	if (addr & GPIO_MASK_1)
-		bfin_write_PORTHIO_SET(GPIO_PIN_1);
-	else
-		bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
 
 #ifdef GPIO_MASK_2
-	if (addr & GPIO_MASK_2)
-		bfin_write_PORTGIO_SET(GPIO_PIN_2);
-	else
-		bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
 #endif
 
 	SSYNC();

@@ -57,7 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {
-	bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
-	bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | GPIO_PIN_2);
+	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
 	gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
 }

index a9e69cf..79ee844 100644
@@ -8,10 +8,11 @@
 
 #include <common.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include "gpio_cfi_flash.h"
 
-#define GPIO_PIN_1  PF4
+#define GPIO_PIN_1  GPIO_PF4
 #define GPIO_MASK_1 (1 << 21)
 #define GPIO_MASK   (GPIO_MASK_1)
 

@@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr)
 {
 	unsigned long addr = (unsigned long)vaddr;
 
-	if (addr & GPIO_MASK_1)
-		bfin_write_PORTFIO_SET(GPIO_PIN_1);
-	else
-		bfin_write_PORTFIO_CLEAR(GPIO_PIN_1);
+	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
 
 #ifdef GPIO_MASK_2
-	if (addr & GPIO_MASK_2)
-		bfin_write_PORTGIO_SET(GPIO_PIN_2);
-	else
-		bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
 #endif
 
 	SSYNC();

@@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {
-	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1);
+	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
 	gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
 }

index 68633ec..416c689 100644
@@ -8,10 +8,11 @@
 
 #include <common.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include "gpio_cfi_flash.h"
 
-#define GPIO_PIN_1  PH0
+#define GPIO_PIN_1  GPIO_PH0
 #define GPIO_MASK_1 (1 << 21)
 #define GPIO_MASK   (GPIO_MASK_1)
 

@@ -19,16 +20,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr)
 {
 	unsigned long addr = (unsigned long)vaddr;
 
-	if (addr & GPIO_MASK_1)
-		bfin_write_PORTHIO_SET(GPIO_PIN_1);
-	else
-		bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
 
 #ifdef GPIO_MASK_2
-	if (addr & GPIO_MASK_2)
-		bfin_write_PORTGIO_SET(GPIO_PIN_2);
-	else
-		bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
 #endif
 
 	SSYNC();

@@ -55,6 +50,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {
-	bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
+	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
 	gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
 }

index ac8587c..08ea7af 100644
@@ -8,12 +8,13 @@
 
 #include <common.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/io.h>
 #include "gpio_cfi_flash.h"
 
-#define GPIO_PIN_1  PF4
+#define GPIO_PIN_1  GPIO_PF4
 #define GPIO_MASK_1 (1 << 21)
-#define GPIO_PIN_2  PF5
+#define GPIO_PIN_2  GPIO_PF5
 #define GPIO_MASK_2 (1 << 22)
 #define GPIO_MASK   (GPIO_MASK_1 | GPIO_MASK_2)
 

@@ -21,16 +22,10 @@ void *gpio_cfi_flash_swizzle(void *vaddr)
 {
 	unsigned long addr = (unsigned long)vaddr;
 
-	if (addr & GPIO_MASK_1)
-		bfin_write_PORTFIO_SET(GPIO_PIN_1);
-	else
-		bfin_write_PORTFIO_CLEAR(GPIO_PIN_1);
+	gpio_set_value(GPIO_PIN_1, addr & GPIO_MASK_1);
 
 #ifdef GPIO_MASK_2
-	if (addr & GPIO_MASK_2)
-		bfin_write_PORTFIO_SET(GPIO_PIN_2);
-	else
-		bfin_write_PORTFIO_CLEAR(GPIO_PIN_2);
+	gpio_set_value(GPIO_PIN_2, addr & GPIO_MASK_2);
 #endif
 
 	SSYNC();

@@ -57,6 +52,9 @@ MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
 
 void gpio_cfi_flash_init(void)
 {
-	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() | GPIO_PIN_1 | GPIO_PIN_2);
+	gpio_request(GPIO_PIN_1, "gpio_cfi_flash");
+#ifdef GPIO_MASK_2
+	gpio_request(GPIO_PIN_2, "gpio_cfi_flash");
+#endif
 	gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
 }

index 720e126..ee4ad6c 100644
@@ -16,6 +16,7 @@
 #include <linux/mii.h>
 
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
 #include <asm/mach-common/bits/emac.h>
 #include <asm/mach-common/bits/pll.h>

@@ -213,8 +214,17 @@ static int bfin_EMAC_recv(struct eth_device *dev)
 /* MDC = SCLK / MDC_freq / 2 - 1 */
 #define MDC_FREQ_TO_DIV(mdc_freq) (get_sclk() / (mdc_freq) / 2 - 1)
 
+#ifndef CONFIG_BFIN_MAC_PINS
+# ifdef CONFIG_RMII
+#  define CONFIG_BFIN_MAC_PINS P_RMII0
+# else
+#  define CONFIG_BFIN_MAC_PINS P_MII0
+# endif
+#endif
+
 static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
 {
+	const unsigned short pins[] = CONFIG_BFIN_MAC_PINS;
 	u16 phydat;
 	size_t count;
 

@@ -222,42 +232,7 @@ static int bfin_miiphy_init(struct eth_device *dev, int *opmode)
 	*pVR_CTL |= CLKBUFOE;
 
 	/* Set all the pins to peripheral mode */
-#ifdef CONFIG_RMII
-	/* grab RMII pins */
-# if defined(__ADSPBF51x__)
-	*pPORTF_MUX = (*pPORTF_MUX & \
-		~(PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
-		PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
-	*pPORTF_FER |= PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
-	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
-	*pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
-	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
-	*pPORTG_FER |= PG14 | PG15;
-	*pPORTH_MUX = (*pPORTH_MUX & ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK)) | \
-		PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2;
-	*pPORTH_FER |= PH0 | PH1 | PH2 | PH3 | PH4 | PH5 | PH6 | PH7 | PH8;
-# else
-	*pPORTH_FER |= PH0 | PH1 | PH4 | PH5 | PH6 | PH8 | PH9 | PH14 | PH15;
-# endif
-#else
-	/* grab MII & RMII pins */
-# if defined(__ADSPBF51x__)
-	*pPORTF_MUX = (*pPORTF_MUX & \
-		~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK)) | \
-		PORT_x_MUX_0_FUNC_1 | PORT_x_MUX_1_FUNC_1 | PORT_x_MUX_3_FUNC_1 | PORT_x_MUX_4_FUNC_1 | PORT_x_MUX_5_FUNC_1;
-	*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF8 | PF9 | PF10 | PF11 | PF12 | PF13 | PF14 | PF15;
-	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_0_MASK) | PORT_x_MUX_0_FUNC_1;
-	*pPORTG_FER |= PG0 | PG1 | PG2;
-# elif defined(__ADSPBF52x__)
-	*pPORTG_MUX = (*pPORTG_MUX & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2;
-	*pPORTG_FER |= PG14 | PG15;
-	*pPORTH_MUX = PORT_x_MUX_0_FUNC_2 | PORT_x_MUX_1_FUNC_2 | PORT_x_MUX_2_FUNC_2;
-	*pPORTH_FER = -1; /* all pins */
-# else
-	*pPORTH_FER = -1; /* all pins */
-# endif
-#endif
+	peripheral_request_list(pins, "bfin_mac");
 
 	/* Odd word alignment for Receive Frame DMA word */
 	/* Configure checksum support and rcve frame word alignment */

index 6d3d450..3ee060f 100644
@@ -26,6 +26,7 @@
 #include <nand.h>
 
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 
 /* Bit masks for NFC_CTL */
 

@@ -337,6 +338,12 @@ static struct nand_ecclayout bootrom_ecclayout = {
  */
 int board_nand_init(struct nand_chip *chip)
 {
+	const unsigned short pins[] = {
+		P_NAND_CE, P_NAND_RB, P_NAND_D0, P_NAND_D1, P_NAND_D2,
+		P_NAND_D3, P_NAND_D4, P_NAND_D5, P_NAND_D6, P_NAND_D7,
+		P_NAND_WE, P_NAND_RE, P_NAND_CLE, P_NAND_ALE, 0,
+	};
+
 	pr_stamp();
 
 	/* set width/ecc/timings/etc... */

@@ -347,14 +354,7 @@ int board_nand_init(struct nand_chip *chip)
 	bfin_write_NFC_IRQSTAT(0xffff);
 
 	/* enable GPIO function enable register */
-#ifdef __ADSPBF54x__
-	bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
-#elif defined(__ADSPBF52x__)
-	bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
-	bfin_write_PORTH_MUX(0);
-#else
-# error no support for this variant
-#endif
+	peripheral_request_list(pins, "bfin_nand");
 
 	chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
 	chip->read_buf = bfin_nfc_read_buf;

index f9d560a..4a77779 100644
@@ -15,6 +15,7 @@
 #include <asm/errno.h>
 #include <asm/byteorder.h>
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/sdh.h>
 #include <asm/mach-common/bits/dma.h>
 

@@ -41,11 +42,15 @@
 # define bfin_write_DMA_X_COUNT		bfin_write_DMA4_X_COUNT
 # define bfin_write_DMA_X_MODIFY	bfin_write_DMA4_X_MODIFY
 # define bfin_write_DMA_CONFIG		bfin_write_DMA4_CONFIG
+# define PORTMUX_PINS \
+	{ P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
 #elif defined(__ADSPBF54x__)
 # define bfin_write_DMA_START_ADDR	bfin_write_DMA22_START_ADDR
 # define bfin_write_DMA_X_COUNT		bfin_write_DMA22_X_COUNT
 # define bfin_write_DMA_X_MODIFY	bfin_write_DMA22_X_MODIFY
 # define bfin_write_DMA_CONFIG		bfin_write_DMA22_CONFIG
+# define PORTMUX_PINS \
+	{ P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
 #else
 # error no support for this proc yet
 #endif

@@ -208,18 +213,13 @@ static void bfin_sdh_set_ios(struct mmc *mmc)
 
 static int bfin_sdh_init(struct mmc *mmc)
 {
-
+	const unsigned short pins[] = PORTMUX_PINS;
 	u16 pwr_ctl = 0;
-/* Initialize sdh controller */
+
+	/* Initialize sdh controller */
+	peripheral_request_list(pins, "bfin_sdh");
 #if defined(__ADSPBF54x__)
 	bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
-	bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00);
-	bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000);
-#elif defined(__ADSPBF51x__)
-	bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8);
-	bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154);
-#else
-# error no portmux for this proc yet
 #endif
 	bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
 	/* Disable card detect pin */

index f16dabe..847c032 100644
@@ -14,6 +14,7 @@
 #include <asm/byteorder.h>
 #include <asm/io.h>
 #include <asm/errno.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/pata.h>
 #include <ata.h>
 #include <libata.h>

@@ -769,19 +770,17 @@ static int bfin_ata_reset_port(struct ata_port *ap)
  */
 static int bfin_config_atapi_gpio(struct ata_port *ap)
 {
-	bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0x4);
-	bfin_write_PORTH_MUX(bfin_read_PORTH_MUX() & ~0x30);
-	bfin_write_PORTH_DIR_SET(0x4);
-
-	bfin_write_PORTJ_FER(0x7f8);
-	bfin_write_PORTJ_MUX(bfin_read_PORTI_MUX() & ~0x3fffc0);
-	bfin_write_PORTJ_DIR_SET(0x5f8);
-	bfin_write_PORTJ_DIR_CLEAR(0x200);
-	bfin_write_PORTJ_INEN(0x200);
-
-	bfin_write_PINT2_ASSIGN(0x0707);
-	bfin_write_PINT2_MASK_SET(0x200);
-	SSYNC();
+	const unsigned short pins[] = {
+		P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0,
+		P_ATAPI_CS1, P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ,
+		P_ATAPI_IORDY, P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A,
+		P_ATAPI_D3A, P_ATAPI_D4A, P_ATAPI_D5A, P_ATAPI_D6A,
+		P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A, P_ATAPI_D10A,
+		P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
+		P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A, 0,
+	};
+
+	peripheral_request_list(pins, "pata_bfin");
 
 	return 0;
 }

index 5f9be86..f9e311f 100644
@@ -26,6 +26,8 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/portmux.h>
+
 #define LOB(x) ((x) & 0xFF)
 #define HIB(x) (((x) >> 8) & 0xFF)
 

@@ -103,6 +105,23 @@ struct bfin_mmr_serial {
 __attribute__((always_inline))
 static inline void serial_do_portmux(void)
 {
+	if (!BFIN_DEBUG_EARLY_SERIAL) {
+		const unsigned short pins[] = {
+#if CONFIG_UART_CONSOLE == 0
+			P_UART0_TX, P_UART0_RX,
+#elif CONFIG_UART_CONSOLE == 1
+			P_UART1_TX, P_UART1_RX,
+#elif CONFIG_UART_CONSOLE == 2
+			P_UART2_TX, P_UART2_RX,
+#elif CONFIG_UART_CONSOLE == 3
+			P_UART3_TX, P_UART3_RX,
+#endif
+			0,
+		};
+		peripheral_request_list(pins, "bfin-uart");
+		return;
+	}
+
 #if defined(__ADSPBF51x__)
 # define DO_MUX(port, mux_tx, mux_rx, tx, rx) \
 	bfin_write_PORT##port##_MUX((bfin_read_PORT##port##_MUX() & ~(PORT_x_MUX_##mux_tx##_MASK | PORT_x_MUX_##mux_rx##_MASK)) | PORT_x_MUX_##mux_tx##_FUNC_2 | PORT_x_MUX_##mux_rx##_FUNC_2); \

index f28d42b..4e008a7 100644
@@ -13,6 +13,7 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
 
 struct bfin_spi_slave {

@@ -81,6 +82,42 @@ void spi_init()
 {
 }
 
+#ifdef SPI_CTL
+# define SPI0_CTL SPI_CTL
+#endif
+
+#define SPI_PINS(n) \
+	[n] = { 0, P_SPI##n##_SCK, P_SPI##n##_MISO, P_SPI##n##_MOSI, 0 }
+static unsigned short pins[][5] = {
+#ifdef SPI0_CTL
+	SPI_PINS(0),
+#endif
+#ifdef SPI1_CTL
+	SPI_PINS(1),
+#endif
+#ifdef SPI2_CTL
+	SPI_PINS(2),
+#endif
+};
+
+#define SPI_CS_PINS(n) \
+	[n] = { \
+		P_SPI##n##_SSEL1, P_SPI##n##_SSEL2, P_SPI##n##_SSEL3, \
+		P_SPI##n##_SSEL4, P_SPI##n##_SSEL5, P_SPI##n##_SSEL6, \
+		P_SPI##n##_SSEL7, \
+	}
+static const unsigned short cs_pins[][7] = {
+#ifdef SPI0_CTL
+	SPI_CS_PINS(0),
+#endif
+#ifdef SPI1_CTL
+	SPI_CS_PINS(1),
+#endif
+#ifdef SPI2_CTL
+	SPI_CS_PINS(2),
+#endif
+};
+
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode)
 {

@@ -92,11 +129,14 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 	if (!spi_cs_is_valid(bus, cs))
 		return NULL;
 
+	if (bus >= ARRAY_SIZE(pins) || pins[bus] == NULL) {
+		debug("%s: invalid bus %u\n", __func__, bus);
+		return NULL;
+	}
 	switch (bus) {
-#ifdef SPI_CTL
-# define SPI0_CTL SPI_CTL
-#endif
+#ifdef SPI0_CTL
 		case 0: mmr_base = SPI0_CTL; break;
+#endif
 #ifdef SPI1_CTL
 		case 1: mmr_base = SPI1_CTL; break;
 #endif

@@ -142,168 +182,15 @@ void spi_free_slave(struct spi_slave *slave)
 	free(bss);
 }
 
-static void spi_portmux(struct spi_slave *slave)
-{
-#if defined(__ADSPBF51x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
-	u16 f_mux = bfin_read_PORTF_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	u16 g_mux = bfin_read_PORTG_MUX();
-	u16 g_fer = bfin_read_PORTG_FER();
-	u16 h_mux = bfin_read_PORTH_MUX();
-	u16 h_fer = bfin_read_PORTH_FER();
-	switch (slave->bus) {
-	case 0:
-		/* set SCK/MISO/MOSI */
-		SET_MUX(g, 7, 1);
-		g_fer |= PG12 | PG13 | PG14;
-		switch (slave->cs) {
-			case 1: SET_MUX(f, 2, 1); f_fer |= PF7;  break;
-			case 2: /* see G above */ g_fer |= PG15; break;
-			case 3: SET_MUX(h, 1, 3); f_fer |= PH4;  break;
-			case 4: /* no muxing */   h_fer |= PH8;  break;
-			case 5: SET_MUX(g, 1, 3); h_fer |= PG3;  break;
-			case 6: /* no muxing */                  break;
-			case 7: /* no muxing */                  break;
-		}
-	case 1:
-		/* set SCK/MISO/MOSI */
-		SET_MUX(h, 0, 2);
-		h_fer |= PH1 | PH2 | PH3;
-		switch (slave->cs) {
-			case 1: SET_MUX(h, 2, 3); h_fer |= PH6;  break;
-			case 2: SET_MUX(f, 0, 3); f_fer |= PF0;  break;
-			case 3: SET_MUX(g, 0, 3); g_fer |= PG0;  break;
-			case 4: SET_MUX(f, 3, 3); f_fer |= PF8;  break;
-			case 5: SET_MUX(g, 6, 3); h_fer |= PG11; break;
-			case 6: /* no muxing */                  break;
-			case 7: /* no muxing */                  break;
-		}
-	}
-	bfin_write_PORTF_MUX(f_mux);
-	bfin_write_PORTF_FER(f_fer);
-	bfin_write_PORTG_MUX(g_mux);
-	bfin_write_PORTG_FER(g_fer);
-	bfin_write_PORTH_MUX(h_mux);
-	bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF52x__)
-#define SET_MUX(port, mux, func) port##_mux = ((port##_mux & ~PORT_x_MUX_##mux##_MASK) | PORT_x_MUX_##mux##_FUNC_##func)
-	u16 f_mux = bfin_read_PORTF_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	u16 g_mux = bfin_read_PORTG_MUX();
-	u16 g_fer = bfin_read_PORTG_FER();
-	u16 h_mux = bfin_read_PORTH_MUX();
-	u16 h_fer = bfin_read_PORTH_FER();
-	/* set SCK/MISO/MOSI */
-	SET_MUX(g, 0, 3);
-	g_fer |= PG2 | PG3 | PG4;
-	switch (slave->cs) {
-		case 1: /* see G above */ g_fer |= PG1;  break;
-		case 2: SET_MUX(f, 4, 3); f_fer |= PF12; break;
-		case 3: SET_MUX(f, 4, 3); f_fer |= PF13; break;
-		case 4: SET_MUX(h, 1, 1); h_fer |= PH8;  break;
-		case 5: SET_MUX(h, 2, 1); h_fer |= PH9;  break;
-		case 6: SET_MUX(f, 1, 3); f_fer |= PF9;  break;
-		case 7: SET_MUX(f, 2, 3); f_fer |= PF10; break;
-	}
-	bfin_write_PORTF_MUX(f_mux);
-	bfin_write_PORTF_FER(f_fer);
-	bfin_write_PORTG_MUX(g_mux);
-	bfin_write_PORTG_FER(g_fer);
-	bfin_write_PORTH_MUX(h_mux);
-	bfin_write_PORTH_FER(h_fer);
-#elif defined(__ADSPBF534__) || defined(__ADSPBF536__) || defined(__ADSPBF537__)
-	u16 mux = bfin_read_PORT_MUX();
-	u16 f_fer = bfin_read_PORTF_FER();
-	/* set SCK/MISO/MOSI */
-	f_fer |= PF11 | PF12 | PF13;
-	switch (slave->cs) {
-		case 1: f_fer |= PF10; break;
-		case 2: mux |= PJSE; break;
-		case 3: mux |= PJSE; break;
-		case 4: mux |= PFS4E; f_fer |= PF6; break;
-		case 5: mux |= PFS5E; f_fer |= PF5; break;
-		case 6: mux |= PFS6E; f_fer |= PF4; break;
-		case 7: mux |= PJCE_SPI; break;
-	}
-	bfin_write_PORT_MUX(mux);
-	bfin_write_PORTF_FER(f_fer);
-#elif defined(__ADSPBF538__) || defined(__ADSPBF539__)
-	u16 fer, pins;
-	if (slave->bus == 1)
-		pins = PD0 | PD1 | PD2 | (slave->cs == 1 ? PD4 : 0);
-	else if (slave->bus == 2)
-		pins = PD5 | PD6 | PD7 | (slave->cs == 1 ? PD9 : 0);
-	else
-		pins = 0;
-	if (pins) {
-		fer = bfin_read_PORTDIO_FER();
-		fer &= ~pins;
-		bfin_write_PORTDIO_FER(fer);
-	}
-#elif defined(__ADSPBF54x__)
-#define DO_MUX(port, pin) \
-	mux = ((mux & ~PORT_x_MUX_##pin##_MASK) | PORT_x_MUX_##pin##_FUNC_1); \
-	fer |= P##port##pin;
-	u32 mux;
-	u16 fer;
-	switch (slave->bus) {
-	case 0:
-		mux = bfin_read_PORTE_MUX();
-		fer = bfin_read_PORTE_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(E, 0);
-		DO_MUX(E, 1);
-		DO_MUX(E, 2);
-		switch (slave->cs) {
-			case 1: DO_MUX(E, 4); break;
-			case 2: DO_MUX(E, 5); break;
-			case 3: DO_MUX(E, 6); break;
-		}
-		bfin_write_PORTE_MUX(mux);
-		bfin_write_PORTE_FER(fer);
-		break;
-	case 1:
-		mux = bfin_read_PORTG_MUX();
-		fer = bfin_read_PORTG_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(G, 8);
-		DO_MUX(G, 9);
-		DO_MUX(G, 10);
-		switch (slave->cs) {
-			case 1: DO_MUX(G, 5); break;
-			case 2: DO_MUX(G, 6); break;
-			case 3: DO_MUX(G, 7); break;
-		}
-		bfin_write_PORTG_MUX(mux);
-		bfin_write_PORTG_FER(fer);
-		break;
-	case 2:
-		mux = bfin_read_PORTB_MUX();
-		fer = bfin_read_PORTB_FER();
-		/* set SCK/MISO/MOSI */
-		DO_MUX(B, 12);
-		DO_MUX(B, 13);
-		DO_MUX(B, 14);
-		switch (slave->cs) {
-			case 1: DO_MUX(B, 9);  break;
-			case 2: DO_MUX(B, 10); break;
-			case 3: DO_MUX(B, 11); break;
-		}
-		bfin_write_PORTB_MUX(mux);
-		bfin_write_PORTB_FER(fer);
-		break;
-	}
-#endif
-}
-
 int spi_claim_bus(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
-	spi_portmux(slave);
+	pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+	peripheral_request_list(pins[slave->bus], "bfin-spi");
+
 	write_SPI_CTL(bss, bss->ctl);
 	write_SPI_BAUD(bss, bss->baud);
 	SSYNC();

@@ -314,7 +201,11 @@ int spi_claim_bus(struct spi_slave *slave)
 void spi_release_bus(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
+
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
+
+	peripheral_free_list(pins[slave->bus]);
+
 	write_SPI_CTL(bss, 0);
 	SSYNC();
 }

index 4e008a7..e0ad029 100644
@@ -13,6 +13,7 @@
 #include <spi.h>
 
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/portmux.h>
 #include <asm/mach-common/bits/spi.h>
 

@@ -34,48 +35,68 @@ MAKE_SPI_FUNC(SPI_BAUD, 0x14)
 
 #define to_bfin_spi_slave(s) container_of(s, struct bfin_spi_slave, slave)
 
-__attribute__((weak))
+#define MAX_CTRL_CS 7
+
+#define gpio_cs(cs) ((cs) - MAX_CTRL_CS)
+#ifdef CONFIG_BFIN_SPI_GPIO_CS
+# define is_gpio_cs(cs) ((cs) > MAX_CTRL_CS)
+#else
+# define is_gpio_cs(cs) 0
+#endif
+
 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 {
-#if defined(__ADSPBF538__) || defined(__ADSPBF539__)
-	/* The SPI1/SPI2 buses are weird ... only 1 CS */
-	if (bus > 0 && cs != 1)
-		return 0;
-#endif
-	return (cs >= 1 && cs <= 7);
+	if (is_gpio_cs(cs))
+		return gpio_is_valid(gpio_cs(cs));
+	else
+		return (cs >= 1 && cs <= MAX_CTRL_CS);
 }
 
-__attribute__((weak))
 void spi_cs_activate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	write_SPI_FLG(bss,
-		(read_SPI_FLG(bss) &
-		~((!bss->flg << 8) << slave->cs)) |
-		(1 << slave->cs));
+
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		write_SPI_FLG(bss,
+			(read_SPI_FLG(bss) &
+			~((!bss->flg << 8) << slave->cs)) |
+			(1 << slave->cs));
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
+
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
-__attribute__((weak))
 void spi_cs_deactivate(struct spi_slave *slave)
 {
 	struct bfin_spi_slave *bss = to_bfin_spi_slave(slave);
-	u16 flg;
-
-	/* make sure we force the cs to deassert rather than let the
-	 * pin float back up.  otherwise, exact timings may not be
-	 * met some of the time leading to random behavior (ugh).
-	 */
-	flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
-	write_SPI_FLG(bss, flg);
-	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 
-	flg &= ~(1 << slave->cs);
-	write_SPI_FLG(bss, flg);
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_set_value(cs, !bss->flg);
+		debug("%s: SPI_CS_GPIO:%x\n", __func__, gpio_get_value(cs));
+	} else {
+		u16 flg;
+
+		/* make sure we force the cs to deassert rather than let the
+		 * pin float back up.  otherwise, exact timings may not be
+		 * met some of the time leading to random behavior (ugh).
+		 */
+		flg = read_SPI_FLG(bss) | ((!bss->flg << 8) << slave->cs);
+		write_SPI_FLG(bss, flg);
+		SSYNC();
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+
+		flg &= ~(1 << slave->cs);
+		write_SPI_FLG(bss, flg);
+		debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
+	}
+
 	SSYNC();
-	debug("%s: SPI_FLG:%x\n", __func__, read_SPI_FLG(bss));
 }
 
 void spi_init()

@@ -188,7 +209,13 @@ int spi_claim_bus(struct spi_slave *slave)
 
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
-	pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
+	if (is_gpio_cs(slave->cs)) {
+		unsigned int cs = gpio_cs(slave->cs);
+		gpio_request(cs, "bfin-spi");
+		gpio_direction_output(cs, !bss->flg);
+		pins[slave->bus][0] = P_DONTCARE;
+	} else
+		pins[slave->bus][0] = cs_pins[slave->bus][slave->cs - 1];
 	peripheral_request_list(pins[slave->bus], "bfin-spi");
 
 	write_SPI_CTL(bss, bss->ctl);

@@ -205,6 +232,8 @@ void spi_release_bus(struct spi_slave *slave)
 	debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
 
 	peripheral_free_list(pins[slave->bus]);
+	if (is_gpio_cs(slave->cs))
+		gpio_free(gpio_cs(slave->cs));
 
 	write_SPI_CTL(bss, 0);
 	SSYNC();

index fa1e694..82daeb1 100644
@@ -254,6 +254,7 @@
 /*
  * Misc Settings
  */
+#define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */
 #define CONFIG_LZMA
 
 #endif

index fd10eae..935aad2 100644
@@ -27,8 +27,7 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/io.h>
-#include "bf533-stamp.h"
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -46,15 +45,10 @@ int checkboard(void)
  */
 void swap_to(int device_id)
 {
-	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0);
-	SSYNC();
-	bfin_write_FIO_FLAG_C(PF1);
-	if (device_id == ETHERNET)
-		bfin_write_FIO_FLAG_S(PF0);
-	else if (device_id == FLASH)
-		bfin_write_FIO_FLAG_C(PF0);
-	else
-		printf("Unknown device to switch\n");
+	gpio_request(GPIO_PF0, "eth_flash_swap");
+	gpio_request(GPIO_PF1, "eth_flash_swap");
+	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
+	gpio_direction_output(GPIO_PF1, 0);
 	SSYNC();
 }
 

@@ -75,24 +69,23 @@ int misc_init_r(void)
 #define STATUS_LED_OFF 0
 #define STATUS_LED_ON  1
 
+static int gpio_setup;
+
 static void stamp_led_set(int LED1, int LED2, int LED3)
 {
-	bfin_write_FIO_INEN(bfin_read_FIO_INEN() & ~(PF2 | PF3 | PF4));
-	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | (PF2 | PF3 | PF4));
-
-	if (LED1 == STATUS_LED_OFF)
-		*pFIO_FLAG_S = PF2;
-	else
-		*pFIO_FLAG_C = PF2;
-	if (LED2 == STATUS_LED_OFF)
-		*pFIO_FLAG_S = PF3;
-	else
-		*pFIO_FLAG_C = PF3;
-	if (LED3 == STATUS_LED_OFF)
-		*pFIO_FLAG_S = PF4;
-	else
-		*pFIO_FLAG_C = PF4;
-	SSYNC();
+	if (!gpio_setup) {
+		gpio_request(GPIO_PF2, "boot_progress");
+		gpio_request(GPIO_PF3, "boot_progress");
+		gpio_request(GPIO_PF4, "boot_progress");
+		gpio_direction_output(GPIO_PF2, LED1);
+		gpio_direction_output(GPIO_PF3, LED2);
+		gpio_direction_output(GPIO_PF4, LED3);
+		gpio_setup = 1;
+	} else {
+		gpio_set_value(GPIO_PF2, LED1);
+		gpio_set_value(GPIO_PF3, LED2);
+		gpio_set_value(GPIO_PF4, LED3);
+	}
 }
 
 void show_boot_progress(int status)

index 6355c10..06d004a 100644
@@ -13,7 +13,7 @@
 
 #include <common.h>
 #include <netdev.h>
-#include <asm/io.h>
+#include <asm/gpio.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -27,14 +27,8 @@ int checkboard(void)
 #ifdef SHARED_RESOURCES
 void swap_to(int device_id)
 {
-	bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF0);
-	SSYNC();
-	if (device_id == ETHERNET)
-		bfin_write_FIO_FLAG_S(PF0);
-	else if (device_id == FLASH)
-		bfin_write_FIO_FLAG_C(PF0);
-	else
-		printf("Unknown device to switch\n");
+	gpio_request(GPIO_PF0, "eth_flash_swap");
+	gpio_direction_output(GPIO_PF0, device_id == ETHERNET);
 	SSYNC();
 }
 #endif

deleted file mode 100644
index ebd39c7..0000000
@@ -1,53 +0,0 @@
-/*
- * U-boot - stamp.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#ifndef __STAMP_H__
-#define __STAMP_H__
-
-extern void init_Flags(void);
-
-extern volatile unsigned long *ambctl0;
-extern volatile unsigned long *ambctl1;
-extern volatile unsigned long *amgctl;
-
-/* Definitions used in  Compact Flash Boot support */
-#define FIO_EDGE_CF_BITS	0x0000
-#define FIO_POLAR_CF_BITS	0x0000
-#define	FIO_EDGE_BITS		0x1E0
-#define	FIO_POLAR_BITS		0x160
-
-/* Compact flash status bits in status register */
-#define CF_STAT_BITS		0x00000060
-
-/* CF Flags used to switch between expansion and external
- * memory banks
- */
-#define CF_PF0			0x0001
-#define CF_PF1			0x0002
-#define CF_PF1_PF0		0x0003
-
-#endif

index 23e786b..3e4080e 100644
@@ -11,7 +11,6 @@
 #include <common.h>
 #include <config.h>
 #include <asm/blackfin.h>
-#include "bf533-stamp.h"
 
 void cf_outb(unsigned char val, volatile unsigned char *addr)
 {

@@ -66,6 +65,15 @@ void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words)
 	swap_to(FLASH);
 }
 
+/* Definitions used in  Compact Flash Boot support */
+#define FIO_EDGE_CF_BITS	0x0000
+#define FIO_POLAR_CF_BITS	0x0000
+#define FIO_EDGE_BITS		0x1E0
+#define FIO_POLAR_BITS		0x160
+
+/* Compact flash status bits in status register */
+#define CF_STAT_BITS	0x00000060
+
 void cf_ide_init(void)
 {
 	int i, cf_stat;

index 85b350f..c2ab598 100644
@@ -61,6 +61,7 @@ static void board_init_enetaddr(uchar *mac_addr)
 #define KSZ_WRITE     0x02
 #define KSZ_READ      0x03
 
+#define KSZ_REG_CHID  0x00	/* Register 0: Chip ID0 */
 #define KSZ_REG_STPID 0x01	/* Register 1: Chip ID1 / Start Switch */
 #define KSZ_REG_GC9   0x0b	/* Register 11: Global Control 9 */
 #define KSZ_REG_P3C0  0x30	/* Register 48: Port 3 Control 0 */

@@ -78,15 +79,17 @@ static int ksz8893m_reg_set(struct spi_slave *slave, uchar reg, uchar data)
 	return ksz8893m_transfer(slave, KSZ_WRITE, reg, data, din);
 }
 
-static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+static int ksz8893m_reg_read(struct spi_slave *slave, uchar reg)
 {
-	int ret = 0;
+	int ret;
 	unsigned char din[3];
+	ret = ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
+	return ret ? ret : din[2];
+}
 
-	ret |= ksz8893m_transfer(slave, KSZ_READ, reg, 0, din);
-	ret |= ksz8893m_reg_set(slave, reg, din[2] & mask);
-
-	return ret;
+static int ksz8893m_reg_clear(struct spi_slave *slave, uchar reg, uchar mask)
+{
+	return ksz8893m_reg_set(slave, reg, ksz8893m_reg_read(slave, reg) & mask);
 }
 
 static int ksz8893m_reset(struct spi_slave *slave)

@@ -107,16 +110,16 @@ static int ksz8893m_reset(struct spi_slave *slave)
 
 int board_eth_init(bd_t *bis)
 {
-	static bool switch_is_alive = false;
+	static bool switch_is_alive = false, phy_is_ksz = true;
 	int ret;
 
 	if (!switch_is_alive) {
 		struct spi_slave *slave = spi_setup_slave(0, 1, KSZ_MAX_HZ, SPI_MODE_3);
 		if (slave) {
 			if (!spi_claim_bus(slave)) {
-				ret = ksz8893m_reset(slave);
-				if (!ret)
-					switch_is_alive = true;
+				phy_is_ksz = (ksz8893m_reg_read(slave, KSZ_REG_CHID) == 0x88);
+				ret = phy_is_ksz ? ksz8893m_reset(slave) : 0;
+				switch_is_alive = (ret == 0);
 				spi_release_bus(slave);
 			}
 			spi_free_slave(slave);

index 1e821d9..7d20b66 100644
@@ -63,6 +63,26 @@
 #if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
 #define ADI_CMDS_NETWORK	1
 #define CONFIG_BFIN_MAC
+#define CONFIG_BFIN_MAC_PINS \
+	{ \
+	P_MII0_ETxD0, \
+	P_MII0_ETxD1, \
+	P_MII0_ETxD2, \
+	P_MII0_ETxD3, \
+	P_MII0_ETxEN, \
+	P_MII0_TxCLK, \
+	P_MII0_PHYINT, \
+	P_MII0_COL, \
+	P_MII0_ERxD0, \
+	P_MII0_ERxD1, \
+	P_MII0_ERxD2, \
+	P_MII0_ERxD3, \
+	P_MII0_ERxDV, \
+	P_MII0_ERxCLK, \
+	P_MII0_CRS, \
+	P_MII0_MDC, \
+	P_MII0_MDIO, \
+	0 }
 #define CONFIG_NETCONSOLE	1
 #define CONFIG_NET_MULTI	1
 #endif

index c2ab598..ff1ac4c 100644
@@ -14,6 +14,7 @@
 #include <spi.h>
 #include <asm/blackfin.h>
 #include <asm/net.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/otp.h>
 #include <asm/sdh.h>
 

@@ -146,18 +147,11 @@ int misc_init_r(void)
 
 int board_early_init_f(void)
 {
-#if !defined(CONFIG_SYS_NO_FLASH)
-	/* setup BF518-EZBRD GPIO pin PG11 to AMS2. */
-	bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_6_MASK) | PORT_x_MUX_6_FUNC_2);
-	bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG11);
-
-# if !defined(CONFIG_BFIN_SPI)
-	/* setup BF518-EZBRD GPIO pin PG15 to AMS3. */
-	bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~PORT_x_MUX_7_MASK) | PORT_x_MUX_7_FUNC_3);
-	bfin_write_PORTG_FER(bfin_read_PORTG_FER() | PG15);
-# endif
-#endif
-	return 0;
+	/* connect async banks by default */
+	const unsigned short pins[] = {
+		P_AMS2, P_AMS3, 0,
+	};
+	return peripheral_request_list(pins, "async");
 }
 
 #ifdef CONFIG_BFIN_SDH

index 65fb81a..cb9ee86 100644
@@ -7,10 +7,12 @@
  */
 
 #include <common.h>
-#include <netdev.h>
 #include <config.h>
 #include <command.h>
+#include <netdev.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
 #include <asm/sdh.h>
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -24,53 +26,13 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-	/* Port H: PH8 - PH13 == A4 - A9
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* configure GPIO 				*
-	* set port H function enable register		*
-	*  configure PH8-PH13 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTH_FER(0x3F03);
-
-	/************************************************
-	* set port H MUX to configure PH8-PH13		*
-	*  1st Function (MUX = 00) (bits 16-27 == 0)	*
-	*  Set to address signals A4-A9 		*
-	*************************************************/
-	bfin_write_PORTH_MUX(0);
-
-	/************************************************
-	* set port H direction register			*
-	*  enable PH8-PH13 as outputs			*
-	*************************************************/
-	bfin_write_PORTH_DIR_SET(0x3F00);
-
-	/* Port I: PI0 - PH14 == A10 - A24
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* set port I function enable register		*
-	*  configure PI0-PI14 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTI_FER(0x7fff);
-
-	/**************************************************
-	* set PORT I MUX to configure PI14-PI0 as	  *
-	* 1st Function (MUX=00) - address signals A10-A24 *
-	***************************************************/
-	bfin_write_PORTI_MUX(0);
-
-	/****************************************
-	* set PORT I direction register		*
-	*  enable PI0 - PI14 as outputs		*
-	*****************************************/
-	bfin_write_PORTI_DIR_SET(0x7fff);
-
-	return 0;
+	/* Set async addr lines as peripheral */
+	const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+		P_A21, P_A22, P_A23, P_A24, 0
+	};
+	return peripheral_request_list(pins, "async");
 }
 
 #ifdef CONFIG_SMC911X

@@ -96,9 +58,7 @@ void board_musb_init(void)
 	 * be low for device mode and high for host mode.  We set it high
 	 * here because we are in host mode.
 	 */
-	bfin_write_PORTE_FER(bfin_read_PORTE_FER() & ~PE7);
-	bfin_write_PORTE_DIR_SET(PE7);
-	bfin_write_PORTE_SET(PE7);
-	SSYNC();
+	gpio_request(GPIO_PE7, "musb-vbus");
+	gpio_direction_output(GPIO_PE7, 1);
 }
 #endif

index 10b08e2..af3d58b 100644
@@ -11,6 +11,8 @@
 #include <config.h>
 #include <malloc.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
 #include <i2c.h>
 #include <linux/types.h>

@@ -173,22 +175,21 @@ void Init_DMA(void *dst)
 
 void Init_Ports(void)
 {
-	*pPORTF_MUX = 0x00000000;
-	*pPORTF_FER |= 0xFFFF; /* PPI0..15 */
-
-	*pPORTG_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
-	*pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4; /* CLK, FS1, FS2, PPI16..17  */
-
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
 #if !defined(CONFIG_VIDEO_RGB666)
-	*pPORTD_MUX &= ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK | PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
-	*pPORTD_MUX |= (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 | PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
-	*pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5; /* PPI18..23  */
+		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+		P_PPI0_D23,
 #endif
+		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
 
-	*pPORTE_FER &= ~PE3; /* DISP */
-	*pPORTE_DIR_SET = PE3;
-	*pPORTE_SET  = PE3;
-
+	gpio_request(GPIO_PE3, "lcd-disp");
+	gpio_direction_output(GPIO_PE3, 1);
 }
 
 void EnableDMA(void)

index a911880..211cf24 100644
@@ -12,6 +12,7 @@
 #include <net.h>
 #include <netdev.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
 #include <asm/net.h>
 #include <asm/mach-common/bits/otp.h>
 

@@ -75,9 +76,7 @@ void board_musb_init(void)
 	/*
 	 * BF527 EZ-KITs require PG13 to be high for HOST mode
 	 */
-	bfin_write_PORTG_FER(bfin_read_PORTG_FER() & ~PG13);
-	bfin_write_PORTGIO_DIR(bfin_read_PORTGIO_DIR() | PG13);
-	bfin_write_PORTGIO_SET(PG13);
-	SSYNC();
+	gpio_request(GPIO_PG13, "musb-vbus");
+	gpio_direction_output(GPIO_PG13, 1);
 }
 #endif

index 8f6ea23..891070b 100644
@@ -11,6 +11,7 @@
 #include <config.h>
 #include <malloc.h>
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
 #include <spi.h>
 #include <linux/types.h>

@@ -171,13 +172,11 @@ void DisablePPI(void)
 
 void Init_Ports(void)
 {
-	*pPORTF_MUX &= ~PORT_x_MUX_0_MASK;
-	*pPORTF_MUX |= PORT_x_MUX_0_FUNC_1;
-	*pPORTF_FER |= PF0 | PF1 | PF2 | PF3 | PF4 | PF5 | PF6 | PF7;
-
-	*pPORTG_MUX &= ~PORT_x_MUX_1_MASK;
-	*pPORTG_MUX |= PORT_x_MUX_1_FUNC_1;
-	*pPORTG_FER |= PG5;
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
 }
 
 void Init_PPI(void)

index 3627586..90ce4c3 100644
@@ -11,6 +11,7 @@
 #include <command.h>
 #include <netdev.h>
 #include <asm/blackfin.h>
+#include <asm/portmux.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -23,53 +24,13 @@ int checkboard(void)
 
 int board_early_init_f(void)
 {
-	/* Port H: PH8 - PH13 == A4 - A9
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* configure GPIO 				*
-	* set port H function enable register		*
-	*  configure PH8-PH13 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTH_FER(0x3F03);
-
-	/************************************************
-	* set port H MUX to configure PH8-PH13		*
-	*  1st Function (MUX = 00) (bits 16-27 == 0)	*
-	*  Set to address signals A4-A9 		*
-	*************************************************/
-	bfin_write_PORTH_MUX(0);
-
-	/************************************************
-	* set port H direction register			*
-	*  enable PH8-PH13 as outputs			*
-	*************************************************/
-	bfin_write_PORTH_DIR_SET(0x3F00);
-
-	/* Port I: PI0 - PH14 == A10 - A24
-	 * address lines of the parallel asynchronous memory interface
-	 */
-
-	/************************************************
-	* set port I function enable register		*
-	*  configure PI0-PI14 as peripheral (not GPIO) 	*
-	*************************************************/
-	bfin_write_PORTI_FER(0x7fff);
-
-	/**************************************************
-	* set PORT I MUX to configure PI14-PI0 as	  *
-	* 1st Function (MUX=00) - address signals A10-A24 *
-	***************************************************/
-	bfin_write_PORTI_MUX(0);
-
-	/****************************************
-	* set PORT I direction register		*
-	*  enable PI0 - PI14 as outputs		*
-	*****************************************/
-	bfin_write_PORTI_DIR_SET(0x7fff);
-
-	return 0;
+	/* Set async addr lines as peripheral */
+	const unsigned short pins[] = {
+		P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+		P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20,
+		P_A21, P_A22, P_A23, P_A24, 0
+	};
+	return peripheral_request_list(pins, "async");
 }
 
 int board_eth_init(bd_t *bis)

index 4097f09..d43f5a1 100644
@@ -11,6 +11,8 @@
 #include <config.h>
 #include <malloc.h>
 #include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/portmux.h>
 #include <asm/mach-common/bits/dma.h>
 #include <i2c.h>
 #include <linux/types.h>

@@ -174,28 +176,21 @@ void Init_DMA(void *dst)
 
 void Init_Ports(void)
 {
-	*pPORTF_MUX = 0x00000000;
-	*pPORTF_FER |= 0xFFFF;	/* PPI0..15 */
-
-	*pPORTG_MUX &=
-	    ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
-	      PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK);
-	*pPORTG_FER |= PG0 | PG1 | PG2 | PG3 | PG4;	/* CLK, FS1, FS2, PPI16..17  */
-
+	const unsigned short pins[] = {
+		P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3, P_PPI0_D4,
+		P_PPI0_D5, P_PPI0_D6, P_PPI0_D7, P_PPI0_D8, P_PPI0_D9,
+		P_PPI0_D10, P_PPI0_D11, P_PPI0_D12, P_PPI0_D13, P_PPI0_D14,
+		P_PPI0_D15, P_PPI0_D16, P_PPI0_D17,
 #if !defined(CONFIG_VIDEO_RGB666)
-	*pPORTD_MUX &=
-	    ~(PORT_x_MUX_0_MASK | PORT_x_MUX_1_MASK | PORT_x_MUX_2_MASK |
-	      PORT_x_MUX_3_MASK | PORT_x_MUX_4_MASK | PORT_x_MUX_5_MASK);
-	*pPORTD_MUX |=
-	    (PORT_x_MUX_0_FUNC_4 | PORT_x_MUX_1_FUNC_4 | PORT_x_MUX_2_FUNC_4 |
-	     PORT_x_MUX_3_FUNC_4 | PORT_x_MUX_4_FUNC_4 | PORT_x_MUX_5_FUNC_4);
-	*pPORTD_FER |= PD0 | PD1 | PD2 | PD3 | PD4 | PD5;	/* PPI18..23  */
+		P_PPI0_D18, P_PPI0_D19, P_PPI0_D20, P_PPI0_D21, P_PPI0_D22,
+		P_PPI0_D23,
 #endif
+		P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2, 0,
+	};
+	peripheral_request_list(pins, "lcd");
 
-	*pPORTE_FER &= ~PE3;	/* DISP */
-	*pPORTE_DIR_SET = PE3;
-	*pPORTE_SET = PE3;
-
+	gpio_request(GPIO_PE3, "lcd-disp");
+	gpio_direction_output(GPIO_PE3, 1);
 }
 
 void EnableDMA(void)

index 3fd34b3..48f793a 100644
@@ -75,7 +75,15 @@ extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
  * regions can only be accessed via DMA, so if the address in question is in
  * that region, make sure we attempt to DMA indirectly.
  */
-# define addr_bfin_on_chip_mem(addr) (((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+# ifdef __ADSPBF561__
+  /* Core B regions all need dma from Core A */
+#  define addr_bfin_on_chip_mem(addr) \
+	((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
+	 (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
+# else
+#  define addr_bfin_on_chip_mem(addr) \
+	(((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
+# endif
 
 # include <asm/system.h>
 

index 7d20b66..6eec1c9 100644
@@ -137,8 +137,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index ecda216..82396d0 100644
@@ -134,8 +134,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index 7800c32..07e4ce8 100644
@@ -138,8 +138,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index c80ddca..37a7059 100644
@@ -136,8 +136,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 

index 2ec9c42..02c8bc3 100644
@@ -180,8 +180,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 

index cf40d06..8daebc8 100644
@@ -155,8 +155,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 
 
 /*

index cba4ac0..3592862 100644
@@ -137,8 +137,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index 59e0565..1c14b6b 100644
@@ -134,8 +134,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index f9c9711..60cca0c 100644
@@ -140,8 +140,6 @@
  */
 #define CONFIG_BFIN_TWI_I2C	1
 #define CONFIG_HARD_I2C		1
-#define CONFIG_SYS_I2C_SPEED	50000
-#define CONFIG_SYS_I2C_SLAVE	0
 
 
 /*

index 1e3fdef..036bfe4 100644
@@ -151,8 +151,6 @@
 	} while (0)
 #define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */
 
-#define CONFIG_SYS_I2C_SPEED		50000
-#define CONFIG_SYS_I2C_SLAVE		0
 #endif
 
 

index 82daeb1..57a7309 100644
@@ -252,6 +252,18 @@
 #endif
 
 /*
+ * I2C Settings
+ */
+#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
+# ifndef CONFIG_SYS_I2C_SPEED
+#  define CONFIG_SYS_I2C_SPEED 50000
+# endif
+# ifndef CONFIG_SYS_I2C_SLAVE
+#  define CONFIG_SYS_I2C_SLAVE 0
+# endif
+#endif
+
+/*
  * Misc Settings
  */
 #define CONFIG_BFIN_SPI_GPIO_CS /* Only matters if BFIN_SPI is enabled */