x86: Various Patches

index 684cdb8..93f910b 100644
@@ -431,15 +431,30 @@ void hang (void)
 	for (;;);
 }
 
-unsigned long do_go_exec (ulong (*entry)(int, char *[]), int argc, char * const argv[])
+unsigned long do_go_exec (ulong (*entry)(int, char * const []), int argc, char * const argv[])
 {
+	unsigned long ret = 0;
+	char **argv_tmp;
+
 	/*
-	 * x86 does not use a dedicated register to pass the pointer
-	 * to the global_data
+	 * x86 does not use a dedicated register to pass the pointer to
+	 * the global_data, so it is instead passed as argv[-1]. By using
+	 * argv[-1], the called 'Application' can use the contents of
+	 * argv natively. However, to safely use argv[-1] a new copy of
+	 * argv is needed with the extra element
 	 */
-	argv[-1] = (char *)gd;
+	argv_tmp = malloc(sizeof(char *) * (argc + 1));
+
+	if (argv_tmp) {
+		argv_tmp[0] = (char *)gd;
+
+		memcpy(&argv_tmp[1], argv, (size_t)(sizeof(char *) * argc));
+
+		ret = (entry) (argc, &argv_tmp[1]);
+		free(argv_tmp);
+	}
 
-	return (entry) (argc, argv);
+	return ret;
 }
 
 void setup_pcat_compatibility(void)

index fbe73f1..fd6a58c 100644
@@ -35,7 +35,7 @@ static void print_num(const char *, ulong);
 static void print_eth(int idx);
 #endif
 
-#ifndef CONFIG_ARM	/* PowerPC and other */
+#if (!defined(CONFIG_ARM) && !defined(CONFIG_X86))
 static void print_lnum(const char *, u64);
 #endif
 

@@ -348,6 +348,45 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	return 0;
 }
 
+#elif defined(CONFIG_X86)
+
+static void print_str(const char *, const char *);
+
+int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int i;
+	bd_t *bd = gd->bd;
+	char buf[32];
+
+	print_num ("env_t",		(ulong)bd->bi_env);
+	print_num ("boot_params",	(ulong)bd->bi_boot_params);
+	print_num ("bi_memstart",	bd->bi_memstart);
+	print_num ("bi_memsize",	bd->bi_memsize);
+	print_num ("bi_flashstart",	bd->bi_flashstart);
+	print_num ("bi_flashsize",	bd->bi_flashsize);
+	print_num ("bi_flashoffset",	bd->bi_flashoffset);
+	print_num ("bi_sramstart",	bd->bi_sramstart);
+	print_num ("bi_sramsize",	bd->bi_sramsize);
+	print_num ("bi_bootflags",	bd->bi_bootflags);
+	print_str ("cpufreq",		strmhz(buf, bd->bi_intfreq));
+	print_str ("busfreq",		strmhz(buf, bd->bi_busfreq));
+
+	for (i=0; i<CONFIG_NR_DRAM_BANKS; ++i) {
+		print_num("DRAM bank",	i);
+		print_num("-> start",	bd->bi_dram[i].start);
+		print_num("-> size",	bd->bi_dram[i].size);
+	}
+
+#if defined(CONFIG_CMD_NET)
+	print_eth(0);
+	printf ("ip_addr     = %pI4\n", &bd->bi_ip_addr);
+	print_str ("ethspeed",	    strmhz(buf, bd->bi_ethspeed));
+#endif
+	printf ("baudrate    = %d bps\n", bd->bi_baudrate);
+
+	return 0;
+}
+
 #else
  #error "a case for this architecture does not exist!"
 #endif

@@ -372,14 +411,17 @@ static void print_eth(int idx)
 }
 #endif
 
-#ifndef CONFIG_ARM
+#if (!defined(CONFIG_ARM) && !defined(CONFIG_X86))
 static void print_lnum(const char *name, u64 value)
 {
 	printf ("%-12s= 0x%.8llX\n", name, value);
 }
 #endif
 
-#if defined(CONFIG_PPC) || defined(CONFIG_M68K) || defined(CONFIG_BLACKFIN)
+#if defined(CONFIG_PPC) || \
+    defined(CONFIG_M68K) || \
+    defined(CONFIG_BLACKFIN) || \
+    defined(CONFIG_X86)
 static void print_str(const char *name, const char *str)
 {
 	printf ("%-12s= %6s MHz\n", name, str);

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deleted file mode 100644
index 2e7a7e1..0000000

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index 049c44e..1952de7 100644
@@ -21,4 +21,6 @@
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
 
+#define CONFIG_RELOC_FIXUP_WORKS
+
 #endif

index 361fe61..04321e1 100644
@@ -29,8 +29,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_RELOC_FIXUP_WORKS
-
 /*
  * Stuff still to be dealt with -
  */

index 89fe015..f279b43 100644
@@ -248,7 +248,8 @@ void boot_zimage(void *setup_base)
 int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 {
 	void *base_ptr;
-	void *bzImage_addr;
+	void *bzImage_addr = NULL;
+	char *s;
 	ulong bzImage_size = 0;
 
 	disable_interrupts();

@@ -256,10 +257,17 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	/* Setup board for maximum PC/AT Compatibility */
 	setup_pcat_compatibility();
 
-	/* argv[1] holds the address of the bzImage */
-	bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	if (argc >= 2) {
+		/* argv[1] holds the address of the bzImage */
+		bzImage_addr = (void *)simple_strtoul(argv[1], NULL, 16);
+	} else {
+		s = getenv("fileaddr");
+		if (s)
+			bzImage_addr = (void *)simple_strtoul(s, NULL, 16);
+	}
 
-	if (argc == 3)
+	if (argc >= 3)
+		/* argv[2] holds the size of the bzImage */
 		bzImage_size = simple_strtoul(argv[2], NULL, 16);
 
 	/* Lets look for*/

@@ -282,7 +290,7 @@ int do_zboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 }
 
 U_BOOT_CMD(
-	zboot, 3, 0,	do_zboot,
+	zboot, 2, 0,	do_zboot,
 	"Boot bzImage",
 	""
 );

index bd6aced..ae40384 100644
@@ -37,6 +37,61 @@
 #include <command.h>
 #include <asm/interrupt.h>
 
+/* Constructor for a conventional segment GDT (or LDT) entry */
+/* This is a macro so it can be used in initializers */
+#define GDT_ENTRY(flags, base, limit)			\
+	((((base)  & 0xff000000ULL) << (56-24)) |	\
+	 (((flags) & 0x0000f0ffULL) << 40) |		\
+	 (((limit) & 0x000f0000ULL) << (48-16)) |	\
+	 (((base)  & 0x00ffffffULL) << 16) |		\
+	 (((limit) & 0x0000ffffULL)))
+
+/* Simple and small GDT entries for booting only */
+
+#define GDT_ENTRY_32BIT_CS	2
+#define GDT_ENTRY_32BIT_DS	(GDT_ENTRY_32BIT_CS + 1)
+#define GDT_ENTRY_16BIT_CS	(GDT_ENTRY_32BIT_DS + 1)
+#define GDT_ENTRY_16BIT_DS	(GDT_ENTRY_16BIT_CS + 1)
+
+/*
+ * Set up the GDT
+ */
+
+struct gdt_ptr {
+	u16 len;
+	u32 ptr;
+} __attribute__((packed));
+
+static void reload_gdt(void)
+{
+	/* There are machines which are known to not boot with the GDT
+	   being 8-byte unaligned.  Intel recommends 16 byte alignment. */
+	static const u64 boot_gdt[] __attribute__((aligned(16))) = {
+		/* CS: code, read/execute, 4 GB, base 0 */
+		[GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff),
+		/* DS: data, read/write, 4 GB, base 0 */
+		[GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff),
+		/* 16-bit CS: code, read/execute, 64 kB, base 0 */
+		[GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x109b, 0, 0x0ffff),
+		/* 16-bit DS: data, read/write, 64 kB, base 0 */
+		[GDT_ENTRY_16BIT_DS] = GDT_ENTRY(0x1093, 0, 0x0ffff),
+	};
+	static struct gdt_ptr gdt;
+
+	gdt.len = sizeof(boot_gdt)-1;
+	gdt.ptr = (u32)&boot_gdt;
+
+	asm volatile("lgdtl %0\n" \
+		     "movl $((2+1)*8), %%ecx\n" \
+		     "movl %%ecx, %%ds\n" \
+		     "movl %%ecx, %%es\n" \
+		     "movl %%ecx, %%fs\n" \
+		     "movl %%ecx, %%gs\n" \
+		     "movl %%ecx, %%ss" \
+		     : : "m" (gdt) : "ecx");
+}
+
+
 int cpu_init_f(void)
 {
 	/* initialize FPU, reset EM, set MP and NE */

@@ -51,6 +106,8 @@ int cpu_init_f(void)
 
 int cpu_init_r(void)
 {
+	reload_gdt();
+
 	/* Initialize core interrupt and exception functionality of CPU */
 	cpu_init_interrupts ();
 	return 0;

index 519bfd8..7acd471 100644
@@ -41,7 +41,8 @@ volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
 
 void init_sc520(void)
 {
-	/* Set the UARTxCTL register at it's slower,
+	/*
+	 * Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
 	 */
 	writeb(0x07, &sc520_mmcr->uart1ctl);

@@ -50,25 +51,30 @@ void init_sc520(void)
 	/* first set the timer pin mapping */
 	writeb(0x72, &sc520_mmcr->clksel);	/* no clock frequency selected, use 1.1892MHz */
 
-	/* enable PCI bus arbitrer */
-	writeb(0x02, &sc520_mmcr->sysarbctl);	/* enable concurrent mode */
+	/* enable PCI bus arbiter (concurrent mode) */
+	writeb(0x02, &sc520_mmcr->sysarbctl);
 
-	writeb(0x1f, &sc520_mmcr->sysarbmenb);	/* enable external grants */
-	writeb(0x04, &sc520_mmcr->hbctl);	/* enable posted-writes */
+	/* enable external grants */
+	writeb(0x1f, &sc520_mmcr->sysarbmenb);
+
+	/* enable posted-writes */
+	writeb(0x04, &sc520_mmcr->hbctl);
 
 	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		writeb(0x02, &sc520_mmcr->cpuctl);	/* set it to 133 MHz and write back */
+		/* set it to 133 MHz and write back */
+		writeb(0x02, &sc520_mmcr->cpuctl);
 		gd->cpu_clk = 133000000;
 		printf("## CPU Speed set to 133MHz\n");
 	} else {
-		writeb(0x01, &sc520_mmcr->cpuctl);	/* set it to 100 MHz and write back */
+		/* set it to 100 MHz and write back */
+		writeb(0x01, &sc520_mmcr->cpuctl);
 		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
 
 
 	/* wait at least one millisecond */
-	asm("movl	$0x2000,%%ecx\n"
+	asm("movl	$0x2000, %%ecx\n"
 	    "0:		pushl %%ecx\n"
 	    "popl	%%ecx\n"
 	    "loop 0b\n": : : "ecx");

@@ -107,15 +113,15 @@ unsigned long init_sc520_dram(void)
 
 	/* set SDRAM speed here */
 
-	refresh_rate/=78;
-	if (refresh_rate<=1) {
-		val = 0;  /* 7.8us */
-	} else if (refresh_rate==2) {
-		val = 1;  /* 15.6us */
-	} else if (refresh_rate==3 || refresh_rate==4) {
-		val = 2;  /* 31.2us */
+	refresh_rate /= 78;
+	if (refresh_rate <= 1) {
+		val = 0;	/* 7.8us */
+	} else if (refresh_rate == 2) {
+		val = 1;	/* 15.6us */
+	} else if (refresh_rate == 3 || refresh_rate == 4) {
+		val = 2;	/* 31.2us */
 	} else {
-		val = 3;  /* 62.4us */
+		val = 3;	/* 62.4us */
 	}
 
 	tmp = (readb(&sc520_mmcr->drcctl) & 0xcf) | (val<<4);

@@ -124,9 +130,9 @@ unsigned long init_sc520_dram(void)
 	val = readb(&sc520_mmcr->drctmctl) & 0xf0;
 
 	if (cas_precharge_delay==3) {
-		val |= 0x04;   /* 3T */
+		val |= 0x04;	/* 3T */
 	} else if (cas_precharge_delay==4) {
-		val |= 0x08;   /* 4T */
+		val |= 0x08;	/* 4T */
 	} else if (cas_precharge_delay>4) {
 		val |= 0x0c;
 	}

@@ -139,8 +145,10 @@ unsigned long init_sc520_dram(void)
 	writeb(val, &c520_mmcr->drctmctl);
 #endif
 
-	/* We read-back the configuration of the dram
-	 * controller that the assembly code wrote */
+	/*
+	 * We read-back the configuration of the dram
+	 * controller that the assembly code wrote
+	 */
 	dram_ctrl = readl(&sc520_mmcr->drcbendadr);
 
 	bd->bi_dram[0].start = 0;

@@ -148,7 +156,6 @@ unsigned long init_sc520_dram(void)
 		/* bank 0 enabled */
 		dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
 		bd->bi_dram[0].size = bd->bi_dram[1].start;
-
 	} else {
 		bd->bi_dram[0].size = 0;
 		bd->bi_dram[1].start = bd->bi_dram[0].start;

@@ -179,11 +186,6 @@ unsigned long init_sc520_dram(void)
 	} else {
 		bd->bi_dram[3].size = 0;
 	}
-
-
-#if 0
-	printf("Configured %d bytes of dram\n", dram_present);
-#endif
 	gd->ram_size = dram_present;
 
 	return dram_present;

index 7f0e257..700a31e 100644
@@ -204,10 +204,18 @@ void setup_pcat_compatibility()
 	 */
 	writew(0x0000,&sc520_mmcr->intpinpol);
 
-	/* Set PIT 0 -> IRQ0, RTC -> IRQ8, FP error -> IRQ13 */
+	/*
+	 * PIT 0 -> IRQ0
+	 * RTC -> IRQ8
+	 * FP error -> IRQ13
+	 * UART1 -> IRQ4
+	 * UART2 -> IRQ3
+	 */
 	writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
 	writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
 	writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
+	writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
+	writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
 
 	/* Disable all other interrupt sources */
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);

@@ -215,11 +223,6 @@ void setup_pcat_compatibility()
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[0]);	/* disable PCI INT A */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[1]);	/* disable PCI INT B */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[2]);	/* disable PCI INT C */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pci_int_map[3]);	/* disable PCI INT D */
-	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->dmabcintmap);		/* disable DMA INT */
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
 	writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);

index ac4eb6a..155034f 100644
@@ -31,6 +31,12 @@
 #include <command.h>
 #include <rtc.h>
 
+#ifdef __I386__
+#include <asm/io.h>
+#define in8(p) inb(p)
+#define out8(p,v) outb(v,p)
+#endif
+
 #if defined(CONFIG_CMD_DATE)
 
 static uchar rtc_read  (uchar reg);

index 04321e1..ca130c3 100644
@@ -33,6 +33,7 @@
  * Stuff still to be dealt with -
  */
 #define CONFIG_RTC_MC146818
+#define CONFIG_SYS_ISA_IO_BASE_ADDRESS	0
 
 /*
  * High Level Configuration Options

@@ -92,6 +93,7 @@
 #define CONFIG_CMD_BDI		/* bdinfo			*/
 #define CONFIG_CMD_BOOTD	/* bootd			*/
 #define CONFIG_CMD_CONSOLE	/* coninfo			*/
+#define CONFIG_CMD_DATE
 #define CONFIG_CMD_ECHO		/* echo arguments		*/
 #define CONFIG_CMD_FLASH	/* flinfo, erase, protect	*/
 #define CONFIG_CMD_FPGA		/* FPGA configuration Support	*/