those series patches for add ben nanonote board
Subsystems (4)
v4 cover those series patches for add ben nanonote board
Hi Wolfgang
those patches are for add xburst jz4740 and Ben NanoNote(named qi_lb60) to U-Boot
some info about xburst jz4740:
the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box,
this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by USB(by using 'xbboot' or 'usbboot'[1]).
which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand.
in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :)
BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :)
for more info about Ingenic Xburst JZ4740
http://www.ingenic.cn/eng/default.aspx
http://www.linux-mips.org/wiki/Ingenic
====
FIXED in [PATCH v3]
1. describe what Jz4740 SoC
2. remove the ENDIANNESS in config.mk
3. don't breaks the 80-charcter-wide rule
4. get rid of #if 0
5. use proper I/O accessors to access registers.
6. remove C++ comments, cleanup code style.
FIXED in [PATCH v4]
1. add Entry to MAINTAINERS and boards.cfg
2. add ben nanonote(qi_lb60) to Makefile
3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALL mips_el
PATCH v4 1/7 those files are jz4740 base files
Signed-off-by Xiangfu Liu <[email protected]>
--- arch/mips/cpu/xburst/Makefile | 50 +++ arch/mips/cpu/xburst/config.mk | 33 ++ arch/mips/cpu/xburst/cpu.c | 160 ++++++++ arch/mips/cpu/xburst/jz4740.c | 266 ++++++++++++ arch/mips/cpu/xburst/jz_serial.c | 128 ++++++ arch/mips/cpu/xburst/start.S | 164 ++++++++ arch/mips/cpu/xburst/start_spl.S | 63 +++ arch/mips/cpu/xburst/timer.c | 172 ++++++++ arch/mips/cpu/xburst/usbboot.S | 841 ++++++++++++++++++++++++++++++++++++++ 9 files changed, 1877 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cpu/xburst/Makefile create mode 100644 arch/mips/cpu/xburst/config.mk create mode 100644 arch/mips/cpu/xburst/cpu.c create mode 100644 arch/mips/cpu/xburst/jz4740.c create mode 100644 arch/mips/cpu/xburst/jz_serial.c create mode 100644 arch/mips/cpu/xburst/start.S create mode 100644 arch/mips/cpu/xburst/start_spl.S create mode 100644 arch/mips/cpu/xburst/timer.c create mode 100644 arch/mips/cpu/xburst/usbboot.S
arch/mips/cpu/xburst/Makefile new file +50 -0
@@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +SOBJS-y = +COBJS-y = cpu.o timer.o jz_serial.o + +COBJS-$(CONFIG_JZ4740) += jz4740.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
arch/mips/cpu/xburst/config.mk new file +33 -0
@@ -0,0 +1,33 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, <[email protected]> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2) +MIPSFLAGS:=$(shell \ +if [ "$v" -lt "14" ]; then \ + echo "-mcpu=4kc"; \ +else \ + echo "-march=4kc -mtune=4kc"; \ +fi) + +MIPSFLAGS += -mabicalls -mips32 + +PLATFORM_CPPFLAGS += $(MIPSFLAGS)
arch/mips/cpu/xburst/cpu.c new file +160 -0
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arch/mips/cpu/xburst/jz4740.c new file +266 -0
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arch/mips/cpu/xburst/jz_serial.c new file +128 -0
128 lines not on this page · raw message
arch/mips/cpu/xburst/start.S new file +164 -0
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arch/mips/cpu/xburst/start_spl.S new file +63 -0
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arch/mips/cpu/xburst/timer.c new file +172 -0
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arch/mips/cpu/xburst/usbboot.S new file +841 -0
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Signature · 1 line
1.7.0.4
PATCH v4 2/7 this is jz4740 head file
Signed-off-by Xiangfu Liu <[email protected]>
--- arch/mips/include/asm/jz4740.h | 1380 ++++++++++++++++++++++++++++++++++++++++ 1 files changed, 1380 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/jz4740.h
arch/mips/include/asm/jz4740.h new file +1380 -0
@@ -0,0 +1,1380 @@ +/* +* Include file for Ingenic Semiconductor's JZ4740 CPU. +*/ +#ifndef __JZ4740_H__ +#define __JZ4740_H__ + +#include <asm/addrspace.h> +#include <asm/cacheops.h> + +/* Boot ROM Specification */ +/* NOR Boot config */ +#define JZ4740_NORBOOT_8BIT 0x00000000/* 8-bit data bus flash */ +#define JZ4740_NORBOOT_16BIT 0x10101010/* 16-bit data bus flash */ +#define JZ4740_NORBOOT_32BIT 0x20202020/* 32-bit data bus flash */ +/* NAND Boot config */ +#define JZ4740_NANDBOOT_B8R3 0xffffffff/* 8-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B8R2 0xf0f0f0f0/* 8-bit bus & 2 row cycles */ +#define JZ4740_NANDBOOT_B16R3 0x0f0f0f0f/* 16-bit bus & 3 row cycles */ +#define JZ4740_NANDBOOT_B16R2 0x00000000/* 16-bit bus & 2 row cycles */ + +/* Register Definitions */ +#define CPM_BASE 0xB0000000 +#define INTC_BASE 0xB0001000 +#define TCU_BASE 0xB0002000 +#define WDT_BASE 0xB0002000 +#define RTC_BASE 0xB0003000 +#define GPIO_BASE 0xB0010000 +#define AIC_BASE 0xB0020000 +#define ICDC_BASE 0xB0020000 +#define MSC_BASE 0xB0021000 +#define UART0_BASE 0xB0030000 +#define I2C_BASE 0xB0042000 +#define SSI_BASE 0xB0043000 +#define SADC_BASE 0xB0070000 +#define EMC_BASE 0xB3010000 +#define DMAC_BASE 0xB3020000 +#define UHC_BASE 0xB3030000 +#define UDC_BASE 0xB3040000 +#define LCD_BASE 0xB3050000 +#define SLCD_BASE 0xB3050000 +#define CIM_BASE 0xB3060000 +#define ETH_BASE 0xB3100000 + +/* +* INTC (Interrupt Controller) +*/ +#define INTC_ISR (INTC_BASE + 0x00) +#define INTC_IMR (INTC_BASE + 0x04) +#define INTC_IMSR (INTC_BASE + 0x08) +#define INTC_IMCR (INTC_BASE + 0x0c) +#define INTC_IPR (INTC_BASE + 0x10) + + +/* 1st-level interrupts */ +#define IRQ_I2C 1 +#define IRQ_UHC 3 +#define IRQ_UART0 9 +#define IRQ_SADC 12 +#define IRQ_MSC 14 +#define IRQ_RTC 15 +#define IRQ_SSI 16 +#define IRQ_CIM 17 +#define IRQ_AIC 18 +#define IRQ_ETH 19 +#define IRQ_DMAC 20 +#define IRQ_TCU2 21 +#define IRQ_TCU1 22 +#define IRQ_TCU0 23 +#define IRQ_UDC 24 +#define IRQ_GPIO3 25 +#define IRQ_GPIO2 26 +#define IRQ_GPIO1 27 +#define IRQ_GPIO0 28 +#define IRQ_IPU 29 +#define IRQ_LCD 30 + +/* 2nd-level interrupts */ +#define IRQ_DMA_0 32/* 32 to 37 for DMAC channel 0 to 5 */ +#define IRQ_GPIO_0 48/* 48 to 175 for GPIO pin 0 to 127 */ + +/* +* RTC +*/ +#define RTC_RCR (RTC_BASE + 0x00)/* RTC Control Register */ +#define RTC_RSR (RTC_BASE + 0x04)/* RTC Second Register */ +#define RTC_RSAR (RTC_BASE + 0x08)/* RTC Second Alarm Register */ +#define RTC_RGR (RTC_BASE + 0x0c)/* RTC Regulator Register */ + +#define RTC_HCR (RTC_BASE + 0x20)/* Hibernate Control Register */ +#define RTC_HWFCR (RTC_BASE + 0x24)/* Hibernate Wakeup Filter Counter Reg */ +#define RTC_HRCR (RTC_BASE + 0x28)/* Hibernate Reset Counter Register */ +#define RTC_HWCR (RTC_BASE + 0x2c)/* Hibernate Wakeup Control Register */ +#define RTC_HWRSR (RTC_BASE + 0x30)/* Hibernate Wakeup Status Register */ +#define RTC_HSPR (RTC_BASE + 0x34)/* Hibernate Scratch Pattern Register */ + + +/* RTC Control Register */ +#define RTC_RCR_WRDY (1 << 7)/* Write Ready Flag */ +#define RTC_RCR_HZ (1 << 6)/* 1Hz Flag */ +#define RTC_RCR_HZIE (1 << 5)/* 1Hz Interrupt Enable */ +#define RTC_RCR_AF (1 << 4)/* Alarm Flag */ +#define RTC_RCR_AIE (1 << 3)/* Alarm Interrupt Enable */ +#define RTC_RCR_AE (1 << 2)/* Alarm Enable */ +#define RTC_RCR_RTCE (1 << 0)/* RTC Enable */ + +/* RTC Regulator Register */ +#define RTC_RGR_LOCK (1 << 31)/* Lock Bit */ +#define RTC_RGR_ADJC_BIT 16 +#define RTC_RGR_ADJC_MASK (0x3ff << RTC_RGR_ADJC_BIT) +#define RTC_RGR_NC1HZ_BIT 0 +#define RTC_RGR_NC1HZ_MASK (0xffff << RTC_RGR_NC1HZ_BIT) + +/* Hibernate Control Register */ +#define RTC_HCR_PD (1 << 0)/* Power Down */ + +/* Hibernate Wakeup Filter Counter Register */ +#define RTC_HWFCR_BIT 5 +#define RTC_HWFCR_MASK (0x7ff << RTC_HWFCR_BIT) + +/* Hibernate Reset Counter Register */ +#define RTC_HRCR_BIT 5 +#define RTC_HRCR_MASK (0x7f << RTC_HRCR_BIT) + +/* Hibernate Wakeup Control Register */ +#define RTC_HWCR_EALM (1 << 0)/* RTC alarm wakeup enable */ + +/* Hibernate Wakeup Status Register */ +#define RTC_HWRSR_HR (1 << 5)/* Hibernate reset */ +#define RTC_HWRSR_PPR (1 << 4)/* PPR reset */ +#define RTC_HWRSR_PIN (1 << 1)/* Wakeup pin status bit */ +#define RTC_HWRSR_ALM (1 << 0)/* RTC alarm status bit */ + +/* +* CPM (Clock reset and Power control Management) +*/ +#define CPM_CPCCR (CPM_BASE+0x00) +#define CPM_CPPCR (CPM_BASE+0x10) +#define CPM_I2SCDR (CPM_BASE+0x60) +#define CPM_LPCDR (CPM_BASE+0x64) +#define CPM_MSCCDR (CPM_BASE+0x68) +#define CPM_UHCCDR (CPM_BASE+0x6C) + +#define CPM_LCR (CPM_BASE+0x04) +#define CPM_CLKGR (CPM_BASE+0x20) +#define CPM_SCR (CPM_BASE+0x24) + +#define CPM_HCR (CPM_BASE+0x30) +#define CPM_HWFCR (CPM_BASE+0x34) +#define CPM_HRCR (CPM_BASE+0x38) +#define CPM_HWCR (CPM_BASE+0x3c) +#define CPM_HWSR (CPM_BASE+0x40) +#define CPM_HSPR (CPM_BASE+0x44) + +#define CPM_RSR (CPM_BASE+0x08) + +/* Clock Control Register */ +#define CPM_CPCCR_I2CS (1 << 31) +#define CPM_CPCCR_CLKOEN (1 << 30) +#define CPM_CPCCR_UCS (1 << 29) +#define CPM_CPCCR_UDIV_BIT 23 +#define CPM_CPCCR_UDIV_MASK (0x3f << CPM_CPCCR_UDIV_BIT) +#define CPM_CPCCR_CE (1 << 22) +#define CPM_CPCCR_PCS (1 << 21) +#define CPM_CPCCR_LDIV_BIT 16 +#define CPM_CPCCR_LDIV_MASK (0x1f << CPM_CPCCR_LDIV_BIT) +#define CPM_CPCCR_MDIV_BIT 12 +#define CPM_CPCCR_MDIV_MASK (0x0f << CPM_CPCCR_MDIV_BIT) +#define CPM_CPCCR_PDIV_BIT 8 +#define CPM_CPCCR_PDIV_MASK (0x0f << CPM_CPCCR_PDIV_BIT) +#define CPM_CPCCR_HDIV_BIT 4 +#define CPM_CPCCR_HDIV_MASK (0x0f << CPM_CPCCR_HDIV_BIT) +#define CPM_CPCCR_CDIV_BIT 0 +#define CPM_CPCCR_CDIV_MASK (0x0f << CPM_CPCCR_CDIV_BIT) + +/* I2S Clock Divider Register */ +#define CPM_I2SCDR_I2SDIV_BIT 0 +#define CPM_I2SCDR_I2SDIV_MASK (0x1ff << CPM_I2SCDR_I2SDIV_BIT) + +/* LCD Pixel Clock Divider Register */ +#define CPM_LPCDR_PIXDIV_BIT 0 +#define CPM_LPCDR_PIXDIV_MASK (0x1ff << CPM_LPCDR_PIXDIV_BIT) + +/* MSC Clock Divider Register */ +#define CPM_MSCCDR_MSCDIV_BIT 0 +#define CPM_MSCCDR_MSCDIV_MASK (0x1f << CPM_MSCCDR_MSCDIV_BIT) + +/* PLL Control Register */ +#define CPM_CPPCR_PLLM_BIT 23 +#define CPM_CPPCR_PLLM_MASK (0x1ff << CPM_CPPCR_PLLM_BIT) +#define CPM_CPPCR_PLLN_BIT 18 +#define CPM_CPPCR_PLLN_MASK (0x1f << CPM_CPPCR_PLLN_BIT) +#define CPM_CPPCR_PLLOD_BIT 16 +#define CPM_CPPCR_PLLOD_MASK (0x03 << CPM_CPPCR_PLLOD_BIT) +#define CPM_CPPCR_PLLS (1 << 10) +#define CPM_CPPCR_PLLBP (1 << 9) +#define CPM_CPPCR_PLLEN (1 << 8) +#define CPM_CPPCR_PLLST_BIT 0 +#define CPM_CPPCR_PLLST_MASK (0xff << CPM_CPPCR_PLLST_BIT) + +/* Low Power Control Register */ +#define CPM_LCR_DOZE_DUTY_BIT 3 +#define CPM_LCR_DOZE_DUTY_MASK (0x1f << CPM_LCR_DOZE_DUTY_BIT) +#define CPM_LCR_DOZE_ON (1 << 2) +#define CPM_LCR_LPM_BIT 0 +#define CPM_LCR_LPM_MASK (0x3 << CPM_LCR_LPM_BIT) +#define CPM_LCR_LPM_IDLE (0x0 << CPM_LCR_LPM_BIT) +#define CPM_LCR_LPM_SLEEP (0x1 << CPM_LCR_LPM_BIT) + +/* Clock Gate Register */ +#define CPM_CLKGR_UART1 (1 << 15) +#define CPM_CLKGR_UHC (1 << 14) +#define CPM_CLKGR_IPU (1 << 13) +#define CPM_CLKGR_DMAC (1 << 12) +#define CPM_CLKGR_UDC (1 << 11) +#define CPM_CLKGR_LCD (1 << 10) +#define CPM_CLKGR_CIM (1 << 9) +#define CPM_CLKGR_SADC (1 << 8) +#define CPM_CLKGR_MSC (1 << 7) +#define CPM_CLKGR_AIC1 (1 << 6) +#define CPM_CLKGR_AIC2 (1 << 5) +#define CPM_CLKGR_SSI (1 << 4) +#define CPM_CLKGR_I2C (1 << 3) +#define CPM_CLKGR_RTC (1 << 2) +#define CPM_CLKGR_TCU (1 << 1) +#define CPM_CLKGR_UART0 (1 << 0) + +/* Sleep Control Register */ +#define CPM_SCR_O1ST_BIT 8 +#define CPM_SCR_O1ST_MASK (0xff << CPM_SCR_O1ST_BIT) +#define CPM_SCR_UDCPHY_ENABLE (1 << 6) +#define CPM_SCR_USBPHY_DISABLE (1 << 7) +#define CPM_SCR_OSC_ENABLE (1 << 4) + +/* Hibernate Control Register */ +#define CPM_HCR_PD (1 << 0) + +/* Wakeup Filter Counter Register in Hibernate Mode */ +#define CPM_HWFCR_TIME_BIT 0 +#define CPM_HWFCR_TIME_MASK (0x3ff << CPM_HWFCR_TIME_BIT) + +/* Reset Counter Register in Hibernate Mode */ +#define CPM_HRCR_TIME_BIT 0 +#define CPM_HRCR_TIME_MASK (0x7f << CPM_HRCR_TIME_BIT) + +/* Wakeup Control Register in Hibernate Mode */ +#define CPM_HWCR_WLE_LOW (0 << 2) +#define CPM_HWCR_WLE_HIGH (1 << 2) +#define CPM_HWCR_PIN_WAKEUP (1 << 1) +#define CPM_HWCR_RTC_WAKEUP (1 << 0) + +/* Wakeup Status Register in Hibernate Mode */ +#define CPM_HWSR_WSR_PIN (1 << 1) +#define CPM_HWSR_WSR_RTC (1 << 0) + +/* Reset Status Register */ +#define CPM_RSR_HR (1 << 2) +#define CPM_RSR_WR (1 << 1) +#define CPM_RSR_PR (1 << 0) + +/* +* TCU (Timer Counter Unit) +*/ +#define TCU_TSR (TCU_BASE + 0x1C)/* Timer Stop Register */ +#define TCU_TSSR (TCU_BASE + 0x2C)/* Timer Stop Set Register */ +#define TCU_TSCR (TCU_BASE + 0x3C)/* Timer Stop Clear Register */ +#define TCU_TER (TCU_BASE + 0x10)/* Timer Counter Enable Register */ +#define TCU_TESR (TCU_BASE + 0x14)/* Timer Counter Enable Set Register */ +#define TCU_TECR (TCU_BASE + 0x18)/* Timer Counter Enable Clear Register */ +#define TCU_TFR (TCU_BASE + 0x20)/* Timer Flag Register */ +#define TCU_TFSR (TCU_BASE + 0x24)/* Timer Flag Set Register */ +#define TCU_TFCR (TCU_BASE + 0x28)/* Timer Flag Clear Register */ +#define TCU_TMR (TCU_BASE + 0x30)/* Timer Mask Register */ +#define TCU_TMSR (TCU_BASE + 0x34)/* Timer Mask Set Register */ +#define TCU_TMCR (TCU_BASE + 0x38)/* Timer Mask Clear Register */ +#define TCU_TDFR0 (TCU_BASE + 0x40)/* Timer Data Full Register */ +#define TCU_TDHR0 (TCU_BASE + 0x44)/* Timer Data Half Register */ +#define TCU_TCNT0 (TCU_BASE + 0x48)/* Timer Counter Register */ +#define TCU_TCSR0 (TCU_BASE + 0x4C)/* Timer Control Register */ +#define TCU_TDFR1 (TCU_BASE + 0x50) +#define TCU_TDHR1 (TCU_BASE + 0x54) +#define TCU_TCNT1 (TCU_BASE + 0x58) +#define TCU_TCSR1 (TCU_BASE + 0x5C) +#define TCU_TDFR2 (TCU_BASE + 0x60) +#define TCU_TDHR2 (TCU_BASE + 0x64) +#define TCU_TCNT2 (TCU_BASE + 0x68) +#define TCU_TCSR2 (TCU_BASE + 0x6C) +#define TCU_TDFR3 (TCU_BASE + 0x70) +#define TCU_TDHR3 (TCU_BASE + 0x74) +#define TCU_TCNT3 (TCU_BASE + 0x78) +#define TCU_TCSR3 (TCU_BASE + 0x7C) +#define TCU_TDFR4 (TCU_BASE + 0x80) +#define TCU_TDHR4 (TCU_BASE + 0x84) +#define TCU_TCNT4 (TCU_BASE + 0x88) +#define TCU_TCSR4 (TCU_BASE + 0x8C) +#define TCU_TDFR5 (TCU_BASE + 0x90) +#define TCU_TDHR5 (TCU_BASE + 0x94) +#define TCU_TCNT5 (TCU_BASE + 0x98) +#define TCU_TCSR5 (TCU_BASE + 0x9C) + +/* n = 0,1,2,3,4,5 */ +#define TCU_TDFR (n) (TCU_BASE + (0x40 + (n)*0x10))/* Timer Data Full Reg */ +#define TCU_TDHR (n) (TCU_BASE + (0x44 + (n)*0x10))/* Timer Data Half Reg */ +#define TCU_TCNT (n) (TCU_BASE + (0x48 + (n)*0x10))/* Timer Counter Reg */ +#define TCU_TCSR (n) (TCU_BASE + (0x4C + (n)*0x10))/* Timer Control Reg */ + +/* Register definitions */ +#define TCU_TCSR_PWM_SD (1 << 9) +#define TCU_TCSR_PWM_INITL_HIGH (1 << 8) +#define TCU_TCSR_PWM_EN (1 << 7) +#define TCU_TCSR_PRESCALE_BIT 3 +#define TCU_TCSR_PRESCALE_MASK (0x7 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1 (0x0 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE4 (0x1 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE16 (0x2 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE64 (0x3 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE256 (0x4 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_PRESCALE1024 (0x5 << TCU_TCSR_PRESCALE_BIT) +#define TCU_TCSR_EXT_EN (1 << 2) +#define TCU_TCSR_RTC_EN (1 << 1) +#define TCU_TCSR_PCK_EN (1 << 0) + +#define TCU_TER_TCEN5 (1 << 5) +#define TCU_TER_TCEN4 (1 << 4) +#define TCU_TER_TCEN3 (1 << 3) +#define TCU_TER_TCEN2 (1 << 2) +#define TCU_TER_TCEN1 (1 << 1) +#define TCU_TER_TCEN0 (1 << 0) + +#define TCU_TESR_TCST5 (1 << 5) +#define TCU_TESR_TCST4 (1 << 4) +#define TCU_TESR_TCST3 (1 << 3) +#define TCU_TESR_TCST2 (1 << 2) +#define TCU_TESR_TCST1 (1 << 1) +#define TCU_TESR_TCST0 (1 << 0) + +#define TCU_TECR_TCCL5 (1 << 5) +#define TCU_TECR_TCCL4 (1 << 4) +#define TCU_TECR_TCCL3 (1 << 3) +#define TCU_TECR_TCCL2 (1 << 2) +#define TCU_TECR_TCCL1 (1 << 1) +#define TCU_TECR_TCCL0 (1 << 0) + +#define TCU_TFR_HFLAG5 (1 << 21) +#define TCU_TFR_HFLAG4 (1 << 20) +#define TCU_TFR_HFLAG3 (1 << 19) +#define TCU_TFR_HFLAG2 (1 << 18) +#define TCU_TFR_HFLAG1 (1 << 17) +#define TCU_TFR_HFLAG0 (1 << 16) +#define TCU_TFR_FFLAG5 (1 << 5) +#define TCU_TFR_FFLAG4 (1 << 4) +#define TCU_TFR_FFLAG3 (1 << 3) +#define TCU_TFR_FFLAG2 (1 << 2) +#define TCU_TFR_FFLAG1 (1 << 1) +#define TCU_TFR_FFLAG0 (1 << 0) + +#define TCU_TFSR_HFLAG5 (1 << 21) +#define TCU_TFSR_HFLAG4 (1 << 20) +#define TCU_TFSR_HFLAG3 (1 << 19) +#define TCU_TFSR_HFLAG2 (1 << 18) +#define TCU_TFSR_HFLAG1 (1 << 17) +#define TCU_TFSR_HFLAG0 (1 << 16) +#define TCU_TFSR_FFLAG5 (1 << 5) +#define TCU_TFSR_FFLAG4 (1 << 4) +#define TCU_TFSR_FFLAG3 (1 << 3) +#define TCU_TFSR_FFLAG2 (1 << 2) +#define TCU_TFSR_FFLAG1 (1 << 1) +#define TCU_TFSR_FFLAG0 (1 << 0) + +#define TCU_TFCR_HFLAG5 (1 << 21) +#define TCU_TFCR_HFLAG4 (1 << 20) +#define TCU_TFCR_HFLAG3 (1 << 19) +#define TCU_TFCR_HFLAG2 (1 << 18) +#define TCU_TFCR_HFLAG1 (1 << 17) +#define TCU_TFCR_HFLAG0 (1 << 16) +#define TCU_TFCR_FFLAG5 (1 << 5) +#define TCU_TFCR_FFLAG4 (1 << 4) +#define TCU_TFCR_FFLAG3 (1 << 3) +#define TCU_TFCR_FFLAG2 (1 << 2) +#define TCU_TFCR_FFLAG1 (1 << 1) +#define TCU_TFCR_FFLAG0 (1 << 0) + +#define TCU_TMR_HMASK5 (1 << 21) +#define TCU_TMR_HMASK4 (1 << 20) +#define TCU_TMR_HMASK3 (1 << 19) +#define TCU_TMR_HMASK2 (1 << 18) +#define TCU_TMR_HMASK1 (1 << 17) +#define TCU_TMR_HMASK0 (1 << 16) +#define TCU_TMR_FMASK5 (1 << 5) +#define TCU_TMR_FMASK4 (1 << 4) +#define TCU_TMR_FMASK3 (1 << 3) +#define TCU_TMR_FMASK2 (1 << 2) +#define TCU_TMR_FMASK1 (1 << 1) +#define TCU_TMR_FMASK0 (1 << 0) + +#define TCU_TMSR_HMST5 (1 << 21) +#define TCU_TMSR_HMST4 (1 << 20) +#define TCU_TMSR_HMST3 (1 << 19) +#define TCU_TMSR_HMST2 (1 << 18) +#define TCU_TMSR_HMST1 (1 << 17) +#define TCU_TMSR_HMST0 (1 << 16) +#define TCU_TMSR_FMST5 (1 << 5) +#define TCU_TMSR_FMST4 (1 << 4) +#define TCU_TMSR_FMST3 (1 << 3) +#define TCU_TMSR_FMST2 (1 << 2) +#define TCU_TMSR_FMST1 (1 << 1) +#define TCU_TMSR_FMST0 (1 << 0) + +#define TCU_TMCR_HMCL5 (1 << 21) +#define TCU_TMCR_HMCL4 (1 << 20) +#define TCU_TMCR_HMCL3 (1 << 19) +#define TCU_TMCR_HMCL2 (1 << 18) +#define TCU_TMCR_HMCL1 (1 << 17) +#define TCU_TMCR_HMCL0 (1 << 16) +#define TCU_TMCR_FMCL5 (1 << 5) +#define TCU_TMCR_FMCL4 (1 << 4) +#define TCU_TMCR_FMCL3 (1 << 3) +#define TCU_TMCR_FMCL2 (1 << 2) +#define TCU_TMCR_FMCL1 (1 << 1) +#define TCU_TMCR_FMCL0 (1 << 0) + +#define TCU_TSR_WDTS (1 << 16) +#define TCU_TSR_STOP5 (1 << 5) +#define TCU_TSR_STOP4 (1 << 4) +#define TCU_TSR_STOP3 (1 << 3) +#define TCU_TSR_STOP2 (1 << 2) +#define TCU_TSR_STOP1 (1 << 1) +#define TCU_TSR_STOP0 (1 << 0) + +#define TCU_TSSR_WDTSS (1 << 16) +#define TCU_TSSR_STPS5 (1 << 5) +#define TCU_TSSR_STPS4 (1 << 4) +#define TCU_TSSR_STPS3 (1 << 3) +#define TCU_TSSR_STPS2 (1 << 2) +#define TCU_TSSR_STPS1 (1 << 1) +#define TCU_TSSR_STPS0 (1 << 0) + +#define TCU_TSSR_WDTSC (1 << 16) +#define TCU_TSSR_STPC5 (1 << 5) +#define TCU_TSSR_STPC4 (1 << 4) +#define TCU_TSSR_STPC3 (1 << 3) +#define TCU_TSSR_STPC2 (1 << 2) +#define TCU_TSSR_STPC1 (1 << 1) +#define TCU_TSSR_STPC0 (1 << 0) + +/* +* WDT (WatchDog Timer) +*/ +#define WDT_TDR (WDT_BASE + 0x00) +#define WDT_TCER (WDT_BASE + 0x04) +#define WDT_TCNT (WDT_BASE + 0x08) +#define WDT_TCSR (WDT_BASE + 0x0C) + +/* Register definition */ +#define WDT_TCSR_PRESCALE_BIT 3 +#define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) +#define WDT_TCSR_EXT_EN (1 << 2) +#define WDT_TCSR_RTC_EN (1 << 1) +#define WDT_TCSR_PCK_EN (1 << 0) + +#define WDT_TCER_TCEN (1 << 0) + +/* +* GPIO (General-Purpose I/O Ports) +*/ +#define MAX_GPIO_NUM 128 + +/* = 0,1,2,3 */ +#define GPIO_PXPIN (n) (GPIO_BASE + (0x00 + (n)*0x100))/* PIN Level Register */ +#define GPIO_PXDAT (n) (GPIO_BASE + (0x10 + (n)*0x100))/* Port Data Register */ +#define GPIO_PXDATS (n) (GPIO_BASE + (0x14 + (n)*0x100))/* Port Data Set Register */ +#define GPIO_PXDATC (n) (GPIO_BASE + (0x18 + (n)*0x100))/* Port Data Clear Register */ +#define GPIO_PXIM (n) (GPIO_BASE + (0x20 + (n)*0x100))/* Interrupt Mask Register */ +#define GPIO_PXIMS (n) (GPIO_BASE + (0x24 + (n)*0x100))/* Interrupt Mask Set Reg */ +#define GPIO_PXIMC (n) (GPIO_BASE + (0x28 + (n)*0x100))/* Interrupt Mask Clear Reg */ +#define GPIO_PXPE (n) (GPIO_BASE + (0x30 + (n)*0x100))/* Pull Enable Register */ +#define GPIO_PXPES (n) (GPIO_BASE + (0x34 + (n)*0x100))/* Pull Enable Set Reg. */ +#define GPIO_PXPEC (n) (GPIO_BASE + (0x38 + (n)*0x100))/* Pull Enable Clear Reg. */ +#define GPIO_PXFUN (n) (GPIO_BASE + (0x40 + (n)*0x100))/* Function Register */ +#define GPIO_PXFUNS (n) (GPIO_BASE + (0x44 + (n)*0x100))/* Function Set Register */ +#define GPIO_PXFUNC (n) (GPIO_BASE + (0x48 + (n)*0x100))/* Function Clear Register */ +#define GPIO_PXSEL (n) (GPIO_BASE + (0x50 + (n)*0x100))/* Select Register */ +#define GPIO_PXSELS (n) (GPIO_BASE + (0x54 + (n)*0x100))/* Select Set Register */ +#define GPIO_PXSELC (n) (GPIO_BASE + (0x58 + (n)*0x100))/* Select Clear Register */ +#define GPIO_PXDIR (n) (GPIO_BASE + (0x60 + (n)*0x100))/* Direction Register */ +#define GPIO_PXDIRS (n) (GPIO_BASE + (0x64 + (n)*0x100))/* Direction Set Register */ +#define GPIO_PXDIRC (n) (GPIO_BASE + (0x68 + (n)*0x100))/* Direction Clear Register */ +#define GPIO_PXTRG (n) (GPIO_BASE + (0x70 + (n)*0x100))/* Trigger Register */ +#define GPIO_PXTRGS (n) (GPIO_BASE + (0x74 + (n)*0x100))/* Trigger Set Register */ +#define GPIO_PXTRGC (n) (GPIO_BASE + (0x78 + (n)*0x100))/* Trigger Set Register */ +#define GPIO_PXFLG (n) (GPIO_BASE + (0x80 + (n)*0x100))/* Port Flag Register */ +#define GPIO_PXFLGC (n) (GPIO_BASE + (0x14 + (n)*0x100))/* Port Flag clear Register */ + +/* +* UART +*/ +#define IRDA_BASE UART0_BASE +#define UART_BASE UART0_BASE +#define UART_OFF 0x1000 + +/* Register Offset */ +#define OFF_RDR (0x00)/* R 8b H'xx */ +#define OFF_TDR (0x00)/* W 8b H'xx */ +#define OFF_DLLR (0x00)/* RW 8b H'00 */ +#define OFF_DLHR (0x04)/* RW 8b H'00 */ +#define OFF_IER (0x04)/* RW 8b H'00 */ +#define OFF_ISR (0x08)/* R 8b H'01 */ +#define OFF_FCR (0x08)/* W 8b H'00 */ +#define OFF_LCR (0x0C)/* RW 8b H'00 */ +#define OFF_MCR (0x10)/* RW 8b H'00 */ +#define OFF_LSR (0x14)/* R 8b H'00 */ +#define OFF_MSR (0x18)/* R 8b H'00 */ +#define OFF_SPR (0x1C)/* RW 8b H'00 */ +#define OFF_SIRCR (0x20)/* RW 8b H'00, UART0 */ +#define OFF_UMR (0x24)/* RW 8b H'00, UART M Register */ +#define OFF_UACR (0x28)/* RW 8b H'00, UART Add Cycle Register */ + +/* Register Address */ +#define UART0_RDR (UART0_BASE + OFF_RDR) +#define UART0_TDR (UART0_BASE + OFF_TDR) +#define UART0_DLLR (UART0_BASE + OFF_DLLR) +#define UART0_DLHR (UART0_BASE + OFF_DLHR) +#define UART0_IER (UART0_BASE + OFF_IER) +#define UART0_ISR (UART0_BASE + OFF_ISR) +#define UART0_FCR (UART0_BASE + OFF_FCR) +#define UART0_LCR (UART0_BASE + OFF_LCR) +#define UART0_MCR (UART0_BASE + OFF_MCR) +#define UART0_LSR (UART0_BASE + OFF_LSR) +#define UART0_MSR (UART0_BASE + OFF_MSR) +#define UART0_SPR (UART0_BASE + OFF_SPR) +#define UART0_SIRCR (UART0_BASE + OFF_SIRCR) +#define UART0_UMR (UART0_BASE + OFF_UMR) +#define UART0_UACR (UART0_BASE + OFF_UACR) + +/* +* Define macros for UART_IER +* UART Interrupt Enable Register +*/ +#define UART_IER_RIE (1 << 0)/* 0: receive fifo "full" interrupt disable */ +#define UART_IER_TIE (1 << 1)/* 0: transmit fifo "empty" interrupt disable */ +#define UART_IER_RLIE (1 << 2)/* 0: receive line status interrupt disable */ +#define UART_IER_MIE (1 << 3)/* 0: modem status interrupt disable */ +#define UART_IER_RTIE (1 << 4)/* 0: receive timeout interrupt disable */ + +/* +* Define macros for UART_ISR +* UART Interrupt Status Register +*/ +#define UART_ISR_IP (1 << 0)/* 0: interrupt is pending 1: no interrupt */ +#define UART_ISR_IID (7 << 1)/* Source of Interrupt */ +#define UART_ISR_IID_MSI (0 << 1)/* Modem status interrupt */ +#define UART_ISR_IID_THRI (1 << 1)/* Transmitter holding register empty */ +#define UART_ISR_IID_RDI (2 << 1)/* Receiver data interrupt */ +#define UART_ISR_IID_RLSI (3 << 1)/* Receiver line status interrupt */ +#define UART_ISR_FFMS (3 << 6)/* FIFO mode select, set when UART_FCR.FE is set to 1 */ +#define UART_ISR_FFMS_NO_FIFO (0 << 6) +#define UART_ISR_FFMS_FIFO_MODE (3 << 6) + +/* +* Define macros for UART_FCR +* UART FIFO Control Register +*/ +#define UART_FCR_FE (1 << 0)/* 0: non-FIFO mode 1: FIFO mode */ +#define UART_FCR_RFLS (1 << 1)/* write 1 to flush receive FIFO */ +#define UART_FCR_TFLS (1 << 2)/* write 1 to flush transmit FIFO */ +#define UART_FCR_DMS (1 << 3)/* 0: disable DMA mode */ +#define UART_FCR_UUE (1 << 4)/* 0: disable UART */ +#define UART_FCR_RTRG (3 << 6)/* Receive FIFO Data Trigger */ +#define UART_FCR_RTRG_1 (0 << 6) +#define UART_FCR_RTRG_4 (1 << 6) +#define UART_FCR_RTRG_8 (2 << 6) +#define UART_FCR_RTRG_15 (3 << 6) + +/* +* Define macros for UART_LCR +* UART Line Control Register +*/ +#define UART_LCR_WLEN (3 << 0)/* word length */ +#define UART_LCR_WLEN_5 (0 << 0) +#define UART_LCR_WLEN_6 (1 << 0) +#define UART_LCR_WLEN_7 (2 << 0) +#define UART_LCR_WLEN_8 (3 << 0) +#define UART_LCR_STOP (1 << 2)/* 0: 1 stop bit when word length is 5,6,7,8 +1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ +#define UART_LCR_STOP_1 (0 << 2)/* 0: 1 stop bit when word length is 5,6,7,8 +1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ +#define UART_LCR_STOP_2 (1 << 2)/* 0: 1 stop bit when word length is 5,6,7,8 +1: 1.5 stop bits when 5; 2 stop bits when 6,7,8 */ + +#define UART_LCR_PE (1 << 3)/* 0: parity disable */ +#define UART_LCR_PROE (1 << 4)/* 0: even parity 1: odd parity */ +#define UART_LCR_SPAR (1 << 5)/* 0: sticky parity disable */ +#define UART_LCR_SBRK (1 << 6)/* write 0 normal, write 1 send break */ +#define UART_LCR_DLAB (1 << 7)/* 0: access UART_RDR/TDR/IER 1: access UART_DLLR/DLHR */ + +/* +* Define macros for UART_LSR +* UART Line Status Register +*/ +#define UART_LSR_DR (1 << 0)/* 0: receive FIFO is empty 1: receive data is ready */ +#define UART_LSR_ORER (1 << 1)/* 0: no overrun error */ +#define UART_LSR_PER (1 << 2)/* 0: no parity error */ +#define UART_LSR_FER (1 << 3)/* 0; no framing error */ +#define UART_LSR_BRK (1 << 4)/* 0: no break detected 1: receive a break signal */ +#define UART_LSR_TDRQ (1 << 5)/* 1: transmit FIFO half "empty" */ +#define UART_LSR_TEMT (1 << 6)/* 1: transmit FIFO and shift registers empty */ +#define UART_LSR_RFER (1 << 7)/* 0: no receive error 1: receive error in FIFO mode */ + +/* +* Define macros for UART_MCR +* UART Modem Control Register +*/ +#define UART_MCR_DTR (1 << 0)/* 0: DTR_ ouput high */ +#define UART_MCR_RTS (1 << 1)/* 0: RTS_ output high */ +#define UART_MCR_OUT1 (1 << 2)/* 0: UART_MSR.RI is set to 0 and RI_ input high */ +#define UART_MCR_OUT2 (1 << 3)/* 0: UART_MSR.DCD is set to 0 and DCD_ input high */ +#define UART_MCR_LOOP (1 << 4)/* 0: normal 1: loopback mode */ +#define UART_MCR_MCE (1 << 7)/* 0: modem function is disable */ + +/* +* Define macros for UART_MSR +* UART Modem Status Register +*/ +#define UART_MSR_DCTS (1 << 0)/* 0: no change on CTS_ pin since last read of UART_MSR */ +#define UART_MSR_DDSR (1 << 1)/* 0: no change on DSR_ pin since last read of UART_MSR */ +#define UART_MSR_DRI (1 << 2)/* 0: no change on RI_ pin since last read of UART_MSR */ +#define UART_MSR_DDCD (1 << 3)/* 0: no change on DCD_ pin since last read of UART_MSR */ +#define UART_MSR_CTS (1 << 4)/* 0: CTS_ pin is high */ +#define UART_MSR_DSR (1 << 5)/* 0: DSR_ pin is high */ +#define UART_MSR_RI (1 << 6)/* 0: RI_ pin is high */ +#define UART_MSR_DCD (1 << 7)/* 0: DCD_ pin is high */ + +/* +* Define macros for SIRCR +* Slow IrDA Control Register +*/ +#define SIRCR_TSIRE (1 << 0)/* 0: transmitter is in UART mode 1: IrDA mode */ +#define SIRCR_RSIRE (1 << 1)/* 0: receiver is in UART mode 1: IrDA mode */ +#define SIRCR_TPWS (1 << 2)/* 0: transmit 0 pulse width is 3/16 of bit length +1: 0 pulse width is 1.6us for 115.2Kbps */ +#define SIRCR_TXPL (1 << 3)/* 0: encoder generates a positive pulse for 0 */ +#define SIRCR_RXPL (1 << 4)/* 0: decoder interprets positive pulse as 0 */ + +/* +* MSC +*/ +#define MSC_STRPCL (MSC_BASE + 0x000) +#define MSC_STAT (MSC_BASE + 0x004) +#define MSC_CLKRT (MSC_BASE + 0x008) +#define MSC_CMDAT (MSC_BASE + 0x00C) +#define MSC_RESTO (MSC_BASE + 0x010) +#define MSC_RDTO (MSC_BASE + 0x014) +#define MSC_BLKLEN (MSC_BASE + 0x018) +#define MSC_NOB (MSC_BASE + 0x01C) +#define MSC_SNOB (MSC_BASE + 0x020) +#define MSC_IMASK (MSC_BASE + 0x024) +#define MSC_CMD (MSC_BASE + 0x02C) +#define MSC_ARG (MSC_BASE + 0x030) +#define MSC_RES (MSC_BASE + 0x034) +#define MSC_RXFIFO (MSC_BASE + 0x038) +#define MSC_TXFIFO (MSC_BASE + 0x03C) + +/* MSC Clock and Control Register (MSC_STRPCL) */ +#define MSC_STRPCL_EXIT_MULTIPLE (1 << 7) +#define MSC_STRPCL_EXIT_TRANSFER (1 << 6) +#define MSC_STRPCL_START_READWAIT (1 << 5) +#define MSC_STRPCL_STOP_READWAIT (1 << 4) +#define MSC_STRPCL_RESET (1 << 3) +#define MSC_STRPCL_START_OP (1 << 2) +#define MSC_STRPCL_CLOCK_CONTROL_BIT 0 +#define MSC_STRPCL_CLOCK_CONTROL_MASK (0x3 << MSC_STRPCL_CLOCK_CONTROL_BIT) +#define MSC_STRPCL_CLOCK_CONTROL_STOP (0x1 << MSC_STRPCL_CLOCK_CONTROL_BIT)/* Stop MMC/SD clock */ +#define MSC_STRPCL_CLOCK_CONTROL_START (0x2 << MSC_STRPCL_CLOCK_CONTROL_BIT)/* Start MMC/SD clock */ + +/* MSC Status Register (MSC_STAT) */ +#define MSC_STAT_IS_RESETTING (1 << 15) +#define MSC_STAT_SDIO_INT_ACTIVE (1 << 14) +#define MSC_STAT_PRG_DONE (1 << 13) +#define MSC_STAT_DATA_TRAN_DONE (1 << 12) +#define MSC_STAT_END_CMD_RES (1 << 11) +#define MSC_STAT_DATA_FIFO_AFULL (1 << 10) +#define MSC_STAT_IS_READWAIT (1 << 9) +#define MSC_STAT_CLK_EN (1 << 8) +#define MSC_STAT_DATA_FIFO_FULL (1 << 7) +#define MSC_STAT_DATA_FIFO_EMPTY (1 << 6) +#define MSC_STAT_CRC_RES_ERR (1 << 5) +#define MSC_STAT_CRC_READ_ERROR (1 << 4) +#define MSC_STAT_CRC_WRITE_ERROR_BIT 2 +#define MSC_STAT_CRC_WRITE_ERROR_MASK (0x3 << MSC_STAT_CRC_WRITE_ERROR_BIT) +#define MSC_STAT_CRC_WRITE_ERROR_NO (0 << MSC_STAT_CRC_WRITE_ERROR_BIT)/* No error on transmission of data */ +#define MSC_STAT_CRC_WRITE_ERROR (1 << MSC_STAT_CRC_WRITE_ERROR_BIT)/* Card observed erroneous transmission of data */ +#define MSC_STAT_CRC_WRITE_ERROR_NOSTS (2 << MSC_STAT_CRC_WRITE_ERROR_BIT)/* No CRC status is sent back */ +#define MSC_STAT_TIME_OUT_RES (1 << 1) +#define MSC_STAT_TIME_OUT_READ (1 << 0) + +/* MSC Bus Clock Control Register (MSC_CLKRT) */ + +#define MSC_CLKRT_CLK_RATE_BIT 0 +#define MSC_CLKRT_CLK_RATE_MASK (0x7 << MSC_CLKRT_CLK_RATE_BIT) +#define MSC_CLKRT_CLK_RATE_DIV_1 (0x0 << MSC_CLKRT_CLK_RATE_BIT)/* CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_2 (0x1 << MSC_CLKRT_CLK_RATE_BIT)/* 1/2 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_4 (0x2 << MSC_CLKRT_CLK_RATE_BIT)/* 1/4 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_8 (0x3 << MSC_CLKRT_CLK_RATE_BIT)/* 1/8 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_16 (0x4 << MSC_CLKRT_CLK_RATE_BIT)/* 1/16 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_32 (0x5 << MSC_CLKRT_CLK_RATE_BIT)/* 1/32 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_64 (0x6 << MSC_CLKRT_CLK_RATE_BIT)/* 1/64 of CLK_SRC */ +#define MSC_CLKRT_CLK_RATE_DIV_128 (0x7 << MSC_CLKRT_CLK_RATE_BIT)/* 1/128 of CLK_SRC */ + +/* MSC Command Sequence Control Register (MSC_CMDAT) */ +#define MSC_CMDAT_IO_ABORT (1 << 11) +#define MSC_CMDAT_BUS_WIDTH_BIT 9 +#define MSC_CMDAT_BUS_WIDTH_MASK (0x3 << MSC_CMDAT_BUS_WIDTH_BIT) +#define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << MSC_CMDAT_BUS_WIDTH_BIT) +#define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << MSC_CMDAT_BUS_WIDTH_BIT) +#define MSC_CMDAT_DMA_EN (1 << 8) +#define MSC_CMDAT_INIT (1 << 7) +#define MSC_CMDAT_BUSY (1 << 6) +#define MSC_CMDAT_STREAM_BLOCK (1 << 5) +#define MSC_CMDAT_WRITE (1 << 4) +#define MSC_CMDAT_READ (0 << 4) +#define MSC_CMDAT_DATA_EN (1 << 3) +#define MSC_CMDAT_RESPONSE_BIT 0 +#define MSC_CMDAT_RESPONSE_MASK (0x7 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_NONE (0x0 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R1 (0x1 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R2 (0x2 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R3 (0x3 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R4 (0x4 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R5 (0x5 << MSC_CMDAT_RESPONSE_BIT) +#define MSC_CMDAT_RESPONSE_R6 (0x6 << MSC_CMDAT_RESPONSE_BIT) + +/* MSC Interrupts Mask Register (MSC_IMASK) */ +#define MSC_IMASK_SDIO (1 << 7) +#define MSC_IMASK_TXFIFO_WR_REQ (1 << 6) +#define MSC_IMASK_RXFIFO_RD_REQ (1 << 5) +#define MSC_IMASK_END_CMD_RES (1 << 2) +#define MSC_IMASK_PRG_DONE (1 << 1) +#define MSC_IMASK_DATA_TRAN_DONE (1 << 0) + +/* +* EMC (External Memory Controller) +*/ +#define EMC_BCR (EMC_BASE + 0x0)/* BCR */ + +#define EMC_SMCR0 (EMC_BASE + 0x10)/* Static Memory Control Register 0 */ +#define EMC_SMCR1 (EMC_BASE + 0x14)/* Static Memory Control Register 1 */ +#define EMC_SMCR2 (EMC_BASE + 0x18)/* Static Memory Control Register 2 */ +#define EMC_SMCR3 (EMC_BASE + 0x1c)/* Static Memory Control Register 3 */ +#define EMC_SMCR4 (EMC_BASE + 0x20)/* Static Memory Control Register 4 */ +#define EMC_SACR0 (EMC_BASE + 0x30)/* Static Memory Bank 0 Addr Config Reg */ +#define EMC_SACR1 (EMC_BASE + 0x34)/* Static Memory Bank 1 Addr Config Reg */ +#define EMC_SACR2 (EMC_BASE + 0x38)/* Static Memory Bank 2 Addr Config Reg */ +#define EMC_SACR3 (EMC_BASE + 0x3c)/* Static Memory Bank 3 Addr Config Reg */ +#define EMC_SACR4 (EMC_BASE + 0x40)/* Static Memory Bank 4 Addr Config Reg */ + +#define EMC_NFCSR (EMC_BASE + 0x050)/* NAND Flash Control/Status Register */ +#define EMC_NFECR (EMC_BASE + 0x100)/* NAND Flash ECC Control Register */ +#define EMC_NFECC (EMC_BASE + 0x104)/* NAND Flash ECC Data Register */ +#define EMC_NFPAR0 (EMC_BASE + 0x108)/* NAND Flash RS Parity 0 Register */ +#define EMC_NFPAR1 (EMC_BASE + 0x10c)/* NAND Flash RS Parity 1 Register */ +#define EMC_NFPAR2 (EMC_BASE + 0x110)/* NAND Flash RS Parity 2 Register */ +#define EMC_NFINTS (EMC_BASE + 0x114)/* NAND Flash Interrupt Status Register */ +#define EMC_NFINTE (EMC_BASE + 0x118)/* NAND Flash Interrupt Enable Register */ +#define EMC_NFERR0 (EMC_BASE + 0x11c)/* NAND Flash RS Error Report 0 Register */ +#define EMC_NFERR1 (EMC_BASE + 0x120)/* NAND Flash RS Error Report 1 Register */ +#define EMC_NFERR2 (EMC_BASE + 0x124)/* NAND Flash RS Error Report 2 Register */ +#define EMC_NFERR3 (EMC_BASE + 0x128)/* NAND Flash RS Error Report 3 Register */ + +#define EMC_DMCR (EMC_BASE + 0x80)/* DRAM Control Register */ +#define EMC_RTCSR (EMC_BASE + 0x84)/* Refresh Time Control/Status Register */ +#define EMC_RTCNT (EMC_BASE + 0x88)/* Refresh Timer Counter */ +#define EMC_RTCOR (EMC_BASE + 0x8c)/* Refresh Time Constant Register */ +#define EMC_DMAR0 (EMC_BASE + 0x90)/* SDRAM Bank 0 Addr Config Register */ +#define EMC_SDMR0 (EMC_BASE + 0xa000)/* Mode Register of SDRAM bank 0 */ + +/* Static Memory Control Register */ +#define EMC_SMCR_STRV_BIT 24 +#define EMC_SMCR_STRV_MASK (0x0f << EMC_SMCR_STRV_BIT) +#define EMC_SMCR_TAW_BIT 20 +#define EMC_SMCR_TAW_MASK (0x0f << EMC_SMCR_TAW_BIT) +#define EMC_SMCR_TBP_BIT 16 +#define EMC_SMCR_TBP_MASK (0x0f << EMC_SMCR_TBP_BIT) +#define EMC_SMCR_TAH_BIT 12 +#define EMC_SMCR_TAH_MASK (0x07 << EMC_SMCR_TAH_BIT) +#define EMC_SMCR_TAS_BIT 8 +#define EMC_SMCR_TAS_MASK (0x07 << EMC_SMCR_TAS_BIT) +#define EMC_SMCR_BW_BIT 6 +#define EMC_SMCR_BW_MASK (0x03 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BW_8BIT (0 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BW_16BIT (1 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BW_32BIT (2 << EMC_SMCR_BW_BIT) +#define EMC_SMCR_BCM (1 << 3) +#define EMC_SMCR_BL_BIT 1 +#define EMC_SMCR_BL_MASK (0x03 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_BL_4 (0 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_BL_8 (1 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_BL_16 (2 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_BL_32 (3 << EMC_SMCR_BL_BIT) +#define EMC_SMCR_SMT (1 << 0) + +/* Static Memory Bank Addr Config Reg */ +#define EMC_SACR_BASE_BIT 8 +#define EMC_SACR_BASE_MASK (0xff << EMC_SACR_BASE_BIT) +#define EMC_SACR_MASK_BIT 0 +#define EMC_SACR_MASK_MASK (0xff << EMC_SACR_MASK_BIT) + +/* NAND Flash Control/Status Register */ +#define EMC_NFCSR_NFCE4 (1 << 7)/* NAND Flash Enable */ +#define EMC_NFCSR_NFE4 (1 << 6)/* NAND Flash FCE# Assertion Enable */ +#define EMC_NFCSR_NFCE3 (1 << 5) +#define EMC_NFCSR_NFE3 (1 << 4) +#define EMC_NFCSR_NFCE2 (1 << 3) +#define EMC_NFCSR_NFE2 (1 << 2) +#define EMC_NFCSR_NFCE1 (1 << 1) +#define EMC_NFCSR_NFE1 (1 << 0) + +/* NAND Flash ECC Control Register */ +#define EMC_NFECR_PRDY (1 << 4)/* Parity Ready */ +#define EMC_NFECR_RS_DECODING (0 << 3)/* RS is in decoding phase */ +#define EMC_NFECR_RS_ENCODING (1 << 3)/* RS is in encoding phase */ +#define EMC_NFECR_HAMMING (0 << 2)/* Select HAMMING Correction Algorithm */ +#define EMC_NFECR_RS (1 << 2)/* Select RS Correction Algorithm */ +#define EMC_NFECR_ERST (1 << 1)/* ECC Reset */ +#define EMC_NFECR_ECCE (1 << 0)/* ECC Enable */ + +/* NAND Flash ECC Data Register */ +#define EMC_NFECC_ECC2_BIT 16 +#define EMC_NFECC_ECC2_MASK (0xff << EMC_NFECC_ECC2_BIT) +#define EMC_NFECC_ECC1_BIT 8 +#define EMC_NFECC_ECC1_MASK (0xff << EMC_NFECC_ECC1_BIT) +#define EMC_NFECC_ECC0_BIT 0 +#define EMC_NFECC_ECC0_MASK (0xff << EMC_NFECC_ECC0_BIT) + +/* NAND Flash Interrupt Status Register */ +#define EMC_NFINTS_ERRCNT_BIT 29/* Error Count */ +#define EMC_NFINTS_ERRCNT_MASK (0x7 << EMC_NFINTS_ERRCNT_BIT) +#define EMC_NFINTS_PADF (1 << 4)/* Padding Finished */ +#define EMC_NFINTS_DECF (1 << 3)/* Decoding Finished */ +#define EMC_NFINTS_ENCF (1 << 2)/* Encoding Finished */ +#define EMC_NFINTS_UNCOR (1 << 1)/* Uncorrectable Error Occurred */ +#define EMC_NFINTS_ERR (1 << 0)/* Error Occurred */ + +/* NAND Flash Interrupt Enable Register */ +#define EMC_NFINTE_PADFE (1 << 4)/* Padding Finished Interrupt Enable */ +#define EMC_NFINTE_DECFE (1 << 3)/* Decoding Finished Interrupt Enable */ +#define EMC_NFINTE_ENCFE (1 << 2)/* Encoding Finished Interrupt Enable */ +#define EMC_NFINTE_UNCORE (1 << 1)/* Uncorrectable Error Occurred Intr Enable */ +#define EMC_NFINTE_ERRE (1 << 0)/* Error Occurred Interrupt */ + +/* NAND Flash RS Error Report Register */ +#define EMC_NFERR_INDEX_BIT 16/* Error Symbol Index */ +#define EMC_NFERR_INDEX_MASK (0x1ff << EMC_NFERR_INDEX_BIT) +#define EMC_NFERR_MASK_BIT 0/* Error Symbol Value */ +#define EMC_NFERR_MASK_MASK (0x1ff << EMC_NFERR_MASK_BIT) + +/* DRAM Control Register */ +#define EMC_DMCR_BW_BIT 31 +#define EMC_DMCR_BW (1 << EMC_DMCR_BW_BIT) +#define EMC_DMCR_CA_BIT 26 +#define EMC_DMCR_CA_MASK (0x07 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_CA_8 (0 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_CA_9 (1 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_CA_10 (2 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_CA_11 (3 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_CA_12 (4 << EMC_DMCR_CA_BIT) +#define EMC_DMCR_RMODE (1 << 25) +#define EMC_DMCR_RFSH (1 << 24) +#define EMC_DMCR_MRSET (1 << 23) +#define EMC_DMCR_RA_BIT 20 +#define EMC_DMCR_RA_MASK (0x03 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_RA_11 (0 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_RA_12 (1 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_RA_13 (2 << EMC_DMCR_RA_BIT) +#define EMC_DMCR_BA_BIT 19 +#define EMC_DMCR_BA (1 << EMC_DMCR_BA_BIT) +#define EMC_DMCR_PDM (1 << 18) +#define EMC_DMCR_EPIN (1 << 17) +#define EMC_DMCR_TRAS_BIT 13 +#define EMC_DMCR_TRAS_MASK (0x07 << EMC_DMCR_TRAS_BIT) +#define EMC_DMCR_RCD_BIT 11 +#define EMC_DMCR_RCD_MASK (0x03 << EMC_DMCR_RCD_BIT) +#define EMC_DMCR_TPC_BIT 8 +#define EMC_DMCR_TPC_MASK (0x07 << EMC_DMCR_TPC_BIT) +#define EMC_DMCR_TRWL_BIT 5 +#define EMC_DMCR_TRWL_MASK (0x03 << EMC_DMCR_TRWL_BIT) +#define EMC_DMCR_TRC_BIT 2 +#define EMC_DMCR_TRC_MASK (0x07 << EMC_DMCR_TRC_BIT) +#define EMC_DMCR_TCL_BIT 0 +#define EMC_DMCR_TCL_MASK (0x03 << EMC_DMCR_TCL_BIT) + +/* Refresh Time Control/Status Register */ +#define EMC_RTCSR_CMF (1 << 7) +#define EMC_RTCSR_CKS_BIT 0 +#define EMC_RTCSR_CKS_MASK (0x07 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_DISABLE (0 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_4 (1 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_16 (2 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_64 (3 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_256 (4 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_1024 (5 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_2048 (6 << EMC_RTCSR_CKS_BIT) +#define EMC_RTCSR_CKS_4096 (7 << EMC_RTCSR_CKS_BIT) + +/* SDRAM Bank Address Configuration Register */ +#define EMC_DMAR_BASE_BIT 8 +#define EMC_DMAR_BASE_MASK (0xff << EMC_DMAR_BASE_BIT) +#define EMC_DMAR_MASK_BIT 0 +#define EMC_DMAR_MASK_MASK (0xff << EMC_DMAR_MASK_BIT) + +/* Mode Register of SDRAM bank 0 */ +#define EMC_SDMR_BM (1 << 9)/* Write Burst Mode */ +#define EMC_SDMR_OM_BIT 7/* Operating Mode */ +#define EMC_SDMR_OM_MASK (3 << EMC_SDMR_OM_BIT) +#define EMC_SDMR_OM_NORMAL (0 << EMC_SDMR_OM_BIT) +#define EMC_SDMR_CAS_BIT 4/* CAS Latency */ +#define EMC_SDMR_CAS_MASK (7 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_CAS_1 (1 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_CAS_2 (2 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_CAS_3 (3 << EMC_SDMR_CAS_BIT) +#define EMC_SDMR_BT_BIT 3/* Burst Type */ +#define EMC_SDMR_BT_MASK (1 << EMC_SDMR_BT_BIT) +#define EMC_SDMR_BT_SEQ (0 << EMC_SDMR_BT_BIT)/* Sequential */ +#define EMC_SDMR_BT_INT (1 << EMC_SDMR_BT_BIT)/* Interleave */ +#define EMC_SDMR_BL_BIT 0/* Burst Length */ +#define EMC_SDMR_BL_MASK (7 << EMC_SDMR_BL_BIT) +#define EMC_SDMR_BL_1 (0 << EMC_SDMR_BL_BIT) +#define EMC_SDMR_BL_2 (1 << EMC_SDMR_BL_BIT) +#define EMC_SDMR_BL_4 (2 << EMC_SDMR_BL_BIT) +#define EMC_SDMR_BL_8 (3 << EMC_SDMR_BL_BIT) + +#define EMC_SDMR_CAS2_16BIT \ + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS2_32BIT \ + (EMC_SDMR_CAS_2 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) +#define EMC_SDMR_CAS3_16BIT \ + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_2) +#define EMC_SDMR_CAS3_32BIT \ + (EMC_SDMR_CAS_3 | EMC_SDMR_BT_SEQ | EMC_SDMR_BL_4) + +/* +* CIM +*/ +#define CIM_CFG (CIM_BASE + 0x0000) +#define CIM_CTRL (CIM_BASE + 0x0004) +#define CIM_STATE (CIM_BASE + 0x0008) +#define CIM_IID (CIM_BASE + 0x000C) +#define CIM_RXFIFO (CIM_BASE + 0x0010) +#define CIM_DA (CIM_BASE + 0x0020) +#define CIM_FA (CIM_BASE + 0x0024) +#define CIM_FID (CIM_BASE + 0x0028) +#define CIM_CMD (CIM_BASE + 0x002C) + + +/* CIM Configuration Register (CIM_CFG) */ +#define CIM_CFG_INV_DAT (1 << 15) +#define CIM_CFG_VSP (1 << 14) +#define CIM_CFG_HSP (1 << 13) +#define CIM_CFG_PCP (1 << 12) +#define CIM_CFG_DUMMY_ZERO (1 << 9) +#define CIM_CFG_EXT_VSYNC (1 << 8) +#define CIM_CFG_PACK_BIT 4 +#define CIM_CFG_PACK_MASK (0x7 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_0 (0 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_1 (1 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_2 (2 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_3 (3 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_4 (4 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_5 (5 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_6 (6 << CIM_CFG_PACK_BIT) +#define CIM_CFG_PACK_7 (7 << CIM_CFG_PACK_BIT) +#define CIM_CFG_DSM_BIT 0 +#define CIM_CFG_DSM_MASK (0x3 << CIM_CFG_DSM_BIT) +#define CIM_CFG_DSM_CPM (0 << CIM_CFG_DSM_BIT)/* CCIR656 Progressive Mode */ +#define CIM_CFG_DSM_CIM (1 << CIM_CFG_DSM_BIT)/* CCIR656 Interlace Mode */ +#define CIM_CFG_DSM_GCM (2 << CIM_CFG_DSM_BIT)/* Gated Clock Mode */ +#define CIM_CFG_DSM_NGCM (3 << CIM_CFG_DSM_BIT)/* Non-Gated Clock Mode */ + +/* CIM Control Register (CIM_CTRL) */ +#define CIM_CTRL_MCLKDIV_BIT 24 +#define CIM_CTRL_MCLKDIV_MASK (0xff << CIM_CTRL_MCLKDIV_BIT) +#define CIM_CTRL_FRC_BIT 16 +#define CIM_CTRL_FRC_MASK (0xf << CIM_CTRL_FRC_BIT) +#define CIM_CTRL_FRC_1 (0x0 << CIM_CTRL_FRC_BIT)/* Sample every frame */ +#define CIM_CTRL_FRC_2 (0x1 << CIM_CTRL_FRC_BIT)/* Sample 1/2 frame */ +#define CIM_CTRL_FRC_3 (0x2 << CIM_CTRL_FRC_BIT)/* Sample 1/3 frame */ +#define CIM_CTRL_FRC_4 (0x3 << CIM_CTRL_FRC_BIT)/* Sample 1/4 frame */ +#define CIM_CTRL_FRC_5 (0x4 << CIM_CTRL_FRC_BIT)/* Sample 1/5 frame */ +#define CIM_CTRL_FRC_6 (0x5 << CIM_CTRL_FRC_BIT)/* Sample 1/6 frame */ +#define CIM_CTRL_FRC_7 (0x6 << CIM_CTRL_FRC_BIT)/* Sample 1/7 frame */ +#define CIM_CTRL_FRC_8 (0x7 << CIM_CTRL_FRC_BIT)/* Sample 1/8 frame */ +#define CIM_CTRL_FRC_9 (0x8 << CIM_CTRL_FRC_BIT)/* Sample 1/9 frame */ +#define CIM_CTRL_FRC_10 (0x9 << CIM_CTRL_FRC_BIT)/* Sample 1/10 frame */ +#define CIM_CTRL_FRC_11 (0xA << CIM_CTRL_FRC_BIT)/* Sample 1/11 frame */ +#define CIM_CTRL_FRC_12 (0xB << CIM_CTRL_FRC_BIT)/* Sample 1/12 frame */ +#define CIM_CTRL_FRC_13 (0xC << CIM_CTRL_FRC_BIT)/* Sample 1/13 frame */ +#define CIM_CTRL_FRC_14 (0xD << CIM_CTRL_FRC_BIT)/* Sample 1/14 frame */ +#define CIM_CTRL_FRC_15 (0xE << CIM_CTRL_FRC_BIT)/* Sample 1/15 frame */ +#define CIM_CTRL_FRC_16 (0xF << CIM_CTRL_FRC_BIT)/* Sample 1/16 frame */ +#define CIM_CTRL_VDDM (1 << 13) +#define CIM_CTRL_DMA_SOFM (1 << 12) +#define CIM_CTRL_DMA_EOFM (1 << 11) +#define CIM_CTRL_DMA_STOPM (1 << 10) +#define CIM_CTRL_RXF_TRIGM (1 << 9) +#define CIM_CTRL_RXF_OFM (1 << 8) +#define CIM_CTRL_RXF_TRIG_BIT 4 +#define CIM_CTRL_RXF_TRIG_MASK (0x7 << CIM_CTRL_RXF_TRIG_BIT) +#define CIM_CTRL_RXF_TRIG_4 (0 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 4 */ +#define CIM_CTRL_RXF_TRIG_8 (1 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 8 */ +#define CIM_CTRL_RXF_TRIG_12 (2 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 12 */ +#define CIM_CTRL_RXF_TRIG_16 (3 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 16 */ +#define CIM_CTRL_RXF_TRIG_20 (4 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 20 */ +#define CIM_CTRL_RXF_TRIG_24 (5 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 24 */ +#define CIM_CTRL_RXF_TRIG_28 (6 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 28 */ +#define CIM_CTRL_RXF_TRIG_32 (7 << CIM_CTRL_RXF_TRIG_BIT)/* RXFIFO Trigger Value is 32 */ +#define CIM_CTRL_DMA_EN (1 << 2) +#define CIM_CTRL_RXF_RST (1 << 1) +#define CIM_CTRL_ENA (1 << 0) + +/* CIM State Register (CIM_STATE) */ +#define CIM_STATE_DMA_SOF (1 << 6) +#define CIM_STATE_DMA_EOF (1 << 5) +#define CIM_STATE_DMA_STOP (1 << 4) +#define CIM_STATE_RXF_OF (1 << 3) +#define CIM_STATE_RXF_TRIG (1 << 2) +#define CIM_STATE_RXF_EMPTY (1 << 1) +#define CIM_STATE_VDD (1 << 0) + +/* CIM DMA Command Register (CIM_CMD) */ +#define CIM_CMD_SOFINT (1 << 31) +#define CIM_CMD_EOFINT (1 << 30) +#define CIM_CMD_STOP (1 << 28) +#define CIM_CMD_LEN_BIT 0 +#define CIM_CMD_LEN_MASK (0xffffff << CIM_CMD_LEN_BIT) + +/* ADC Control Register */ +#define SADC_CTRL_PENDM (1 << 4)/* Pen Down Interrupt Mask */ +#define SADC_CTRL_PENUM (1 << 3)/* Pen Up Interrupt Mask */ +#define SADC_CTRL_TSRDYM (1 << 2)/* Touch Screen Data Ready Interrupt Mask */ +#define SADC_CTRL_PBATRDYM (1 << 1)/* PBAT Data Ready Interrupt Mask */ +#define SADC_CTRL_SRDYM (1 << 0)/* SADCIN Data Ready Interrupt Mask */ + +/* ADC Status Register */ +#define SADC_STATE_TSBUSY (1 << 7)/* TS A/D is working */ +#define SADC_STATE_PBATBUSY (1 << 6)/* PBAT A/D is working */ +#define SADC_STATE_SBUSY (1 << 5)/* SADCIN A/D is working */ +#define SADC_STATE_PEND (1 << 4)/* Pen Down Interrupt Flag */ +#define SADC_STATE_PENU (1 << 3)/* Pen Up Interrupt Flag */ +#define SADC_STATE_TSRDY (1 << 2)/* Touch Screen Data Ready Interrupt Flag */ +#define SADC_STATE_PBATRDY (1 << 1)/* PBAT Data Ready Interrupt Flag */ +#define SADC_STATE_SRDY (1 << 0)/* SADCIN Data Ready Interrupt Flag */ + +/* ADC Touch Screen Data Register */ +#define SADC_TSDAT_DATA0_BIT 0 +#define SADC_TSDAT_DATA0_MASK (0xfff << SADC_TSDAT_DATA0_BIT) +#define SADC_TSDAT_TYPE0 (1 << 15) +#define SADC_TSDAT_DATA1_BIT 16 +#define SADC_TSDAT_DATA1_MASK (0xfff << SADC_TSDAT_DATA1_BIT) +#define SADC_TSDAT_TYPE1 (1 << 31) + +/* SLCD Control Register */ +#define SLCD_CTRL_DMA_EN (1 << 0) + +/* SLCD Status Register */ +#define SLCD_STATE_BUSY (1 << 0) + +/* SLCD Data Register */ +#define SLCD_DATA_RS_DATA (0 << 31) +#define SLCD_DATA_RS_COMMAND (1 << 31) + +/* SLCD FIFO Register */ +#define SLCD_FIFO_RS_DATA (0 << 31) +#define SLCD_FIFO_RS_COMMAND (1 << 31) + +/* Vertical Synchronize Register */ +#define LCD_VSYNC_VPS_BIT 16/* VSYNC pulse start in line clock, fixed to 0 */ +#define LCD_VSYNC_VPS_MASK (0xffff << LCD_VSYNC_VPS_BIT) +#define LCD_VSYNC_VPE_BIT 0/* VSYNC pulse end in line clock */ +#define LCD_VSYNC_VPE_MASK (0xffff << LCD_VSYNC_VPS_BIT) + +/* Horizontal Synchronize Register */ +#define LCD_HSYNC_HPS_BIT 16/* HSYNC pulse start position in dot clock */ +#define LCD_HSYNC_HPS_MASK (0xffff << LCD_HSYNC_HPS_BIT) +#define LCD_HSYNC_HPE_BIT 0/* HSYNC pulse end position in dot clock */ +#define LCD_HSYNC_HPE_MASK (0xffff << LCD_HSYNC_HPE_BIT) + +/* Virtual Area Setting Register */ +#define LCD_VAT_HT_BIT 16/* Horizontal Total size in dot clock */ +#define LCD_VAT_HT_MASK (0xffff << LCD_VAT_HT_BIT) +#define LCD_VAT_VT_BIT 0/* Vertical Total size in dot clock */ +#define LCD_VAT_VT_MASK (0xffff << LCD_VAT_VT_BIT) + +/* Display Area Horizontal Start/End Point Register */ +#define LCD_DAH_HDS_BIT 16/* Horizontal display area start in dot clock */ +#define LCD_DAH_HDS_MASK (0xffff << LCD_DAH_HDS_BIT) +#define LCD_DAH_HDE_BIT 0/* Horizontal display area end in dot clock */ +#define LCD_DAH_HDE_MASK (0xffff << LCD_DAH_HDE_BIT) + +/* Display Area Vertical Start/End Point Register */ +#define LCD_DAV_VDS_BIT 16/* Vertical display area start in line clock */ +#define LCD_DAV_VDS_MASK (0xffff << LCD_DAV_VDS_BIT) +#define LCD_DAV_VDE_BIT 0/* Vertical display area end in line clock */ +#define LCD_DAV_VDE_MASK (0xffff << LCD_DAV_VDE_BIT) + +/* PS Signal Setting */ +#define LCD_PS_PSS_BIT 16/* PS signal start position in dot clock */ +#define LCD_PS_PSS_MASK (0xffff << LCD_PS_PSS_BIT) +#define LCD_PS_PSE_BIT 0/* PS signal end position in dot clock */ +#define LCD_PS_PSE_MASK (0xffff << LCD_PS_PSE_BIT) + +/* CLS Signal Setting */ +#define LCD_CLS_CLSS_BIT 16/* CLS signal start position in dot clock */ +#define LCD_CLS_CLSS_MASK (0xffff << LCD_CLS_CLSS_BIT) +#define LCD_CLS_CLSE_BIT 0/* CLS signal end position in dot clock */ +#define LCD_CLS_CLSE_MASK (0xffff << LCD_CLS_CLSE_BIT) + +/* SPL Signal Setting */ +#define LCD_SPL_SPLS_BIT 16/* SPL signal start position in dot clock */ +#define LCD_SPL_SPLS_MASK (0xffff << LCD_SPL_SPLS_BIT) +#define LCD_SPL_SPLE_BIT 0/* SPL signal end position in dot clock */ +#define LCD_SPL_SPLE_MASK (0xffff << LCD_SPL_SPLE_BIT) + +/* REV Signal Setting */ +#define LCD_REV_REVS_BIT 16/* REV signal start position in dot clock */ +#define LCD_REV_REVS_MASK (0xffff << LCD_REV_REVS_BIT) + +/* LCD Control Register */ +#define LCD_CTRL_BST_BIT 28/* Burst Length Selection */ +#define LCD_CTRL_BST_MASK (0x03 << LCD_CTRL_BST_BIT) +#define LCD_CTRL_BST_4 (0 << LCD_CTRL_BST_BIT)/* 4-word */ +#define LCD_CTRL_BST_8 (1 << LCD_CTRL_BST_BIT)/* 8-word */ +#define LCD_CTRL_BST_16 (2 << LCD_CTRL_BST_BIT)/* 16-word */ +#define LCD_CTRL_RGB565 (0 << 27)/* RGB565 mode */ +#define LCD_CTRL_RGB555 (1 << 27)/* RGB555 mode */ +#define LCD_CTRL_OFUP (1 << 26)/* Output FIFO underrun protection enable */ +#define LCD_CTRL_FRC_BIT 24/* STN FRC Algorithm Selection */ +#define LCD_CTRL_FRC_MASK (0x03 << LCD_CTRL_FRC_BIT) +#define LCD_CTRL_FRC_16 (0 << LCD_CTRL_FRC_BIT)/* 16 grayscale */ +#define LCD_CTRL_FRC_4 (1 << LCD_CTRL_FRC_BIT)/* 4 grayscale */ +#define LCD_CTRL_FRC_2 (2 << LCD_CTRL_FRC_BIT)/* 2 grayscale */ +#define LCD_CTRL_PDD_BIT 16/* Load Palette Delay Counter */ +#define LCD_CTRL_PDD_MASK (0xff << LCD_CTRL_PDD_BIT) +#define LCD_CTRL_EOFM (1 << 13)/* EOF interrupt mask */ +#define LCD_CTRL_SOFM (1 << 12)/* SOF interrupt mask */ +#define LCD_CTRL_OFUM (1 << 11)/* Output FIFO underrun interrupt mask */ +#define LCD_CTRL_IFUM0 (1 << 10)/* Input FIFO 0 underrun interrupt mask */ +#define LCD_CTRL_IFUM1 (1 << 9)/* Input FIFO 1 underrun interrupt mask */ +#define LCD_CTRL_LDDM (1 << 8)/* LCD disable done interrupt mask */ +#define LCD_CTRL_QDM (1 << 7)/* LCD quick disable done interrupt mask */ +#define LCD_CTRL_BEDN (1 << 6)/* Endian selection */ +#define LCD_CTRL_PEDN (1 << 5)/* Endian in byte:0-msb first, 1-lsb first */ +#define LCD_CTRL_DIS (1 << 4)/* Disable indicate bit */ +#define LCD_CTRL_ENA (1 << 3)/* LCD enable bit */ +#define LCD_CTRL_BPP_BIT 0/* Bits Per Pixel */ +#define LCD_CTRL_BPP_MASK (0x07 << LCD_CTRL_BPP_BIT) +#define LCD_CTRL_BPP_1 (0 << LCD_CTRL_BPP_BIT)/* 1 bpp */ +#define LCD_CTRL_BPP_2 (1 << LCD_CTRL_BPP_BIT)/* 2 bpp */ +#define LCD_CTRL_BPP_4 (2 << LCD_CTRL_BPP_BIT)/* 4 bpp */ +#define LCD_CTRL_BPP_8 (3 << LCD_CTRL_BPP_BIT)/* 8 bpp */ +#define LCD_CTRL_BPP_16 (4 << LCD_CTRL_BPP_BIT)/* 15/16 bpp */ +#define LCD_CTRL_BPP_18_24 (5 << LCD_CTRL_BPP_BIT)/* 18/24/32 bpp */ + +/* Module Operation Definitions */ +#ifndef __ASSEMBLY__ + +/* +* CS1#, CLE, ALE, FRE#, FWE#, FRB#, RDWE#/BUFD# +*/ +#define __gpio_as_nand () \ +do { \ + writel(0x02018000, GPIO_PXFUNS(1)); \ + writel(0x02018000, GPIO_PXSELC(1)); \ + writel(0x02018000, GPIO_PXPES(1)); \ + writel(0x30000000, GPIO_PXFUNS(2)); \ + writel(0x30000000, GPIO_PXSELC(2)); \ + writel(0x30000000, GPIO_PXPES(2)); \ + writel(0x40000000, GPIO_PXFUNC(2)); \ + writel(0x40000000, GPIO_PXSELC(2)); \ + writel(0x40000000, GPIO_PXDIRC(2)); \ + writel(0x40000000, GPIO_PXPES(2)); \ + writel(0x00400000, GPIO_PXFUNS(1)); \ + writel(0x00400000, GPIO_PXSELC(1)); \ +} while (0) + +#define __gpio_as_sdram_16bit_4720 () \ +do { \ + writel(0x5442bfaa, GPIO_PXFUNS(0)); \ + writel(0x5442bfaa, GPIO_PXSELC(0)); \ + writel(0x5442bfaa, GPIO_PXPES(0)); \ + writel(0x81f9ffff, GPIO_PXFUNS(1)); \ + writel(0x81f9ffff, GPIO_PXSELC(1)); \ + writel(0x81f9ffff, GPIO_PXPES(1)); \ + writel(0x01000000, GPIO_PXFUNS(2)); \ + writel(0x01000000, GPIO_PXSELC(2)); \ + writel(0x01000000, GPIO_PXPES(2)); \ +} while (0) +#define __gpio_as_lcd_18bit () \ +do { \ + writel(0x003fffff, GPIO_PXFUNS(2)); \ + writel(0x003fffff, GPIO_PXSELC(2)); \ + writel(0x003fffff, GPIO_PXPES(2)); \ +} while (0) + +/* +* MSC_CMD, MSC_CLK, MSC_D0 ~ MSC_D3 +*/ +#define __gpio_as_msc () \ +do { \ + writel(0x00003f00, GPIO_PXFUNS(3)); \ + writel(0x00003f00, GPIO_PXSELC(3)); \ + writel(0x00003f00, GPIO_PXPES(3)); \ +} while (0) + +#define __gpio_get_port (p) (readl(GPIO_PXPIN(p))) + +#define __gpio_disable_pull (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + writel((1 << o), GPIO_PXPES(p)); \ +} while (0) + +#define __gpio_enable_pull (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + writel(1 << (o), GPIO_PXPEC(p)); \ +} while (0) + +#define __gpio_port_as_output (p, o) \ +do { \ + writel(1 << (o), GPIO_PXFUNC(p)); \ + writel(1 << (o), GPIO_PXSELC(p)); \ + writel(1 << (o), GPIO_PXDIRS(p)); \ +} while (0) + +#define __gpio_port_as_input (p, o) \ +do { \ + writel(1 << (o), GPIO_PXFUNC(p)); \ + writel(1 << (o), GPIO_PXSELC(p)); \ + writel(1 << (o), GPIO_PXDIRC(p)); \ +} while (0) + +#define __gpio_as_output (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + __gpio_port_as_output(p, o); \ +} while (0) + +#define __gpio_as_input (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + __gpio_port_as_input(p, o); \ +} while (0) + +#define __gpio_set_pin (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + writel((1 << o), GPIO_PXDATS(p)); \ +} while (0) + +#define __gpio_clear_pin (n) \ +do { \ + unsigned int p, o; \ + p = (n) / 32; \ + o = (n) % 32; \ + writel((1 << o), GPIO_PXDATC(p)); \ +} while (0) + +#define __gpio_get_pin (n) \ +({ \ + unsigned int p, o, v; \ + p = (n) / 32; \ + o = (n) % 32; \ + if (__gpio_get_port(p) & (1 << o)) \ + v = 1; \ + else \ + v = 0; \ + v; \ +}) + +#define __gpio_as_uart0 () \ +do { \ + writel(0x06000000, GPIO_PXFUNS(3)); \ + writel(0x06000000, GPIO_PXSELS(3)); \ + writel(0x06000000, GPIO_PXPES(3)); \ +} while (0) + +#define __gpio_jtag_to_uart0 () \ +do { \ + writel(0x80000000, GPIO_PXSELS(2)); \ +} while (0) + +/* Clock Control Register */ +#define __cpm_get_pllm () \ + ((readl(CPM_CPPCR) & CPM_CPPCR_PLLM_MASK) >> CPM_CPPCR_PLLM_BIT) +#define __cpm_get_plln () \ + ((readl(CPM_CPPCR) & CPM_CPPCR_PLLN_MASK) >> CPM_CPPCR_PLLN_BIT) +#define __cpm_get_pllod () \ + ((readl(CPM_CPPCR) & CPM_CPPCR_PLLOD_MASK) >> CPM_CPPCR_PLLOD_BIT) +#define __cpm_get_hdiv () \ + ((readl(CPM_CPCCR) & CPM_CPCCR_HDIV_MASK) >> CPM_CPCCR_HDIV_BIT) +#define __cpm_get_pdiv () \ + ((readl(CPM_CPCCR) & CPM_CPCCR_PDIV_MASK) >> CPM_CPCCR_PDIV_BIT) +#define __cpm_get_cdiv () \ + ((readl(CPM_CPCCR) & CPM_CPCCR_CDIV_MASK) >> CPM_CPCCR_CDIV_BIT) +#define __cpm_get_mdiv () \ + ((readl(CPM_CPCCR) & CPM_CPCCR_MDIV_MASK) >> CPM_CPCCR_MDIV_BIT) + +static __inline__unsigned int __cpm_get_pllout (void ) +{ +unsigned long m, n, no, pllout; +unsigned long cppcr =readl (CPM_CPPCR ); +unsigned long od[4 ] = {1 ,2 ,2 ,4 }; + +if ((cppcr &CPM_CPPCR_PLLEN ) && !(cppcr &CPM_CPPCR_PLLBP )) { + m =__cpm_get_pllm () +2 ; + n =__cpm_get_plln () +2 ; + no = od[__cpm_get_pllod ()]; + pllout = (CONFIG_SYS_EXTAL / (n * no)) * m; + }else + pllout =CONFIG_SYS_EXTAL ; + +return pllout; +} + + +#define __cpm_stop_all () writel(0x7fff, CPM_CLKGR) +#define __cpm_stop_uart1 () writel(readl(CPM_CLKGR) |= CPM_CLKGR_UART1, CPM_CLKGR) +#define __cpm_stop_uhc () writel(readl(CPM_CLKGR) |= CPM_CLKGR_UHC, CPM_CLKGR) +#define __cpm_stop_ipu () writel(readl(CPM_CLKGR) |= CPM_CLKGR_IPU, CPM_CLKGR) +#define __cpm_stop_dmac () writel(readl(CPM_CLKGR) |= CPM_CLKGR_DMAC, CPM_CLKGR) +#define __cpm_stop_udc () writel(readl(CPM_CLKGR) |= CPM_CLKGR_UDC, CPM_CLKGR) +#define __cpm_stop_lcd () writel(readl(CPM_CLKGR) |= CPM_CLKGR_LCD, CPM_CLKGR) +#define __cpm_stop_cim () writel(readl(CPM_CLKGR) |= CPM_CLKGR_CIM, CPM_CLKGR) +#define __cpm_stop_sadc () writel(readl(CPM_CLKGR) |= CPM_CLKGR_SADC, CPM_CLKGR) +#define __cpm_stop_msc () writel(readl(CPM_CLKGR) |= CPM_CLKGR_MSC, CPM_CLKGR) +#define __cpm_stop_aic1 () writel(readl(CPM_CLKGR) |= CPM_CLKGR_AIC1, CPM_CLKGR) +#define __cpm_stop_aic2 () writel(readl(CPM_CLKGR) |= CPM_CLKGR_AIC2, CPM_CLKGR) +#define __cpm_stop_ssi () writel(readl(CPM_CLKGR) |= CPM_CLKGR_SSI, CPM_CLKGR) +#define __cpm_stop_i2c () writel(readl(CPM_CLKGR) |= CPM_CLKGR_I2C, CPM_CLKGR) +#define __cpm_stop_rtc () writel(readl(CPM_CLKGR) |= CPM_CLKGR_RTC, CPM_CLKGR) +#define __cpm_stop_tcu () writel(readl(CPM_CLKGR) |= CPM_CLKGR_TCU, CPM_CLKGR) +#define __cpm_stop_uart0 () writel(readl(CPM_CLKGR) |= CPM_CLKGR_UART0, CPM_CLKGR) + +#define __wdt_start () writeb(readb(WDT_TCER) | WDT_TCER_TCEN, WDT_TCER) +#define __wdt_stop () writeb(readb(WDT_TCER) & ~WDT_TCER_TCEN, WDT_TCER) +#define __wdt_set_count (v) writew((v), WDT_TCNT) +#define __wdt_set_data (v) writew((v), WDT_TDR) +#define __wdt_select_extalclk () \ + (writew((readw(WDT_TCSR) & \ + ~(WDT_TCSR_EXT_EN | WDT_TCSR_RTC_EN | \ + WDT_TCSR_PCK_EN)) \ + | WDT_TCSR_EXT_EN, WDT_TCSR)) +#define __wdt_select_clk_div64 () \ + (writew((readw(WDT_TCSR) & \ + ~WDT_TCSR_PRESCALE_MASK) | WDT_TCSR_PRESCALE64, WDT_TCSR)) +#define __tcu_start_wdt_clock () (writew(TCU_TSSR_WDTSC, TCU_TSCR)) + +#define __rtc_write_ready () (readl(RTC_RCR) & RTC_RCR_WRDY) +#define __rtc_enable_alarm () \ +do{ \ + while(!__rtc_write_ready()); \ + writel(readl(RTC_RCR) | RTC_RCR_AE, RTC_RCR); \ +}while(0) + +#endif /* !__ASSEMBLY__ */ +#endif /* __JZ4740_H__ */
Signature · 1 line
1.7.0.4
PATCH v4 3/7 jz4740 nand spl files
Signed-off-by Xiangfu Liu <[email protected]>
--- nand_spl/board/xburst/nanonote/Makefile | 96 ++++++++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++++++ nand_spl/nand_boot_jz4740.c | 344 +++++++++++++++++++++++++++++ 3 files changed, 503 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds create mode 100644 nand_spl/nand_boot_jz4740.c
nand_spl/board/xburst/nanonote/Makefile new file +96 -0
@@ -0,0 +1,96 @@ +# +# (C) Copyright 2006 +# Stefan Roese, DENX Software Engineering, sr at denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk +TEXT_BASE = 0x80000000 + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL -O2 + +SOBJS = start.o usbboot.o +COBJS = nand_boot_jz4740.o cpu.o jz4740.o jz_serial.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl.bin + dd bs=1024 count=8 if=/dev/zero of=$(nandobj)junk1 + cat $< $(nandobj)junk1 > $(nandobj)junk2 + dd bs=1024 count=8 if=$(nandobj)junk2 of=$(nandobj)junk3 + cat $(nandobj)junk3 $(nandobj)junk3 > $(nandobj)junk4 + dd bs=1024 count=256 if=/dev/zero of=$(nandobj)junk5 + cat $(nandobj)junk4 $(nandobj)junk5 > $(nandobj)junk6 + dd bs=1024 count=256 if=$(nandobj)junk6 of=$@ + rm -f $(nandobj)junk* + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files +$(obj)start.S: + @rm -f $(obj)start.S + ln -s $(SRCTREE)/arch/mips/cpu/xburst/start_spl.S $(obj)start.S + +$(obj)usbboot.S: + @rm -f $(obj)usbboot.S + ln -s $(SRCTREE)/arch/mips/cpu/xburst/usbboot.S $(obj)usbboot.S + +$(obj)cpu.c: + @rm -f $(obj)cpu.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/cpu.c $(obj)cpu.c + +$(obj)jz4740.c: + @rm -f $(obj)jz4740.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz4740.c $(obj)jz4740.c + +$(obj)jz_serial.c: + @rm -f $(obj)jz_serial.c + ln -s $(SRCTREE)/arch/mips/cpu/xburst/jz_serial.c $(obj)jz_serial.c + +$(obj)nand_boot_jz4740.c: + @rm -f $(obj)nand_boot_jz4740.c + ln -s $(SRCTREE)/nand_spl/nand_boot_jz4740.c $(obj)nand_boot_jz4740.c + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend
nand_spl/board/xburst/nanonote/u-boot.lds new file +63 -0
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nand_spl/nand_boot_jz4740.c new file +344 -0
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Signature · 1 line
1.7.0.4
PATCH v4 4/7 jz4740 nand driver
Signed-off-by Xiangfu Liu <[email protected]>
--- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/jz4740_nand.c | 252 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 253 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/jz4740_nand.c
drivers/mtd/nand/Makefile +1 -0
@@ -50,6 +50,7 @@ COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS-$(CONFIG_NAND_SPEAR) += spr_nand.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o COBJS-$(CONFIG_NAND_PLAT) += nand_plat.o +COBJS-$(CONFIG_NAND_JZ4740) += jz4740_nand.o endif COBJS := $(COBJS-y)
drivers/mtd/nand/jz4740_nand.c new file +252 -0
252 lines not on this page · raw message
Signature · 1 line
1.7.0.4
PATCH v4 5/7 add Ben NanoNote board
Signed-off-by Xiangfu Liu <[email protected]>
--- board/xburst/nanonote/Makefile | 45 ++++++++ board/xburst/nanonote/config.mk | 31 ++++++ board/xburst/nanonote/nanonote.c | 96 +++++++++++++++++ board/xburst/nanonote/u-boot-nand.lds | 63 +++++++++++ include/configs/nanonote.h | 188 +++++++++++++++++++++++++++++++++ include/configs/qi_lb60.h | 28 +++++ 6 files changed, 451 insertions(+), 0 deletions(-) create mode 100644 board/xburst/nanonote/Makefile create mode 100644 board/xburst/nanonote/config.mk create mode 100644 board/xburst/nanonote/nanonote.c create mode 100644 board/xburst/nanonote/u-boot-nand.lds create mode 100644 include/configs/nanonote.h create mode 100644 include/configs/qi_lb60.h
board/xburst/nanonote/Makefile new file +45 -0
@@ -0,0 +1,45 @@ +# +# (C) Copyright 2006 +# Ingenic Semiconductor, <[email protected]> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +#########################################################################
board/xburst/nanonote/config.mk new file +31 -0
@@ -0,0 +1,31 @@ +# +# (C) Copyright 2006 Qi Hardware, Inc. +# Author: Xiangfu Liu <[email protected]> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Qi Hardware, Inc. Ben NanoNote (QI_LB60) +# + +ifndef TEXT_BASE +# ROM version +# TEXT_BASE = 0x88000000 + +# RAM version +TEXT_BASE = 0x80100000 +endif
board/xburst/nanonote/nanonote.c new file +96 -0
96 lines not on this page · raw message
board/xburst/nanonote/u-boot-nand.lds new file +63 -0
63 lines not on this page · raw message
include/configs/nanonote.h new file +188 -0
188 lines not on this page · raw message
include/configs/qi_lb60.h new file +28 -0
@@ -0,0 +1,28 @@ +#ifndef __CONFIG_QI_LB60_H +#define __CONFIG_QI_LB60_H + +#include <configs/nanonote.h> + +#define CONFIG_QI_LB60 1 + +//#define DEBUG +#define CONFIG_BOOTARGS "mem=32M console=tty0 console=ttyS0,57600n8 ubi.mtd=2 rootfstype=ubifs root=ubi0:rootfs rw rootwait" +#define CONFIG_BOOTARGSFROMSD "mem=32M console=tty0 console=ttyS0,57600n8 rootfstype=ext2 root=/dev/mmcblk0p1 rw rootwait" +#define CONFIG_BOOTCOMMAND "nand read 0x80600000 0x400000 0x200000;bootm" +#define CONFIG_BOOTCOMMANDFROMSD "mmc init; ext2load mmc 0 0x80600000 /boot/uImage; bootm" + +/* SDRAM paramters */ +#define SDRAM_BW16 1/* Data bus width: 0-32bit, 1-16bit */ +#define SDRAM_BANK4 1/* Banks each chip: 0-2bank, 1-4bank */ +#define SDRAM_ROW 13/* Row address: 11 to 13 */ +#define SDRAM_COL 9/* Column address: 8 to 12 */ +#define SDRAM_CASL 2/* CAS latency: 2 or 3 */ + +/* SDRAM Timings, unit: ns */ +#define SDRAM_TRAS 45/* RAS# Active Time */ +#define SDRAM_RCD 20/* RAS# to CAS# Delay */ +#define SDRAM_TPC 20/* RAS# Precharge Time */ +#define SDRAM_TRWL 7/* Write Latency Time */ +#define SDRAM_TREF 15625/* Refresh period: 8192 cycles/64ms */ + +#endif
Signature · 1 line
1.7.0.4
PATCH v4 6/7 add entry to MAINTAINERS and boards.cfg
Signed-off-by Xiangfu Liu <[email protected]>
--- MAINTAINERS | 4 ++++ boards.cfg | 1 + 2 files changed, 5 insertions(+), 0 deletions(-)
MAINTAINERS +4 -0
@@ -900,6 +900,10 @@ Stefan Roese <[email protected]> vct_xxx MIPS32 4Kc +Xiangfu Liu <[email protected]> + + qi_lb60 MIPS32 jz4740 + ######################################################################### # Nios-II Systems: # # #
boards.cfg +1 -0
@@ -202,6 +202,7 @@ EP2500 m68k mcf52x2 ep2500 Mercury microblaze-generic microblaze microblaze microblaze-generic xilinx purple mips mips tb0229 mips mips +qi_lb60 mips mips PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xx evb64260 - - EVB64260
Signature · 1 line
1.7.0.4
PATCH v4 7/7 modify files for ben nanonote board
Signed-off-by Xiangfu Liu <[email protected]>
--- MAKEALL | 4 +++- Makefile | 10 ++++++++++ arch/mips/include/asm/global_data.h | 9 +++++++++ arch/mips/lib/board.c | 8 ++++++++ arch/mips/lib/time.c | 2 ++ 5 files changed, 32 insertions(+), 1 deletions(-)
MAKEALL +3 -1
@@ -541,7 +541,9 @@ LIST_mips=" \ ## MIPS Systems (little endian) ######################################################################### -LIST_mips4kc_el="" +LIST_mips4kc_el=" \ + qi_lb60 +" LIST_mips5kc_el=""
Makefile +10 -0
@@ -1176,6 +1176,16 @@ qemu_mips_config : unconfig @echo "#define CONFIG_QEMU_MIPS 1" >$(obj)include/config.h @$(MKCONFIG) -a qemu-mips mips mips qemu-mips +######################################################################### +## MIPS32 XBurst jz4740 +######################################################################### +qi_lb60_config : unconfig + @mkdir -p $(obj)include + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @echo "Compile NAND boot image for QI LB60" + @$(MKCONFIG) -a qi_lb60 mips xburst nanonote xburst + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + #======================================================================== # Nios #========================================================================
arch/mips/include/asm/global_data.h +9 -0
@@ -39,6 +39,15 @@ typedef struct global_data { bd_t *bd; unsigned long flags; +#if defined(CONFIG_JZSOC) + /* There are other clocks in the jz4740 */ + unsigned long cpu_clk; /* CPU core clock */ + unsigned long sys_clk; /* System bus clock */ + unsigned long per_clk; /* Peripheral bus clock */ + unsigned long mem_clk; /* Memory bus clock */ + unsigned long dev_clk; /* Device clock */ + unsigned long fb_base; /* base address of framebuffer */ +#endif unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */
arch/mips/lib/board.c +8 -0
@@ -136,10 +136,18 @@ static int init_baudrate (void)* argument, and returns an integer return code, where 0 means * "continue" and != 0 means "fatal error, hang the system". */ + +#if defined(CONFIG_JZSOC ) +extern int jzsoc_init (void ); +#endif +typedef int (init_fnc_t ) (void );init_fnc_t *init_sequence[] = { board_early_init_f, +#if defined(CONFIG_JZSOC) + jzsoc_init,/* init gpio/clocks/dram etc. */ +#endif timer_init, env_init,/* initialize environment */ #ifdef CONFIG_INCA_IP
arch/mips/lib/time.c +2 -0
@@ -24,6 +24,7 @@#include <common.h> #include <asm/mipsregs.h> +#ifndef CONFIG_JZSOC static unsigned long timestamp;/* how many counter cycles in a jiffy */
@@ -96,3 +97,4 @@ ulong get_tbclk(void) {return CONFIG_SYS_HZ ; } +#endif
Signature · 1 line
1.7.0.4
PATCH v4 4/7 jz4740 nand driver
In reply to Xiangfu Liudrivers/mtd/nand/jz4740_nand.c line 101
Quoted 6 lines · Xiangfu Liu
drivers/mtd/nand/jz4740_nand.c new file +6
-0+do { + status =readl (EMC_NFINTS ); + }while (!(status &EMC_NFINTS_ENCF )); + +/* disable ecc */ +writel (readl (EMC_NFECR ) & ~EMC_NFECR_ECCE ,EMC_NFECR );
readl() and other I/O accessors take pointers, not integer addresses.
drivers/mtd/nand/jz4740_nand.c line 104
Quoted 3 lines
drivers/mtd/nand/jz4740_nand.c new file +3
-0+ +for (i =0 ; i <9 ; i++) + ecc_code[i] = *(paraddr + i);
Use I/O accesors.
drivers/mtd/nand/jz4740_nand.c line 195
Quoted 8 lines
drivers/mtd/nand/jz4740_nand.c new file +8
-0+/* Check decoding */ +if (status &EMC_NFINTS_ERR ) { +if (status &EMC_NFINTS_UNCOR ) { +printk ("uncorrectable ecc\n" ); +return -1 ; + } + +uint32_t errcnt = (status &EMC_NFINTS_ERRCNT_MASK ) >>EMC_NFINTS_ERRCNT_BIT ;
U-Boot coding style prohibits declarations mid-block.
Quoted 8 lines
drivers/mtd/nand/jz4740_nand.c new file +8
-0+switch (errcnt) { +case 4 : +jz_rs_correct (dat, + (readl (EMC_NFERR3 ) &EMC_NFERR_INDEX_MASK ) >>EMC_NFERR_INDEX_BIT , + (readl (EMC_NFERR3 ) &EMC_NFERR_MASK_MASK ) >>EMC_NFERR_MASK_BIT ); +case 3 : + jz_rs_correct(dat, + (readl(EMC_NFERR2) & EMC_NFERR_INDEX_MASK) >> EMC_NFERR_INDEX_BIT,
drivers/mtd/nand/jz4740_nand.c line 213
Quoted 10 lines
drivers/mtd/nand/jz4740_nand.c new file +10
-0+ (readl(EMC_NFERR2) & EMC_NFERR_MASK_MASK) >> EMC_NFERR_MASK_BIT); +case 2 : +jz_rs_correct (dat, + (readl (EMC_NFERR1 ) &EMC_NFERR_INDEX_MASK ) >>EMC_NFERR_INDEX_BIT , + (readl (EMC_NFERR1 ) &EMC_NFERR_MASK_MASK ) >>EMC_NFERR_MASK_BIT ); +case 1 : +jz_rs_correct (dat, + (readl (EMC_NFERR0 ) &EMC_NFERR_INDEX_MASK ) >>EMC_NFERR_INDEX_BIT , + (readl (EMC_NFERR0 ) &EMC_NFERR_MASK_MASK ) >>EMC_NFERR_MASK_BIT ); +return errcnt;
Line length.
drivers/mtd/nand/jz4740_nand.c line 233
Quoted 1 line
drivers/mtd/nand/jz4740_nand.c new file +1
-0+writel (0x094c4400 ,EMC_SMCR1 );
Please symbolically define what went into that magic number.
-Scott
PATCH v4 4/7 jz4740 nand driver
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Quoted 4 lines · Scott Wood
Review
Quoted 1 line · Xiangfu Liu
(quoted diff) +1
-0+ writel(readl(EMC_NFECR) & ~EMC_NFECR_ECCE, EMC_NFECR);
readl()and other I/O accessors take pointers, not integer addresses.
Hi Scott
I fixed the others error, only this one I don't know how to do that. can you point me to some example.
thanks for your emails.
Quoted 7 lines
Use I/O accesors.
U-Boot coding style prohibits declarations mid-block. Line length.
Please symbolically define what went into that magic number.-Scott
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
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PATCH v4 4/7 jz4740 nand driver
Quoted 4 lines · On Sun, 9 Jan 2011 18:35:56 +0800 Xiangfu Liu <[email protected]>…
-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1On 01/05/2011 04:16 AM, Scott Wood wrote:
Quoted 8 lines
Quoted 4 lines · Xiangfu Liu
Review
Quoted 1 line
(quoted diff) +1
-0+ writel(readl(EMC_NFECR) & ~EMC_NFECR_ECCE, EMC_NFECR);
readl()and other I/O accessors take pointers, not integer addresses.Hi Scott
I fixed the others error, only this one I don't know how to do that. can you point me to some example.
You need a pointer of appropriate type (u32, in this case) that points to the address. Usually this is done with a struct that describes the register layout (e.g. struct nfc_regs in drivers/mtd/nand/mxc_nand.c).
The alternative is to cast the address to a pointer before passing it to the accessor, though Wolfgang doesn't like this.
-Scott
Scott Wood
NAKPATCH v4 3/7 jz4740 nand spl files
In reply to Xiangfu LiuQuoted 9 lines · Xiangfu Liu
Signed-off-by Xiangfu Liu <[email protected]>--- nand_spl/board/xburst/nanonote/Makefile | 96 ++++++++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++++++ nand_spl/nand_boot_jz4740.c | 344 +++++++++++++++++++++++++++++ 3 files changed, 503 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds create mode 100644 nand_spl/nand_boot_jz4740.c
I don't see any of my comments on v3 addressed or responded to:
http://lists.denx.de/pipermail/u-boot/2010-December/083601.html
NACK.
-Scott
PATCH v4 3/7 jz4740 nand spl files
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Hash: SHA1
Quoted 11 lines · Scott Wood
Quoted 9 lines · Xiangfu Liu
Signed-off-by Xiangfu Liu <[email protected]>--- nand_spl/board/xburst/nanonote/Makefile | 96 ++++++++ nand_spl/board/xburst/nanonote/u-boot.lds | 63 ++++++ nand_spl/nand_boot_jz4740.c | 344 +++++++++++++++++++++++++++++ 3 files changed, 503 insertions(+), 0 deletions(-) create mode 100644 nand_spl/board/xburst/nanonote/Makefile create mode 100644 nand_spl/board/xburst/nanonote/u-boot.lds create mode 100644 nand_spl/nand_boot_jz4740.c
Quoted 3 lines
I don't see any of my comments on v3 addressed or responded to:
http://lists.denx.de/pipermail/u-boot/2010-December/083601.html
Hi Scott
thanks the comments, I am working on the nand_boot_jz4740.c now. I try to using the system nand_boot.c, but it's need sometime. I will try to send another patch in next two days.
thanks again.
Quoted 4 lines
NACK.
-Scott
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
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v4 cover those series patches for add ben nanonote board
In reply to Xiangfu Liu-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA1
Hi All
I just got one email form Ingenic people. the "Peter <[email protected]>" doesn't work for Ingenic any more, mean the email address is abandon. and there are another two ingenic people for contact window.
Daniel <[email protected]>
ChangWei Jia <[email protected]>
I have sended those patches to them. should I add
"
Acked-by Daniel <[email protected]>
Acked-by ChangWei Jia <[email protected]>
"
in next version patch,
(I think this patch v4 still not good enough merge to upstream :)
Please give me some feedback. very thanks.
Quoted 38 lines · Xiangfu Liu
Hi Wolfgang
those patches are for add xburst jz4740 and BenNanoNote(named qi_lb60)to U-Bootsome info about xburst jz4740:
the xburst jz4740 is recently added to linux 2.6.36 and it's support the device Ben NanoNote out of box,this xburst jz4740 cpu have one feature is Boot From USB, there is a small rom in jz4740, but LOW some PIN, the cpu will boot to this small rom, then init cpu and USB module, then we can send 8KB bin file to the cpu by
USB(by using 'xbboot' or 'usbboot'[1]).which means if your bootloader is borken,(the first few KBs in NAND) you can always boot the device from usb, then reflash the nand.
in OpenMoko FreeRunner, there are NOR and NAND. when people broken the nand bootloader, it's must boot from NOR, reflash the bootloader back when people broken the NAND and NOR, he(she) must reflash by using JTAG but in Ben NanoNote, we just need boot from usb. flash the nand again :)
BTW:there are a lot of PMP, Audio device in China use the Xburst cpu, but I think they are all base on u-boot 1.1.6. by working on Ben NanoNote (http://en.qi-hardware.com) one year, we try to update the u-boot to last version and send it to upstream. :)
for more info about Ingenic Xburst JZ4740
http://www.ingenic.cn/eng/default.aspx
http://www.linux-mips.org/wiki/Ingenic====
FIXED in [PATCH v3]
1. describe what Jz4740 SoC
2. remove the ENDIANNESS in config.mk
3. don't breaks the 80-charcter-wide rule
4. get rid of #if 0
5. use proper I/O accessors to access registers.
6. remove C++ comments, cleanup code style.
Quoted 5 lines
FIXED in [PATCH v4]
1. add Entry toMAINTAINERSand boards.cfg
2. add bennanonote(qi_lb60)toMakefile
3. tested with CROSS_COMPILE=mips_4KCle- ./MAKEALLmips_el
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
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v4 cover those series patches for add ben nanonote board
Dear Xiangfu Liu,
Quoted 5 lines · In message <[email protected]> you wrote:
I have sended those patches to them. should I add
"Acked-by Daniel <[email protected]>Acked-by ChangWei Jia <[email protected]>
Please do so if and only if they explicitly send you their ACK. Normally these ACKs schould be sent to the mailing list so we all can see them.
And please do not top post / full quote.
Thanks.
Wolfgang Denk
Signature · 4 lines
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de Status quo. Latin for "the mess we're in."
v4 cover those series patches for add ben nanonote board
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Hash: SHA1
Hi Wolfgang Denk
Quoted 10 lines · Wolfgang Denk
Dear Xiangfu Liu,
Quoted 5 lines · In message <[email protected]> you wrote:
I have sended those patches to them. should I add
"Acked-by Daniel <[email protected]>Acked-by ChangWei Jia <[email protected]>Please do so if and only if they explicitly send you their ACK.
ok. got it.
Quoted 1 line
Normally these ACKs schould be sent to the mailing list so we all can
oh. the patches I send to them is just the same [PATCH v4 ...] I send to mailing list. just for them easy review the code. I will CC to them next time. :)
Quoted 4 lines
see them.
And please do not top post / full quote.
sorry.
- --
Best Regards
Xiangfu Liu
http://www.openmobilefree.net
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