arm: fix flush cache function on arm926ejs

PATCH New Lei Wen 3 participants 5 messages Jan 11, 2011 – Jan 12, 2011 Arm (32-bit)

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Lei Wen

author

2011-01-11 15:40 UTC #0 lore raw

PATCH 1/1 arm: fix flush cache function on arm926ejs

flush_cache function should only be called when the dcache is on. And original flush method for arm926ejs seems don't work, replace it with new version.

Test on Marvell Pantheon pxa920 board with usb ether function.

Signed-off-by Lei Wen <[email protected]>

---
 arch/arm/lib/cache.c |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/lib/cache.c +4 -4

index 30686fe..b8d5eee 100644
@@ -27,16 +27,16 @@
 
 void  flush_cache (unsigned long dummy1, unsigned long dummy2)
 {
+	if (!dcache_status())
+		return;
 #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
 	void arm1136_cache_flush(void);
 
 	arm1136_cache_flush();
 #endif
 #ifdef CONFIG_ARM926EJS
-	/* test and clean, page 2-23 of arm926ejs manual */
-	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-	/* disable write buffer as well (page 2-22) */
-	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+	/* clean & invalidate all D cache */
+	asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
 #endif
 #ifdef CONFIG_OMAP34XX
 	void v7_flush_cache_all(void);

Signature · 1 line

1.7.0.4

Albert ARIBAUD

2011-01-11 19:53 UTC #1 lore raw

PATCH 1/1 arm: fix flush cache function on arm926ejs

Hi,

Le 11/01/2011 16:40, Lei Wen a ?crit :

Quoted 23 lines

flush_cache function should only be called when the dcache is on. And original flush method for arm926ejs seems don't work, replace it with new version.
Test on Marvell Pantheon pxa920 board with usb ether function.
Signed-off-by Lei Wen<[email protected]>
---
  arch/arm/lib/cache.c |    8 ++++----
  1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/lib/cache.c +2 -0
index 30686fe..b8d5eee 100644
@@ -27,16 +27,16 @@
 
  void  flush_cache (unsigned long dummy1, unsigned long dummy2)
  {
+	if (!dcache_status())
+		return;
  #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
  	void arm1136_cache_flush(void);

arch/arm/lib/cache.c line 39

Quoted 10 lines

arch/arm/lib/cache.c +2 -4

 
  	arm1136_cache_flush();
  #endif
  #ifdef CONFIG_ARM926EJS
-	/* test and clean, page 2-23 of arm926ejs manual */
-	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-	/* disable write buffer as well (page 2-22) */
-	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+	/* clean&  invalidate all D cache */
+	asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));

ARM's ARM926EJ-S r0p4/r0p5 TRM does not define "... c7, c14, 0". Where did you find this exact cp15 instruction?

arch/arm/lib/cache.c line 42

Quoted 3 lines

arch/arm/lib/cache.c +0 -0

  #endif
  #ifdef CONFIG_OMAP34XX
  	void v7_flush_cache_all(void);

Amicalement,

Signature · 1 line

Albert.

Lei Wen

2011-01-12 04:27 UTC #2 lore raw

PATCH 1/1 arm: fix flush cache function on arm926ejs

Hi Albert,

Quoted 27 lines · Albert ARIBAUD

Hi,
Le 11/01/2011 16:40, Lei Wen a ?crit :
Quoted 24 lines
flush_cache function should only be called when the dcache is on. And original flush method for arm926ejs seems don't work, replace it with new version.
Test on Marvell Pantheon pxa920 board with usb ether function.
Signed-off-by Lei Wen<[email protected]>
---
? arch/arm/lib/cache.c | ? ?8 ++++----
? 1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/lib/cache.c +2 -0
index 30686fe..b8d5eee 100644
@@ -27,16 +27,16 @@
 
 ? void ?flush_cache (unsigned long dummy1, unsigned long dummy2)
 ? {
+ ? ? if (!dcache_status())
+ ? ? ? ? ? ? return;
 ? #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
 ? ? ? void arm1136_cache_flush(void);
 

Quoted 13 lines

Quoted 9 lines
arch/arm/lib/cache.c +0 -0
 ? ? ? arm1136_cache_flush();
? #endif
? #ifdef CONFIG_ARM926EJS
- ? ? /* test and clean, page 2-23 of arm926ejs manual */
- ? ? asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- ? ? /* disable write buffer as well (page 2-22) */
- ? ? asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ ? ? /* clean& ?invalidate all D cache */
+ ? ? asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
ARM's ARM926EJ-S r0p4/r0p5 TRM does not define "... c7, c14, 0". Where did you find this exact cp15 instruction?

My mistake...
Pantheon board's sheeva core modify the standard cp15 op code a bit... With one opcode, it could invalidate and clean the dcache all.

So could I modify the original patch like below?
asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
This would only invalidate all dcache. Since current dcache enable is just write-through,
I think it is safe to just do the invalidate operation.

This also could works for my board.

Best regards,
Lei

Lei Wen

2011-01-12 04:31 UTC #3 lore raw

PATCH 1/1 arm: fix flush cache function on arm926ejs

Quoted 48 lines · Lei Wen

Hi Albert,
Quoted 27 lines · Albert ARIBAUD
Hi,
Le 11/01/2011 16:40, Lei Wen a ?crit :
Quoted 24 lines
flush_cache function should only be called when the dcache is on. And original flush method for arm926ejs seems don't work, replace it with new version.
Test on Marvell Pantheon pxa920 board with usb ether function.
Signed-off-by Lei Wen<[email protected]>
---
? arch/arm/lib/cache.c | ? ?8 ++++----
? 1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/lib/cache.c +2 -0
index 30686fe..b8d5eee 100644
@@ -27,16 +27,16 @@
 
 ? void ?flush_cache (unsigned long dummy1, unsigned long dummy2)
 ? {
+ ? ? if (!dcache_status())
+ ? ? ? ? ? ? return;
 ? #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
 ? ? ? void arm1136_cache_flush(void);
 
Quoted 13 lines
Quoted 9 lines
arch/arm/lib/cache.c +0 -0
 ? ? ? arm1136_cache_flush();
? #endif
? #ifdef CONFIG_ARM926EJS
- ? ? /* test and clean, page 2-23 of arm926ejs manual */
- ? ? asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
- ? ? /* disable write buffer as well (page 2-22) */
- ? ? asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ ? ? /* clean& ?invalidate all D cache */
+ ? ? asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
ARM's ARM926EJ-S r0p4/r0p5 TRM does not define "... c7, c14, 0". Where did you find this exact cp15 instruction?
My mistake...
Pantheon board's sheeva core modify the standard cp15 op code a bit... With one opcode, it could invalidate and clean the dcache all.

Quoted 7 lines

So could I modify the original patch like below?
asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
This would only invalidate all dcache. Since current dcache enable is just write-through,
I think it is safe to just do the invalidate operation.
This also could works for my board.

I take my words back...
I forget to open the dcache... After dcache is on, the usb tftp still cannot works...
Seems still do the clean cache operation...

Best regards,
Lei

Albert ARIBAUD

2011-01-12 18:49 UTC #4 lore raw

PATCH 1/1 arm: fix flush cache function on arm926ejs

Le 12/01/2011 05:31, Lei Wen a ?crit :

Quoted 55 lines · Lei Wen

Quoted 54 lines
Hi Albert,
Quoted 27 lines · Albert ARIBAUD
Hi,
Le 11/01/2011 16:40, Lei Wen a ?crit :
Quoted 24 lines
flush_cache function should only be called when the dcache is on. And original flush method for arm926ejs seems don't work, replace it with new version.
Test on Marvell Pantheon pxa920 board with usb ether function.
Signed-off-by Lei Wen<[email protected]>
---
   arch/arm/lib/cache.c |    8 ++++----
   1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/lib/cache.c +2 -0
index 30686fe..b8d5eee 100644
@@ -27,16 +27,16 @@
 
   void  flush_cache (unsigned long dummy1, unsigned long dummy2)
   {
+     if (!dcache_status())
+             return;
   #if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
       void arm1136_cache_flush(void);
 
Quoted 13 lines
arch/arm/lib/cache.c line 39
Quoted 9 lines
arch/arm/lib/cache.c +2 -4
       arm1136_cache_flush();
   #endif
   #ifdef CONFIG_ARM926EJS
-     /* test and clean, page 2-23 of arm926ejs manual */
-     asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-     /* disable write buffer as well (page 2-22) */
-     asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+     /* clean&    invalidate all D cache */
+     asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
ARM's ARM926EJ-S r0p4/r0p5 TRM does not define "... c7, c14, 0". Where did you find this exact cp15 instruction?
My mistake...
Pantheon board's sheeva core modify the standard cp15 op code a bit... With one opcode, it could invalidate and clean the dcache all.
So could I modify the original patch like below?
asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
This would only invalidate all dcache. Since current dcache enable is just write-through,
I think it is safe to just do the invalidate operation.

Quoted 6 lines

Quoted 1 line
This also could works for my board.
I take my words back...
I forget to open the dcache... After dcache is on, the usb tftp still cannot works...
Seems still do the clean cache operation...

Anyway, changes to ARM926E-JS common code must work with existing ARM926E-JS SoCs, so this patch is NAK. Pantheon-specific cache ops should only be executed for Pantheon-based boards.

Quoted 2 lines

Best regards,
Lei

Amicalement,

Signature · 1 line

Albert.