ppc, 8xx: remove obsolete km8xx boards from keymile

The MPC852 based mgsuvd and kmsupx4 boards from keymile were initially ported but later on not developed further. So the respective files were removed to avoid unneeded merging and maintenance.

---
Changes for v2:
- fix typos in commit message
- remove boards from MAINTAINERS file

 MAINTAINERS                           |    2 -
 board/keymile/km8xx/Makefile          |   48 -----
 board/keymile/km8xx/km8xx.c           |  197 -------------------
 board/keymile/km8xx/km8xx_hdlc_enet.c |  278 ---------------------------
 board/keymile/km8xx/u-boot.lds        |   97 ----------
 boards.cfg                            |    2 -
 include/configs/km8xx.h               |  332 ---------------------------------
 include/configs/kmsupx4.h             |   43 -----
 include/configs/mgsuvd.h              |   40 ----
 9 files changed, 0 insertions(+), 1039 deletions(-)
 delete mode 100644 board/keymile/km8xx/Makefile
 delete mode 100644 board/keymile/km8xx/km8xx.c
 delete mode 100644 board/keymile/km8xx/km8xx_hdlc_enet.c
 delete mode 100644 board/keymile/km8xx/u-boot.lds
 delete mode 100644 include/configs/km8xx.h
 delete mode 100644 include/configs/kmsupx4.h
 delete mode 100644 include/configs/mgsuvd.h

index c46bc07..38056ce 100644
@@ -419,9 +419,7 @@ Heiko Schocher <[email protected]>
 	ids8247		MPC8247
 	jupiter		MPC5200
 	kmeter1		MPC8360
-	kmsupx4		MPC852T
 	mgcoge		MPC8247
-	mgsuvd		MPC852
 	mucmc52		MPC5200
 	muas3001	MPC8270
 	municse		MPC5200

b/board/keymile/km8xx/km8xx_hdlc_enet.c
deleted file mode 100644
index ca00576..0000000

index 4bc3d08..c5c0489 100644
@@ -594,8 +594,6 @@ SXNI855T                     powerpc     mpc8xx      sixnet
 v37                          powerpc     mpc8xx
 MHPC                         powerpc     mpc8xx      mhpc                eltec
 TOP860                       powerpc     mpc8xx      top860              emk
-kmsupx4                      powerpc     mpc8xx      km8xx               keymile
-mgsuvd                       powerpc     mpc8xx      km8xx               keymile
 KUP4K                        powerpc     mpc8xx      kup4k               kup
 KUP4X                        powerpc     mpc8xx      kup4x               kup
 ELPT860                      powerpc     mpc8xx      elpt860             LEOX

GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
- -/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xf0000000
-#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 kB for Monitor */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
- -/*-----------------------------------------------------------------------
- * FLASH organization
- */
-/* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_SIZE 32
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* (in ms) */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-#define CONFIG_ENV_BUFFER_PRINT 1
- -/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
-#endif
- -/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 11-9
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
- */
-#define CONFIG_SYS_SYPCR 0xffffff89
- -/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 11-6
- *-----------------------------------------------------------------------
- */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_SIUMCR 0x00610480
-#else
-#define CONFIG_SYS_SIUMCR 0x00610400
-#endif
- -/*-----------------------------------------------------------------------
- * TBSCR - Time Base Status and Control 11-26
- *-----------------------------------------------------------------------
- * Clear Reference Interrupt Status, Timebase freezing enabled
- */
-#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
- -/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 11-31
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
- */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
- -/*-----------------------------------------------------------------------
- * SCCR - System Clock and reset Control Register 15-27
- *-----------------------------------------------------------------------
- * Set clock output, timebase and RTC source and divider,
- * power management and some other internal clocks
- */
-#if defined(CONFIG_MGSUVD)
-#define SCCR_MASK 0x01800000
-#else
-#define SCCR_MASK 0x00000000
-#endif
-#define CONFIG_SYS_SCCR 0x01800000
-
-#define CONFIG_SYS_DER 0
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
-
-/* used to re-map FLASH both when starting from SRAM or FLASH:
- * restrict access enough to keep SRAM working (if any)
- * but not too much to meddle with FLASH accesses
- */
-#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
-#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
-
-/*
- * FLASH timing: Default value of OR0 after reset
- */
-#define CONFIG_SYS_OR0_PRELIM 0xfe000954
-#define CONFIG_SYS_BR0_PRELIM 0xf0000401
-
-/*
- * BR1 and OR1 (SDRAM)
- *
- */
-#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
-#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
-
-/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
-#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
-
-#define CONFIG_SYS_OR1_PRELIM 0xfc000800
-#define CONFIG_SYS_BR1_PRELIM (0x000000C0 | 0x01)
-
-#define CONFIG_SYS_MPTPR 0x0200
-/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
- 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_MBMR 0x10964111
-#else
-#define CONFIG_SYS_MBMR 0x20964111
-#endif
-#define CONFIG_SYS_MAR 0x00000088
-
-/*
- * 4096 Rows from SDRAM example configuration
- * 1000 factor s -> ms
- * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
-
-/* GPIO/PIGGY on CS3 initialization values
-*/
-#define CONFIG_SYS_PIGGY_BASE (0x30000000)
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_SYS_OR3_PRELIM (0xfe000d24)
-#define CONFIG_SYS_BR3_PRELIM (0x30000401)
-#else
-#define CONFIG_SYS_OR3_PRELIM (0xf8000d26)
-#define CONFIG_SYS_BR3_PRELIM (0x30000401)
-#endif
-
-#define CONFIG_SCC3_ENET
-#define CONFIG_ETHPRIME "SCC"
-#define CONFIG_HAS_ETH0
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_STDOUT_PATH "/soc/cpm/serial at a80"
-
-/* enable I2C and select the hardware/software driver */
-#undef CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
-/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SPEED 50000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define I2C_SOFT_DECLARATIONS
-
-/*
- * Software (bit-bang) I2C driver configuration
- */
-#define I2C_BASE_DIR ((u16 *)(CONFIG_SYS_PIGGY_BASE + 0x04))
-#define I2C_BASE_PORT ((u8 *)(CONFIG_SYS_PIGGY_BASE + 0x09))
-
-#define SDA_BIT 0x40
-#define SCL_BIT 0x80
-#define SDA_CONF 0x1000
-#define SCL_CONF 0x2000
-
-#define I2C_ACTIVE do {} while (0)
-#define I2C_TRISTATE do {} while (0)
-#define I2C_READ ((in_8(I2C_BASE_PORT) & SDA_BIT) == SDA_BIT)
-#define I2C_SDA(bit) if(bit) { \
- clrbits(be16, I2C_BASE_DIR, SDA_CONF); \
- } else { \
- clrbits(8, I2C_BASE_PORT, SDA_BIT); \
- setbits(be16, I2C_BASE_DIR, SDA_CONF); \
- }
-#define I2C_SCL(bit) if(bit) { \
- clrbits(be16, I2C_BASE_DIR, SCL_CONF); \
- } else { \
- clrbits(8, I2C_BASE_PORT, SCL_BIT); \
- setbits(be16, I2C_BASE_DIR, SCL_CONF); \
- }
-#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-
-/* I2C SYSMON (LM75, AD7414 is almost compatible) */
-#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
-#if defined(CONFIG_MGSUVD)
-#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
-#else
-#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
-#endif
-#define CONFIG_SYS_DTT_MAX_TEMP 70
-#define CONFIG_SYS_DTT_LOW_TEMP -30
-#define CONFIG_SYS_DTT_HYSTERESIS 3
-#define CONFIG_SYS_DTT_BUS_NUM (CONFIG_SYS_MAX_I2C_BUS)
-#endif /* __CONFIG_KM8XX_H */

deleted file mode 100644
index 6036da8..0000000
@@ -1,40 +0,0 @@
-/*
- * (C) Copyright 2007
- * Heiko Schocher, DENX Software Engineering, hs at denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
-#define CONFIG_MGSUVD		1	/* ...on a mgsuvd board	*/
-#define CONFIG_HOSTNAME		mgsuvd
-
-#define	CONFIG_SYS_TEXT_BASE	0xf0000000
-
-/* include common defines/options for all Keymile 8xx boards */
-#include "km8xx.h"
-
-#endif	/* __CONFIG_H */

1.7.0.5

Hallo Holger,

Thanks!

bye,
Heiko

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

Dear Holger Brunck,

Sorry, does not apply:

Applying: ppc, 8xx: remove obsolete km8xx boards from keymile
fatal: corrupt patch at line 814
Repository lacks necessary blobs to fall back on 3-way merge. Cannot fall back to three-way merge.
Patch failed at 0001 ppc, 8xx: remove obsolete km8xx boards from keymile

Please fix and resubmit.

Best regards,

Wolfgang Denk

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I'm what passes for a Unix guru in my office. This is  a  frightening
concept. - Lee Ann Goldstein, in <[email protected]>