mpc83xx:fix pcie configuration space read/write
PATCH 1/1 mpc83xx:fix pcie configuration space read/write
This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller.
--- arch/powerpc/cpu/mpc83xx/pcie.c | 19 ++++++++++++++++++- include/pci.h | 2 ++ 2 files changed, 20 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc83xx/pcie.c +18 -1
@@ -30,6 +30,20 @@ DECLARE_GLOBAL_DATA_PTR;#define PCIE_MAX_BUSES 2 +/*private struct for mpc83xx pcie hose*/ +static struct mpc83xx_pcie_priv { +u8 index; +}pcie_priv[PCIE_MAX_BUSES ] = { + { +/*pcie controller 1*/ + .index =0 , + }, + { +/*pcie controller 2*/ + .index =1 , + }, +}; + static struct { u32 base; u32 size;
@@ -52,7 +66,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) {int bus =PCI_BUS (dev) - hose->first_busno;immap_t *immr = (immap_t *)CONFIG_SYS_IMMR ; -pex83xx_t *pex = &immr->pciexp[bus]; +struct mpc83xx_pcie_priv *pcie_priv = (struct mpc83xx_pcie_priv *)hose->priv_data; +pex83xx_t *pex = &immr->pciexp[pcie_priv->index];struct pex_outbound_window *out_win = &pex->bridge.pex_outbound_win[0 ];u8 devfn =PCI_DEV (dev) <<3 |PCI_FUNC (dev);u32 dev_base = bus <<24 | devfn <<16 ;
@@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = (void *)&pcie_priv[bus]; + pci_set_ops(hose, pcie_read_config_byte, pcie_read_config_word,
include/pci.h +2 -0
@@ -420,6 +420,8 @@ struct pci_controller {/* Used by ppc405 autoconfig*/ struct pci_region *pci_fb;int current_busno; + +void *priv_data; }; extern __inline__ void pci_set_ops(struct pci_controller *hose,
Signature · 1 line
1.7.3.1.msysgit.0
PATCH 1/1 mpc83xx:fix pcie configuration space read/write
Hello.
Quoted 4 lines · Baidu Boy
This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is connected with switch or we use both of the two pcie controller.
Signed-off-by Baidu Boy <[email protected]>
[...]
arch/powerpc/cpu/mpc83xx/pcie.c DECLARE_GLOBAL_DATA_PTR; · line 34
Quoted 10 lines
arch/powerpc/cpu/mpc83xx/pcie.c +2
-0@@ -30,6 +30,20 @@ DECLARE_GLOBAL_DATA_PTR;#define PCIE_MAX_BUSES 2 +/*private struct for mpc83xx pcie hose*/ +static struct mpc83xx_pcie_priv{
Need space before { here.
arch/powerpc/cpu/mpc83xx/pcie.c DECLARE_GLOBAL_DATA_PTR; · line 36
Quoted 2 lines
arch/powerpc/cpu/mpc83xx/pcie.c +2
-0+u8 index; +}pcie_priv[PCIE_MAX_BUSES] = {
And after } here.
arch/powerpc/cpu/mpc83xx/pcie.c static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) · line 69
Quoted 6 lines
arch/powerpc/cpu/mpc83xx/pcie.c +1
-1@@ -52,7 +66,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) {int bus =PCI_BUS (dev) - hose->first_busno;immap_t *immr = (immap_t *)CONFIG_SYS_IMMR ; -pex83xx_t *pex =&immr->pciexp[bus]; +struct mpc83xx_pcie_priv *pcie_priv = (struct mpc83xx_pcie_priv *)hose->priv_data;
'priv_data' is of type 'void *', so the type cast is not needed.
arch/powerpc/cpu/mpc83xx/pcie.c static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, · line 160
Quoted 9 lines
arch/powerpc/cpu/mpc83xx/pcie.c +2
-0+pex83xx_t *pex =&immr->pciexp[pcie_priv->index];struct pex_outbound_window *out_win =&pex->bridge.pex_outbound_win[0 ];u8 devfn =PCI_DEV (dev)<<3 |PCI_FUNC (dev);u32 dev_base = bus<<24 | devfn<<16 ;@@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + hose->priv_data = (void *)&pcie_priv[bus];
Likewise, there's no need to cast to 'void *' -- the cast is automatic.
WBR, Sergei
PATCH 1/1 mpc83xx:fix pcie configuration space read/write
hi , Sergei
2011/1/16 Sergei Shtylyov <[email protected]>:
Quoted 50 lines
Hello.
Quoted 5 lines · Baidu Boy
This patch fix a problem for the pcie enumeration when the mpc83xx pcie controller is
connected with switch or we use both of the two pcie controller.Signed-off-by Baidu Boy <[email protected]>[...]
arch/powerpc/cpu/mpc83xx/pcie.c DECLARE_GLOBAL_DATA_PTR; · line 34
Quoted 11 lines
arch/powerpc/cpu/mpc83xx/pcie.c +0
-0@@ -30,6 +30,20 @@ DECLARE_GLOBAL_DATA_PTR;?#define
PCIE_MAX_BUSES2arch/powerpc/cpu/mpc83xx/pcie.c +2
-0+/*private struct for mpc83xx pcie hose*/ +static struct mpc83xx_pcie_priv{? Need space before { here.
Quoted 2 lines
+ ? ? ? u8 index;
+}pcie_priv[PCIE_MAX_BUSES] = {? And after } here.
arch/powerpc/cpu/mpc83xx/pcie.c static int mpc83xx_pcie_remap_cfg(struct pci_controller · line 71
Quoted 8 lines
arch/powerpc/cpu/mpc83xx/pcie.c +1
-1@@ -52,7 +66,8 @@ static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) ?{ ? ? ? ?int bus = PCI_BUS(dev) - hose->first_busno; ? ? ? ?immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; - ? ? ? pex83xx_t *pex =&immr->pciexp[bus]; + ? ? ? struct mpc83xx_pcie_priv *pcie_priv = (struct mpc83xx_pcie_priv *)hose->priv_data;? '
priv_data' is of type 'void *', so the type cast is not needed.Quoted 8 lines
arch/powerpc/cpu/mpc83xx/pcie.c +1
-0+ ? ? ? pex83xx_t *pex =&immr->pciexp[pcie_priv->index];? ? ? ?struct
pex_outbound_window*out_win=&pex->bridge.pex_outbound_win[0];
? ? ? ?u8 devfn = PCI_DEV(dev)<< ?3 |PCI_FUNC(dev); ? ? ? ?u32dev_base= bus<< ?24 | devfn<< ?16;arch/powerpc/cpu/mpc83xx/pcie.c +0
-0@@ -142,6 +157,8 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg,
Quoted 8 lines
arch/powerpc/cpu/mpc83xx/pcie.c static void mpc83xx_pcie_register_hose(int bus, struct · line 161
Quoted 3 lines
arch/powerpc/cpu/mpc83xx/pcie.c +1
-0? ? ? ?hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; + ? ? ? hose->priv_data = (void *)&pcie_priv[bus];? Likewise, there's no need to cast to 'void *' -- the cast is automatic.
WBR, Sergei
I have re-submit the patch:
http://patchwork.ozlabs.org/patch/79075/
Thanks