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OMAP4: hwmod data: Add McSPI

PATCH Superseded Govindraj.R 4 participants 4 messages Jan 17, 2011 – Jan 18, 2011

Subsystems (5)
Arm (32-bit) Arm sub-architectures SPI OMAP2+ support +1 more subsystems

v3 of 6 Superseded Latest is v6 →

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Govindraj.R

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#0 lore raw

PATCH v3 4/6 OMAP4: hwmod data: Add McSPI

Update omap4 hwmod file with McSPI info.

Signed-off-by Benoit Cousson <[email protected]>
Signed-off-by Charulatha V <[email protected]>
Signed-off-by Govindraj.R <[email protected]>
Acked-by Grant Likely <[email protected]>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  266 ++++++++++++++++++++++++++++
 1 files changed, 266 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +266 -0
index c2806bd..d4cd695 100644
@@ -24,6 +24,7 @@
 #include <plat/cpu.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 

@@ -2001,6 +2002,265 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+			   SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+	.name = "mcspi",
+	.sysc = &omap44xx_mcspi_sysc,
+	.rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480981ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi1_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi1_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi1_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+	&omap44xx_l4_per__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+	.num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+	.name		= "mcspi1",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi1_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_irqs),
+	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi1_slaves),
+	.dev_attr       = &omap_mcspi1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi2_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi2_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi2_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+	&omap44xx_l4_per__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+	.num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+	.name		= "mcspi2",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi2_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_irqs),
+	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi2_slaves),
+	.dev_attr       = &omap_mcspi2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+	{
+		.pa_start	= 0x480b8000,
+		.pa_end		= 0x480b81ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi3_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi3_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi3_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+	&omap44xx_l4_per__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+	.num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+	.name		= "mcspi3",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi3_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_irqs),
+	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+	.main_clk	= "mcspi3_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi3_slaves),
+	.dev_attr       = &omap_mcspi3_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+	{
+		.pa_start	= 0x480ba000,
+		.pa_end		= 0x480ba1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi4_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi4_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi4_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+	&omap44xx_l4_per__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+	.num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+	.name		= "mcspi4",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi4_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_irqs),
+	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+	.main_clk	= "mcspi4_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi4_slaves),
+	.dev_attr       = &omap_mcspi4_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* dmm class */

@@ -2068,6 +2328,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_wd_timer2_hwmod,
 	&omap44xx_wd_timer3_hwmod,
 
+	/* mcspi class */
+	&omap44xx_mcspi1_hwmod,
+	&omap44xx_mcspi2_hwmod,
+	&omap44xx_mcspi3_hwmod,
+	&omap44xx_mcspi4_hwmod,
+
 	NULL,
 };
Signature · 1 line
1.7.1
#1 lore raw

PATCH v3 4/6 OMAP4: hwmod data: Add McSPI

Quoted 6 lines · Govindraj.R

Update omap4 hwmod file with McSPI info.

Signed-off-by Benoit Cousson <[email protected]>
Signed-off-by Charulatha V <[email protected]>
Signed-off-by Govindraj.R <[email protected]>
Acked-by Grant Likely <[email protected]>

Shouldn't Benoit be the author of this patch?

Kevin

Quoted 294 lines
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  266 ++++++++++++++++++++++++++++
 1 files changed, 266 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +266 -0
index c2806bd..d4cd695 100644
@@ -24,6 +24,7 @@
 #include <plat/cpu.h>
 #include <plat/gpio.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 

@@ -2001,6 +2002,265 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+			   SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+	.name = "mcspi",
+	.sysc = &omap44xx_mcspi_sysc,
+	.rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480981ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi1_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi1_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi1_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+	&omap44xx_l4_per__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+	.num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+	.name		= "mcspi1",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi1_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_irqs),
+	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi1_slaves),
+	.dev_attr       = &omap_mcspi1_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi2_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi2_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi2_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+	&omap44xx_l4_per__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+	.num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+	.name		= "mcspi2",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi2_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_irqs),
+	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi2_slaves),
+	.dev_attr       = &omap_mcspi2_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+	{
+		.pa_start	= 0x480b8000,
+		.pa_end		= 0x480b81ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi3_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi3_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi3_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+	&omap44xx_l4_per__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+	.num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+	.name		= "mcspi3",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi3_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_irqs),
+	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+	.main_clk	= "mcspi3_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi3_slaves),
+	.dev_attr       = &omap_mcspi3_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+	{
+		.pa_start	= 0x480ba000,
+		.pa_end		= 0x480ba1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi4_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi4_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi4_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+	&omap44xx_l4_per__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+	.num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+	.name		= "mcspi4",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi4_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_irqs),
+	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+	.main_clk	= "mcspi4_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi4_slaves),
+	.dev_attr       = &omap_mcspi4_dev_attr,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* dmm class */

@@ -2068,6 +2328,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	&omap44xx_wd_timer2_hwmod,
 	&omap44xx_wd_timer3_hwmod,
 
+	/* mcspi class */
+	&omap44xx_mcspi1_hwmod,
+	&omap44xx_mcspi2_hwmod,
+	&omap44xx_mcspi3_hwmod,
+	&omap44xx_mcspi4_hwmod,
+
 	NULL,
 };
#2 lore raw

PATCH v3 4/6 OMAP4: hwmod data: Add McSPI

Quoted 10 lines · Kevin Hilman
Quoted 6 lines · Govindraj.R

Update omap4 hwmod file with McSPI info.

Signed-off-by Benoit Cousson <[email protected]>
Signed-off-by Charulatha V <[email protected]>
Signed-off-by Govindraj.R <[email protected]>
Acked-by Grant Likely <[email protected]>

Shouldn't Benoit be the author of this patch?

Sorry my mistake, will give a quick respin and post out a new version today.

--
Thanks,
Govindraj.R

Quoted 302 lines

Kevin

Quoted 284 lines

---
?arch/arm/mach-omap2/omap_hwmod_44xx_data.c | ?266 ++++++++++++++++++++++++++++ ?1 files changed, 266 insertions(+), 0 deletions(-)

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0 -0
index c2806bd..d4cd695 100644
@@ -24,6 +24,7 @@

?#include <plat/cpu.h>
?#include <plat/gpio.h>
?#include <plat/dma.h>
+#include <plat/mcspi.h>

?#include "omap_hwmod_common_data.h"

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +259 -0
@@ -2001,6 +2002,265 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
 ? ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 ?};
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+ ? ? .rev_offs ? ? ? = 0x0000,
+ ? ? .sysc_offs ? ? ?= 0x0010,
+ ? ? .sysc_flags ? ? = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+ ? ? ? ? ? ? ? ? ? ? ? ?SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),
+ ? ? .idlemodes ? ? ?= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ ? ? .sysc_fields ? ?= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+ ? ? .name = "mcspi",
+ ? ? .sysc = &omap44xx_mcspi_sysc,
+ ? ? .rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+ ? ? { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+ ? ? { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+ ? ? {
+ ? ? ? ? ? ? .pa_start ? ? ? = 0x48098000,
+ ? ? ? ? ? ? .pa_end ? ? ? ? = 0x480981ff,
+ ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT
+ ? ? },
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+ ? ? .master ? ? ? ? = &omap44xx_l4_per_hwmod,
+ ? ? .slave ? ? ? ? ?= &omap44xx_mcspi1_hwmod,
+ ? ? .clk ? ? ? ? ? ?= "l4_div_ck",
+ ? ? .addr ? ? ? ? ? = omap44xx_mcspi1_addrs,
+ ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+ ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+ ? ? &omap44xx_l4_per__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+ ? ? .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+ ? ? .name ? ? ? ? ? = "mcspi1",
+ ? ? .class ? ? ? ? ?= &omap44xx_mcspi_hwmod_class,
+ ? ? .mpu_irqs ? ? ? = omap44xx_mcspi1_irqs,
+ ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+ ? ? .sdma_reqs ? ? ?= omap44xx_mcspi1_sdma_reqs,
+ ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+ ? ? .main_clk ? ? ? = "mcspi1_fck",
+ ? ? .prcm = {
+ ? ? ? ? ? ? .omap4 = {
+ ? ? ? ? ? ? ? ? ? ? .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+ ? ? ? ? ? ? },
+ ? ? },
+ ? ? .slaves ? ? ? ? = omap44xx_mcspi1_slaves,
+ ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+ ? ? .dev_attr ? ? ? = &omap_mcspi1_dev_attr,
+ ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+ ? ? { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+ ? ? { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+ ? ? {
+ ? ? ? ? ? ? .pa_start ? ? ? = 0x4809a000,
+ ? ? ? ? ? ? .pa_end ? ? ? ? = 0x4809a1ff,
+ ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT
+ ? ? },
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+ ? ? .master ? ? ? ? = &omap44xx_l4_per_hwmod,
+ ? ? .slave ? ? ? ? ?= &omap44xx_mcspi2_hwmod,
+ ? ? .clk ? ? ? ? ? ?= "l4_div_ck",
+ ? ? .addr ? ? ? ? ? = omap44xx_mcspi2_addrs,
+ ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+ ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+ ? ? &omap44xx_l4_per__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+ ? ? .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+ ? ? .name ? ? ? ? ? = "mcspi2",
+ ? ? .class ? ? ? ? ?= &omap44xx_mcspi_hwmod_class,
+ ? ? .mpu_irqs ? ? ? = omap44xx_mcspi2_irqs,
+ ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+ ? ? .sdma_reqs ? ? ?= omap44xx_mcspi2_sdma_reqs,
+ ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+ ? ? .main_clk ? ? ? = "mcspi2_fck",
+ ? ? .prcm = {
+ ? ? ? ? ? ? .omap4 = {
+ ? ? ? ? ? ? ? ? ? ? .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+ ? ? ? ? ? ? },
+ ? ? },
+ ? ? .slaves ? ? ? ? = omap44xx_mcspi2_slaves,
+ ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+ ? ? .dev_attr ? ? ? = &omap_mcspi2_dev_attr,
+ ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+ ? ? { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+ ? ? { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+ ? ? {
+ ? ? ? ? ? ? .pa_start ? ? ? = 0x480b8000,
+ ? ? ? ? ? ? .pa_end ? ? ? ? = 0x480b81ff,
+ ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT
+ ? ? },
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+ ? ? .master ? ? ? ? = &omap44xx_l4_per_hwmod,
+ ? ? .slave ? ? ? ? ?= &omap44xx_mcspi3_hwmod,
+ ? ? .clk ? ? ? ? ? ?= "l4_div_ck",
+ ? ? .addr ? ? ? ? ? = omap44xx_mcspi3_addrs,
+ ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+ ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+ ? ? &omap44xx_l4_per__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+ ? ? .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+ ? ? .name ? ? ? ? ? = "mcspi3",
+ ? ? .class ? ? ? ? ?= &omap44xx_mcspi_hwmod_class,
+ ? ? .mpu_irqs ? ? ? = omap44xx_mcspi3_irqs,
+ ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+ ? ? .sdma_reqs ? ? ?= omap44xx_mcspi3_sdma_reqs,
+ ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+ ? ? .main_clk ? ? ? = "mcspi3_fck",
+ ? ? .prcm = {
+ ? ? ? ? ? ? .omap4 = {
+ ? ? ? ? ? ? ? ? ? ? .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+ ? ? ? ? ? ? },
+ ? ? },
+ ? ? .slaves ? ? ? ? = omap44xx_mcspi3_slaves,
+ ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+ ? ? .dev_attr ? ? ? = &omap_mcspi3_dev_attr,
+ ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+ ? ? { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+ ? ? { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+ ? ? { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+ ? ? {
+ ? ? ? ? ? ? .pa_start ? ? ? = 0x480ba000,
+ ? ? ? ? ? ? .pa_end ? ? ? ? = 0x480ba1ff,
+ ? ? ? ? ? ? .flags ? ? ? ? ?= ADDR_TYPE_RT
+ ? ? },
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+ ? ? .master ? ? ? ? = &omap44xx_l4_per_hwmod,
+ ? ? .slave ? ? ? ? ?= &omap44xx_mcspi4_hwmod,
+ ? ? .clk ? ? ? ? ? ?= "l4_div_ck",
+ ? ? .addr ? ? ? ? ? = omap44xx_mcspi4_addrs,
+ ? ? .addr_cnt ? ? ? = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+ ? ? .user ? ? ? ? ? = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+ ? ? &omap44xx_l4_per__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+ ? ? .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+ ? ? .name ? ? ? ? ? = "mcspi4",
+ ? ? .class ? ? ? ? ?= &omap44xx_mcspi_hwmod_class,
+ ? ? .mpu_irqs ? ? ? = omap44xx_mcspi4_irqs,
+ ? ? .mpu_irqs_cnt ? = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+ ? ? .sdma_reqs ? ? ?= omap44xx_mcspi4_sdma_reqs,
+ ? ? .sdma_reqs_cnt ?= ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+ ? ? .main_clk ? ? ? = "mcspi4_fck",
+ ? ? .prcm = {
+ ? ? ? ? ? ? .omap4 = {
+ ? ? ? ? ? ? ? ? ? ? .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+ ? ? ? ? ? ? },
+ ? ? },
+ ? ? .slaves ? ? ? ? = omap44xx_mcspi4_slaves,
+ ? ? .slaves_cnt ? ? = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+ ? ? .dev_attr ? ? ? = &omap_mcspi4_dev_attr,
+ ? ? .omap_chip ? ? ?= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 ?static __initdata struct omap_hwmod *omap44xx_hwmods[] = {

? ? ? /* dmm class */

arch/arm/mach-omap2/omap_hwmod_44xx_data.c +0 -0
@@ -2068,6 +2328,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 ? ? ? &omap44xx_wd_timer2_hwmod,

arch/arm/mach-omap2/omap_hwmod_44xx_data.c static __initdata struct omap_hwmod *omap44xx_hwmods[] = { · line 2338

Quoted 10 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +6 -0
 ? ? ? &omap44xx_wd_timer3_hwmod,
 
+ ? ? /* mcspi class */
+ ? ? &omap44xx_mcspi1_hwmod,
+ ? ? &omap44xx_mcspi2_hwmod,
+ ? ? &omap44xx_mcspi3_hwmod,
+ ? ? &omap44xx_mcspi4_hwmod,
+
 ? ? ? NULL,
 ?};

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#3 lore raw

PATCH v3 4/6 OMAP4: hwmod data: Add McSPI

Hi Govindraj,

Quoted 10 lines · Govindraj
Quoted 9 lines · Kevin Hilman
Quoted 6 lines · Govindraj.R

Update omap4 hwmod file with McSPI info.

Signed-off-by Benoit Cousson<[email protected]>
Signed-off-by Charulatha V<[email protected]>
Signed-off-by Govindraj.R<[email protected]>
Acked-by Grant Likely<[email protected]>
Quoted 4 lines
Quoted 1 line

Shouldn't Benoit be the author of this patch?

Sorry my mistake, will give a quick respin and post out a new version today.

Since you will respin, could you please fix the position of the data in order to stick to the original one? Same thing for the list at the end.

One flag introduced in 2.6.38 is missing, and the flags are now sorted. See comments below.

If you need to check what should be the final result after the merge of every hwmods series, you can check here:
git://gitorious.org/omap-pm/linux.git pm-wip/hwmods-omap4-full

Quoted 28 lines

--
Thanks,
Govindraj.R

Quoted 23 lines

Kevin

Quoted 20 lines
---
  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  266 ++++++++++++++++++++++++++++
  1 files changed, 266 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +1 -0
index c2806bd..d4cd695 100644
@@ -24,6 +24,7 @@
  #include<plat/cpu.h>
  #include<plat/gpio.h>
  #include<plat/dma.h>
+#include<plat/mcspi.h>
 
  #include "omap_hwmod_common_data.h"
 

@@ -2001,6 +2002,265 @@ static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
       .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
  };
Quoted 11 lines
Quoted 11 lines

arch/arm/mach-omap2/omap_hwmod_44xx_data.c static struct omap_hwmod omap44xx_wd_timer3_hwmod = { · line 2015

Quoted 11 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +11 -0
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+     .rev_offs       = 0x0000,
+     .sysc_offs      = 0x0010,
+     .sysc_flags     = (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+                        SYSC_HAS_SOFTRESET | SYSC_HAS_RESET_STATUS),

The order is slightly different due to a sort that was not done before.

.sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),

>>> + .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),

SIDLE_SMART_WKUP is missing

Quoted 254 lines
Quoted 254 lines
Quoted 254 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +247 -0
+     .sysc_fields    =&omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+     .name = "mcspi",
+     .sysc =&omap44xx_mcspi_sysc,
+     .rev = OMAP4_MCSPI_REV,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+     { .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+     { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+     { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+     { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+     { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+     {
+             .pa_start       = 0x48098000,
+             .pa_end         = 0x480981ff,
+             .flags          = ADDR_TYPE_RT
+     },
+};
+
+/* l4_per ->  mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+     .master         =&omap44xx_l4_per_hwmod,
+     .slave          =&omap44xx_mcspi1_hwmod,
+     .clk            = "l4_div_ck",
+     .addr           = omap44xx_mcspi1_addrs,
+     .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi1_addrs),
+     .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+&omap44xx_l4_per__mcspi1,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
+     .num_chipselect = 4,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+     .name           = "mcspi1",
+     .class          =&omap44xx_mcspi_hwmod_class,
+     .mpu_irqs       = omap44xx_mcspi1_irqs,
+     .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi1_irqs),
+     .sdma_reqs      = omap44xx_mcspi1_sdma_reqs,
+     .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+     .main_clk       = "mcspi1_fck",
+     .prcm = {
+             .omap4 = {
+                     .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+             },
+     },
+     .slaves         = omap44xx_mcspi1_slaves,
+     .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi1_slaves),
+     .dev_attr       =&omap_mcspi1_dev_attr,
+     .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+     { .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+     { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+     { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+     {
+             .pa_start       = 0x4809a000,
+             .pa_end         = 0x4809a1ff,
+             .flags          = ADDR_TYPE_RT
+     },
+};
+
+/* l4_per ->  mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+     .master         =&omap44xx_l4_per_hwmod,
+     .slave          =&omap44xx_mcspi2_hwmod,
+     .clk            = "l4_div_ck",
+     .addr           = omap44xx_mcspi2_addrs,
+     .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi2_addrs),
+     .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+&omap44xx_l4_per__mcspi2,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
+     .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+     .name           = "mcspi2",
+     .class          =&omap44xx_mcspi_hwmod_class,
+     .mpu_irqs       = omap44xx_mcspi2_irqs,
+     .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi2_irqs),
+     .sdma_reqs      = omap44xx_mcspi2_sdma_reqs,
+     .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+     .main_clk       = "mcspi2_fck",
+     .prcm = {
+             .omap4 = {
+                     .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+             },
+     },
+     .slaves         = omap44xx_mcspi2_slaves,
+     .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi2_slaves),
+     .dev_attr       =&omap_mcspi2_dev_attr,
+     .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+     { .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+     { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+     { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+     {
+             .pa_start       = 0x480b8000,
+             .pa_end         = 0x480b81ff,
+             .flags          = ADDR_TYPE_RT
+     },
+};
+
+/* l4_per ->  mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+     .master         =&omap44xx_l4_per_hwmod,
+     .slave          =&omap44xx_mcspi3_hwmod,
+     .clk            = "l4_div_ck",
+     .addr           = omap44xx_mcspi3_addrs,
+     .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi3_addrs),
+     .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+&omap44xx_l4_per__mcspi3,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
+     .num_chipselect = 2,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+     .name           = "mcspi3",
+     .class          =&omap44xx_mcspi_hwmod_class,
+     .mpu_irqs       = omap44xx_mcspi3_irqs,
+     .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi3_irqs),
+     .sdma_reqs      = omap44xx_mcspi3_sdma_reqs,
+     .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+     .main_clk       = "mcspi3_fck",
+     .prcm = {
+             .omap4 = {
+                     .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+             },
+     },
+     .slaves         = omap44xx_mcspi3_slaves,
+     .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi3_slaves),
+     .dev_attr       =&omap_mcspi3_dev_attr,
+     .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+     { .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+     { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+     { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+     {
+             .pa_start       = 0x480ba000,
+             .pa_end         = 0x480ba1ff,
+             .flags          = ADDR_TYPE_RT
+     },
+};
+
+/* l4_per ->  mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+     .master         =&omap44xx_l4_per_hwmod,
+     .slave          =&omap44xx_mcspi4_hwmod,
+     .clk            = "l4_div_ck",
+     .addr           = omap44xx_mcspi4_addrs,
+     .addr_cnt       = ARRAY_SIZE(omap44xx_mcspi4_addrs),
+     .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+&omap44xx_l4_per__mcspi4,
+};
+
+static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
+     .num_chipselect = 1,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+     .name           = "mcspi4",
+     .class          =&omap44xx_mcspi_hwmod_class,
+     .mpu_irqs       = omap44xx_mcspi4_irqs,
+     .mpu_irqs_cnt   = ARRAY_SIZE(omap44xx_mcspi4_irqs),
+     .sdma_reqs      = omap44xx_mcspi4_sdma_reqs,
+     .sdma_reqs_cnt  = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+     .main_clk       = "mcspi4_fck",
+     .prcm = {
+             .omap4 = {
+                     .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+             },
+     },
+     .slaves         = omap44xx_mcspi4_slaves,
+     .slaves_cnt     = ARRAY_SIZE(omap44xx_mcspi4_slaves),
+     .dev_attr       =&omap_mcspi4_dev_attr,
+     .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
  static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
       /* dmm class */

@@ -2068,6 +2328,12 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
       &omap44xx_wd_timer2_hwmod,
       &omap44xx_wd_timer3_hwmod,
Quoted 5 lines
Quoted 5 lines

arch/arm/mach-omap2/omap_hwmod_44xx_data.c static __initdata struct omap_hwmod *omap44xx_hwmods[] = { · line 2335

Quoted 5 lines
arch/arm/mach-omap2/omap_hwmod_44xx_data.c +5 -0
+     /* mcspi class */
+&omap44xx_mcspi1_hwmod,
+&omap44xx_mcspi2_hwmod,
+&omap44xx_mcspi3_hwmod,
+&omap44xx_mcspi4_hwmod,

mcspi should not be after wd_timer.

Regards,
Benoit