sh: add support for sh7757lcr board

The R0P7757LC0030RL board has SH7757, 256MB DDR3-SDRAM, SPI ROM, Ethernet, and more.

This patch supports the following functions:
?- 256MB DDR3-SDRAM
?- SPI ROM
?- Ethernet

Signed-off-by Yoshihiro Shimoda <[email protected]>

---
?about v3:
?- change my email address in Makefile and u-boot.lds

?MAINTAINERS ? ? ? ? ? ? ? ? ? ? ? ? ? ? | ? ?1 +
?arch/sh/include/asm/cpu_sh4.h ? ? ? ? ? | ? ?2 +
?arch/sh/include/asm/cpu_sh7757.h ? ? ? ?| ?218 ++++++++++++
?board/renesas/sh7757lcr/Makefile ? ? ? ?| ? 43 +++
?board/renesas/sh7757lcr/lowlevel_init.S | ?558 +++++++++++++++++++++++++++++++
?board/renesas/sh7757lcr/sh7757lcr.c ? ? | ?454 +++++++++++++++++++++++++
?board/renesas/sh7757lcr/spi-boot.c ? ? ?| ?109 ++++++
?board/renesas/sh7757lcr/u-boot.lds ? ? ?| ?101 ++++++
?boards.cfg ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?| ? ?1 +
?doc/README.sh7757lcr ? ? ? ? ? ? ? ? ? ?| ? 64 ++++
?include/configs/sh7757lcr.h ? ? ? ? ? ? | ?146 ++++++++

?11 files changed, 1697 insertions(+), 0 deletions(-) ?create mode 100644 arch/sh/include/asm/cpu_sh7757.h ?create mode 100644 board/renesas/sh7757lcr/Makefile ?create mode 100644 board/renesas/sh7757lcr/lowlevel_init.S ?create mode 100644 board/renesas/sh7757lcr/sh7757lcr.c ?create mode 100644 board/renesas/sh7757lcr/spi-boot.c ?create mode 100644 board/renesas/sh7757lcr/u-boot.lds ?create mode 100644 doc/README.sh7757lcr
?create mode 100644 include/configs/sh7757lcr.h

MAINTAINERS +0 -0

index d7cd09c..7313542 100644
@@ -1020,6 +1020,7 @@ Mark Jonas <[email protected]>

?Yoshihiro Shimoda <[email protected]>

? ? ? ?MS7720SE ? ? ? ?SH7720
+ ? ? ? R0P77570030RL ? SH7757
? ? ? ?R0P77850011RL ? SH7785

?#########################################################################

arch/sh/include/asm/cpu_sh4.h +0 -0

index fdcebd6..9b29d3a 100644
@@ -44,6 +44,8 @@

?# include <asm/cpu_sh7722.h>
?#elif defined (CONFIG_CPU_SH7723)
?# include <asm/cpu_sh7723.h>

arch/sh/include/asm/cpu_sh4.h +2 -0

+#elif defined (CONFIG_CPU_SH7757)
+# include <asm/cpu_sh7757.h>

?#elif defined (CONFIG_CPU_SH7763)
?# include <asm/cpu_sh7763.h>
?#elif defined (CONFIG_CPU_SH7780)

arch/sh/include/asm/cpu_sh7757.h new file +218 -0

new file mode 100644
index 0000000..17a6537
@@ -0,0 +1,218 @@
+/*
+ * Copyright (C) 2011 ?Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _ASM_CPU_SH7757_H_
+#define _ASM_CPU_SH7757_H_
+
+#define CCR ? ? ? ? ? ?0xFF00001C
+#define WTCNT ? ? ? ? ?0xFFCC0000
+#define CCR_CACHE_INIT 0x0000090b
+#define CACHE_OC_NUM_WAYS ? ? ?1
+
+#ifndef __ASSEMBLY__ ? ? ? ? ? /* put C only stuff in this section */
+/* MMU */
+struct mmu_regs {
+ ? ? ? unsigned int ? ?reserved[4];
+ ? ? ? unsigned int ? ?mmucr;
+};
+#define MMU_BASE ? ? ? ((struct mmu_regs *)0xff000000)
+
+/* Watchdog */
+#define WTCSR0 ? ? ? ? 0xffcc0002
+#define WRSTCSR_R ? ? ?0xffcc0003
+#define WRSTCSR_W ? ? ?0xffcc0002
+#define WTCSR_PREFIX ? ? ? ? ? 0xa500
+#define WRSTCSR_PREFIX ? ? ? ? 0x6900
+#define WRSTCSR_WOVF_PREFIX ? ?0x9600
+
+/* SCIF */
+#define SCIF0_BASE ? ? 0xfe4b0000 ? ? ?/* The real name is SCIF2 */
+#define SCIF1_BASE ? ? 0xfe4c0000 ? ? ?/* The real name is SCIF3 */
+#define SCIF2_BASE ? ? 0xfe4d0000 ? ? ?/* The real name is SCIF4 */
+
+/* SerMux */
+#define SMR0 ? ? ? ? ? 0xfe470000
+
+/* TMU0 */
+#define TSTR ? ? ? ? ? 0xFE430004
+#define TOCR ? ? ? ? ? 0xFE430000
+#define TSTR0 ? ? ? ? ?0xFE430004
+#define TCOR0 ? ? ? ? ?0xFE430008
+#define TCNT0 ? ? ? ? ?0xFE43000C
+#define TCR0 ? ? ? ? ? 0xFE430010
+#define TCOR1 ? ? ? ? ?0xFE430014
+#define TCNT1 ? ? ? ? ?0xFE430018
+#define TCR1 ? ? ? ? ? 0xFE43001C
+#define TCOR2 ? ? ? ? ?0xFE430020
+#define TCNT2 ? ? ? ? ?0xFE430024
+#define TCR2 ? ? ? ? ? 0xFE430028
+#define TCPR2 ? ? ? ? ?0xFE43002C
+
+/* ETHER, GETHER MAC address */
+struct ether_mac_regs {
+ ? ? ? unsigned int ? ?reserved[114];
+ ? ? ? unsigned int ? ?mahr;
+ ? ? ? unsigned int ? ?reserved2;
+ ? ? ? unsigned int ? ?malr;
+};
+#define GETHER0_MAC_BASE ? ? ? ((struct ether_mac_regs *)0xfee0400)
+#define GETHER1_MAC_BASE ? ? ? ((struct ether_mac_regs *)0xfee0c00)
+#define ETHER0_MAC_BASE ? ? ? ? ? ? ? ?((struct ether_mac_regs *)0xfef0000)
+#define ETHER1_MAC_BASE ? ? ? ? ? ? ? ?((struct ether_mac_regs *)0xfef0800)
+
+/* GETHER */
+struct gether_control_regs {
+ ? ? ? unsigned int ? ?gbecont;
+};
+#define GETHER_CONTROL_BASE ? ?((struct gether_control_regs *)0xffc10100)
+#define GBECONT_RMII1 ? ? ? ? ?0x00020000
+#define GBECONT_RMII0 ? ? ? ? ?0x00010000
+
+/* USB0/1 */
+struct usb_common_regs {
+ ? ? ? unsigned short ?reserved[129];
+ ? ? ? unsigned short ?suspmode;
+};
+#define USB0_COMMON_BASE ? ? ? ((struct usb_common_regs *)0xfe450000)
+#define USB1_COMMON_BASE ? ? ? ((struct usb_common_regs *)0xfe4f0000)
+
+struct usb0_phy_regs {
+ ? ? ? unsigned short ?reset;
+ ? ? ? unsigned short ?reserved[4];
+ ? ? ? unsigned short ?portsel;
+};
+#define USB0_PHY_BASE ? ? ? ? ?((struct usb0_phy_regs *)0xfe5f0000)
+
+struct usb1_port_regs {
+ ? ? ? unsigned int ? ?port1sel;
+ ? ? ? unsigned int ? ?reserved;
+ ? ? ? unsigned int ? ?usb1intsts;
+};
+#define USB1_PORT_BASE ? ? ? ? ((struct usb1_port_regs *)0xfe4f2000)
+
+struct usb1_alignment_regs {
+ ? ? ? unsigned int ? ?ehcidatac; ? ? ?/* 0xfe4fe018 */
+ ? ? ? unsigned int ? ?reserved[63];
+ ? ? ? unsigned int ? ?ohcidatac;
+};
+#define USB1_ALIGNMENT_BASE ? ?((struct usb1_alignment_regs *)0xfe4fe018)
+
+/* GCTRL, GRA */
+struct gctrl_regs {
+ ? ? ? unsigned int ? ?wprotect;
+ ? ? ? unsigned int ? ?gplldiv;
+ ? ? ? unsigned int ? ?gracr2; ? ? ? ? /* GRA */
+ ? ? ? unsigned int ? ?gracr3; ? ? ? ? /* GRA */
+ ? ? ? unsigned int ? ?reserved[4];
+ ? ? ? unsigned int ? ?fcntcr1;
+ ? ? ? unsigned int ? ?fcntcr2;
+ ? ? ? unsigned int ? ?reserved2[2];
+ ? ? ? unsigned int ? ?gpll1div;
+ ? ? ? unsigned int ? ?vcompsel;
+ ? ? ? unsigned int ? ?reserved3[62];
+ ? ? ? unsigned int ? ?fdlmon;
+ ? ? ? unsigned int ? ?reserved4[2];
+ ? ? ? unsigned int ? ?flcrmon;
+ ? ? ? unsigned int ? ?reserved5[944];
+ ? ? ? unsigned int ? ?spibootcan;
+};
+#define GCTRL_BASE ? ? ? ? ? ? ((struct gctrl_regs *)0xffc10000)
+
+/* PCIe setup */
+struct pcie_setup_regs {
+ ? ? ? unsigned int ? ?pbictl0;
+ ? ? ? unsigned int ? ?gradevctl;
+ ? ? ? unsigned int ? ?reserved[2];
+ ? ? ? unsigned int ? ?bmcinf[6];
+ ? ? ? unsigned int ? ?reserved2[118];
+ ? ? ? unsigned int ? ?idset[2];
+ ? ? ? unsigned int ? ?subidset;
+ ? ? ? unsigned int ? ?reserved3[2];
+ ? ? ? unsigned int ? ?linkconfset[4];
+ ? ? ? unsigned int ? ?trsid;
+ ? ? ? unsigned int ? ?reserved4[6];
+ ? ? ? unsigned int ? ?toutset;
+ ? ? ? unsigned int ? ?reserved5[7];
+ ? ? ? unsigned int ? ?lad0;
+ ? ? ? unsigned int ? ?ladmsk0;
+ ? ? ? unsigned int ? ?lad1;
+ ? ? ? unsigned int ? ?ladmsk1;
+ ? ? ? unsigned int ? ?lad2;
+ ? ? ? unsigned int ? ?ladmsk2;
+ ? ? ? unsigned int ? ?lad3;
+ ? ? ? unsigned int ? ?ladmsk3;
+ ? ? ? unsigned int ? ?lad4;
+ ? ? ? unsigned int ? ?ladmsk4;
+ ? ? ? unsigned int ? ?lad5;
+ ? ? ? unsigned int ? ?ladmsk5;
+ ? ? ? unsigned int ? ?reserved6[94];
+ ? ? ? unsigned int ? ?vdmrxvid[2];
+ ? ? ? unsigned int ? ?reserved7;
+ ? ? ? unsigned int ? ?pbiintfr;
+ ? ? ? unsigned int ? ?pbiinten;
+ ? ? ? unsigned int ? ?msimap;
+ ? ? ? unsigned int ? ?barmap;
+ ? ? ? unsigned int ? ?baracsize;
+ ? ? ? unsigned int ? ?advserest;
+ ? ? ? unsigned int ? ?pbictl3;
+ ? ? ? unsigned int ? ?reserved8[8];
+ ? ? ? unsigned int ? ?pbictl1;
+ ? ? ? unsigned int ? ?scratch0;
+ ? ? ? unsigned int ? ?reserved9[6];
+ ? ? ? unsigned int ? ?pbictl2;
+ ? ? ? unsigned int ? ?reserved10;
+ ? ? ? unsigned int ? ?pbirev;
+};
+#define PCIE_SETUP_BASE ? ? ? ? ? ? ? ?((struct pcie_setup_regs *)0xffca1000)
+
+struct pcie_system_bus_regs {
+ ? ? ? unsigned int ? ?reserved[3];
+ ? ? ? unsigned int ? ?endictl0;
+ ? ? ? unsigned int ? ?endictl1;
+};
+#define PCIE_SYSTEM_BUS_BASE ? ((struct pcie_system_bus_regs *)0xffca1600)
+
+
+/* PCIe-Bridge */
+struct pciebrg_regs {
+ ? ? ? unsigned short ?ctrl_h8s;
+ ? ? ? unsigned short ?reserved[7];
+ ? ? ? unsigned short ?cp_addr;
+ ? ? ? unsigned short ?reserved2;
+ ? ? ? unsigned short ?cp_data;
+ ? ? ? unsigned short ?reserved3;
+ ? ? ? unsigned short ?cp_ctrl;
+};
+#define PCIEBRG_BASE ? ? ? ? ? ((struct pciebrg_regs *)0xffd60000)
+
+/* CPU version */
+#define CCN_PRR ? ? ? ? ? ? ? ? ? ? ? ?0xff000044
+#define prr_mask(_val) ? ? ? ? ((_val >> 4) & 0xff)
+#define PRR_SH7757_B0 ? ? ? ? ?0x10
+#define PRR_SH7757_C0 ? ? ? ? ?0x11
+
+#define is_sh7757_b0(_val) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
+({ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
+ ? ? ? int __ret = prr_mask(__raw_readl(CCN_PRR)) == PRR_SH7757_B0; ? ?\
+ ? ? ? __ret; ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
+})
+#endif /* ifndef __ASSEMBLY__ */
+
+#endif /* _ASM_CPU_SH7757_H_ */

board/renesas/sh7757lcr/Makefile new file +43 -0

new file mode 100644
index 0000000..e2e46ba
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011 ?Yoshihiro Shimoda <[email protected]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB ? ?= $(obj)lib$(BOARD).o
+
+COBJS ?:= sh7757lcr.o spi-boot.o
+SOBJS ?:= lowlevel_init.o
+
+$(LIB): ? ? ? ?$(obj).depend $(COBJS) $(SOBJS)
+ ? ? ? $(call cmd_link_o_target, $(COBJS) $(SOBJS))
+
+clean:
+ ? ? ? rm -f $(SOBJS) $(OBJS)
+
+distclean: ? ? clean
+ ? ? ? rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+

board/renesas/sh7757lcr/lowlevel_init.S new file +558 -0

new file mode 100644
index 0000000..ab1aa49
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) 2011 ?Renesas Solutions Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/processor.h>
+#include <asm/macro.h>
+
+.macro or32, addr, data
+ ? ? ? mov.l \addr, r1
+ ? ? ? mov.l \data, r0
+ ? ? ? mov.l @r1, r2
+ ? ? ? or ? ?r2, r0
+ ? ? ? mov.l r0, @r1
+.endm
+
+.macro wait_DBCMD
+ ? ? ? mov.l ? DBWAIT_A, r0
+ ? ? ? mov.l ? @r0, r1
+.endm
+
+ ? ? ? .global lowlevel_init
+ ? ? ? .section ? ? ? ?.spiboot1.text
+ ? ? ? .align ?2
+
+lowlevel_init:
+
+ ? ? ? /*------- GPIO -------*/
+ ? ? ? write8 PGDR_A, ?PGDR_D ?/* eMMC power off */
+
+ ? ? ? write16 PACR_A, PACR_D
+ ? ? ? write16 PBCR_A, PBCR_D
+ ? ? ? write16 PCCR_A, PCCR_D
+ ? ? ? write16 PDCR_A, PDCR_D
+ ? ? ? write16 PECR_A, PECR_D
+ ? ? ? write16 PFCR_A, PFCR_D
+ ? ? ? write16 PGCR_A, PGCR_D
+ ? ? ? write16 PHCR_A, PHCR_D
+ ? ? ? write16 PICR_A, PICR_D
+ ? ? ? write16 PJCR_A, PJCR_D
+ ? ? ? write16 PKCR_A, PKCR_D
+ ? ? ? write16 PLCR_A, PLCR_D
+ ? ? ? write16 PMCR_A, PMCR_D
+ ? ? ? write16 PNCR_A, PNCR_D
+ ? ? ? write16 POCR_A, POCR_D
+ ? ? ? write16 PQCR_A, PQCR_D
+ ? ? ? write16 PRCR_A, PRCR_D
+ ? ? ? write16 PSCR_A, PSCR_D
+ ? ? ? write16 PTCR_A, PTCR_D
+ ? ? ? write16 PUCR_A, PUCR_D
+ ? ? ? write16 PVCR_A, PVCR_D
+ ? ? ? write16 PWCR_A, PWCR_D
+ ? ? ? write16 PXCR_A, PXCR_D
+ ? ? ? write16 PYCR_A, PYCR_D
+ ? ? ? write16 PZCR_A, PZCR_D
+ ? ? ? write16 PSEL0_A, PSEL0_D
+ ? ? ? write16 PSEL1_A, PSEL1_D
+ ? ? ? write16 PSEL2_A, PSEL2_D
+ ? ? ? write16 PSEL3_A, PSEL3_D
+ ? ? ? write16 PSEL4_A, PSEL4_D
+ ? ? ? write16 PSEL5_A, PSEL5_D
+ ? ? ? write16 PSEL6_A, PSEL6_D
+ ? ? ? write16 PSEL7_A, PSEL7_D
+ ? ? ? write16 PSEL8_A, PSEL8_D
+
+ ? ? ? bra ? ? exit_gpio
+ ? ? ? nop
+
+ ? ? ? .align ?4
+
+/*------- GPIO -------*/
+PGDR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0040
+PACR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0000
+PBCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0002
+PCCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0004
+PDCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0006
+PECR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0008
+PFCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec000a
+PGCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec000c
+PHCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec000e
+PICR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0010
+PJCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0012
+PKCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0014
+PLCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0016
+PMCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0018
+PNCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec001a
+POCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec001c
+PQCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0020
+PRCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0022
+PSCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0024
+PTCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0026
+PUCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0028
+PVCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec002a
+PWCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec002c
+PXCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec002e
+PYCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0030
+PZCR_A: ? ? ? ? ? ? ? ?.long ? 0xffec0032
+PSEL0_A: ? ? ? .long ? 0xffec0070
+PSEL1_A: ? ? ? .long ? 0xffec0072
+PSEL2_A: ? ? ? .long ? 0xffec0074
+PSEL3_A: ? ? ? .long ? 0xffec0076
+PSEL4_A: ? ? ? .long ? 0xffec0078
+PSEL5_A: ? ? ? .long ? 0xffec007a
+PSEL6_A: ? ? ? .long ? 0xffec007c
+PSEL7_A: ? ? ? .long ? 0xffec0082
+PSEL8_A: ? ? ? .long ? 0xffec0084
+
+PGDR_D: ? ? ? ? ? ? ? ?.long ? 0x80
+PACR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PBCR_D: ? ? ? ? ? ? ? ?.long ? 0x0001
+PCCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PDCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PECR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PFCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PGCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PHCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PICR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PJCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PKCR_D: ? ? ? ? ? ? ? ?.long ? 0x0003
+PLCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PMCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PNCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+POCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PQCR_D: ? ? ? ? ? ? ? ?.long ? 0xc000
+PRCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PSCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PTCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+PUCR_D: ? ? ? ? ? ? ? ?.long ? 0x0055
+#else
+PUCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+#endif
+PVCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PWCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PXCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PYCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PZCR_D: ? ? ? ? ? ? ? ?.long ? 0x0000
+PSEL0_D: ? ? ? .long ? 0xfe00
+PSEL1_D: ? ? ? .long ? 0x0000
+PSEL2_D: ? ? ? .long ? 0x3000
+PSEL3_D: ? ? ? .long ? 0xff00
+PSEL4_D: ? ? ? .long ? 0x771f
+PSEL5_D: ? ? ? .long ? 0x0ffc
+PSEL6_D: ? ? ? .long ? 0x00ff
+PSEL7_D: ? ? ? .long ? 0xfc00
+PSEL8_D: ? ? ? .long ? 0x0000
+
+ ? ? ? .align ?2
+
+exit_gpio:
+ ? ? ? mov ? ? #0, r14
+ ? ? ? mova ? ?2f, r0
+ ? ? ? mov.l ? PC_MASK, r1
+ ? ? ? tst ? ? r0, r1
+ ? ? ? bf ? ? ?2f
+
+ ? ? ? bra ? ? exit_pmb
+ ? ? ? nop
+
+ ? ? ? .align ?2
+
+/* If CPU runs on SDRAM, PC is 0x8???????. */
+PC_MASK: ? ? ? .long ? 0x20000000
+
+2:
+ ? ? ? mov ? ? #1, r14
+
+ ? ? ? mov.l ? EXPEVT_A, r0
+ ? ? ? mov.l ? @r0, r0
+ ? ? ? mov.l ? EXPEVT_POWER_ON_RESET, r1
+ ? ? ? cmp/eq ?r0, r1
+ ? ? ? bt ? ? ?1f
+
+ ? ? ? /*
+ ? ? ? ?* If EXPEVT value is manual reset or tlb multipul-hit,
+ ? ? ? ?* initialization of DDR3IF is not necessary.
+ ? ? ? ?*/
+ ? ? ? bra ? ? exit_ddr
+ ? ? ? nop
+
+1:
+ ? ? ? /* For Core Reset */
+ ? ? ? mov.l ? DBACEN_A, r0
+ ? ? ? mov.l ? @r0, r0
+ ? ? ? cmp/eq ?#0, r0
+ ? ? ? bt ? ? ?3f
+
+ ? ? ? /*
+ ? ? ? ?* If DBACEN == 1(DBSC was already enabled), we have to avoid the
+ ? ? ? ?* initialization of DDR3-SDRAM.
+ ? ? ? ?*/
+ ? ? ? bra ? ? exit_ddr
+ ? ? ? nop
+
+3:
+ ? ? ? /*------- DDR3IF -------*/
+ ? ? ? /* oscillation stabilization time */
+ ? ? ? wait_timer ? ? ?WAIT_OSC_TIME
+
+ ? ? ? /* step 3 */
+ ? ? ? write32 DBCMD_A, DBCMD_RSTL_VAL
+ ? ? ? wait_timer ? ? ?WAIT_30US
+
+ ? ? ? /* step 4 */
+ ? ? ? write32 DBCMD_A, DBCMD_PDEN_VAL
+
+ ? ? ? /* step 5 */
+ ? ? ? write32 DBKIND_A, DBKIND_D
+
+ ? ? ? /* step 6 */
+ ? ? ? write32 DBCONF_A, DBCONF_D
+ ? ? ? write32 DBTR0_A, DBTR0_D
+ ? ? ? write32 DBTR1_A, DBTR1_D
+ ? ? ? write32 DBTR2_A, DBTR2_D
+ ? ? ? write32 DBTR3_A, DBTR3_D
+ ? ? ? write32 DBTR4_A, DBTR4_D
+ ? ? ? write32 DBTR5_A, DBTR5_D
+ ? ? ? write32 DBTR6_A, DBTR6_D
+ ? ? ? write32 DBTR7_A, DBTR7_D
+ ? ? ? write32 DBTR8_A, DBTR8_D
+ ? ? ? write32 DBTR9_A, DBTR9_D
+ ? ? ? write32 DBTR10_A, DBTR10_D
+ ? ? ? write32 DBTR11_A, DBTR11_D
+ ? ? ? write32 DBTR12_A, DBTR12_D
+ ? ? ? write32 DBTR13_A, DBTR13_D
+ ? ? ? write32 DBTR14_A, DBTR14_D
+ ? ? ? write32 DBTR15_A, DBTR15_D
+ ? ? ? write32 DBTR16_A, DBTR16_D
+ ? ? ? write32 DBTR17_A, DBTR17_D
+ ? ? ? write32 DBTR18_A, DBTR18_D
+ ? ? ? write32 DBTR19_A, DBTR19_D
+ ? ? ? write32 DBRNK0_A, DBRNK0_D
+
+ ? ? ? /* step 7 */
+ ? ? ? write32 DBPDCNT3_A, DBPDCNT3_D
+
+ ? ? ? /* step 8 */
+ ? ? ? write32 DBPDCNT1_A, DBPDCNT1_D
+ ? ? ? write32 DBPDCNT2_A, DBPDCNT2_D
+ ? ? ? write32 DBPDLCK_A, DBPDLCK_D
+ ? ? ? write32 DBPDRGA_A, DBPDRGA_D
+ ? ? ? write32 DBPDRGD_A, DBPDRGD_D
+
+ ? ? ? /* step 9 */
+ ? ? ? wait_timer ? ? ?WAIT_30US
+
+ ? ? ? /* step 10 */
+ ? ? ? write32 DBPDCNT0_A, DBPDCNT0_D
+
+ ? ? ? /* step 11 */
+ ? ? ? wait_timer ? ? ?WAIT_30US
+ ? ? ? wait_timer ? ? ?WAIT_30US
+
+ ? ? ? /* step 12 */
+ ? ? ? write32 DBCMD_A, DBCMD_WAIT_VAL
+ ? ? ? wait_DBCMD
+
+ ? ? ? /* step 13 */
+ ? ? ? write32 DBCMD_A, DBCMD_RSTH_VAL
+ ? ? ? wait_DBCMD
+
+ ? ? ? /* step 14 */
+ ? ? ? write32 DBCMD_A, DBCMD_WAIT_VAL
+ ? ? ? write32 DBCMD_A, DBCMD_WAIT_VAL
+ ? ? ? write32 DBCMD_A, DBCMD_WAIT_VAL
+ ? ? ? write32 DBCMD_A, DBCMD_WAIT_VAL
+
+ ? ? ? /* step 15 */
+ ? ? ? write32 DBCMD_A, DBCMD_PDXT_VAL
+
+ ? ? ? /* step 16 */
+ ? ? ? write32 DBCMD_A, DBCMD_MRS2_VAL
+
+ ? ? ? /* step 17 */
+ ? ? ? write32 DBCMD_A, DBCMD_MRS3_VAL
+
+ ? ? ? /* step 18 */
+ ? ? ? write32 DBCMD_A, DBCMD_MRS1_VAL
+
+ ? ? ? /* step 19 */
+ ? ? ? write32 DBCMD_A, DBCMD_MRS0_VAL
+
+ ? ? ? /* step 20 */
+ ? ? ? write32 DBCMD_A, DBCMD_ZQCL_VAL
+
+ ? ? ? write32 DBCMD_A, DBCMD_REF_VAL
+ ? ? ? write32 DBCMD_A, DBCMD_REF_VAL
+ ? ? ? wait_DBCMD
+
+ ? ? ? /* step 21 */
+ ? ? ? write32 DBADJ0_A, DBADJ0_D
+ ? ? ? write32 DBADJ1_A, DBADJ1_D
+ ? ? ? write32 DBADJ2_A, DBADJ2_D
+
+ ? ? ? /* step 22 */
+ ? ? ? write32 DBRFCNF0_A, DBRFCNF0_D
+ ? ? ? write32 DBRFCNF1_A, DBRFCNF1_D
+ ? ? ? write32 DBRFCNF2_A, DBRFCNF2_D
+
+ ? ? ? /* step 23 */
+ ? ? ? write32 DBCALCNF_A, DBCALCNF_D
+
+ ? ? ? /* step 24 */
+ ? ? ? write32 DBRFEN_A, DBRFEN_D
+ ? ? ? write32 DBCMD_A, DBCMD_SRXT_VAL
+
+ ? ? ? /* step 25 */
+ ? ? ? write32 DBACEN_A, DBACEN_D
+
+ ? ? ? /* step 26 */
+ ? ? ? wait_DBCMD
+
+ ? ? ? /* enable DDR-ECC */
+ ? ? ? write32 ECD_ECDEN_A, ECD_ECDEN_D
+ ? ? ? write32 ECD_INTSR_A, ECD_INTSR_D
+ ? ? ? write32 ECD_SPACER_A, ECD_SPACER_D
+ ? ? ? write32 ECD_MCR_A, ECD_MCR_D
+
+ ? ? ? bra ? ? exit_ddr
+ ? ? ? nop
+
+ ? ? ? .align 4
+
+EXPEVT_A: ? ? ? ? ? ? ?.long ? 0xff000024
+EXPEVT_POWER_ON_RESET: .long ? 0x00000000
+
+/*------- DDR3IF -------*/
+DBCMD_A: ? ? ? .long ? 0xfe800018
+DBKIND_A: ? ? ?.long ? 0xfe800020
+DBCONF_A: ? ? ?.long ? 0xfe800024
+DBTR0_A: ? ? ? .long ? 0xfe800040
+DBTR1_A: ? ? ? .long ? 0xfe800044
+DBTR2_A: ? ? ? .long ? 0xfe800048
+DBTR3_A: ? ? ? .long ? 0xfe800050
+DBTR4_A: ? ? ? .long ? 0xfe800054
+DBTR5_A: ? ? ? .long ? 0xfe800058
+DBTR6_A: ? ? ? .long ? 0xfe80005c
+DBTR7_A: ? ? ? .long ? 0xfe800060
+DBTR8_A: ? ? ? .long ? 0xfe800064
+DBTR9_A: ? ? ? .long ? 0xfe800068
+DBTR10_A: ? ? ?.long ? 0xfe80006c
+DBTR11_A: ? ? ?.long ? 0xfe800070
+DBTR12_A: ? ? ?.long ? 0xfe800074
+DBTR13_A: ? ? ?.long ? 0xfe800078
+DBTR14_A: ? ? ?.long ? 0xfe80007c
+DBTR15_A: ? ? ?.long ? 0xfe800080
+DBTR16_A: ? ? ?.long ? 0xfe800084
+DBTR17_A: ? ? ?.long ? 0xfe800088
+DBTR18_A: ? ? ?.long ? 0xfe80008c
+DBTR19_A: ? ? ?.long ? 0xfe800090
+DBRNK0_A: ? ? ?.long ? 0xfe800100
+DBPDCNT0_A: ? ?.long ? 0xfe800200
+DBPDCNT1_A: ? ?.long ? 0xfe800204
+DBPDCNT2_A: ? ?.long ? 0xfe800208
+DBPDCNT3_A: ? ?.long ? 0xfe80020c
+DBPDLCK_A: ? ? .long ? 0xfe800280
+DBPDRGA_A: ? ? .long ? 0xfe800290
+DBPDRGD_A: ? ? .long ? 0xfe8002a0
+DBADJ0_A: ? ? ?.long ? 0xfe8000c0
+DBADJ1_A: ? ? ?.long ? 0xfe8000c4
+DBADJ2_A: ? ? ?.long ? 0xfe8000c8
+DBRFCNF0_A: ? ?.long ? 0xfe8000e0
+DBRFCNF1_A: ? ?.long ? 0xfe8000e4
+DBRFCNF2_A: ? ?.long ? 0xfe8000e8
+DBCALCNF_A: ? ?.long ? 0xfe8000f4
+DBRFEN_A: ? ? ?.long ? 0xfe800014
+DBACEN_A: ? ? ?.long ? 0xfe800010
+DBWAIT_A: ? ? ?.long ? 0xfe80001c
+
+WAIT_OSC_TIME: .long ? 6000
+WAIT_30US: ? ? .long ? 13333
+
+DBCMD_RSTL_VAL: ? ? ? ?.long ? 0x20000000
+DBCMD_PDEN_VAL: ? ? ? ?.long ? 0x1000d73c
+DBCMD_WAIT_VAL: ? ? ? ?.long ? 0x0000d73c
+DBCMD_RSTH_VAL: ? ? ? ?.long ? 0x2100d73c
+DBCMD_PDXT_VAL: ? ? ? ?.long ? 0x110000c8
+DBCMD_MRS0_VAL: ? ? ? ?.long ? 0x28000930
+DBCMD_MRS1_VAL: ? ? ? ?.long ? 0x29000004
+DBCMD_MRS2_VAL: ? ? ? ?.long ? 0x2a000008
+DBCMD_MRS3_VAL: ? ? ? ?.long ? 0x2b000000
+DBCMD_ZQCL_VAL: ? ? ? ?.long ? 0x03000200
+DBCMD_REF_VAL: .long ? 0x0c000000
+DBCMD_SRXT_VAL: ? ? ? ?.long ? 0x19000000
+DBKIND_D: ? ? ?.long ? 0x00000007
+DBCONF_D: ? ? ?.long ? 0x0f030a01
+DBTR0_D: ? ? ? .long ? 0x00000007
+DBTR1_D: ? ? ? .long ? 0x00000006
+DBTR2_D: ? ? ? .long ? 0x00000000
+DBTR3_D: ? ? ? .long ? 0x00000007
+DBTR4_D: ? ? ? .long ? 0x00070007
+DBTR5_D: ? ? ? .long ? 0x0000001b
+DBTR6_D: ? ? ? .long ? 0x00000014
+DBTR7_D: ? ? ? .long ? 0x00000005
+DBTR8_D: ? ? ? .long ? 0x00000015
+DBTR9_D: ? ? ? .long ? 0x00000006
+DBTR10_D: ? ? ?.long ? 0x00000008
+DBTR11_D: ? ? ?.long ? 0x00000007
+DBTR12_D: ? ? ?.long ? 0x0000000e
+DBTR13_D: ? ? ?.long ? 0x00000056
+DBTR14_D: ? ? ?.long ? 0x00000006
+DBTR15_D: ? ? ?.long ? 0x00000004
+DBTR16_D: ? ? ?.long ? 0x00150002
+DBTR17_D: ? ? ?.long ? 0x000c0017
+DBTR18_D: ? ? ?.long ? 0x00000200
+DBTR19_D: ? ? ?.long ? 0x00000040
+DBRNK0_D: ? ? ?.long ? 0x00000001
+DBPDCNT0_D: ? ?.long ? 0x00000001
+DBPDCNT1_D: ? ?.long ? 0x00000001
+DBPDCNT2_D: ? ?.long ? 0x00000000
+DBPDCNT3_D: ? ?.long ? 0x00004010
+DBPDLCK_D: ? ? .long ? 0x0000a55a
+DBPDRGA_D: ? ? .long ? 0x00000028
+DBPDRGD_D: ? ? .long ? 0x00017100
+
+DBADJ0_D: ? ? ?.long ? 0x00000000
+DBADJ1_D: ? ? ?.long ? 0x00000000
+DBADJ2_D: ? ? ?.long ? 0x18061806
+DBRFCNF0_D: ? ?.long ? 0x000001ff
+DBRFCNF1_D: ? ?.long ? 0x08001000
+DBRFCNF2_D: ? ?.long ? 0x00000000
+DBCALCNF_D: ? ?.long ? 0x0000ffff
+DBRFEN_D: ? ? ?.long ? 0x00000001
+DBACEN_D: ? ? ?.long ? 0x00000001
+
+/*------- DDR-ECC -------*/
+ECD_ECDEN_A: ? .long ? 0xffc1012c
+ECD_ECDEN_D: ? .long ? 0x00000001
+ECD_INTSR_A: ? .long ? 0xfe900024
+ECD_INTSR_D: ? .long ? 0xffffffff
+ECD_SPACER_A: ?.long ? 0xfe900018
+ECD_SPACER_D: ?.long ? SH7757LCR_SDRAM_ECC_SETTING
+ECD_MCR_A: ? ? .long ? 0xfe900010
+ECD_MCR_D: ? ? .long ? 0x00000001
+
+ ? ? ? .align 2
+exit_ddr:
+
+#if defined(CONFIG_SH_32BIT)
+ ? ? ? /*------- set PMB -------*/
+ ? ? ? write32 PASCR_A, ? ? ? ?PASCR_29BIT_D
+ ? ? ? write32 MMUCR_A, ? ? ? ?MMUCR_D
+
+ ? ? ? /*****************************************************************
+ ? ? ? ?* ent ?virt ? ? ? ? ? ?phys ? ? ? ? ? ?v ? ? ? sz ? ? ?c ? ? ? wt
+ ? ? ? ?* 0 ? ?0xa0000000 ? ? ?0x00000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ ? ? ? ?* 1 ? ?0xa8000000 ? ? ?0x48000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ ? ? ? ?* 5 ? ?0x88000000 ? ? ?0x48000000 ? ? ?1 ? ? ? 128M ? ?1 ? ? ? 1
+ ? ? ? ?*/
+ ? ? ? write32 PMB_ADDR_SPIBOOT_A, ? ? PMB_ADDR_SPIBOOT_D
+ ? ? ? write32 PMB_DATA_SPIBOOT_A, ? ? PMB_DATA_SPIBOOT_D
+ ? ? ? write32 PMB_ADDR_DDR_C1_A, ? ? ?PMB_ADDR_DDR_C1_D
+ ? ? ? write32 PMB_DATA_DDR_C1_A, ? ? ?PMB_DATA_DDR_C1_D
+ ? ? ? write32 PMB_ADDR_DDR_N1_A, ? ? ?PMB_ADDR_DDR_N1_D
+ ? ? ? write32 PMB_DATA_DDR_N1_A, ? ? ?PMB_DATA_DDR_N1_D
+
+ ? ? ? write32 PMB_ADDR_ENTRY2, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY3, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY4, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY6, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY7, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY8, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY9, ? ? ? ?PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY10, ? ? ? PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY11, ? ? ? PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY12, ? ? ? PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY13, ? ? ? PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY14, ? ? ? PMB_ADDR_NOT_USE_D
+ ? ? ? write32 PMB_ADDR_ENTRY15, ? ? ? PMB_ADDR_NOT_USE_D
+
+ ? ? ? write32 PASCR_A, ? ? ? ?PASCR_INIT
+ ? ? ? mov.l ? DUMMY_ADDR, r0
+ ? ? ? icbi ? ?@r0
+#endif /* if defined(CONFIG_SH_32BIT) */
+
+exit_pmb:
+ ? ? ? /* CPU is running on ILRAM? */
+ ? ? ? mov ? ? r14, r0
+ ? ? ? tst ? ? #1, r0
+ ? ? ? bt ? ? ?1f
+
+ ? ? ? mov.l ? _bss_start, r15
+ ? ? ? mov.l ? _spiboot_main, r0
+100: ? bsrf ? ?r0
+ ? ? ? nop
+
+ ? ? ? .align ?2
+_spiboot_main: .long ? (spiboot_main - (100b + 4))
+_bss_start: ? ?.long ? bss_start
+
+1:
+
+ ? ? ? write32 CCR_A, ?CCR_D
+
+ ? ? ? rts
+ ? ? ? ?nop
+
+ ? ? ? .align 4
+
+#if defined(CONFIG_SH_32BIT)
+/*------- set PMB -------*/
+PMB_ADDR_SPIBOOT_A: ? ?.long ? PMB_ADDR_BASE(0)
+PMB_ADDR_DDR_N1_A: ? ? .long ? PMB_ADDR_BASE(1)
+PMB_ADDR_DDR_C1_A: ? ? .long ? PMB_ADDR_BASE(5)
+PMB_ADDR_ENTRY2: ? ? ? .long ? PMB_ADDR_BASE(2)
+PMB_ADDR_ENTRY3: ? ? ? .long ? PMB_ADDR_BASE(3)
+PMB_ADDR_ENTRY4: ? ? ? .long ? PMB_ADDR_BASE(4)
+PMB_ADDR_ENTRY6: ? ? ? .long ? PMB_ADDR_BASE(6)
+PMB_ADDR_ENTRY7: ? ? ? .long ? PMB_ADDR_BASE(7)
+PMB_ADDR_ENTRY8: ? ? ? .long ? PMB_ADDR_BASE(8)
+PMB_ADDR_ENTRY9: ? ? ? .long ? PMB_ADDR_BASE(9)
+PMB_ADDR_ENTRY10: ? ? ?.long ? PMB_ADDR_BASE(10)
+PMB_ADDR_ENTRY11: ? ? ?.long ? PMB_ADDR_BASE(11)
+PMB_ADDR_ENTRY12: ? ? ?.long ? PMB_ADDR_BASE(12)
+PMB_ADDR_ENTRY13: ? ? ?.long ? PMB_ADDR_BASE(13)
+PMB_ADDR_ENTRY14: ? ? ?.long ? PMB_ADDR_BASE(14)
+PMB_ADDR_ENTRY15: ? ? ?.long ? PMB_ADDR_BASE(15)
+
+PMB_ADDR_SPIBOOT_D: ? ?.long ? mk_pmb_addr_val(0xa0)
+PMB_ADDR_DDR_C1_D: ? ? .long ? mk_pmb_addr_val(0x88)
+PMB_ADDR_DDR_N1_D: ? ? .long ? mk_pmb_addr_val(0xa8)
+PMB_ADDR_NOT_USE_D: ? ?.long ? 0x00000000
+
+PMB_DATA_SPIBOOT_A: ? ?.long ? PMB_DATA_BASE(0)
+PMB_DATA_DDR_N1_A: ? ? .long ? PMB_DATA_BASE(1)
+PMB_DATA_DDR_C1_A: ? ? .long ? PMB_DATA_BASE(5)
+
+/* ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ppn ? ub v s1 s0 ?c ?wt */
+PMB_DATA_SPIBOOT_D: ? ?.long ? mk_pmb_data_val(0x00, 0, 1, 1, 0, 0, 1)
+PMB_DATA_DDR_C1_D: ? ? .long ? mk_pmb_data_val(0x48, 0, 1, 1, 0, 1, 1)
+PMB_DATA_DDR_N1_D: ? ? .long ? mk_pmb_data_val(0x48, 1, 1, 1, 0, 0, 1)
+
+PASCR_A: ? ? ? ? ? ? ? .long ? 0xff000070
+DUMMY_ADDR: ? ? ? ? ? ?.long ? 0xa0000000
+PASCR_29BIT_D: ? ? ? ? .long ? 0x00000000
+PASCR_INIT: ? ? ? ? ? ?.long ? 0x80000080
+MMUCR_A: ? ? ? ? ? ? ? .long ? 0xff000010
+MMUCR_D: ? ? ? ? ? ? ? .long ? 0x00000004 ? ? ?/* clear ITLB */
+#endif /* CONFIG_SH_32BIT */
+
+CCR_A: ? ? ? ? .long ? CCR
+CCR_D: ? ? ? ? .long ? CCR_CACHE_INIT

board/renesas/sh7757lcr/sh7757lcr.c new file +454 -0

new file mode 100644
index 0000000..a62be24
@@ -0,0 +1,454 @@
+/*
+ * Copyright (C) 2011 ?Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+#include <spi_flash.h>
+
+int checkboard(void)
+{
+ ? ? ? puts("BOARD: R0P7757LC0030RL board\n");
+
+ ? ? ? return 0;
+}
+
+static void init_gctrl(void)
+{
+ ? ? ? struct gctrl_regs *gctrl = GCTRL_BASE;
+ ? ? ? unsigned long graofst;
+
+ ? ? ? graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ ? ? ? writel(graofst | 0x20000f00, &gctrl->gracr3);
+}
+
+static int init_pcie_bridge_from_spi(void *buf, size_t size)
+{
+ ? ? ? struct spi_flash *spi;
+ ? ? ? int ret;
+ ? ? ? unsigned long pcie_addr;
+
+ ? ? ? spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ ? ? ? if (!spi) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash probe error.\n", __func__);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+
+ ? ? ? if (is_sh7757_b0())
+ ? ? ? ? ? ? ? pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
+ ? ? ? else
+ ? ? ? ? ? ? ? pcie_addr = SH7757LCR_PCIEBRG_ADDR;
+
+ ? ? ? ret = spi_flash_read(spi, pcie_addr, size, buf);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash read error.\n", __func__);
+ ? ? ? ? ? ? ? spi_flash_free(spi);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+ ? ? ? spi_flash_free(spi);
+
+ ? ? ? return 0;
+}
+
+static void init_pcie_bridge(void)
+{
+ ? ? ? struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
+ ? ? ? struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ ? ? ? int i;
+ ? ? ? unsigned char *data;
+ ? ? ? unsigned short tmp;
+ ? ? ? unsigned long pcie_size;
+
+ ? ? ? if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
+ ? ? ? ? ? ? ? return;
+
+ ? ? ? if (is_sh7757_b0())
+ ? ? ? ? ? ? ? pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
+ ? ? ? else
+ ? ? ? ? ? ? ? pcie_size = SH7757LCR_PCIEBRG_SIZE;
+
+ ? ? ? data = malloc(pcie_size);
+ ? ? ? if (!data) {
+ ? ? ? ? ? ? ? printf("%s: malloc error.\n", __func__);
+ ? ? ? ? ? ? ? return;
+ ? ? ? }
+ ? ? ? if (init_pcie_bridge_from_spi(data, pcie_size)) {
+ ? ? ? ? ? ? ? free(data);
+ ? ? ? ? ? ? ? return;
+ ? ? ? }
+
+ ? ? ? if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
+ ? ? ? ? ? data[3] == 0xff) {
+ ? ? ? ? ? ? ? free(data);
+ ? ? ? ? ? ? ? printf("%s: skipped initialization\n", __func__);
+ ? ? ? ? ? ? ? return;
+ ? ? ? }
+
+ ? ? ? writew(0xa501, &pciebrg->ctrl_h8s); ? ? /* reset */
+ ? ? ? writew(0x0000, &pciebrg->cp_ctrl);
+ ? ? ? writew(0x0000, &pciebrg->cp_addr);
+
+ ? ? ? for (i = 0; i < pcie_size; i += 2) {
+ ? ? ? ? ? ? ? tmp = (data[i] << 8) | data[i + 1];
+ ? ? ? ? ? ? ? writew(tmp, &pciebrg->cp_data);
+ ? ? ? }
+
+ ? ? ? writew(0xa500, &pciebrg->ctrl_h8s); ? ? /* start */
+ ? ? ? if (!is_sh7757_b0())
+ ? ? ? ? ? ? ? writel(0x00000001, &pcie_setup->pbictl3);
+
+ ? ? ? free(data);
+}
+
+static void init_usb_phy(void)
+{
+ ? ? ? struct usb_common_regs *common0 = USB0_COMMON_BASE;
+ ? ? ? struct usb_common_regs *common1 = USB1_COMMON_BASE;
+ ? ? ? struct usb0_phy_regs *phy = USB0_PHY_BASE;
+ ? ? ? struct usb1_port_regs *port = USB1_PORT_BASE;
+ ? ? ? struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
+
+ ? ? ? writew(0x0100, &phy->reset); ? ? ? ? ? ?/* set reset */
+ ? ? ? /* port0 = USB0, port1 = USB1 */
+ ? ? ? writew(0x0002, &phy->portsel);
+ ? ? ? writel(0x0001, &port->port1sel); ? ? ? ?/* port1 = Host */
+ ? ? ? writew(0x0111, &phy->reset); ? ? ? ? ? ?/* clear reset */
+
+ ? ? ? writew(0x4000, &common0->suspmode);
+ ? ? ? writew(0x4000, &common1->suspmode);
+
+#if defined(__LITTLE_ENDIAN)
+ ? ? ? writel(0x00000000, &align->ehcidatac);
+ ? ? ? writel(0x00000000, &align->ohcidatac);
+#endif
+}
+
+static void set_mac_to_sh_eth_register(int channel, char *mac_string)
+{
+ ? ? ? struct ether_mac_regs *ether;
+ ? ? ? unsigned char mac[6];
+ ? ? ? unsigned long val;
+
+ ? ? ? eth_parse_enetaddr(mac_string, mac);
+
+ ? ? ? if (!channel)
+ ? ? ? ? ? ? ? ether = ETHER0_MAC_BASE;
+ ? ? ? else
+ ? ? ? ? ? ? ? ether = ETHER1_MAC_BASE;
+
+ ? ? ? val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ ? ? ? writel(val, &ether->mahr);
+ ? ? ? val = (mac[4] << 8) | mac[5];
+ ? ? ? writel(val, &ether->malr);
+}
+
+static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
+{
+ ? ? ? struct ether_mac_regs *ether;
+ ? ? ? unsigned char mac[6];
+ ? ? ? unsigned long val;
+
+ ? ? ? eth_parse_enetaddr(mac_string, mac);
+
+ ? ? ? if (!channel)
+ ? ? ? ? ? ? ? ether = GETHER0_MAC_BASE;
+ ? ? ? else
+ ? ? ? ? ? ? ? ether = GETHER1_MAC_BASE;
+
+ ? ? ? val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
+ ? ? ? writel(val, &ether->mahr);
+ ? ? ? val = (mac[4] << 8) | mac[5];
+ ? ? ? writel(val, &ether->malr);
+}
+
+/*****************************************************************
+ * This PMB must be set on this timing. The lowlevel_init is run on
+ * Area 0(phys 0x00000000), so we have to map it.
+ *
+ * The new PMB table is following:
+ * ent virt ? ? ? ? ? ?phys ? ? ? ? ? ?v ? ? ? sz ? ? ?c ? ? ? wt
+ * 0 ? 0xa0000000 ? ? ?0x40000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ * 1 ? 0xa8000000 ? ? ?0x48000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ * 2 ? 0xb0000000 ? ? ?0x50000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ * 3 ? 0xb8000000 ? ? ?0x58000000 ? ? ?1 ? ? ? 128M ? ?0 ? ? ? 1
+ * 4 ? 0x80000000 ? ? ?0x40000000 ? ? ?1 ? ? ? 128M ? ?1 ? ? ? 1
+ * 5 ? 0x88000000 ? ? ?0x48000000 ? ? ?1 ? ? ? 128M ? ?1 ? ? ? 1
+ * 6 ? 0x90000000 ? ? ?0x50000000 ? ? ?1 ? ? ? 128M ? ?1 ? ? ? 1
+ * 7 ? 0x98000000 ? ? ?0x58000000 ? ? ?1 ? ? ? 128M ? ?1 ? ? ? 1
+ */
+static void set_pmb_on_board_init(void)
+{
+ ? ? ? struct mmu_regs *mmu = MMU_BASE;
+
+ ? ? ? /* clear ITLB */
+ ? ? ? writel(0x00000004, &mmu->mmucr);
+
+ ? ? ? /* delete PMB for SPIBOOT */
+ ? ? ? writel(0, PMB_ADDR_BASE(0));
+ ? ? ? writel(0, PMB_DATA_BASE(0));
+
+ ? ? ? /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
+ ? ? ? /* ? ? ? ? ? ? ? ? ? ? ?ppn ?ub v s1 s0 ?c ?wt */
+ ? ? ? writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
+ ? ? ? writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
+ ? ? ? writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
+ ? ? ? writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
+ ? ? ? writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
+ ? ? ? writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
+ ? ? ? writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
+ ? ? ? writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
+ ? ? ? writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
+ ? ? ? writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
+ ? ? ? writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
+ ? ? ? writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
+}
+
+int board_init(void)
+{
+ ? ? ? struct gether_control_regs *gether = GETHER_CONTROL_BASE;
+
+ ? ? ? set_pmb_on_board_init();
+
+ ? ? ? /* enable RMII's MDIO (disable GRMII's MDIO) */
+ ? ? ? writel(0x00030000, &gether->gbecont);
+
+ ? ? ? init_gctrl();
+ ? ? ? init_usb_phy();
+
+ ? ? ? return 0;
+}
+
+int dram_init(void)
+{
+ ? ? ? DECLARE_GLOBAL_DATA_PTR;
+
+ ? ? ? gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+ ? ? ? gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+ ? ? ? printf("DRAM: ?%dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
+ ? ? ? printf(" ? ?Physical address\n");
+ ? ? ? printf(" ? ?0x%08x - 0x%08x : Accessible Space as ECC Area\n",
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP,
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE - 1);
+ ? ? ? printf(" ? ?0x%08x - 0x%08x : No Access Area\n",
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE,
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_SIZE * 2 - 1);
+ ? ? ? printf(" ? ?0x%08x - 0x%08x : Non-ECC Area for DVC/AVC\n",
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2,
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_SDRAM_ECC_SETTING * 2 +
+ ? ? ? ? ? ? ? ? ? ? ? SH7757LCR_SDRAM_DVC_SIZE - 1);
+ ? ? ? printf(" ? ?0x%08x - 0x%08x : Non-ECC Area for G200eR2\n",
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET,
+ ? ? ? ? ? ? ? SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET + 0x00ffffff);
+
+ ? ? ? return 0;
+}
+
+static int get_sh_eth_mac_raw(unsigned char *buf, int size)
+{
+ ? ? ? struct spi_flash *spi;
+ ? ? ? int ret;
+
+ ? ? ? spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ ? ? ? if (spi == NULL) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash probe error.\n", __func__);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+
+ ? ? ? ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash read error.\n", __func__);
+ ? ? ? ? ? ? ? spi_flash_free(spi);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+ ? ? ? spi_flash_free(spi);
+
+ ? ? ? return 0;
+}
+
+static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
+{
+ ? ? ? memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
+ ? ? ? ? ? ? ? SH7757LCR_ETHERNET_MAC_SIZE);
+ ? ? ? mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
+
+ ? ? ? return 0;
+}
+
+static void init_ethernet_mac(void)
+{
+ ? ? ? char mac_string[64];
+ ? ? ? char env_string[64];
+ ? ? ? int i;
+ ? ? ? unsigned char *buf;
+
+ ? ? ? buf = malloc(256);
+ ? ? ? if (!buf) {
+ ? ? ? ? ? ? ? printf("%s: malloc error.\n", __func__);
+ ? ? ? ? ? ? ? return;
+ ? ? ? }
+ ? ? ? get_sh_eth_mac_raw(buf, 256);
+
+ ? ? ? /* Fast Ethernet */
+ ? ? ? for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
+ ? ? ? ? ? ? ? get_sh_eth_mac(i, mac_string, buf);
+ ? ? ? ? ? ? ? if (i == 0)
+ ? ? ? ? ? ? ? ? ? ? ? setenv("ethaddr", mac_string);
+ ? ? ? ? ? ? ? else {
+ ? ? ? ? ? ? ? ? ? ? ? sprintf(env_string, "eth%daddr", i);
+ ? ? ? ? ? ? ? ? ? ? ? setenv(env_string, mac_string);
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? set_mac_to_sh_eth_register(i, mac_string);
+ ? ? ? }
+
+ ? ? ? /* Gigabit Ethernet */
+ ? ? ? for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
+ ? ? ? ? ? ? ? get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
+ ? ? ? ? ? ? ? sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
+ ? ? ? ? ? ? ? setenv(env_string, mac_string);
+
+ ? ? ? ? ? ? ? set_mac_to_sh_giga_eth_register(i, mac_string);
+ ? ? ? }
+
+ ? ? ? free(buf);
+}
+
+static void init_pcie(void)
+{
+ ? ? ? struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
+ ? ? ? struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
+
+ ? ? ? writel(0x00000ff2, &pcie_setup->ladmsk0);
+ ? ? ? writel(0x00000001, &pcie_setup->barmap);
+ ? ? ? writel(0xffcaa000, &pcie_setup->lad0);
+ ? ? ? writel(0x00030000, &pcie_sysbus->endictl0);
+ ? ? ? writel(0x00000003, &pcie_sysbus->endictl1);
+ ? ? ? writel(0x00000004, &pcie_setup->pbictl2);
+}
+
+static void finish_spiboot(void)
+{
+ ? ? ? struct gctrl_regs *gctrl = GCTRL_BASE;
+ ? ? ? /*
+ ? ? ? ?* ?SH7757 B0 does not use LBSC.
+ ? ? ? ?* ?So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
+ ? ? ? ?* ?This setting is not cleared by manual reset, So we have to set it
+ ? ? ? ?* ?to 0.
+ ? ? ? ?*/
+ ? ? ? writel(0x00000000, &gctrl->spibootcan);
+}
+
+int board_late_init(void)
+{
+ ? ? ? init_ethernet_mac();
+ ? ? ? init_pcie_bridge();
+ ? ? ? init_pcie();
+ ? ? ? finish_spiboot();
+
+ ? ? ? return 0;
+}
+
+int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ? ? ? struct gctrl_regs *gctrl = GCTRL_BASE;
+ ? ? ? unsigned long graofst;
+
+ ? ? ? writel(0xfedcba98, &gctrl->wprotect);
+ ? ? ? graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
+ ? ? ? writel(graofst | 0xa0000f00, &gctrl->gracr3);
+
+ ? ? ? return 0;
+}
+
+U_BOOT_CMD(
+ ? ? ? sh_g200, ? ? ? ?1, ? ? ?1, ? ? ?do_sh_g200,
+ ? ? ? "enable sh-g200",
+ ? ? ? "enable SH-G200 bus (disable PCIe-G200)"
+);
+
+int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ ? ? ? int i, ret;
+ ? ? ? char mac_string[256];
+ ? ? ? struct spi_flash *spi;
+ ? ? ? unsigned char *buf;
+
+ ? ? ? if (argc != 5) {
+ ? ? ? ? ? ? ? buf = malloc(256);
+ ? ? ? ? ? ? ? if (!buf) {
+ ? ? ? ? ? ? ? ? ? ? ? printf("%s: malloc error.\n", __func__);
+ ? ? ? ? ? ? ? ? ? ? ? return 1;
+ ? ? ? ? ? ? ? }
+
+ ? ? ? ? ? ? ? get_sh_eth_mac_raw(buf, 256);
+
+ ? ? ? ? ? ? ? /* print current MAC address */
+ ? ? ? ? ? ? ? for (i = 0; i < 4; i++) {
+ ? ? ? ? ? ? ? ? ? ? ? get_sh_eth_mac(i, mac_string, buf);
+ ? ? ? ? ? ? ? ? ? ? ? if (i < 2)
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf(" ETHERC ch%d = %s\n", i, mac_string);
+ ? ? ? ? ? ? ? ? ? ? ? else
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? printf("GETHERC ch%d = %s\n", i-2, mac_string);
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? free(buf);
+ ? ? ? ? ? ? ? return 0;
+ ? ? ? }
+
+ ? ? ? /* new setting */
+ ? ? ? memset(mac_string, 0xff, sizeof(mac_string));
+ ? ? ? sprintf(mac_string, "%s\t%s\t%s\t%s",
+ ? ? ? ? ? ? ? argv[1], argv[2], argv[3], argv[4]);
+
+ ? ? ? /* write MAC data to SPI rom */
+ ? ? ? spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
+ ? ? ? if (!spi) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash probe error.\n", __func__);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+
+ ? ? ? ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SH7757LCR_SPI_SECTOR_SIZE);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash erase error.\n", __func__);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+
+ ? ? ? ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? sizeof(mac_string), mac_string);
+ ? ? ? if (ret) {
+ ? ? ? ? ? ? ? printf("%s: spi_flash write error.\n", __func__);
+ ? ? ? ? ? ? ? spi_flash_free(spi);
+ ? ? ? ? ? ? ? return 1;
+ ? ? ? }
+ ? ? ? spi_flash_free(spi);
+
+ ? ? ? puts("The writing of the MAC address to SPI ROM was completed.\n");
+
+ ? ? ? return 0;
+}
+
+U_BOOT_CMD(
+ ? ? ? write_mac, ? ? ?5, ? ? ?1, ? ? ?do_write_mac,
+ ? ? ? "write MAC address for ETHERC/GETHERC",
+ ? ? ? "[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
+);

board/renesas/sh7757lcr/spi-boot.c new file +109 -0

new file mode 100644
index 0000000..823844e
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2011 ?Renesas Solutions Corp.
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License. ?See the file "COPYING.LIB" in the main
+ * directory of this archive for more details.
+ */
+
+#include <common.h>
+
+#define CONFIG_RAM_BOOT_PHYS ? 0x4ef80000
+#if defined(CONFIG_SH7757_OFFSET_SPI)
+#define CONFIG_SPI_ADDR ? ? ? ? ? ? ? ?0x00010000
+#else
+#define CONFIG_SPI_ADDR ? ? ? ? ? ? ? ?0x00000000
+#endif
+#define CONFIG_SPI_LENGTH ? ? ?0x00030000
+#define CONFIG_RAM_BOOT ? ? ? ? ? ? ? ?0x8ef80000
+
+#define SPIWDMADR ? ? ?0xFE001018
+#define SPIWDMCNTR ? ? 0xFE001020
+#define SPIDMCOR ? ? ? 0xFE001028
+#define SPIDMINTSR ? ? 0xFE001188
+#define SPIDMINTMR ? ? 0xFE001190
+
+#define SPIDMINTSR_DMEND ? ? ? 0x00000004
+
+#define TBR ? ?0xFE002000
+#define RBR ? ?0xFE002000
+
+#define CR1 ? ?0xFE002008
+#define CR2 ? ?0xFE002010
+#define CR3 ? ?0xFE002018
+#define CR4 ? ?0xFE002020
+
+/* CR1 */
+#define SPI_TBE ? ? ? ? ? ? ? ?0x80
+#define SPI_TBF ? ? ? ? ? ? ? ?0x40
+#define SPI_RBE ? ? ? ? ? ? ? ?0x20
+#define SPI_RBF ? ? ? ? ? ? ? ?0x10
+#define SPI_PFONRD ? ? 0x08
+#define SPI_SSDB ? ? ? 0x04
+#define SPI_SSD ? ? ? ? ? ? ? ?0x02
+#define SPI_SSA ? ? ? ? ? ? ? ?0x01
+
+/* CR2 */
+#define SPI_RSTF ? ? ? 0x80
+#define SPI_LOOPBK ? ? 0x40
+#define SPI_CPOL ? ? ? 0x20
+#define SPI_CPHA ? ? ? 0x10
+#define SPI_L1M0 ? ? ? 0x08
+
+/* CR4 */
+#define SPI_TBEI ? ? ? 0x80
+#define SPI_TBFI ? ? ? 0x40
+#define SPI_RBEI ? ? ? 0x20
+#define SPI_RBFI ? ? ? 0x10
+#define SPI_SSS ? ? ? ? ? ? ? ?0x01
+
+#define spi_write(val, addr) ? (*(volatile unsigned long *)(addr)) = val
+#define spi_read(addr) ? ? ? ? (*(volatile unsigned long *)(addr))
+
+/* M25P80 */
+#define M25_READ ? ? ? 0x03
+
+#define __uses_spiboot2 ? ? ? ?__attribute__((section(".spiboot2.text")))
+static void __uses_spiboot2 spi_reset(void)
+{
+ ? ? ? spi_write(0xfe, CR1);
+
+ ? ? ? spi_write(0, SPIDMCOR);
+ ? ? ? spi_write(0x00, CR1);
+
+ ? ? ? spi_write(spi_read(CR2) | SPI_RSTF, CR2); ? ? ? /* fifo reset */
+ ? ? ? spi_write(spi_read(CR2) & ~SPI_RSTF, CR2);
+}
+
+static void __uses_spiboot2 spi_read_flash(void *buf, unsigned long addr,
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned long len)
+{
+ ? ? ? spi_write(M25_READ, TBR);
+ ? ? ? spi_write((addr >> 16) & 0xFF, TBR);
+ ? ? ? spi_write((addr >> 8) & 0xFF, TBR);
+ ? ? ? spi_write(addr & 0xFF, TBR);
+
+ ? ? ? spi_write(SPIDMINTSR_DMEND, SPIDMINTSR);
+ ? ? ? spi_write((unsigned long)buf, SPIWDMADR);
+ ? ? ? spi_write(len & 0xFFFFFFE0, SPIWDMCNTR);
+ ? ? ? spi_write(1, SPIDMCOR);
+
+ ? ? ? spi_write(0xff, CR3);
+ ? ? ? spi_write(spi_read(CR1) | SPI_SSDB, CR1);
+ ? ? ? spi_write(spi_read(CR1) | SPI_SSA, CR1);
+
+ ? ? ? while (!(spi_read(SPIDMINTSR) & SPIDMINTSR_DMEND))
+ ? ? ? ? ? ? ? ;
+}
+
+void __uses_spiboot2 spiboot_main(void)
+{
+ ? ? ? void (*_start)(void) = (void *)CONFIG_SYS_TEXT_BASE;
+
+ ? ? ? spi_reset();
+ ? ? ? spi_read_flash((void *)CONFIG_RAM_BOOT_PHYS, CONFIG_SPI_ADDR,
+ ? ? ? ? ? ? ? ? ? ? ? CONFIG_SPI_LENGTH);
+
+ ? ? ? _start();
+}
+

board/renesas/sh7757lcr/u-boot.lds new file +101 -0

new file mode 100644
index 0000000..a88d781
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2007
+ * Nobuhiro Iwamatsu <[email protected]>
+ *
+ * Copyright (C) 2011
+ * Yoshihiro Shimoda <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-sh-linux", "elf32-sh-linux", "elf32-sh-linux")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+
+SECTIONS
+{
+ ? ? ? /*
+ ? ? ? ?* entry and reloct_dst will be provided via ldflags
+ ? ? ? ?*/
+ ? ? ? . = .;
+
+ ? ? ? PROVIDE (_ftext = .);
+ ? ? ? PROVIDE (_fcode = .);
+ ? ? ? PROVIDE (_start = .);
+
+ ? ? ? .text :
+ ? ? ? {
+ ? ? ? ? ? ? ? arch/sh/cpu/sh4/start.o ? ? ? ? (.text)
+ ? ? ? ? ? ? ? *(.spiboot1.text)
+ ? ? ? ? ? ? ? *(.spiboot2.text)
+ ? ? ? ? ? ? ? . = ALIGN(8192);
+ ? ? ? ? ? ? ? common/env_embedded.o ? (.ppcenv)
+ ? ? ? ? ? ? ? . = ALIGN(8192);
+ ? ? ? ? ? ? ? common/env_embedded.o ? (.ppcenvr)
+ ? ? ? ? ? ? ? . = ALIGN(8192);
+ ? ? ? ? ? ? ? *(.text)
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? } =0xFF
+ ? ? ? PROVIDE (_ecode = .);
+ ? ? ? .rodata :
+ ? ? ? {
+ ? ? ? ? ? ? ? *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? }
+ ? ? ? PROVIDE (_etext = .);
+
+
+ ? ? ? PROVIDE (_fdata = .);
+ ? ? ? .data :
+ ? ? ? {
+ ? ? ? ? ? ? ? *(.data)
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? }
+ ? ? ? PROVIDE (_edata = .);
+
+ ? ? ? PROVIDE (_fgot = .);
+ ? ? ? .got :
+ ? ? ? {
+ ? ? ? ? ? ? ? *(.got)
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? }
+ ? ? ? PROVIDE (_egot = .);
+
+ ? ? ? PROVIDE (__u_boot_cmd_start = .);
+ ? ? ? .u_boot_cmd :
+ ? ? ? {
+ ? ? ? ? ? ? ? *(.u_boot_cmd)
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? }
+ ? ? ? PROVIDE (__u_boot_cmd_end = .);
+
+ ? ? ? PROVIDE (reloc_dst_end = .);
+ ? ? ? /* _reloc_dst_end = .; */
+
+ ? ? ? PROVIDE (bss_start = .);
+ ? ? ? PROVIDE (__bss_start = .);
+ ? ? ? .bss (NOLOAD) :
+ ? ? ? {
+ ? ? ? ? ? ? ? *(.bss)
+ ? ? ? ? ? ? ? . = ALIGN(4);
+ ? ? ? }
+ ? ? ? PROVIDE (bss_end = .);
+
+ ? ? ? PROVIDE (_end = .);
+}

boards.cfg +0 -0

index 0574bb2..417ed1d 100644
@@ -752,6 +752,7 @@ ms7750se ? ? ? ? ? ? ? ? ? ? sh ? ? ? ? ?sh4 ? ? ? ? ms7750se ? ? ? ? ? ?-

?ap325rxa ? ? ? ? ? ? ? ? ? ? sh ? ? ? ? ?sh4 ? ? ? ? ap325rxa ? ? ? ? ? ?renesas ? ? ? ?-
?r2dplus ? ? ? ? ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? r2dplus ? ? ? ? ? ? renesas ? ? ? ?-
?r7780mp ? ? ? ? ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? r7780mp ? ? ? ? ? ? renesas ? ? ? ?-
+sh7757lcr ? ? ? ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? sh7757lcr ? ? ? ? ? renesas ? ? ? ?-
?sh7763rdp ? ? ? ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? sh7763rdp ? ? ? ? ? renesas ? ? ? ?-
?sh7785lcr ? ? ? ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? sh7785lcr ? ? ? ? ? renesas ? ? ? ?- ?sh7785lcr_32bit ? ? ? ? ? ? ?sh ? ? ? ? ?sh4 ? ? ? ? sh7785lcr ? ? ? ? ? renesas ? ? ? ?- ? ? ? ? ? sh7785lcr:SH_32BIT=1

doc/README.sh7757lcr new file +64 -0

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@@ -0,0 +1,64 @@
+========================================
+Renesas R0P7757LC0030RL board
+========================================
+
+This board specification:
+=========================
+
+The R0P7757LC0030RL(board config name:sh7757lcr) has the following device:
+
+ - SH7757 (SH-4A)
+ - DDR3-SDRAM 256MB (with ECC)
+ - SPI ROM 8MB
+ - 2D Graphic controller
+ - Ethernet controller
+
+
+configuration for This board:
+=============================
+
+You can select the configuration as follows:
+
+ - make sh7785lcr_config
+
+
+This board specific command:
+============================
+
+This board has the following its specific command:
+
+ - sh_g200
+ - write_mac
+
+
+1. sh_g200
+
+If we run this command, SH4 can control the G200.
+The default setting is that SH4 cannot control the G200.
+
+
+2. write_mac
+
+You can write MAC address to SPI ROM.
+
+ Usage 1) Write MAC address
+
+ ? write_mac [ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]
+
+ ? ? ? For example)
+ ? ? ? ?=> write_mac 00:00:87:6c:21:80 00:00:87:6c:21:81 00:00:87:6c:21:82 00:00:87:6c:21:83
+ ? ? ? ? ? ? ? *) We have to input the command as a single line
+ ? ? ? ? ? ? ? ? ?(without carriage return)
+ ? ? ? ? ? ? ? *) We have to reset after input the command.
+
+ Usage 2) Show current data
+
+ ? write_mac
+
+ ? ? ? For example)
+ ? ? ? ? ? ? ? => write_mac
+ ? ? ? ? ? ? ? ?ETHERC ch0 = 00:00:87:6c:21:80
+ ? ? ? ? ? ? ? ?ETHERC ch1 = 00:00:87:6c:21:81
+ ? ? ? ? ? ? ? GETHERC ch0 = 00:00:87:6c:21:82
+ ? ? ? ? ? ? ? GETHERC ch1 = 00:00:87:6c:21:83
+

include/configs/sh7757lcr.h new file +146 -1

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@@ -0,0 +1,146 @@
+/*
+ * Configuation settings for the sh7757lcr board
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SH7757LCR_H
+#define __SH7757LCR_H
+
+#undef DEBUG
+#define CONFIG_SH ? ? ? ? ? ? ?1
+#define CONFIG_SH4A ? ? ? ? ? ?1
+#define CONFIG_SH_32BIT ? ? ? ? ? ? ? ?1
+#define CONFIG_CPU_SH7757 ? ? ?1
+#define CONFIG_SH7757LCR ? ? ? 1
+
+#define CONFIG_SYS_TEXT_BASE ? 0x8ef80000
+#define CONFIG_SYS_LDSCRIPT ? ?"board/renesas/sh7757lcr/u-boot.lds"
+
+#define CONFIG_CMD_MEMORY
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_DFL
+#define CONFIG_CMD_SDRAM
+#define CONFIG_CMD_SF
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_MD5SUM
+#define CONFIG_MD5
+#define CONFIG_CMD_LOADS
+
+#define CONFIG_BAUDRATE ? ? ? ? ? ? ? ?115200
+#define CONFIG_BOOTDELAY ? ? ? 3
+#define CONFIG_BOOTARGS ? ? ? ? ? ? ? ?"console=ttySC2,115200 root=/dev/nfs ip=dhcp"
+
+#define CONFIG_VERSION_VARIABLE
+#undef CONFIG_SHOW_BOOT_PROGRESS
+
+/* MEMORY */
+#define SH7757LCR_SDRAM_BASE ? ? ? ? ? (0x80000000)
+#define SH7757LCR_SDRAM_SIZE ? ? ? ? ? (240 * 1024 * 1024)
+#define SH7757LCR_SDRAM_ECC_SETTING ? ?0x0f000000 ? ? ?/* 240MByte */
+#define SH7757LCR_SDRAM_DVC_SIZE ? ? ? (16 * 1024 * 1024)
+
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT ? ? ? ? ? ? ?"=> "
+#define CONFIG_SYS_CBSIZE ? ? ? ? ? ? ?256
+#define CONFIG_SYS_PBSIZE ? ? ? ? ? ? ?256
+#define CONFIG_SYS_MAXARGS ? ? ? ? ? ? 16
+#define CONFIG_SYS_BARGSIZE ? ? ? ? ? ?512
+#define CONFIG_SYS_BAUDRATE_TABLE ? ? ?{ 115200 }
+
+/* SCIF */
+#define CONFIG_SCIF_CONSOLE ? ?1
+#define CONFIG_CONS_SCIF2 ? ? ?1
+#undef CONFIG_SYS_CONSOLE_INFO_QUIET
+#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
+#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
+
+#define CONFIG_SYS_MEMTEST_START ? ? ? (SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_MEMTEST_END ? ? ? ? (CONFIG_SYS_MEMTEST_START + \
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?224 * 1024 * 1024)
+#undef CONFIG_SYS_ALT_MEMTEST
+#undef CONFIG_SYS_MEMTEST_SCRATCH
+#undef CONFIG_SYS_LOADS_BAUD_CHANGE
+
+#define CONFIG_SYS_SDRAM_BASE ? ? ? ? ?(SH7757LCR_SDRAM_BASE)
+#define CONFIG_SYS_SDRAM_SIZE ? ? ? ? ?(SH7757LCR_SDRAM_SIZE)
+#define CONFIG_SYS_LOAD_ADDR ? ? ? ? ? (CONFIG_SYS_SDRAM_BASE + \
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?(128 + 16) * 1024 * 1024)
+
+#define CONFIG_SYS_MONITOR_BASE ? ? ? ? ? ? ? ?0x00000000
+#define CONFIG_SYS_MONITOR_LEN ? ? ? ? (256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN ? ? ? ? ?(4 * 1024 * 1024)
+#define CONFIG_SYS_BOOTMAPSZ ? ? ? ? ? (8 * 1024 * 1024)
+
+/* FLASH */
+#define CONFIG_SYS_NO_FLASH
+
+/* Ether */
+#define CONFIG_NET_MULTI ? ? ? ? ? ? ? 1
+#define CONFIG_SH_ETHER ? ? ? ? ? ? ? ? ? ? ? ?1
+#define CONFIG_SH_ETHER_USE_PORT ? ? ? 0
+#define CONFIG_SH_ETHER_PHY_ADDR ? ? ? 1
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK ? ? ? ?1
+
+#define SH7757LCR_ETHERNET_MAC_BASE_SPI ? ? ? ?0x000b0000
+#define SH7757LCR_SPI_SECTOR_SIZE ? ? ?(64 * 1024)
+#define SH7757LCR_ETHERNET_MAC_BASE ? ?SH7757LCR_ETHERNET_MAC_BASE_SPI
+#define SH7757LCR_ETHERNET_MAC_SIZE ? ?17
+#define SH7757LCR_ETHERNET_NUM_CH ? ? ?2
+#define BOARD_LATE_INIT ? ? ? ? ? ? ? ? ? ? ? ?1
+
+/* Gigabit Ether */
+#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
+
+/* SPI */
+#define CONFIG_SH_SPI ? ? ? ? ? ? ? ? ?1
+#define CONFIG_SH_SPI_BASE ? ? ? ? ? ? 0xfe002000
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO ? ? ? 1
+
+/* SH7757 board */
+#define SH7757LCR_SDRAM_PHYS_TOP ? ? ? 0x40000000
+#define SH7757LCR_GRA_OFFSET ? ? ? ? ? 0x1f000000
+#define SH7757LCR_PCIEBRG_ADDR_B0 ? ? ?0x000a0000
+#define SH7757LCR_PCIEBRG_SIZE_B0 ? ? ?(64 * 1024)
+#define SH7757LCR_PCIEBRG_ADDR ? ? ? ? 0x00090000
+#define SH7757LCR_PCIEBRG_SIZE ? ? ? ? (96 * 1024)
+
+/* ENV setting */
+#define CONFIG_ENV_IS_EMBEDDED
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SECT_SIZE ? (64 * 1024)
+#define CONFIG_ENV_ADDR ? ? ? ? ? ? ? ?(0x00080000)
+#define CONFIG_ENV_OFFSET ? ? ?(CONFIG_ENV_ADDR)
+#define CONFIG_ENV_OVERWRITE ? 1
+#define CONFIG_ENV_SIZE ? ? ? ? ? ? ? ?(CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
+#define CONFIG_EXTRA_ENV_SETTINGS ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?\
+ ? ? ? ? ? ? ? "netboot=bootp; bootm\0"
+
+/* Board Clock */
+#define CONFIG_SYS_CLK_FREQ ? ?48000000
+#define CONFIG_SYS_TMU_CLK_DIV 4
+#define CONFIG_SYS_HZ ? ? ? ? ?1000
+#endif /* __SH7757LCR_H */
--

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