powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
The write recovery time of both registers should match. Since mode register doesn't support cycles of 9,11,13,15, we should use next higher number for both registers.
--- arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c | 28 ++++++++++++++++++++++++---- 1 files changed, 24 insertions(+), 4 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +24 -4
@@ -371,6 +371,21 @@ static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, refrec_ctrl =picos_to_mclk (common_dimm->tRFC_ps) -8 ; wrrec_mclk =picos_to_mclk (common_dimm->tWR_ps); + +switch (wrrec_mclk) {/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ +case 9 : + wrrec_mclk =10 ; +break ; +case 11 : + wrrec_mclk =12 ; +break ; +case 13 : + wrrec_mclk =14 ; +break ; +case 16 : + wrrec_mclk =16 ; +break ; + }if (popts->OTF_burst_chop_en) wrrec_mclk +=2 ;
@@ -854,12 +869,17 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,*/ dll_on =1 ; wr_mclk = (common_dimm->tWR_ps + mclk_ps -1 ) / mclk_ps; -if (wr_mclk >=12 ) - wr =6 ; +if (wr_mclk >=15 ) + wr =0 ;/* 16 cycles */ +else if (wr_mclk >=13 ) + wr =7 ;/* 14 cycles */ +else if (wr_mclk >=11 ) + wr =6 ;/* 12 cycles */ else if (wr_mclk >=9 ) - wr =5 ; + wr =5 ;/* 10 cycles */ else - wr = wr_mclk -4 ; + wr = wr_mclk -4 ;/* 5~8 cycles */ + dll_rst =0 ;/* dll no reset */ mode =0 ;/* normal mode */
Signature · 1 line
1.7.0.4
PATCH 2/2 powerpc/corenet_ds: revise platform dependent parameters
This patch revised clk_adjust and wrlvl_start timings for corenet_ds, based on testing on Virtium VL33B5163F-K9S and Kingston KVR1333D3Q8R9S/4G.
--- board/freescale/corenet_ds/ddr.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-)
board/freescale/corenet_ds/ddr.c +4 -4
@@ -170,8 +170,8 @@ const board_specific_parameters_t board_specific_parameters[][30] = {* lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 850, 4, 1, 5, 0xff, 2, 0}, - {851, 950, 4, 3, 5, 0xff, 2, 0}, + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0},
@@ -188,8 +188,8 @@ const board_specific_parameters_t board_specific_parameters[][30] = {* lo| hi| num| clk| wrlvl | cpo |wrdata|2T * mhz| mhz|ranks|adjst| start | delay| */ - { 0, 850, 4, 1, 5, 0xff, 2, 0}, - {851, 950, 4, 3, 5, 0xff, 2, 0}, + { 0, 850, 4, 4, 6, 0xff, 2, 0}, + {851, 950, 4, 5, 7, 0xff, 2, 0}, {951, 1050, 4, 5, 8, 0xff, 2, 0}, {1051, 1250, 4, 5, 10, 0xff, 2, 0}, {1251, 1350, 4, 5, 11, 0xff, 2, 0},
Signature · 1 line
1.7.0.4
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
In reply to York Sunarch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, · line 385
Quoted 11 lines · York Sun
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +11
-0+switch (wrrec_mclk) {/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ +case 9 : + wrrec_mclk =10 ; +break ; +case 11 : + wrrec_mclk =12 ; +break ; +case 13 : + wrrec_mclk =14 ; +break ; +case 16 :
15?
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, · line 388
Quoted 3 lines
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +3
-0+ wrrec_mclk =16 ; +break ; + }
How about something simpler:
if (wrrec_mclk & 1)
wrrec_mclk++;
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
Quoted 14 lines · Timur Tabi
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, · line 385
Quoted 11 lines · York Sun
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +11
-0+switch (wrrec_mclk) {/* DDR_SDRAM_MODE doesn't support 9,11,13,15 */ +case 9 : + wrrec_mclk =10 ; +break ; +case 11 : + wrrec_mclk =12 ; +break ; +case 13 : + wrrec_mclk =14 ; +break ; +case 16 :15?
Nice catch. Thank you. I will submit a fixed version.
Quoted 9 lines
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c static void set_timing_cfg_1(fsl_ddr_cfg_regs_t *ddr, · line 388
Quoted 3 lines
arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +3
-0+ wrrec_mclk =16 ; +break ; + }How about something simpler:
if (
wrrec_mclk& 1)wrrec_mclk++;
Only 9, 11, 13, 15 need to round up.
York
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
Quoted 4 lines · York Sun
Quoted 3 lines
Quoted 3 lines
if (
wrrec_mclk& 1)wrrec_mclk++;Only 9, 11, 13, 15 need to round up.
What are all the possible values for wrrec_mclk?
Signature · 2 lines
Timur Tabi Linux kernel developer at Freescale
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
Quoted 8 lines · Timur Tabi
Quoted 4 lines · York Sun
Quoted 3 lines
Quoted 3 lines
if (
wrrec_mclk& 1)wrrec_mclk++;Only 9, 11, 13, 15 need to round up.
What are all the possible values for
wrrec_mclk?
There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be any value. The limitation comes from JEDEC spec on mode register MR0. The write recovery for autoprecharge is within the values of 5, 6, 7, 8, 10, 12, 14, 16.
York
PATCH 1/2 powerpc/mpc8xxx: Fix DDR3 timing_cfg_1 and sdram_mode registers
Quoted 7 lines · York Sun
Quoted 6 lines · Timur Tabi
Quoted 4 lines · York Sun
Quoted 3 lines
Quoted 3 lines
if (
wrrec_mclk& 1)wrrec_mclk++;Only 9, 11, 13, 15 need to round up.
Quoted 7 lines
Quoted 2 lines
What are all the possible values for
wrrec_mclk?There is no limitation on register timing_cfg_1[wrrec_mclk]. It can be any value. The limitation comes from JEDEC spec on mode register MR0. The write recovery for autoprecharge is within the values of 5, 6, 7, 8, 10, 12, 14, 16.
My point is that we can do something like this:
if (wrrec_mclk > 8 && wrrec_mclk < 16 && wrrec_mclk & 1)
wrrec_mclk++;
But we can simplify this if I can know what all possible values are.
Signature · 2 lines
Timur Tabi Linux kernel developer@Freescale