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SPEAr3xx & SPEAr6xx Fixes

PATCH Superseded Viresh Kumar 2 participants 17 messages Mar 1, 2011 – Mar 9, 2011

Subsystems (2)
Arm (32-bit) Arm sub-architectures
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Viresh Kumar

author
#0 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

This patchset contains minor fixes, renames, & reordering of code of #include files.

Note: These patches were earlier sent as part of a larger patchset:
"Updating SPEAr Support"

Now it is divided into smaller patchsets. In order to apply these patches cleanly following order of patchsets must be maintained.
- SPEAr3xx & SPEAr6xx Fixes
- SPEAr3xx & SPEAr6xx: Single Image solution and padmux updates
- Adding SPEAr13xx support
- Adding devices support for all spear machines
- Clock Framework & CPU Freq Updates

Shiraz Hashim (1):
ST SPEAr: Append UL to device address macros.

Viresh Kumar (7):
ST SPEAr: Reordering #includes in .h & .c files.
ST SPEAr: Include mach/hardware.h instead of mach/spear.h ST SPEAr3xx: Rename sdio to sdhci
ST SPEAr Clock Framework: Rename usbd clock and align apb_clk entry ST SPEAr3xx: Declare device structures after shirq code ST SPEAr: Replacing SIZE macro's with SZ_4K macros
ST SPEAr: Remove unused *_SIZE macros from spear*.h files

 arch/arm/mach-spear3xx/clock.c                    |    6 +-
 arch/arm/mach-spear3xx/include/mach/entry-macro.S |    3 +-
 arch/arm/mach-spear3xx/include/mach/generic.h     |   12 +-
 arch/arm/mach-spear3xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear3xx/include/mach/irqs.h        |    4 +-
 arch/arm/mach-spear3xx/include/mach/misc_regs.h   |    2 +-
 arch/arm/mach-spear3xx/include/mach/spear.h       |  135 +++++------------
 arch/arm/mach-spear3xx/include/mach/spear300.h    |   59 ++-----
 arch/arm/mach-spear3xx/include/mach/spear310.h    |   34 ++---
 arch/arm/mach-spear3xx/include/mach/spear320.h    |   67 +++------
 arch/arm/mach-spear3xx/spear300.c                 |   70 ++++-----
 arch/arm/mach-spear3xx/spear300_evb.c             |    4 +-
 arch/arm/mach-spear3xx/spear310.c                 |   10 +-
 arch/arm/mach-spear3xx/spear310_evb.c             |    2 +-
 arch/arm/mach-spear3xx/spear320.c                 |   30 ++--
 arch/arm/mach-spear3xx/spear320_evb.c             |    4 +-
 arch/arm/mach-spear3xx/spear3xx.c                 |   14 +-
 arch/arm/mach-spear6xx/clock.c                    |    6 +-
 arch/arm/mach-spear6xx/include/mach/entry-macro.S |    3 +-
 arch/arm/mach-spear6xx/include/mach/generic.h     |    4 +-
 arch/arm/mach-spear6xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear6xx/include/mach/misc_regs.h   |    2 +-
 arch/arm/mach-spear6xx/include/mach/spear.h       |  175 ++++++---------------
 arch/arm/mach-spear6xx/spear600.c                 |    2 +-
 arch/arm/mach-spear6xx/spear600_evb.c             |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c                 |   29 ++--
 arch/arm/plat-spear/include/plat/debug-macro.S    |    2 +-
 arch/arm/plat-spear/include/plat/system.h         |    4 +-
 arch/arm/plat-spear/include/plat/uncompress.h     |    2 +-
 arch/arm/plat-spear/time.c                        |    5 +-
 30 files changed, 235 insertions(+), 459 deletions(-)
Signature · 1 line
1.7.2.2
author
#1 lore raw

PATCH v6 1/8 ST SPEAr: Reordering #includes in .h & .c files.

Order of inclusion of .h files must be: <linux/...>, <asm/...>, <plat/...>, <mach/...>. This patch corrects this ordering whereever it is not followed.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/clock.c                    |    2 +-
 arch/arm/mach-spear3xx/include/mach/entry-macro.S |    2 +-
 arch/arm/mach-spear3xx/include/mach/generic.h     |    4 ++--
 arch/arm/mach-spear3xx/spear300.c                 |    2 +-
 arch/arm/mach-spear3xx/spear310.c                 |    2 +-
 arch/arm/mach-spear3xx/spear320.c                 |    2 +-
 arch/arm/mach-spear6xx/clock.c                    |    2 +-
 arch/arm/mach-spear6xx/include/mach/entry-macro.S |    2 +-
 arch/arm/mach-spear6xx/include/mach/generic.h     |    4 ++--
 arch/arm/mach-spear6xx/spear6xx.c                 |    2 +-
 arch/arm/plat-spear/include/plat/system.h         |    2 +-
 arch/arm/plat-spear/time.c                        |    4 ++--
 12 files changed, 15 insertions(+), 15 deletions(-)
arch/arm/mach-spear3xx/clock.c +1 -1
index 8ae4ad0..5bfeb6f 100644
@@ -13,8 +13,8 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <mach/misc_regs.h>
 #include <plat/clock.h>
+#include <mach/misc_regs.h>
 
 /* root clks */
 /* 32 KHz oscillator clock */
arch/arm/mach-spear3xx/include/mach/entry-macro.S +1 -1
index 947625d..e8e7dc0 100644
@@ -11,9 +11,9 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <asm/hardware/vic.h>
 #include <mach/hardware.h>
 #include <mach/spear.h>
-#include <asm/hardware/vic.h>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-spear3xx/include/mach/generic.h +2 -2
index e7d2de8..aaaa046 100644
@@ -14,11 +14,11 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
 #include <plat/padmux.h>
 
 /* spear3xx declarations */
arch/arm/mach-spear3xx/spear300.c +1 -1
index 7e01677..80ca04a 100644
@@ -15,9 +15,9 @@
 #include <linux/amba/pl061.h>
 #include <linux/ptrace.h>
 #include <asm/irq.h>
+#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
-#include <plat/shirq.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear3xx/spear310.c +1 -1
index f38eb21..ca1109d 100644
@@ -13,9 +13,9 @@
 
 #include <linux/ptrace.h>
 #include <asm/irq.h>
+#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
-#include <plat/shirq.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear3xx/spear320.c +1 -1
index 456bb33..ceb04e8 100644
@@ -13,9 +13,9 @@
 
 #include <linux/ptrace.h>
 #include <asm/irq.h>
+#include <plat/shirq.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
-#include <plat/shirq.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear6xx/clock.c +1 -1
index 9171952..4f351b4 100644
@@ -13,8 +13,8 @@
 
 #include <linux/init.h>
 #include <linux/kernel.h>
-#include <mach/misc_regs.h>
 #include <plat/clock.h>
+#include <mach/misc_regs.h>
 
 /* root clks */
 /* 32 KHz oscillator clock */
arch/arm/mach-spear6xx/include/mach/entry-macro.S +1 -1
index 9eaecae..bc55e8b 100644
@@ -11,9 +11,9 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <asm/hardware/vic.h>
 #include <mach/hardware.h>
 #include <mach/spear.h>
-#include <asm/hardware/vic.h>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-spear6xx/include/mach/generic.h +2 -2
index e5967ed..94cf4a6 100644
@@ -14,11 +14,11 @@
 #ifndef __MACH_GENERIC_H
 #define __MACH_GENERIC_H
 
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/amba/bus.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
 
 /*
  * Each GPT has 2 timer channels
arch/arm/mach-spear6xx/spear6xx.c +1 -1
index 9cd3a68..2d95715 100644
@@ -18,8 +18,8 @@
 #include <asm/hardware/vic.h>
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
-#include <mach/irqs.h>
 #include <mach/generic.h>
+#include <mach/irqs.h>
 #include <mach/spear.h>
 
 /* Add spear6xx machines common devices here */
arch/arm/plat-spear/include/plat/system.h +1 -1
index 55a4e40..d52db68 100644
@@ -14,8 +14,8 @@
 #ifndef __PLAT_SYSTEM_H
 #define __PLAT_SYSTEM_H
 
-#include <asm/hardware/sp810.h>
 #include <linux/io.h>
+#include <asm/hardware/sp810.h>
 #include <mach/spear.h>
 
 static inline void arch_idle(void)
arch/arm/plat-spear/time.c +2 -2
index 100672f..de0a81b 100644
@@ -20,10 +20,10 @@
 #include <linux/time.h>
 #include <linux/irq.h>
 #include <asm/mach/time.h>
-#include <mach/irqs.h>
+#include <mach/generic.h>
 #include <mach/hardware.h>
+#include <mach/irqs.h>
 #include <mach/spear.h>
-#include <mach/generic.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
Signature · 1 line
1.7.2.2
author
#2 lore raw

PATCH v6 2/8 ST SPEAr: Include mach/hardware.h instead of mach/spear.h

In reply to Viresh Kumar

This patch makes inclusion of hardware.h and spear.h consistent over all spear variants. Now we will include hardware.h, wherever we need to use hardware macros. spear.h will be automatically included by hardware.h

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/include/mach/entry-macro.S |    1 -
 arch/arm/mach-spear3xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear3xx/include/mach/misc_regs.h   |    2 +-
 arch/arm/mach-spear3xx/include/mach/spear.h       |    1 -
 arch/arm/mach-spear3xx/spear300.c                 |    2 +-
 arch/arm/mach-spear3xx/spear300_evb.c             |    2 +-
 arch/arm/mach-spear3xx/spear310.c                 |    2 +-
 arch/arm/mach-spear3xx/spear310_evb.c             |    2 +-
 arch/arm/mach-spear3xx/spear320.c                 |    2 +-
 arch/arm/mach-spear3xx/spear320_evb.c             |    2 +-
 arch/arm/mach-spear3xx/spear3xx.c                 |    2 +-
 arch/arm/mach-spear6xx/include/mach/entry-macro.S |    1 -
 arch/arm/mach-spear6xx/include/mach/hardware.h    |    1 +
 arch/arm/mach-spear6xx/include/mach/misc_regs.h   |    2 +-
 arch/arm/mach-spear6xx/include/mach/spear.h       |    1 -
 arch/arm/mach-spear6xx/spear600.c                 |    2 +-
 arch/arm/mach-spear6xx/spear600_evb.c             |    2 +-
 arch/arm/mach-spear6xx/spear6xx.c                 |    2 +-
 arch/arm/plat-spear/include/plat/debug-macro.S    |    2 +-
 arch/arm/plat-spear/include/plat/system.h         |    2 +-
 arch/arm/plat-spear/include/plat/uncompress.h     |    2 +-
 arch/arm/plat-spear/time.c                        |    1 -
 22 files changed, 17 insertions(+), 20 deletions(-)
arch/arm/mach-spear3xx/include/mach/entry-macro.S +0 -1
index e8e7dc0..53da422 100644
@@ -13,7 +13,6 @@
 
 #include <asm/hardware/vic.h>
 #include <mach/hardware.h>
-#include <mach/spear.h>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-spear3xx/include/mach/hardware.h +1 -0
index 490e86a..4660c0d 100644
@@ -15,6 +15,7 @@
 #define __MACH_HARDWARE_H
 
 #include <plat/hardware.h>
+#include <mach/spear.h>
 
 /* Vitual to physical translation of statically mapped space */
 #define IO_ADDRESS(x)		(x | 0xF0000000)
arch/arm/mach-spear3xx/include/mach/misc_regs.h +1 -1
index 0b93347..5bd8cd8 100644
@@ -14,7 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 #define MISC_BASE		IOMEM(VA_SPEAR3XX_ICM3_MISC_REG_BASE)
arch/arm/mach-spear3xx/include/mach/spear.h +0 -1
index dcca856..8745802 100644
@@ -14,7 +14,6 @@
 #ifndef __MACH_SPEAR3XX_H
 #define __MACH_SPEAR3XX_H
 
-#include <mach/hardware.h>
 #include <mach/spear300.h>
 #include <mach/spear310.h>
 #include <mach/spear320.h>
arch/arm/mach-spear3xx/spear300.c +1 -1
index 80ca04a..e15c684 100644
@@ -17,7 +17,7 @@
 #include <asm/irq.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear3xx/spear300_evb.c +1 -1
index cd23c98..77c9b83 100644
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
arch/arm/mach-spear3xx/spear310.c +1 -1
index ca1109d..5bfab14 100644
@@ -15,7 +15,7 @@
 #include <asm/irq.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear3xx/spear310_evb.c +1 -1
index 3855431..2d7f333 100644
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
arch/arm/mach-spear3xx/spear320.c +1 -1
index ceb04e8..c25f909 100644
@@ -15,7 +15,7 @@
 #include <asm/irq.h>
 #include <plat/shirq.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* pad multiplexing support */
 /* muxing registers */
arch/arm/mach-spear3xx/spear320_evb.c +1 -1
index 4a7ce35..0b80a15 100644
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* padmux devices to enable */
 static struct pmx_dev *pmx_devs[] = {
arch/arm/mach-spear3xx/spear3xx.c +1 -1
index e12a06c..634116f 100644
@@ -19,7 +19,7 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* Add spear3xx machines common devices here */
 /* gpio device registration */
arch/arm/mach-spear6xx/include/mach/entry-macro.S +0 -1
index bc55e8b..8a0b0ed 100644
@@ -13,7 +13,6 @@
 
 #include <asm/hardware/vic.h>
 #include <mach/hardware.h>
-#include <mach/spear.h>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-spear6xx/include/mach/hardware.h +1 -0
index 0291476..0b3f96a 100644
@@ -15,6 +15,7 @@
 #define __MACH_HARDWARE_H
 
 #include <plat/hardware.h>
+#include <mach/spear.h>
 
 /* Vitual to physical translation of statically mapped space */
 #define IO_ADDRESS(x)		(x | 0xF0000000)
arch/arm/mach-spear6xx/include/mach/misc_regs.h +1 -1
index 45571c1..68c20a0 100644
@@ -14,7 +14,7 @@
 #ifndef __MACH_MISC_REGS_H
 #define __MACH_MISC_REGS_H
 
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 #define MISC_BASE		IOMEM(VA_SPEAR6XX_ICM3_MISC_REG_BASE)
arch/arm/mach-spear6xx/include/mach/spear.h +0 -1
index a835f5b..17ab5aa 100644
@@ -14,7 +14,6 @@
 #ifndef __MACH_SPEAR6XX_H
 #define __MACH_SPEAR6XX_H
 
-#include <mach/hardware.h>
 #include <mach/spear600.h>
 
 #define SPEAR6XX_ML_SDRAM_BASE		0x00000000
arch/arm/mach-spear6xx/spear600.c +1 -1
index 5c484c4..d0e6eea 100644
@@ -14,7 +14,7 @@
 #include <linux/ptrace.h>
 #include <asm/irq.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 /* Add spear600 specific devices here */
arch/arm/mach-spear6xx/spear600_evb.c +1 -1
index b0ed0df..f19cefe 100644
@@ -14,7 +14,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 #include <mach/generic.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 static struct amba_device *amba_devs[] __initdata = {
 	&gpio_device[0],
arch/arm/mach-spear6xx/spear6xx.c +1 -1
index 2d95715..378440b 100644
@@ -19,8 +19,8 @@
 #include <asm/irq.h>
 #include <asm/mach/arch.h>
 #include <mach/generic.h>
+#include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/spear.h>
 
 /* Add spear6xx machines common devices here */
 /* uart device registration */
arch/arm/plat-spear/include/plat/debug-macro.S +1 -1
index e91270e..8501bbf 100644
@@ -12,7 +12,7 @@
  */
 
 #include <linux/amba/serial.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 		.macro	addruart, rp, rv
 		mov	\rp, #SPEAR_DBG_UART_BASE		@ Physical base
arch/arm/plat-spear/include/plat/system.h +1 -1
index d52db68..a235fa0 100644
@@ -16,7 +16,7 @@
 
 #include <linux/io.h>
 #include <asm/hardware/sp810.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 static inline void arch_idle(void)
 {
arch/arm/plat-spear/include/plat/uncompress.h +1 -1
index 6dd455b..1bf8452 100644
@@ -13,7 +13,7 @@
 
 #include <linux/io.h>
 #include <linux/amba/serial.h>
-#include <mach/spear.h>
+#include <mach/hardware.h>
 
 #ifndef __PLAT_UNCOMPRESS_H
 #define __PLAT_UNCOMPRESS_H
arch/arm/plat-spear/time.c +0 -1
index de0a81b..dbb6e4f 100644
@@ -23,7 +23,6 @@
 #include <mach/generic.h>
 #include <mach/hardware.h>
 #include <mach/irqs.h>
-#include <mach/spear.h>
 
 /*
  * We would use TIMER0 and TIMER1 as clockevent and clocksource.
Signature · 1 line
1.7.2.2
author
#3 lore raw

PATCH v6 3/8 ST SPEAr3xx: Rename sdio to sdhci

In reply to Viresh Kumar

Device name of SD/MMC/SDIO controller in linux is sdhci. To maintain consistency across all spear code, rename sdio to sdhci.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/include/mach/generic.h  |    8 ++++----
 arch/arm/mach-spear3xx/include/mach/irqs.h     |    4 ++--
 arch/arm/mach-spear3xx/include/mach/spear300.h |    4 ++--
 arch/arm/mach-spear3xx/include/mach/spear320.h |    6 +++---
 arch/arm/mach-spear3xx/spear300.c              |   20 ++++++++++----------
 arch/arm/mach-spear3xx/spear300_evb.c          |    2 +-
 arch/arm/mach-spear3xx/spear320.c              |   20 ++++++++++----------
 arch/arm/mach-spear3xx/spear320_evb.c          |    2 +-
 8 files changed, 33 insertions(+), 33 deletions(-)
arch/arm/mach-spear3xx/include/mach/generic.h +4 -4
index aaaa046..8e30636 100644
@@ -129,8 +129,8 @@ extern struct pmx_dev pmx_telecom_camera;
 extern struct pmx_dev pmx_telecom_dac;
 extern struct pmx_dev pmx_telecom_i2s;
 extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdio_4bit;
-extern struct pmx_dev pmx_telecom_sdio_8bit;
+extern struct pmx_dev pmx_telecom_sdhci_4bit;
+extern struct pmx_dev pmx_telecom_sdhci_8bit;
 extern struct pmx_dev pmx_gpio1;
 
 /* Add spear300 machine function declarations here */

@@ -172,14 +172,14 @@ extern struct pmx_dev pmx_clcd;
 extern struct pmx_dev pmx_emi;
 extern struct pmx_dev pmx_fsmc;
 extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdio;
+extern struct pmx_dev pmx_sdhci;
 extern struct pmx_dev pmx_i2s;
 extern struct pmx_dev pmx_uart1;
 extern struct pmx_dev pmx_uart1_modem;
 extern struct pmx_dev pmx_uart2;
 extern struct pmx_dev pmx_touchscreen;
 extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdio_led;
+extern struct pmx_dev pmx_sdhci_led;
 extern struct pmx_dev pmx_pwm0;
 extern struct pmx_dev pmx_pwm1;
 extern struct pmx_dev pmx_pwm2;
arch/arm/mach-spear3xx/include/mach/irqs.h +2 -2
index 7f940b8..a1a7f48 100644
@@ -69,7 +69,7 @@
 #define IRQ_CLCD				IRQ_GEN_RAS_3
 
 /* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDIO				IRQ_INTRCOMM_RAS_ARM
+#define IRQ_SDHCI				IRQ_INTRCOMM_RAS_ARM
 
 /* GPIO pins virtual irqs */
 #define SPEAR_GPIO_INT_BASE			(VIRQ_START + 9)

@@ -115,7 +115,7 @@
 #define VIRQ_SPP				(VIRQ_START + 2)
 
 /* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDIO				IRQ_GEN_RAS_2
+#define IRQ_SDHCI				IRQ_GEN_RAS_2
 
 /* IRQs sharing IRQ_GEN_RAS_3 */
 #define VIRQ_PLGPIO				(VIRQ_START + 3)
arch/arm/mach-spear3xx/include/mach/spear300.h +2 -2
index ccaa765..1059d5a 100644
@@ -39,8 +39,8 @@
 #define SPEAR300_CLCD_BASE		0x60000000
 #define SPEAR300_CLCD_SIZE		0x10000000
 
-#define SPEAR300_SDIO_BASE		0x70000000
-#define SPEAR300_SDIO_SIZE		0x10000000
+#define SPEAR300_SDHCI_BASE		0x70000000
+#define SPEAR300_SDHCI_SIZE		0x10000000
 
 #define SPEAR300_NAND_0_BASE		0x80000000
 #define SPEAR300_NAND_0_SIZE		0x04000000
arch/arm/mach-spear3xx/include/mach/spear320.h +3 -3
index 53677e4..1c9d310 100644
@@ -25,8 +25,8 @@
 #define SPEAR320_I2S_BASE		0x60000000
 #define SPEAR320_I2S_SIZE		0x10000000
 
-#define SPEAR320_SDIO_BASE		0x70000000
-#define SPEAR320_SDIO_SIZE		0x10000000
+#define SPEAR320_SDHCI_BASE		0x70000000
+#define SPEAR320_SDHCI_SIZE		0x10000000
 
 #define SPEAR320_CLCD_BASE		0x90000000
 #define SPEAR320_CLCD_SIZE		0x10000000

@@ -74,7 +74,7 @@
 #define EMI_IRQ_MASK			(1 << 7)
 #define CLCD_IRQ_MASK			(1 << 8)
 #define SPP_IRQ_MASK			(1 << 9)
-#define SDIO_IRQ_MASK			(1 << 10)
+#define SDHCI_IRQ_MASK			(1 << 10)
 #define CAN_U_IRQ_MASK			(1 << 11)
 #define CAN_L_IRQ_MASK			(1 << 12)
 #define UART1_IRQ_MASK			(1 << 13)
arch/arm/mach-spear3xx/spear300.c +10 -10
index e15c684..42dc29b 100644
@@ -310,7 +310,7 @@ struct pmx_dev pmx_telecom_boot_pins = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |

@@ -323,14 +323,14 @@ struct pmx_dev_mode pmx_telecom_sdio_4bit_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_sdio_4bit = {
-	.name = "telecom_sdio_4bit",
-	.modes = pmx_telecom_sdio_4bit_modes,
-	.mode_count = ARRAY_SIZE(pmx_telecom_sdio_4bit_modes),
+struct pmx_dev pmx_telecom_sdhci_4bit = {
+	.name = "telecom_sdhci_4bit",
+	.modes = pmx_telecom_sdhci_4bit_modes,
+	.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
+struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
 	{
 		.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
 			HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |

@@ -342,10 +342,10 @@ struct pmx_dev_mode pmx_telecom_sdio_8bit_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_telecom_sdio_8bit = {
-	.name = "telecom_sdio_8bit",
-	.modes = pmx_telecom_sdio_8bit_modes,
-	.mode_count = ARRAY_SIZE(pmx_telecom_sdio_8bit_modes),
+struct pmx_dev pmx_telecom_sdhci_8bit = {
+	.name = "telecom_sdhci_8bit",
+	.modes = pmx_telecom_sdhci_8bit_modes,
+	.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
 	.enb_on_reset = 1,
 };
arch/arm/mach-spear3xx/spear300_evb.c +1 -1
index 77c9b83..42d2253 100644
@@ -28,7 +28,7 @@ static struct pmx_dev *pmx_devs[] = {
 	/* spear300 specific devices */
 	&pmx_fsmc_2_chips,
 	&pmx_clcd,
-	&pmx_telecom_sdio_4bit,
+	&pmx_telecom_sdhci_4bit,
 	&pmx_gpio1,
 };
arch/arm/mach-spear3xx/spear320.c +10 -10
index c25f909..6dba628 100644
@@ -110,7 +110,7 @@ struct pmx_dev pmx_spp = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_modes[] = {
+struct pmx_dev_mode pmx_sdhci_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
 			SMALL_PRINTERS_MODE,

@@ -118,10 +118,10 @@ struct pmx_dev_mode pmx_sdio_modes[] = {
 	},
 };
 
-struct pmx_dev pmx_sdio = {
-	.name = "sdio",
-	.modes = pmx_sdio_modes,
-	.mode_count = ARRAY_SIZE(pmx_sdio_modes),
+struct pmx_dev pmx_sdhci = {
+	.name = "sdhci",
+	.modes = pmx_sdhci_modes,
+	.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
 	.enb_on_reset = 1,
 };
 

@@ -215,17 +215,17 @@ struct pmx_dev pmx_can = {
 	.enb_on_reset = 1,
 };
 
-struct pmx_dev_mode pmx_sdio_led_modes[] = {
+struct pmx_dev_mode pmx_sdhci_led_modes[] = {
 	{
 		.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
 		.mask = PMX_SSP_CS_MASK,
 	},
 };
 
-struct pmx_dev pmx_sdio_led = {
-	.name = "sdio_led",
-	.modes = pmx_sdio_led_modes,
-	.mode_count = ARRAY_SIZE(pmx_sdio_led_modes),
+struct pmx_dev pmx_sdhci_led = {
+	.name = "sdhci_led",
+	.modes = pmx_sdhci_led_modes,
+	.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
 	.enb_on_reset = 1,
 };
arch/arm/mach-spear3xx/spear320_evb.c +1 -1
index 0b80a15..8213e4b 100644
@@ -26,7 +26,7 @@ static struct pmx_dev *pmx_devs[] = {
 
 	/* spear320 specific devices */
 	&pmx_fsmc,
-	&pmx_sdio,
+	&pmx_sdhci,
 	&pmx_i2s,
 	&pmx_uart1,
 	&pmx_uart2,
Signature · 1 line
1.7.2.2
author
#4 lore raw

PATCH v6 4/8 ST SPEAr Clock Framework: Rename usbd clock and align apb_clk entry

In reply to Viresh Kumar
Signed-off-by Deepak Sikri <[email protected]>
Signed-off-by shiraz hashim <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/clock.c |    4 ++--
 arch/arm/mach-spear6xx/clock.c |    4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/mach-spear3xx/clock.c +2 -2
index 5bfeb6f..98bc7ed 100644
@@ -650,7 +650,7 @@ static struct clk pwm_clk = {
 
 /* array of all spear 3xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",	.clk = &dummy_apb_pclk},
+	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
 	/* root clks */
 	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
 	{ .con_id = "osc_24m_clk",	.clk = &osc_24m_clk},

@@ -674,8 +674,8 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .dev_id = "gpt1",		.clk = &gpt1_clk},
 	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
 	/* clock derived from pll3 clk */
+	{ .dev_id = "designware_udc",   .clk = &usbd_clk},
 	{ .con_id = "usbh_clk",		.clk = &usbh_clk},
-	{ .dev_id = "usbd",		.clk = &usbd_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
 	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
arch/arm/mach-spear6xx/clock.c +2 -2
index 4f351b4..88b748b 100644
@@ -622,7 +622,7 @@ static struct clk dummy_apb_pclk;
 
 /* array of all spear 6xx clock lookups */
 static struct clk_lookup spear_clk_lookups[] = {
-	{ .con_id = "apb_pclk",	.clk = &dummy_apb_pclk},
+	{ .con_id = "apb_pclk",		.clk = &dummy_apb_pclk},
 	/* root clks */
 	{ .con_id = "osc_32k_clk",	.clk = &osc_32k_clk},
 	{ .con_id = "osc_30m_clk",	.clk = &osc_30m_clk},

@@ -650,9 +650,9 @@ static struct clk_lookup spear_clk_lookups[] = {
 	{ .dev_id = "gpt2",		.clk = &gpt2_clk},
 	{ .dev_id = "gpt3",		.clk = &gpt3_clk},
 	/* clock derived from pll3 clk */
+	{ .dev_id = "designware_udc",	.clk = &usbd_clk},
 	{ .con_id = "usbh.0_clk",	.clk = &usbh0_clk},
 	{ .con_id = "usbh.1_clk",	.clk = &usbh1_clk},
-	{ .dev_id = "usbd",		.clk = &usbd_clk},
 	/* clock derived from ahb clk */
 	{ .con_id = "apb_clk",		.clk = &apb_clk},
 	{ .dev_id = "i2c_designware.0",	.clk = &i2c_clk},
Signature · 1 line
1.7.2.2
author
#5 lore raw

PATCH v6 5/8 ST SPEAr3xx: Declare device structures after shirq code

In reply to Viresh Kumar

Order of declarations should be: pmx_devs, shirq support, amba_devices, plat_devices, routines. This patch moves gpio_device below shirq support.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/spear300.c |   40 ++++++++++++++++++------------------
 arch/arm/mach-spear3xx/spear310.c |    4 +-
 arch/arm/mach-spear3xx/spear320.c |    4 +-
 3 files changed, 24 insertions(+), 24 deletions(-)
arch/arm/mach-spear3xx/spear300.c +20 -20
index 42dc29b..23d2a14 100644
@@ -370,26 +370,6 @@ struct pmx_driver pmx_driver = {
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear300 specific devices here */
-/* arm gpio1 device registration */
-static struct pl061_platform_data gpio1_plat_data = {
-	.gpio_base	= 8,
-	.irq_base	= SPEAR_GPIO1_INT_BASE,
-};
-
-struct amba_device gpio1_device = {
-	.dev = {
-		.init_name = "gpio1",
-		.platform_data = &gpio1_plat_data,
-	},
-	.res = {
-		.start = SPEAR300_GPIO_BASE,
-		.end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
-		.flags = IORESOURCE_MEM,
-	},
-	.irq = {VIRQ_GPIO1, NO_IRQ},
-};
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
 	{

@@ -443,6 +423,26 @@ struct spear_shirq shirq_ras1 = {
 	},
 };
 
+/* Add spear300 specific devices here */
+/* arm gpio1 device registration */
+static struct pl061_platform_data gpio1_plat_data = {
+	.gpio_base	= 8,
+	.irq_base	= SPEAR_GPIO1_INT_BASE,
+};
+
+struct amba_device gpio1_device = {
+	.dev = {
+		.init_name = "gpio1",
+		.platform_data = &gpio1_plat_data,
+	},
+	.res = {
+		.start = SPEAR300_GPIO_BASE,
+		.end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
+		.flags = IORESOURCE_MEM,
+	},
+	.irq = {VIRQ_GPIO1, NO_IRQ},
+};
+
 /* spear300 routines */
 void __init spear300_init(void)
 {
arch/arm/mach-spear3xx/spear310.c +2 -2
index 5bfab14..3a3d548 100644
@@ -139,8 +139,6 @@ struct pmx_driver pmx_driver = {
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear310 specific devices here */
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
 	{

@@ -257,6 +255,8 @@ struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
+/* Add spear310 specific devices here */
+
 /* spear310 routines */
 void __init spear310_init(void)
 {
arch/arm/mach-spear3xx/spear320.c +2 -2
index 6dba628..8ba3ff2 100644
@@ -384,8 +384,6 @@ struct pmx_driver pmx_driver = {
 	.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
 };
 
-/* Add spear320 specific devices here */
-
 /* spear3xx shared irq */
 struct shirq_dev_config shirq_ras1_config[] = {
 	{

@@ -510,6 +508,8 @@ struct spear_shirq shirq_intrcomm_ras = {
 	},
 };
 
+/* Add spear320 specific devices here */
+
 /* spear320 routines */
 void __init spear320_init(void)
 {
Signature · 1 line
1.7.2.2
author
#6 lore raw

PATCH v6 6/8 ST SPEAr: Replacing SIZE macro's with SZ_4K macros

In reply to Viresh Kumar

Resource size required mostly is 4K for all devices, whereas currently reserved space is much beyond that. This patch replaces SIZE macro's used at multiple places with SZ_4K.

Reviewed-by Stanley Miao <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/spear300.c |    8 +++-----
 arch/arm/mach-spear3xx/spear310.c |    2 +-
 arch/arm/mach-spear3xx/spear320.c |    2 +-
 arch/arm/mach-spear3xx/spear3xx.c |   12 ++++++------
 arch/arm/mach-spear6xx/spear6xx.c |   25 ++++++++++---------------
 5 files changed, 21 insertions(+), 28 deletions(-)
arch/arm/mach-spear3xx/spear300.c +3 -5
index 23d2a14..2697e65 100644
@@ -437,7 +437,7 @@ struct amba_device gpio1_device = {
 	},
 	.res = {
 		.start = SPEAR300_GPIO_BASE,
-		.end = SPEAR300_GPIO_BASE + SPEAR300_GPIO_SIZE - 1,
+		.end = SPEAR300_GPIO_BASE + SZ_4K - 1,
 		.flags = IORESOURCE_MEM,
 	},
 	.irq = {VIRQ_GPIO1, NO_IRQ},

@@ -452,8 +452,7 @@ void __init spear300_init(void)
 	spear3xx_init();
 
 	/* shared irq registration */
-	shirq_ras1.regs.base =
-		ioremap(SPEAR300_TELECOM_BASE, SPEAR300_TELECOM_REG_SIZE);
+	shirq_ras1.regs.base = ioremap(SPEAR300_TELECOM_BASE, SZ_4K);
 	if (shirq_ras1.regs.base) {
 		ret = spear_shirq_register(&shirq_ras1);
 		if (ret)

@@ -461,8 +460,7 @@ void __init spear300_init(void)
 	}
 
 	/* pmx initialization */
-	pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE,
-			SPEAR300_SOC_CONFIG_SIZE);
+	pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
 	if (pmx_driver.base) {
 		ret = pmx_register(&pmx_driver);
 		if (ret)
arch/arm/mach-spear3xx/spear310.c +1 -1
index 3a3d548..5c0a67b 100644
@@ -267,7 +267,7 @@ void __init spear310_init(void)
 	spear3xx_init();
 
 	/* shared irq registration */
-	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SPEAR310_SOC_CONFIG_SIZE);
+	base = ioremap(SPEAR310_SOC_CONFIG_BASE, SZ_4K);
 	if (base) {
 		/* shirq 1 */
 		shirq_ras1.regs.base = base;
arch/arm/mach-spear3xx/spear320.c +1 -1
index 8ba3ff2..741c1f4 100644
@@ -520,7 +520,7 @@ void __init spear320_init(void)
 	spear3xx_init();
 
 	/* shared irq registration */
-	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SPEAR320_SOC_CONFIG_SIZE);
+	base = ioremap(SPEAR320_SOC_CONFIG_BASE, SZ_4K);
 	if (base) {
 		/* shirq 1 */
 		shirq_ras1.regs.base = base;
arch/arm/mach-spear3xx/spear3xx.c +6 -6
index 634116f..d3ba8ca 100644
@@ -35,7 +35,7 @@ struct amba_device gpio_device = {
 	},
 	.res = {
 		.start = SPEAR3XX_ICM3_GPIO_BASE,
-		.end = SPEAR3XX_ICM3_GPIO_BASE + SPEAR3XX_ICM3_GPIO_SIZE - 1,
+		.end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
 		.flags = IORESOURCE_MEM,
 	},
 	.irq = {IRQ_BASIC_GPIO, NO_IRQ},

@@ -48,7 +48,7 @@ struct amba_device uart_device = {
 	},
 	.res = {
 		.start = SPEAR3XX_ICM1_UART_BASE,
-		.end = SPEAR3XX_ICM1_UART_BASE + SPEAR3XX_ICM1_UART_SIZE - 1,
+		.end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
 		.flags = IORESOURCE_MEM,
 	},
 	.irq = {IRQ_UART, NO_IRQ},

@@ -71,22 +71,22 @@ struct map_desc spear3xx_io_desc[] __initdata = {
 	{
 		.virtual	= VA_SPEAR3XX_ICM1_UART_BASE,
 		.pfn		= __phys_to_pfn(SPEAR3XX_ICM1_UART_BASE),
-		.length		= SPEAR3XX_ICM1_UART_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR3XX_ML1_VIC_BASE,
 		.pfn		= __phys_to_pfn(SPEAR3XX_ML1_VIC_BASE),
-		.length		= SPEAR3XX_ML1_VIC_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR3XX_ICM3_SYS_CTRL_BASE,
 		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_SYS_CTRL_BASE),
-		.length		= SPEAR3XX_ICM3_SYS_CTRL_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR3XX_ICM3_MISC_REG_BASE,
 		.pfn		= __phys_to_pfn(SPEAR3XX_ICM3_MISC_REG_BASE),
-		.length		= SPEAR3XX_ICM3_MISC_REG_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	},
 };
arch/arm/mach-spear6xx/spear6xx.c +10 -15
index 378440b..9818129 100644
@@ -31,8 +31,7 @@ struct amba_device uart_device[] = {
 		},
 		.res = {
 			.start = SPEAR6XX_ICM1_UART0_BASE,
-			.end = SPEAR6XX_ICM1_UART0_BASE +
-				SPEAR6XX_ICM1_UART0_SIZE - 1,
+			.end = SPEAR6XX_ICM1_UART0_BASE + SZ_4K - 1,
 			.flags = IORESOURCE_MEM,
 		},
 		.irq = {IRQ_UART_0, NO_IRQ},

@@ -42,8 +41,7 @@ struct amba_device uart_device[] = {
 		},
 		.res = {
 			.start = SPEAR6XX_ICM1_UART1_BASE,
-			.end = SPEAR6XX_ICM1_UART1_BASE +
-				SPEAR6XX_ICM1_UART1_SIZE - 1,
+			.end = SPEAR6XX_ICM1_UART1_BASE + SZ_4K - 1,
 			.flags = IORESOURCE_MEM,
 		},
 		.irq = {IRQ_UART_1, NO_IRQ},

@@ -72,8 +70,7 @@ struct amba_device gpio_device[] = {
 		},
 		.res = {
 			.start = SPEAR6XX_CPU_GPIO_BASE,
-			.end = SPEAR6XX_CPU_GPIO_BASE +
-				SPEAR6XX_CPU_GPIO_SIZE - 1,
+			.end = SPEAR6XX_CPU_GPIO_BASE + SZ_4K - 1,
 			.flags = IORESOURCE_MEM,
 		},
 		.irq = {IRQ_LOCAL_GPIO, NO_IRQ},

@@ -84,8 +81,7 @@ struct amba_device gpio_device[] = {
 		},
 		.res = {
 			.start = SPEAR6XX_ICM3_GPIO_BASE,
-			.end = SPEAR6XX_ICM3_GPIO_BASE +
-				SPEAR6XX_ICM3_GPIO_SIZE - 1,
+			.end = SPEAR6XX_ICM3_GPIO_BASE + SZ_4K - 1,
 			.flags = IORESOURCE_MEM,
 		},
 		.irq = {IRQ_BASIC_GPIO, NO_IRQ},

@@ -96,8 +92,7 @@ struct amba_device gpio_device[] = {
 		},
 		.res = {
 			.start = SPEAR6XX_ICM2_GPIO_BASE,
-			.end = SPEAR6XX_ICM2_GPIO_BASE +
-				SPEAR6XX_ICM2_GPIO_SIZE - 1,
+			.end = SPEAR6XX_ICM2_GPIO_BASE + SZ_4K - 1,
 			.flags = IORESOURCE_MEM,
 		},
 		.irq = {IRQ_APPL_GPIO, NO_IRQ},

@@ -122,27 +117,27 @@ static struct map_desc spear6xx_io_desc[] __initdata = {
 	{
 		.virtual	= VA_SPEAR6XX_ICM1_UART0_BASE,
 		.pfn		= __phys_to_pfn(SPEAR6XX_ICM1_UART0_BASE),
-		.length		= SPEAR6XX_ICM1_UART0_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR6XX_CPU_VIC_PRI_BASE,
 		.pfn		= __phys_to_pfn(SPEAR6XX_CPU_VIC_PRI_BASE),
-		.length		= SPEAR6XX_CPU_VIC_PRI_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR6XX_CPU_VIC_SEC_BASE,
 		.pfn		= __phys_to_pfn(SPEAR6XX_CPU_VIC_SEC_BASE),
-		.length		= SPEAR6XX_CPU_VIC_SEC_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR6XX_ICM3_SYS_CTRL_BASE,
 		.pfn		= __phys_to_pfn(SPEAR6XX_ICM3_SYS_CTRL_BASE),
-		.length		= SPEAR6XX_ICM3_MISC_REG_BASE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	}, {
 		.virtual	= VA_SPEAR6XX_ICM3_MISC_REG_BASE,
 		.pfn		= __phys_to_pfn(SPEAR6XX_ICM3_MISC_REG_BASE),
-		.length		= SPEAR6XX_ICM3_MISC_REG_SIZE,
+		.length		= SZ_4K,
 		.type		= MT_DEVICE
 	},
 };
Signature · 1 line
1.7.2.2
author
#7 lore raw

PATCH v6 7/8 ST SPEAr: Remove unused *_SIZE macros from spear*.h files

In reply to Viresh Kumar

Now we used standard SZ_* macros instead of self defined *_SIZE macros. This patch removes all such unused *_SIZE macros for spear3xx & 6xx.

Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/include/mach/spear.h    |   63 ------------------
 arch/arm/mach-spear3xx/include/mach/spear300.h |   29 --------
 arch/arm/mach-spear3xx/include/mach/spear310.h |   14 +----
 arch/arm/mach-spear3xx/include/mach/spear320.h |   32 +---------
 arch/arm/mach-spear6xx/include/mach/spear.h    |   83 ------------------------
 5 files changed, 2 insertions(+), 219 deletions(-)
arch/arm/mach-spear3xx/include/mach/spear.h +0 -63
index 8745802..df60e30 100644
@@ -19,118 +19,55 @@
 #include <mach/spear320.h>
 
 #define SPEAR3XX_ML_SDRAM_BASE		0x00000000
-#define SPEAR3XX_ML_SDRAM_SIZE		0x40000000
 
 #define SPEAR3XX_ICM9_BASE		0xC0000000
-#define SPEAR3XX_ICM9_SIZE		0x10000000
 
 /* ICM1 - Low speed connection */
 #define SPEAR3XX_ICM1_2_BASE		0xD0000000
-#define SPEAR3XX_ICM1_2_SIZE		0x10000000
-
 #define SPEAR3XX_ICM1_UART_BASE		0xD0000000
 #define VA_SPEAR3XX_ICM1_UART_BASE	IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_UART_SIZE		0x00080000
-
 #define SPEAR3XX_ICM1_ADC_BASE		0xD0080000
-#define SPEAR3XX_ICM1_ADC_SIZE		0x00080000
-
 #define SPEAR3XX_ICM1_SSP_BASE		0xD0100000
-#define SPEAR3XX_ICM1_SSP_SIZE		0x00080000
-
 #define SPEAR3XX_ICM1_I2C_BASE		0xD0180000
-#define SPEAR3XX_ICM1_I2C_SIZE		0x00080000
-
 #define SPEAR3XX_ICM1_JPEG_BASE		0xD0800000
-#define SPEAR3XX_ICM1_JPEG_SIZE		0x00800000
-
 #define SPEAR3XX_ICM1_IRDA_BASE		0xD1000000
-#define SPEAR3XX_ICM1_IRDA_SIZE		0x00080000
-
 #define SPEAR3XX_ICM1_SRAM_BASE		0xD2800000
-#define SPEAR3XX_ICM1_SRAM_SIZE		0x05800000
 
 /* ICM2 - Application Subsystem */
 #define SPEAR3XX_ICM2_HWACCEL0_BASE	0xD8800000
-#define SPEAR3XX_ICM2_HWACCEL0_SIZE	0x00800000
-
 #define SPEAR3XX_ICM2_HWACCEL1_BASE	0xD9000000
-#define SPEAR3XX_ICM2_HWACCEL1_SIZE	0x00800000
 
 /* ICM4 - High Speed Connection */
 #define SPEAR3XX_ICM4_BASE		0xE0000000
-#define SPEAR3XX_ICM4_SIZE		0x08000000
-
 #define SPEAR3XX_ICM4_MII_BASE		0xE0800000
-#define SPEAR3XX_ICM4_MII_SIZE		0x00800000
-
 #define SPEAR3XX_ICM4_USBD_FIFO_BASE	0xE1000000
-#define SPEAR3XX_ICM4_USBD_FIFO_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USBD_CSR_BASE	0xE1100000
-#define SPEAR3XX_ICM4_USBD_CSR_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USBD_PLDT_BASE	0xE1200000
-#define SPEAR3XX_ICM4_USBD_PLDT_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USB_EHCI0_1_BASE	0xE1800000
-#define SPEAR3XX_ICM4_USB_EHCI0_1_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USB_OHCI0_BASE	0xE1900000
-#define SPEAR3XX_ICM4_USB_OHCI0_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USB_OHCI1_BASE	0xE2100000
-#define SPEAR3XX_ICM4_USB_OHCI1_SIZE	0x00100000
-
 #define SPEAR3XX_ICM4_USB_ARB_BASE	0xE2800000
-#define SPEAR3XX_ICM4_USB_ARB_SIZE	0x00010000
 
 /* ML1 - Multi Layer CPU Subsystem */
 #define SPEAR3XX_ICM3_ML1_2_BASE	0xF0000000
-#define SPEAR3XX_ICM3_ML1_2_SIZE	0x0F000000
-
 #define SPEAR3XX_ML1_TMR_BASE		0xF0000000
-#define SPEAR3XX_ML1_TMR_SIZE		0x00100000
-
 #define SPEAR3XX_ML1_VIC_BASE		0xF1100000
 #define VA_SPEAR3XX_ML1_VIC_BASE	IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
-#define SPEAR3XX_ML1_VIC_SIZE		0x00100000
 
 /* ICM3 - Basic Subsystem */
 #define SPEAR3XX_ICM3_SMEM_BASE		0xF8000000
-#define SPEAR3XX_ICM3_SMEM_SIZE		0x04000000
-
 #define SPEAR3XX_ICM3_SMI_CTRL_BASE	0xFC000000
-#define SPEAR3XX_ICM3_SMI_CTRL_SIZE	0x00200000
-
 #define SPEAR3XX_ICM3_DMA_BASE		0xFC400000
-#define SPEAR3XX_ICM3_DMA_SIZE		0x00200000
-
 #define SPEAR3XX_ICM3_SDRAM_CTRL_BASE	0xFC600000
-#define SPEAR3XX_ICM3_SDRAM_CTRL_SIZE	0x00200000
-
 #define SPEAR3XX_ICM3_TMR0_BASE		0xFC800000
-#define SPEAR3XX_ICM3_TMR0_SIZE		0x00080000
-
 #define SPEAR3XX_ICM3_WDT_BASE		0xFC880000
-#define SPEAR3XX_ICM3_WDT_SIZE		0x00080000
-
 #define SPEAR3XX_ICM3_RTC_BASE		0xFC900000
-#define SPEAR3XX_ICM3_RTC_SIZE		0x00080000
-
 #define SPEAR3XX_ICM3_GPIO_BASE		0xFC980000
-#define SPEAR3XX_ICM3_GPIO_SIZE		0x00080000
-
 #define SPEAR3XX_ICM3_SYS_CTRL_BASE	0xFCA00000
 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE	IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_SYS_CTRL_SIZE	0x00080000
-
 #define SPEAR3XX_ICM3_MISC_REG_BASE	0xFCA80000
 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE	IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_SIZE	0x00080000
-
 #define SPEAR3XX_ICM3_TMR1_BASE		0xFCB00000
-#define SPEAR3XX_ICM3_TMR1_SIZE		0x00080000
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE		SPEAR3XX_ICM1_UART_BASE
arch/arm/mach-spear3xx/include/mach/spear300.h +0 -29
index 1059d5a..8f96cc5 100644
@@ -18,10 +18,8 @@
 
 /* Base address of various IPs */
 #define SPEAR300_TELECOM_BASE		0x50000000
-#define SPEAR300_TELECOM_SIZE		0x10000000
 
 /* Interrupt registers offsets and masks */
-#define SPEAR300_TELECOM_REG_SIZE	0x00010000
 #define INT_ENB_MASK_REG		0x54
 #define INT_STS_MASK_REG		0x58
 #define IT_PERS_S_IRQ_MASK		(1 << 0)

@@ -37,46 +35,19 @@
 #define SHIRQ_RAS1_MASK			0x1FF
 
 #define SPEAR300_CLCD_BASE		0x60000000
-#define SPEAR300_CLCD_SIZE		0x10000000
-
 #define SPEAR300_SDHCI_BASE		0x70000000
-#define SPEAR300_SDHCI_SIZE		0x10000000
-
 #define SPEAR300_NAND_0_BASE		0x80000000
-#define SPEAR300_NAND_0_SIZE		0x04000000
-
 #define SPEAR300_NAND_1_BASE		0x84000000
-#define SPEAR300_NAND_1_SIZE		0x04000000
-
 #define SPEAR300_NAND_2_BASE		0x88000000
-#define SPEAR300_NAND_2_SIZE		0x04000000
-
 #define SPEAR300_NAND_3_BASE		0x8c000000
-#define SPEAR300_NAND_3_SIZE		0x04000000
-
 #define SPEAR300_NOR_0_BASE		0x90000000
-#define SPEAR300_NOR_0_SIZE		0x01000000
-
 #define SPEAR300_NOR_1_BASE		0x91000000
-#define SPEAR300_NOR_1_SIZE		0x01000000
-
 #define SPEAR300_NOR_2_BASE		0x92000000
-#define SPEAR300_NOR_2_SIZE		0x01000000
-
 #define SPEAR300_NOR_3_BASE		0x93000000
-#define SPEAR300_NOR_3_SIZE		0x01000000
-
 #define SPEAR300_FSMC_BASE		0x94000000
-#define SPEAR300_FSMC_SIZE		0x05000000
-
 #define SPEAR300_SOC_CONFIG_BASE	0x99000000
-#define SPEAR300_SOC_CONFIG_SIZE	0x00000008
-
 #define SPEAR300_KEYBOARD_BASE		0xA0000000
-#define SPEAR300_KEYBOARD_SIZE		0x09000000
-
 #define SPEAR300_GPIO_BASE		0xA9000000
-#define SPEAR300_GPIO_SIZE		0x07000000
 
 #endif /* __MACH_SPEAR300_H */
arch/arm/mach-spear3xx/include/mach/spear310.h +1 -13
index b27bb8a..4f58eb1 100644
@@ -17,29 +17,17 @@
 #define __MACH_SPEAR310_H
 
 #define SPEAR310_NAND_BASE		0x40000000
-#define SPEAR310_NAND_SIZE		0x04000000
-
 #define SPEAR310_FSMC_BASE		0x44000000
-#define SPEAR310_FSMC_SIZE		0x01000000
-
 #define SPEAR310_UART1_BASE		0xB2000000
 #define SPEAR310_UART2_BASE		0xB2080000
 #define SPEAR310_UART3_BASE		0xB2100000
 #define SPEAR310_UART4_BASE		0xB2180000
 #define SPEAR310_UART5_BASE		0xB2200000
-#define SPEAR310_UART_SIZE		0x00080000
-
 #define SPEAR310_HDLC_BASE		0xB2800000
-#define SPEAR310_HDLC_SIZE		0x00800000
-
 #define SPEAR310_RS485_0_BASE		0xB3000000
-#define SPEAR310_RS485_0_SIZE		0x00800000
-
 #define SPEAR310_RS485_1_BASE		0xB3800000
-#define SPEAR310_RS485_1_SIZE		0x00800000
-
 #define SPEAR310_SOC_CONFIG_BASE	0xB4000000
-#define SPEAR310_SOC_CONFIG_SIZE	0x00000070
+
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG		0x04
 #define SMII0_IRQ_MASK			(1 << 0)
arch/arm/mach-spear3xx/include/mach/spear320.h +1 -31
index 1c9d310..95bdb2e 100644
@@ -17,53 +17,23 @@
 #define __MACH_SPEAR320_H
 
 #define SPEAR320_EMI_CTRL_BASE		0x40000000
-#define SPEAR320_EMI_CTRL_SIZE		0x08000000
-
 #define SPEAR320_FSMC_BASE		0x4C000000
-#define SPEAR320_FSMC_SIZE		0x01000000
-
 #define SPEAR320_I2S_BASE		0x60000000
-#define SPEAR320_I2S_SIZE		0x10000000
-
 #define SPEAR320_SDHCI_BASE		0x70000000
-#define SPEAR320_SDHCI_SIZE		0x10000000
-
 #define SPEAR320_CLCD_BASE		0x90000000
-#define SPEAR320_CLCD_SIZE		0x10000000
-
 #define SPEAR320_PAR_PORT_BASE		0xA0000000
-#define SPEAR320_PAR_PORT_SIZE		0x01000000
-
 #define SPEAR320_CAN0_BASE		0xA1000000
-#define SPEAR320_CAN0_SIZE		0x01000000
-
 #define SPEAR320_CAN1_BASE		0xA2000000
-#define SPEAR320_CAN1_SIZE		0x01000000
-
 #define SPEAR320_UART1_BASE		0xA3000000
 #define SPEAR320_UART2_BASE		0xA4000000
-#define SPEAR320_UART_SIZE		0x01000000
-
 #define SPEAR320_SSP0_BASE		0xA5000000
-#define SPEAR320_SSP0_SIZE		0x01000000
-
 #define SPEAR320_SSP1_BASE		0xA6000000
-#define SPEAR320_SSP1_SIZE		0x01000000
-
 #define SPEAR320_I2C_BASE		0xA7000000
-#define SPEAR320_I2C_SIZE		0x01000000
-
 #define SPEAR320_PWM_BASE		0xA8000000
-#define SPEAR320_PWM_SIZE		0x01000000
-
 #define SPEAR320_SMII0_BASE		0xAA000000
-#define SPEAR320_SMII0_SIZE		0x01000000
-
 #define SPEAR320_SMII1_BASE		0xAB000000
-#define SPEAR320_SMII1_SIZE		0x01000000
-
 #define SPEAR320_SOC_CONFIG_BASE	0xB3000000
-#define SPEAR320_SOC_CONFIG_SIZE	0x00000070
+
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG		0x04
 #define INT_CLR_MASK_REG		0x04
arch/arm/mach-spear6xx/include/mach/spear.h +0 -83

149 lines not on this page · raw message

Signature · 1 line
1.7.2.2
#8 lore raw

PATCH v6 7/8 ST SPEAr: Remove unused *_SIZE macros from spear*.h files

Quoted 2 lines · Viresh Kumar

Now we used standard SZ_* macros instead of self defined *_SIZE macros. This patch removes all such unused *_SIZE macros for spear3xx & 6xx.

This doesn't appear to apply to spear320.h:

error: patch failed: arch/arm/mach-spear3xx/include/mach/spear320.h:17
error: arch/arm/mach-spear3xx/include/mach/spear320.h: patch does not apply

author
#9 lore raw

PATCH v6 7/8 ST SPEAr: Remove unused *_SIZE macros from spear*.h files

Quoted 9 lines · Russell King - ARM Linux
Quoted 2 lines · Viresh Kumar

Now we used standard SZ_* macros instead of self defined *_SIZE macros. This patch removes all such unused *_SIZE macros for spear3xx & 6xx.

This doesn't appear to apply to spear320.h:

error: patch failed: arch/arm/mach-spear3xx/include/mach/spear320.h:17
error: arch/arm/mach-spear3xx/include/mach/spear320.h: patch does not apply

Sorry for that.
I rechecked my branch and found, i had rebased this patchset over your devel branch, which contained both spear & fixes changes.

This error came due to a fix in spear320.h file, which was:
-#define SPEAR320_SOC_CONFIG_BASE 0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE 0xB3000000

Just a question, Shouldn't i have rebased it on devel only? As these patches may depend on already committed patches, that are present in spear & fixes branch.

Signature · 1 line
viresh
author
#10 lore raw

PATCH v6 8/8 ST SPEAr: Append UL to device address macros.

In reply to Viresh Kumar

From: Shiraz Hashim <[email protected]>

Reviewed-by Stanley Miao <[email protected]>
Signed-off-by Shiraz Hashim <[email protected]>
Signed-off-by Rajeev Kumar <[email protected]>
Signed-off-by Viresh Kumar <[email protected]>
---
 arch/arm/mach-spear3xx/include/mach/spear.h    |   71 +++++++++---------
 arch/arm/mach-spear3xx/include/mach/spear300.h |   30 ++++----
 arch/arm/mach-spear3xx/include/mach/spear310.h |   22 +++---
 arch/arm/mach-spear3xx/include/mach/spear320.h |   35 +++++-----
 arch/arm/mach-spear6xx/include/mach/spear.h    |   91 ++++++++++++------------
 5 files changed, 126 insertions(+), 123 deletions(-)
arch/arm/mach-spear3xx/include/mach/spear.h +36 -35
index df60e30..63fd983 100644
@@ -14,60 +14,61 @@
 #ifndef __MACH_SPEAR3XX_H
 #define __MACH_SPEAR3XX_H
 
+#include <asm/memory.h>
 #include <mach/spear300.h>
 #include <mach/spear310.h>
 #include <mach/spear320.h>
 
-#define SPEAR3XX_ML_SDRAM_BASE		0x00000000
+#define SPEAR3XX_ML_SDRAM_BASE		UL(0x00000000)
 
-#define SPEAR3XX_ICM9_BASE		0xC0000000
+#define SPEAR3XX_ICM9_BASE		UL(0xC0000000)
 
 /* ICM1 - Low speed connection */
-#define SPEAR3XX_ICM1_2_BASE		0xD0000000
-#define SPEAR3XX_ICM1_UART_BASE		0xD0000000
+#define SPEAR3XX_ICM1_2_BASE		UL(0xD0000000)
+#define SPEAR3XX_ICM1_UART_BASE		UL(0xD0000000)
 #define VA_SPEAR3XX_ICM1_UART_BASE	IO_ADDRESS(SPEAR3XX_ICM1_UART_BASE)
-#define SPEAR3XX_ICM1_ADC_BASE		0xD0080000
-#define SPEAR3XX_ICM1_SSP_BASE		0xD0100000
-#define SPEAR3XX_ICM1_I2C_BASE		0xD0180000
-#define SPEAR3XX_ICM1_JPEG_BASE		0xD0800000
-#define SPEAR3XX_ICM1_IRDA_BASE		0xD1000000
-#define SPEAR3XX_ICM1_SRAM_BASE		0xD2800000
+#define SPEAR3XX_ICM1_ADC_BASE		UL(0xD0080000)
+#define SPEAR3XX_ICM1_SSP_BASE		UL(0xD0100000)
+#define SPEAR3XX_ICM1_I2C_BASE		UL(0xD0180000)
+#define SPEAR3XX_ICM1_JPEG_BASE		UL(0xD0800000)
+#define SPEAR3XX_ICM1_IRDA_BASE		UL(0xD1000000)
+#define SPEAR3XX_ICM1_SRAM_BASE		UL(0xD2800000)
 
 /* ICM2 - Application Subsystem */
-#define SPEAR3XX_ICM2_HWACCEL0_BASE	0xD8800000
-#define SPEAR3XX_ICM2_HWACCEL1_BASE	0xD9000000
+#define SPEAR3XX_ICM2_HWACCEL0_BASE	UL(0xD8800000)
+#define SPEAR3XX_ICM2_HWACCEL1_BASE	UL(0xD9000000)
 
 /* ICM4 - High Speed Connection */
-#define SPEAR3XX_ICM4_BASE		0xE0000000
-#define SPEAR3XX_ICM4_MII_BASE		0xE0800000
-#define SPEAR3XX_ICM4_USBD_FIFO_BASE	0xE1000000
-#define SPEAR3XX_ICM4_USBD_CSR_BASE	0xE1100000
-#define SPEAR3XX_ICM4_USBD_PLDT_BASE	0xE1200000
-#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE	0xE1800000
-#define SPEAR3XX_ICM4_USB_OHCI0_BASE	0xE1900000
-#define SPEAR3XX_ICM4_USB_OHCI1_BASE	0xE2100000
-#define SPEAR3XX_ICM4_USB_ARB_BASE	0xE2800000
+#define SPEAR3XX_ICM4_BASE		UL(0xE0000000)
+#define SPEAR3XX_ICM4_MII_BASE		UL(0xE0800000)
+#define SPEAR3XX_ICM4_USBD_FIFO_BASE	UL(0xE1000000)
+#define SPEAR3XX_ICM4_USBD_CSR_BASE	UL(0xE1100000)
+#define SPEAR3XX_ICM4_USBD_PLDT_BASE	UL(0xE1200000)
+#define SPEAR3XX_ICM4_USB_EHCI0_1_BASE	UL(0xE1800000)
+#define SPEAR3XX_ICM4_USB_OHCI0_BASE	UL(0xE1900000)
+#define SPEAR3XX_ICM4_USB_OHCI1_BASE	UL(0xE2100000)
+#define SPEAR3XX_ICM4_USB_ARB_BASE	UL(0xE2800000)
 
 /* ML1 - Multi Layer CPU Subsystem */
-#define SPEAR3XX_ICM3_ML1_2_BASE	0xF0000000
-#define SPEAR3XX_ML1_TMR_BASE		0xF0000000
-#define SPEAR3XX_ML1_VIC_BASE		0xF1100000
+#define SPEAR3XX_ICM3_ML1_2_BASE	UL(0xF0000000)
+#define SPEAR3XX_ML1_TMR_BASE		UL(0xF0000000)
+#define SPEAR3XX_ML1_VIC_BASE		UL(0xF1100000)
 #define VA_SPEAR3XX_ML1_VIC_BASE	IO_ADDRESS(SPEAR3XX_ML1_VIC_BASE)
 
 /* ICM3 - Basic Subsystem */
-#define SPEAR3XX_ICM3_SMEM_BASE		0xF8000000
-#define SPEAR3XX_ICM3_SMI_CTRL_BASE	0xFC000000
-#define SPEAR3XX_ICM3_DMA_BASE		0xFC400000
-#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE	0xFC600000
-#define SPEAR3XX_ICM3_TMR0_BASE		0xFC800000
-#define SPEAR3XX_ICM3_WDT_BASE		0xFC880000
-#define SPEAR3XX_ICM3_RTC_BASE		0xFC900000
-#define SPEAR3XX_ICM3_GPIO_BASE		0xFC980000
-#define SPEAR3XX_ICM3_SYS_CTRL_BASE	0xFCA00000
+#define SPEAR3XX_ICM3_SMEM_BASE		UL(0xF8000000)
+#define SPEAR3XX_ICM3_SMI_CTRL_BASE	UL(0xFC000000)
+#define SPEAR3XX_ICM3_DMA_BASE		UL(0xFC400000)
+#define SPEAR3XX_ICM3_SDRAM_CTRL_BASE	UL(0xFC600000)
+#define SPEAR3XX_ICM3_TMR0_BASE		UL(0xFC800000)
+#define SPEAR3XX_ICM3_WDT_BASE		UL(0xFC880000)
+#define SPEAR3XX_ICM3_RTC_BASE		UL(0xFC900000)
+#define SPEAR3XX_ICM3_GPIO_BASE		UL(0xFC980000)
+#define SPEAR3XX_ICM3_SYS_CTRL_BASE	UL(0xFCA00000)
 #define VA_SPEAR3XX_ICM3_SYS_CTRL_BASE	IO_ADDRESS(SPEAR3XX_ICM3_SYS_CTRL_BASE)
-#define SPEAR3XX_ICM3_MISC_REG_BASE	0xFCA80000
+#define SPEAR3XX_ICM3_MISC_REG_BASE	UL(0xFCA80000)
 #define VA_SPEAR3XX_ICM3_MISC_REG_BASE	IO_ADDRESS(SPEAR3XX_ICM3_MISC_REG_BASE)
-#define SPEAR3XX_ICM3_TMR1_BASE		0xFCB00000
+#define SPEAR3XX_ICM3_TMR1_BASE		UL(0xFCB00000)
 
 /* Debug uart for linux, will be used for debug and uncompress messages */
 #define SPEAR_DBG_UART_BASE		SPEAR3XX_ICM1_UART_BASE
arch/arm/mach-spear3xx/include/mach/spear300.h +15 -15
index 8f96cc5..c723515 100644
@@ -17,7 +17,7 @@
 #define __MACH_SPEAR300_H
 
 /* Base address of various IPs */
-#define SPEAR300_TELECOM_BASE		0x50000000
+#define SPEAR300_TELECOM_BASE		UL(0x50000000)
 
 /* Interrupt registers offsets and masks */
 #define INT_ENB_MASK_REG		0x54

@@ -34,20 +34,20 @@
 
 #define SHIRQ_RAS1_MASK			0x1FF
 
-#define SPEAR300_CLCD_BASE		0x60000000
-#define SPEAR300_SDHCI_BASE		0x70000000
-#define SPEAR300_NAND_0_BASE		0x80000000
-#define SPEAR300_NAND_1_BASE		0x84000000
-#define SPEAR300_NAND_2_BASE		0x88000000
-#define SPEAR300_NAND_3_BASE		0x8c000000
-#define SPEAR300_NOR_0_BASE		0x90000000
-#define SPEAR300_NOR_1_BASE		0x91000000
-#define SPEAR300_NOR_2_BASE		0x92000000
-#define SPEAR300_NOR_3_BASE		0x93000000
-#define SPEAR300_FSMC_BASE		0x94000000
-#define SPEAR300_SOC_CONFIG_BASE	0x99000000
-#define SPEAR300_KEYBOARD_BASE		0xA0000000
-#define SPEAR300_GPIO_BASE		0xA9000000
+#define SPEAR300_CLCD_BASE		UL(0x60000000)
+#define SPEAR300_SDHCI_BASE		UL(0x70000000)
+#define SPEAR300_NAND_0_BASE		UL(0x80000000)
+#define SPEAR300_NAND_1_BASE		UL(0x84000000)
+#define SPEAR300_NAND_2_BASE		UL(0x88000000)
+#define SPEAR300_NAND_3_BASE		UL(0x8c000000)
+#define SPEAR300_NOR_0_BASE		UL(0x90000000)
+#define SPEAR300_NOR_1_BASE		UL(0x91000000)
+#define SPEAR300_NOR_2_BASE		UL(0x92000000)
+#define SPEAR300_NOR_3_BASE		UL(0x93000000)
+#define SPEAR300_FSMC_BASE		UL(0x94000000)
+#define SPEAR300_SOC_CONFIG_BASE	UL(0x99000000)
+#define SPEAR300_KEYBOARD_BASE		UL(0xA0000000)
+#define SPEAR300_GPIO_BASE		UL(0xA9000000)
 
 #endif /* __MACH_SPEAR300_H */
arch/arm/mach-spear3xx/include/mach/spear310.h +11 -11
index 4f58eb1..1e85347 100644
@@ -16,17 +16,17 @@
 #ifndef __MACH_SPEAR310_H
 #define __MACH_SPEAR310_H
 
-#define SPEAR310_NAND_BASE		0x40000000
-#define SPEAR310_FSMC_BASE		0x44000000
-#define SPEAR310_UART1_BASE		0xB2000000
-#define SPEAR310_UART2_BASE		0xB2080000
-#define SPEAR310_UART3_BASE		0xB2100000
-#define SPEAR310_UART4_BASE		0xB2180000
-#define SPEAR310_UART5_BASE		0xB2200000
-#define SPEAR310_HDLC_BASE		0xB2800000
-#define SPEAR310_RS485_0_BASE		0xB3000000
-#define SPEAR310_RS485_1_BASE		0xB3800000
-#define SPEAR310_SOC_CONFIG_BASE	0xB4000000
+#define SPEAR310_NAND_BASE		UL(0x40000000)
+#define SPEAR310_FSMC_BASE		UL(0x44000000)
+#define SPEAR310_UART1_BASE		UL(0xB2000000)
+#define SPEAR310_UART2_BASE		UL(0xB2080000)
+#define SPEAR310_UART3_BASE		UL(0xB2100000)
+#define SPEAR310_UART4_BASE		UL(0xB2180000)
+#define SPEAR310_UART5_BASE		UL(0xB2200000)
+#define SPEAR310_HDLC_BASE		UL(0xB2800000)
+#define SPEAR310_RS485_0_BASE		UL(0xB3000000)
+#define SPEAR310_RS485_1_BASE		UL(0xB3800000)
+#define SPEAR310_SOC_CONFIG_BASE	UL(0xB4000000)
 
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG		0x04
arch/arm/mach-spear3xx/include/mach/spear320.h +18 -17
index 95bdb2e..940f0d8 100644
@@ -16,23 +16,24 @@
 #ifndef __MACH_SPEAR320_H
 #define __MACH_SPEAR320_H
 
-#define SPEAR320_EMI_CTRL_BASE		0x40000000
-#define SPEAR320_FSMC_BASE		0x4C000000
-#define SPEAR320_I2S_BASE		0x60000000
-#define SPEAR320_SDHCI_BASE		0x70000000
-#define SPEAR320_CLCD_BASE		0x90000000
-#define SPEAR320_PAR_PORT_BASE		0xA0000000
-#define SPEAR320_CAN0_BASE		0xA1000000
-#define SPEAR320_CAN1_BASE		0xA2000000
-#define SPEAR320_UART1_BASE		0xA3000000
-#define SPEAR320_UART2_BASE		0xA4000000
-#define SPEAR320_SSP0_BASE		0xA5000000
-#define SPEAR320_SSP1_BASE		0xA6000000
-#define SPEAR320_I2C_BASE		0xA7000000
-#define SPEAR320_PWM_BASE		0xA8000000
-#define SPEAR320_SMII0_BASE		0xAA000000
-#define SPEAR320_SMII1_BASE		0xAB000000
-#define SPEAR320_SOC_CONFIG_BASE	0xB3000000
+#define SPEAR320_EMI_CTRL_BASE		UL(0x40000000)
+#define SPEAR320_FSMC_BASE		UL(0x4C000000)
+#define SPEAR320_NAND_BASE		UL(0x50000000)
+#define SPEAR320_I2S_BASE		UL(0x60000000)
+#define SPEAR320_SDHCI_BASE		UL(0x70000000)
+#define SPEAR320_CLCD_BASE		UL(0x90000000)
+#define SPEAR320_PAR_PORT_BASE		UL(0xA0000000)
+#define SPEAR320_CAN0_BASE		UL(0xA1000000)
+#define SPEAR320_CAN1_BASE		UL(0xA2000000)
+#define SPEAR320_UART1_BASE		UL(0xA3000000)
+#define SPEAR320_UART2_BASE		UL(0xA4000000)
+#define SPEAR320_SSP0_BASE		UL(0xA5000000)
+#define SPEAR320_SSP1_BASE		UL(0xA6000000)
+#define SPEAR320_I2C_BASE		UL(0xA7000000)
+#define SPEAR320_PWM_BASE		UL(0xA8000000)
+#define SPEAR320_SMII0_BASE		UL(0xAA000000)
+#define SPEAR320_SMII1_BASE		UL(0xAB000000)
+#define SPEAR320_SOC_CONFIG_BASE	UL(0xB3000000)
 
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG		0x04
arch/arm/mach-spear6xx/include/mach/spear.h +46 -45

115 lines not on this page · raw message

Signature · 1 line
1.7.2.2
#11 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

In reply to Viresh Kumar
Quoted 2 lines · Viresh Kumar

This patchset contains minor fixes, renames, & reordering of code of #include files.

This set looks absolutely fine. I assume that it should apply on top of my 'spear' branch? If so, please submit this series to the patch system, thanks.

#12 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

Quoted 7 lines · Russell King - ARM Linux
Quoted 2 lines · Viresh Kumar

This patchset contains minor fixes, renames, & reordering of code of #include files.

This set looks absolutely fine. I assume that it should apply on top of my 'spear' branch? If so, please submit this series to the patch system, thanks.

BTW, please drop the 'ST ' from the subject lines, I don't think there's any other SPEAr which it could be confused with.

For 'ST SPEAr Clock Framework: ...' please use 'SPEAr: Clock Framework: ...' instead.

Thanks.

#13 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

Quoted 9 lines · Russell King - ARM Linux
Quoted 7 lines · Russell King - ARM Linux
Quoted 2 lines · Viresh Kumar

This patchset contains minor fixes, renames, & reordering of code of #include files.

This set looks absolutely fine. I assume that it should apply on top of my 'spear' branch? If so, please submit this series to the patch system, thanks.

Quoted 5 lines

BTW, please drop the 'ST ' from the subject lines, I don't think there's any other SPEAr which it could be confused with.

For 'ST SPEAr Clock Framework: ...' please use 'SPEAr: Clock Framework: ...' instead.

One last comment on the subject lines - please don't use 'Replacing' etc, but 'Replace' - as the replacement is not an ongoing exercise. Same for other patches which use '-ing' verbs in their subject.

author
#14 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

Quoted 13 lines · Russell King - ARM Linux
Quoted 12 lines · Russell King - ARM Linux
Quoted 7 lines · Russell King - ARM Linux
Quoted 2 lines · Viresh Kumar

This patchset contains minor fixes, renames, & reordering of code of #include files.

This set looks absolutely fine. I assume that it should apply on top of my 'spear' branch? If so, please submit this series to the patch system, thanks.

BTW, please drop the 'ST ' from the subject lines, I don't think there's any other SPEAr which it could be confused with.

Quoted 8 lines
Quoted 2 lines

For 'ST SPEAr Clock Framework: ...' please use 'SPEAr: Clock Framework: ...' instead.

One last comment on the subject lines - please don't use 'Replacing' etc, but 'Replace' - as the replacement is not an ongoing exercise. Same for other patches which use '-ing' verbs in their subject.
.

Ok.

Signature · 1 line
viresh
author
#15 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

In reply to Russell King - ARM Linux
Quoted 5 lines · Russell King - ARM Linux

BTW, please drop the 'ST ' from the subject lines, I don't think there's any other SPEAr which it could be confused with.

For 'ST SPEAr Clock Framework: ...' please use 'SPEAr: Clock Framework: ...' instead.

Ok.

Signature · 1 line
viresh
author
#16 lore raw

v6 cover SPEAr3xx & SPEAr6xx Fixes

In reply to Russell King - ARM Linux
Quoted 8 lines · Russell King - ARM Linux
Quoted 2 lines · Viresh Kumar

This patchset contains minor fixes, renames, & reordering of code of #include files.

This set looks absolutely fine. I assume that it should apply on top of my 'spear' branch? If so, please submit this series to the patch system, thanks.
.

Yes, it will apply on spear branch.

Signature · 1 line
viresh