fsl_esdhc: Correcting esdhc timeout counter calculation
PATCH v3 1/1 fsl_esdhc: Correcting esdhc timeout counter calculation
- Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles
- As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles
- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1
---
Changes for v3:
Including code changes of v1 as suggested by Stefano Babic
Changes for v2:
Added proper description as suggested by Wolfgang Denk
drivers/mmc/fsl_esdhc.c | 16 +++++++++++++++- 1 files changed, 15 insertions(+), 1 deletions(-)
drivers/mmc/fsl_esdhc.c +15 -1
@@ -207,7 +207,21 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)esdhc_write32 (®s->blkattr, data->blocks <<16 | data->blocksize);/* Calculate the timeout period for data transactions */ - timeout =fls (mmc->tran_speed/10 ) -1 ; +/* +* 1)Timeout period = (2^(timeout+13)) SD Clock cycles +* 2)Timeout period should be minimum 0.250sec as per SD Card spec +* So, Number of SD Clock cycles for 0.25sec should be minimum +* (SD Clock/sec * 0.25 sec) SD Clock cycles +* = (mmc->tran_speed * 1/4) SD Clock cycles +* As 1) >= 2) +* => (2^(timeout+13)) >= mmc->tran_speed * 1/4 +* Taking log2 both the sides +* => timeout + 13 >= log2(mmc->tran_speed/4) +* Rounding up to next power of 2 +* => timeout + 13 = log2(mmc->tran_speed/4) + 1 +* => timeout + 13 = fls(mmc->tran_speed/4) +*/ + timeout =fls (mmc->tran_speed/4 ); timeout -=13 ;if (timeout >14 )
Signature · 1 line
1.6.5.6
PATCH v3 1/1 fsl_esdhc: Correcting esdhc timeout counter calculation
Quoted 24 lines · Priyanka Jain
- Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles- As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1Signed-off-by Priyanka Jain <[email protected]>Signed-off-by Andy Fleming <[email protected]>Signed-off-by Kumar Gala <[email protected]>Acked-by Mingkai Hu <[email protected]>---
Changes for v3:
Including code changes of v1 as suggested by Stefano Babic
Quoted 5 lines
Changes for v2:
Added proper description as suggested by Wolfgang Denk
drivers/mmc/fsl_esdhc.c| 16 +++++++++++++++-1 files changed, 15 insertions(+), 1 deletions(-)
Stefano,
Got a chance to test on imx? Would like this fix in v2011.03
- k
PATCH v3 1/1 fsl_esdhc: Correcting esdhc timeout counter calculation
In reply to Priyanka JainQuoted 16 lines · Priyanka Jain
- Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles- As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1
Quoted 5 lines
Signed-off-by Priyanka Jain <[email protected]>Signed-off-by Andy Fleming <[email protected]>Signed-off-by Kumar Gala <[email protected]>Acked-by Mingkai Hu <[email protected]>---
Tested on a i.MX51 board.
Best regards,
Stefano Babic
Signature · 5 lines
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Kumar Gala
AppliedPATCH v3 1/1 fsl_esdhc: Correcting esdhc timeout counter calculation
Quoted 23 lines · Stefano Babic
Quoted 16 lines · Priyanka Jain
- Timeout counter value is set as DTOCV bits in SYSCTL register For counter value set as timeout,
Timeout period = (2^(timeout + 13)) SD Clock cycles- As per 4.6.2.2 section of SD Card specification v2.00, host should cofigure timeout period value to minimum 0.25 sec.
- Number of SD Clock cycles for 0.25sec should be minimum
(SD Clock/sec * 0.25 sec) SD Clock cycles = (mmc->tran_speed * 1/4) SD Clock cycles- Calculating timeout based on
(2^(timeout + 13)) >= mmc->tran_speed * 1/4 Taking log2 both the sides and rounding up to next power of 2 => timeout + 13 = log2(mmc->tran_speed/4) + 1Quoted 5 lines
Signed-off-by Priyanka Jain <[email protected]>Signed-off-by Andy Fleming <[email protected]>Signed-off-by Kumar Gala <[email protected]>Acked-by Mingkai Hu <[email protected]>---
Quoted 6 lines
Tested on a i.MX51 board.
Tested-by Stefano Babic <[email protected]>Best regards,
Stefano Babic
thanks
applied.
- k