MIPS: Refactoring of CPU and SoC code

All current Mips CPUs and SoCs except Purple are based on Mips32 arch. The complete code resides in the global arch/mips/cpu directory. All SoC specific code resides in this directory too. This is not suitable if other Mips architectures like Mips64 or Octeon or new SoCs should be supported in the future.

This patch series refactors the Mips CPU directory and put all current code into an own mips32 subdirectory. Furthermore the SoC specific code of IncaIP and Au1x00 is moved to separate SoC subdirectories. The support for Purple is dropped because not actively maintained anymore.

Changes since RFC/v1:
- drop Purple supported as agreed with Wolfgang Denk
- use MIPS rather than Mips in patch subject
- fixed Cc lines in all patches

Daniel Schwierzeck (5):
MIPS: Purple: Remove Purple support
MIPS: Move content of arch/mips/cpu to arch/mips/cpu/mips32
MIPS: Optimize the setup of endianess and CPU optimization flags
MIPS: IncaIP: Move all IncaIP specific code to separate subdirectory
MIPS: Au1x00: Move all Au1x00 specific code to separate subdirectory

 MAINTAINERS                                        |    1 -
 MAKEALL                                            |    4 +-
 arch/mips/cpu/asc_serial.c                         |  368 ------------
 arch/mips/cpu/config.mk                            |   39 --
 arch/mips/cpu/{ => mips32}/Makefile                |    5 -
 .../mips/cpu/mips32/au1x00}/Makefile               |   15 +-
 arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c     |    0
 arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c  |    0
 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c |    0
 .../mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h |    0
 .../mips/cpu/mips32/au1x00}/config.mk              |   12 +-
 arch/mips/cpu/{ => mips32}/cache.S                 |    4 -
 arch/mips/cpu/mips32/config.mk                     |   32 +
 arch/mips/cpu/{ => mips32}/cpu.c                   |    0
 .../mips/cpu/mips32/incaip}/Makefile               |   16 +-
 arch/mips/cpu/mips32/incaip/asc_serial.c           |  285 ++++++++++
 arch/mips/cpu/{ => mips32/incaip}/asc_serial.h     |    0
 .../mips/cpu/mips32/incaip}/config.mk              |   12 +-
 arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c   |    0
 arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S     |    0
 arch/mips/cpu/{ => mips32}/interrupts.c            |    0
 arch/mips/cpu/{ => mips32}/start.S                 |   32 -
 arch/mips/include/asm/inca-ip.h                    |   10 -
 arch/mips/lib/board.c                              |   10 -
 board/purple/flash.c                               |  595 --------------------
 board/purple/lowlevel_init.S                       |   36 --
 board/purple/purple.c                              |  284 ----------
 board/purple/sconsole.c                            |  125 ----
 board/purple/sconsole.h                            |   46 --
 board/purple/u-boot.lds                            |   75 ---
 boards.cfg                                         |   51 +-
 doc/README.Purple                                  |   84 ---
 include/configs/purple.h                           |  173 ------
 33 files changed, 362 insertions(+), 1952 deletions(-)
 delete mode 100644 arch/mips/cpu/asc_serial.c
 delete mode 100644 arch/mips/cpu/config.mk
 rename arch/mips/cpu/{ => mips32}/Makefile (87%)
 copy {board/purple => arch/mips/cpu/mips32/au1x00}/Makefile (83%)
 rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_eth.c (100%)
 rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_serial.c (100%)
 rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.c (100%)
 rename arch/mips/cpu/{ => mips32/au1x00}/au1x00_usb_ohci.h (100%)
 copy {board/purple => arch/mips/cpu/mips32/au1x00}/config.mk (83%)
 rename arch/mips/cpu/{ => mips32}/cache.S (98%)
 create mode 100644 arch/mips/cpu/mips32/config.mk
 rename arch/mips/cpu/{ => mips32}/cpu.c (100%)
 rename {board/purple => arch/mips/cpu/mips32/incaip}/Makefile (83%)
 create mode 100644 arch/mips/cpu/mips32/incaip/asc_serial.c
 rename arch/mips/cpu/{ => mips32/incaip}/asc_serial.h (100%)
 rename {board/purple => arch/mips/cpu/mips32/incaip}/config.mk (83%)
 rename arch/mips/cpu/{ => mips32/incaip}/incaip_clock.c (100%)
 rename arch/mips/cpu/{ => mips32/incaip}/incaip_wdt.S (100%)
 rename arch/mips/cpu/{ => mips32}/interrupts.c (100%)
 rename arch/mips/cpu/{ => mips32}/start.S (92%)
 delete mode 100644 board/purple/flash.c
 delete mode 100644 board/purple/lowlevel_init.S
 delete mode 100644 board/purple/purple.c
 delete mode 100644 board/purple/sconsole.c
 delete mode 100644 board/purple/sconsole.h
 delete mode 100644 board/purple/u-boot.lds
 delete mode 100644 doc/README.Purple
 delete mode 100644 include/configs/purple.h

--
1.7.4.1

The Purple SoC and eval board are not actively maintained since years. This patch removes the support completely as aggreed with Wolfgang Denk.

---
 MAINTAINERS                     |    1 -
 MAKEALL                         |    4 +-
 arch/mips/cpu/Makefile          |    1 -
 arch/mips/cpu/asc_serial.c      |   83 ------
 arch/mips/cpu/cache.S           |    4 -
 arch/mips/cpu/start.S           |   32 --
 arch/mips/include/asm/inca-ip.h |   10 -
 arch/mips/lib/board.c           |   10 -
 board/purple/Makefile           |   46 ---
 board/purple/config.mk          |   32 --
 board/purple/flash.c            |  595 ---------------------------------------
 board/purple/lowlevel_init.S    |   36 ---
 board/purple/purple.c           |  284 -------------------
 board/purple/sconsole.c         |  125 --------
 board/purple/sconsole.h         |   46 ---
 board/purple/u-boot.lds         |   75 -----
 boards.cfg                      |    1 -
 doc/README.Purple               |   84 ------
 include/configs/purple.h        |  173 ------------
 19 files changed, 1 insertions(+), 1641 deletions(-)
 delete mode 100644 board/purple/Makefile
 delete mode 100644 board/purple/config.mk
 delete mode 100644 board/purple/flash.c
 delete mode 100644 board/purple/lowlevel_init.S
 delete mode 100644 board/purple/purple.c
 delete mode 100644 board/purple/sconsole.c
 delete mode 100644 board/purple/sconsole.h
 delete mode 100644 board/purple/u-boot.lds
 delete mode 100644 doc/README.Purple
 delete mode 100644 include/configs/purple.h

index 4756f14..1d7e1f4 100644
@@ -919,7 +919,6 @@ Daniel Engstr
 Wolfgang Denk <[email protected]>
 
 	incaip		MIPS32 4Kc
-	purple		MIPS64 5Kc
 
 Thomas Lange <[email protected]>
 	dbau1x00	MIPS32 Au1000

index a732e6a..e1b928f 100755
@@ -507,9 +507,7 @@ LIST_mips4kc="		\
 	vct_premium_onenand_small	\
 "
 
-LIST_mips5kc="		\
-	purple		\
-"
+LIST_mips5kc=""
 
 LIST_au1xx0="		\
 	dbau1000	\

index 06df8d1..816b76c 100644
@@ -31,7 +31,6 @@ COBJS-y	= cpu.o interrupts.o
 
 SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
 COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
-COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
 COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

index 4b30c89..2965938 100644
@@ -311,11 +311,7 @@ LEAF(dcache_enable)
 * RETURNS: N/A
 *
 */
-#if defined(CONFIG_PURPLE)
-# define	CACHE_LOCK_SIZE	(CONFIG_SYS_DCACHE_SIZE/2)
-#else
 # define	CACHE_LOCK_SIZE	(CONFIG_SYS_DCACHE_SIZE)
-#endif
 	.globl	mips_cache_lock
 	.ent	mips_cache_lock
 mips_cache_lock:

index d6bcef6..e661d46 100644
@@ -67,9 +67,6 @@ _start:
 #if defined(CONFIG_INCA_IP)
 	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
 	.word 0x00000000           /* phase of the flash                    */
-#elif defined(CONFIG_PURPLE)
-	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
-	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
 #else
 	RVECENT(romReserved,2)
 #endif

@@ -203,30 +200,6 @@ _start:
 	 * 128 * 8 == 1024 == 0x400
 	 * so this is address R_VEC+0x400 == 0xbfc00400
 	 */
-#ifdef CONFIG_PURPLE
-/* 0xbfc00400 */
-	.word	0xdc870000
-	.word	0xfca70000
-	.word	0x20840008
-	.word	0x20a50008
-	.word	0x20c6ffff
-	.word	0x14c0fffa
-	.word	0x00000000
-	.word	0x03e00008
-	.word	0x00000000
-	.word	0x00000000
-/* 0xbfc00428 */
-	.word	0xdc870000
-	.word	0xfca70000
-	.word	0x20840008
-	.word	0x20a50008
-	.word	0x20c6ffff
-	.word	0x14c0fffa
-	.word	0x00000000
-	.word	0x03e00008
-	.word	0x00000000
-	.word	0x00000000
-#endif /* CONFIG_PURPLE */
 	.align 4
 reset:
 

@@ -337,17 +310,12 @@ relocate_code:
 	move	a0, t1		/* a0 <-- destination addr	*/
 	sub	a1, t2, t0	/* a1 <-- size			*/
 
-	/* On the purple board we copy the code earlier in a special way
-	 * in order to solve flash problems
-	 */
-#ifndef CONFIG_PURPLE
 1:
 	lw	t3, 0(t0)
 	sw	t3, 0(t1)
 	addu	t0, 4
 	ble	t0, t2, 1b
 	addu	t1, 4		/* delay slot			*/
-#endif
 
 	/* If caches were enabled, we would have to flush them here.
 	 */

index e787a1d..26f1002 100644
@@ -894,12 +894,7 @@
 /*  Module      :  EBU register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_EBU                          (0xB8000200)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_EBU                          (0xB800D800)
-#endif
-
 /***********************************************************************/
 
 

@@ -1495,12 +1490,7 @@ If set and clear bit are written concurrently with 1, the associated bit is not
 /*  Module      :  ASC register address and bits                       */
 /***********************************************************************/
 
-#if defined(CONFIG_INCA_IP)
 #define INCA_IP_ASC                          (0xB8000400)
-#elif defined(CONFIG_PURPLE)
-#define INCA_IP_ASC                          (0xBE500000)
-#endif
-
 /***********************************************************************/
 
 

index f317124..623c4d7 100644
@@ -162,9 +162,6 @@ void board_init_f(ulong bootflag)
 	init_fnc_t **init_fnc_ptr;
 	ulong addr, addr_sp, len = (ulong)&uboot_end - CONFIG_SYS_MONITOR_BASE;
 	ulong *s;
-#ifdef CONFIG_PURPLE
-	void copy_code (ulong);
-#endif
 
 	/* Pointer is writable since we allocated a register for it.
 	 */

@@ -253,13 +250,6 @@ void board_init_f(ulong bootflag)
 
 	memcpy (id, (void *)gd, sizeof (gd_t));
 
-	/* On the purple board we copy the code in a special way
-	 * in order to solve flash problems
-	 */
-#ifdef CONFIG_PURPLE
-	copy_code(addr);
-#endif
-
 	relocate_code (addr_sp, id, addr);
 
 	/* NOTREACHED - relocate_code() does not return */

deleted file mode 100644
index 404c3fb..0000000
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Purple board with MIPS 5Kc CPU core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xB0000000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000

deleted file mode 100644
index 1bd3edb..0000000
@@ -1,36 +0,0 @@
-/*
- *  Memory sub-system initialization code for PURPLE development board.
- *
- *  Copyright (c) 2003	Wolfgang Denk <[email protected]>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-
-#define MC_IOGP	0xBF800800
-
-	.globl	lowlevel_init
-lowlevel_init:
-	li	t0, MC_IOGP
-	li	t1, 0xf24
-	sw	t1, 0(t0)
-	jr	ra
-	nop

index 45c3102..63b1cda 100644
@@ -228,7 +228,6 @@ incaip_100MHz                mips        mips        incaip              -
 incaip_133MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=133000000
 incaip_150MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=150000000
 pb1000                       mips        mips        pb1x00              -              -           pb1x00:PB1000
-purple                       mips        mips
 qemu_mips                    mips        mips        qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips
 vct_premium                  mips        mips        vct                 micronas       -           vct:VCT_PREMIUM

--
1.7.4.1

All current CPUs and SoCs are based on Mips32 arch. The complete code resides in the global arch/mips/cpu directory. This is not suitable if other Mips architectures like Mips64 or Octeon should be supported in the future.

To achieve this the current CPU code is moved to its own mips32 subdirectory. All Mips32 boards have to use mips32 as config switch in board.cfg.

---
 arch/mips/cpu/{ => mips32}/Makefile          |    0
 arch/mips/cpu/{ => mips32}/asc_serial.c      |    0
 arch/mips/cpu/{ => mips32}/asc_serial.h      |    0
 arch/mips/cpu/{ => mips32}/au1x00_eth.c      |    0
 arch/mips/cpu/{ => mips32}/au1x00_serial.c   |    0
 arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.c |    0
 arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.h |    0
 arch/mips/cpu/{ => mips32}/cache.S           |    0
 arch/mips/cpu/{ => mips32}/config.mk         |    0
 arch/mips/cpu/{ => mips32}/cpu.c             |    0
 arch/mips/cpu/{ => mips32}/incaip_clock.c    |    0
 arch/mips/cpu/{ => mips32}/incaip_wdt.S      |    0
 arch/mips/cpu/{ => mips32}/interrupts.c      |    0
 arch/mips/cpu/{ => mips32}/start.S           |    0
 boards.cfg                                   |   50 +++++++++++++-------------
 15 files changed, 25 insertions(+), 25 deletions(-)
 rename arch/mips/cpu/{ => mips32}/Makefile (100%)
 rename arch/mips/cpu/{ => mips32}/asc_serial.c (100%)
 rename arch/mips/cpu/{ => mips32}/asc_serial.h (100%)
 rename arch/mips/cpu/{ => mips32}/au1x00_eth.c (100%)
 rename arch/mips/cpu/{ => mips32}/au1x00_serial.c (100%)
 rename arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.c (100%)
 rename arch/mips/cpu/{ => mips32}/au1x00_usb_ohci.h (100%)
 rename arch/mips/cpu/{ => mips32}/cache.S (100%)
 rename arch/mips/cpu/{ => mips32}/config.mk (100%)
 rename arch/mips/cpu/{ => mips32}/cpu.c (100%)
 rename arch/mips/cpu/{ => mips32}/incaip_clock.c (100%)
 rename arch/mips/cpu/{ => mips32}/incaip_wdt.S (100%)
 rename arch/mips/cpu/{ => mips32}/interrupts.c (100%)
 rename arch/mips/cpu/{ => mips32}/start.S (100%)

similarity index 100%
rename from arch/mips/cpu/Makefile
rename to arch/mips/cpu/mips32/Makefile

similarity index 100%
rename from arch/mips/cpu/asc_serial.c
rename to arch/mips/cpu/mips32/asc_serial.c

similarity index 100%
rename from arch/mips/cpu/asc_serial.h
rename to arch/mips/cpu/mips32/asc_serial.h

similarity index 100%
rename from arch/mips/cpu/au1x00_eth.c
rename to arch/mips/cpu/mips32/au1x00_eth.c

similarity index 100%
rename from arch/mips/cpu/au1x00_serial.c
rename to arch/mips/cpu/mips32/au1x00_serial.c

similarity index 100%
rename from arch/mips/cpu/au1x00_usb_ohci.c
rename to arch/mips/cpu/mips32/au1x00_usb_ohci.c

similarity index 100%
rename from arch/mips/cpu/au1x00_usb_ohci.h
rename to arch/mips/cpu/mips32/au1x00_usb_ohci.h

similarity index 100%
rename from arch/mips/cpu/cache.S
rename to arch/mips/cpu/mips32/cache.S

similarity index 100%
rename from arch/mips/cpu/config.mk
rename to arch/mips/cpu/mips32/config.mk

similarity index 100%
rename from arch/mips/cpu/cpu.c
rename to arch/mips/cpu/mips32/cpu.c

similarity index 100%
rename from arch/mips/cpu/incaip_clock.c
rename to arch/mips/cpu/mips32/incaip_clock.c

similarity index 100%
rename from arch/mips/cpu/incaip_wdt.S
rename to arch/mips/cpu/mips32/incaip_wdt.S

similarity index 100%
rename from arch/mips/cpu/interrupts.c
rename to arch/mips/cpu/mips32/interrupts.c

similarity index 100%
rename from arch/mips/cpu/start.S
rename to arch/mips/cpu/mips32/start.S

--
1.7.4.1

The current Mips CPU config.mk code always expects a Mips 4kc core and toolchain. This is not appropiate for other toolchains and CPUs/SoCs.

Replace the current MIPSFLAGS code by cc-option macro and use -march=mips32r2 as default optimization level for all Mips32 CPUs. Replace the endianess determination code from toolchain prefix by a more generic one inspired by the Linux arch/mips/Makefile.

---
 arch/mips/cpu/mips32/config.mk |   21 +++++++--------------
 1 files changed, 7 insertions(+), 14 deletions(-)

index a173c54..a91dcb4 100644
@@ -20,20 +20,13 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
-MIPSFLAGS:=$(shell \
-if [ "$v" -lt "14" ]; then \
-	echo "-mcpu=4kc"; \
-else \
-	echo "-march=4kc -mtune=4kc"; \
-fi)
 
-ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
-ENDIANNESS = -EL
-else
-ENDIANNESS = -EB
-endif
+# Optimization flags for all Mips32 CPUs
+MIPSFLAGS = $(call cc-option,-march=mips32r2,-mips32r2 -Wa,-mips32r2)
 
-MIPSFLAGS += $(ENDIANNESS)
+# Determine endianess from toolchain prefix
+ENDIANESS = $(shell $(CC) -dumpmachine | \
+		grep -q 'mips.*el-.*' && echo -EL || echo -EB)
+
+PLATFORM_CPPFLAGS += $(MIPSFLAGS) $(ENDIANESS)
 
-PLATFORM_CPPFLAGS += $(MIPSFLAGS)

--
1.7.4.1

[...]

Hi Shinya,

2011/3/15 Shinya Kuribayashi <[email protected]>:

sorry, I missed that discussion

The following code works with ELDK (mips_4KC and mips_4KCle) and my non-ELDK BE toolchain.

ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
ENDIANESS = -EL
else ifneq (,$(findstring 4KC,$(CROSS_COMPILE)))
ENDIANESS = -EB
else

ENDIANESS = $(shell $(CC) -dumpmachine | \
		grep -q 'mips.*el-.*' && echo -EL || echo -EB)

endif

Do we need this endianess flag stuff at all? Each toolchain that is built with a specific
endinaness does not really need the extra setting of -EB/-EL or am I miss something?

Daniel

You can find a lot more in the list archive.

True, as far as toolchain-default-endianness build goes.

The Linux/MIPS kernel however is maintained where Big-Endian and Little- -Endian machines can be configured and compiled using a single toolchain, regardless of its default endianness. CONFIG_LITTLE_ENDIAN is exactly for that purpose.

2011/3/16 Shinya Kuribayashi <[email protected]>:

ok I looked through the past discussions and it seems there is no right solution or approach yet. I'll revert the endianess stuff in my patch. Sorry for the noise ;)

Is my approach with -march acceptable? This is more important to me for supporting
new SoCs with 24k and 34k CPU cores. I think its a clean approach to use a default Mips32
architecture optimization plus a per CPU optimization configured in the SoC directories.

Daniel

IIUC this is a binutils related issue.

2011/3/17 Shinya Kuribayashi <[email protected]>:

Ok I'll test with pre-4.1 ELDK releases too and adapt the code if necessary.

Next time I'll provide a Tested-with ELDK x.y line in the patch for those changes.
Thanks for the feedback.

Daniel

Hi Shinya,

2011/3/17 Shinya Kuribayashi <[email protected]>:

I did some researching and testing with ELDK-4.1, ELDK-4.0 and ELDK-3.1.1.

In ELDK-3.1.1 we have:
- mips_4KC-gcc (GCC) 3.3.3 (DENX ELDK 3.1.1 3.3.3-9)
- GNU assembler 2.14 20030612

Therefore mips32r2 is already supported. But there is another problem with this binutils version. The latest additions to mips.lds and u-boot.lds for supporting recent
binutils are causing parse errors. Thus ELDK-3.1.1 and earlier are not functional with
mainline U-Boot anyway. ELDK-4.0 and 4.1 with gcc-4.0.0 and binutils-2.16.1 are working
properly.

I suggest to drop official support for ELDK-3.1.1 / binutils-2.14 and earlier.

Best regards
Daniel

Thanks, much appreciated.

I wonder what's that 'the latest additions to mips.lds and u-boot.lds for supporting recent binutils' to be exact. Which commit(s) are you referring to? Or could you provide error logs just in case please?

Hmm. According to the README file, even the Linux kernel still builds with at least gcc 3.2. I'm feeling that it might be a bit too early to drop gcc 3.3.3 (ELDK-3.1.1).

So I'd like to take a look at the issue you found this time, first. If it's easy to fix, let's fix it. And if not, revise the patch please. We have not heard of any problem reports on MIPS builds with ELDK-3.1.1 so far (at least I'm not aware of them). The change won't be a problem.

2011/3/23 Shinya Kuribayashi <[email protected]>:

Following changes have been introduced to ld in binutils-2.16:

* Added SORT_BY_NAME and SORT_BY_ALIGNMENT to the linker script language to permit sorting sections by section name or section maximum alignment.

http://sourceware.org/cgi-bin/cvsweb.cgi/~checkout~/src/ld/NEWS?rev=1.116&content-type=text/plain&cvsroot=src&only_with_tag=binutils-binutils-2_21

These new macros are used in mips.lds and all u-boot.lds files. I get follogwing error with ELDK-3.1.1 or other gcc-3.x based toolchains (IncaIP used as sample config):

mips_4KC-ld -g -Ttext 0x80200000 -T mips.lds \
-o <snip>/u-boot-git//build/incaip/examples/standalone/hello_world
-e hello_world <snip>/u-boot-git//build/incaip/examples/standalone/hello_world.o

<snip>/u-boot-git//build/incaip/examples/standalone/libstubs.o \
			-L<snip>/eldk-3.11/usr/bin/../lib/gcc-lib/mips-linux/3.3.3 -lgcc

mips_4KC-ld:mips.lds:37: parse error

This error refers to following line:
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }

Following commit introduced that change for all u-boot.lds files:
http://git.denx.de/?p=u-boot.git;a=commit;h=f62fb99941c625605aa16a0097b396a5c16d2c88

I'd claim that all toolchains with binutils lesser than 2.16 are not working anymore.

I have prepared a v3 of this patch that checks whether -mips32r2 is supported. If not than -mips32
will be used as fallback. But I want to clarify this first before I send it.

Best regards,
Daniel

Sorry for being late,

[...]

[...]

Excellent, no comments from me. Let's forget about all pre-binutils 2.16 releases from now on, and ELDK-3.1.1 as well.

I'm guessting you're worried that the corresponding line will differ from what the Linux/MIPS has, but that's not a problem. The Linux/MIPS tries to tighten the condition in accordance with explicit configuration options such as CONFIG_CPU_MIPS32_R1/R2, CONFIG_CPU_MIPS64_R1/R2.

We U-Boot doesn't have to follow this convention, and can relax the cc- option rules.

I'll wait for v3 patch(es), and push them during the next merge window. Thanks in advance,

2011/3/28 Shinya Kuribayashi <[email protected]>:

No problem

Ok if we drop toolchain support for binutils lesser than 2.16 than I can simplify the
this patch to one line because the assembler check is obsolete too:

MIPSFLAGS = $(call cc-option,-march=mips32r2)

Do you agree?

It sounds you're misunderstanding how cc-option works. Could you take a look at $(TOPDIR)/config.mk again?

2011/3/28 Shinya Kuribayashi <[email protected]>:

Actually not. But you're right, cc-option is not needed ;)

IncaIP is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.

---
 arch/mips/cpu/mips32/Makefile                    |    2 -
 arch/mips/cpu/mips32/incaip/Makefile             |   46 ++++++++++++++++++++++
 arch/mips/cpu/mips32/{ => incaip}/asc_serial.c   |    0
 arch/mips/cpu/mips32/{ => incaip}/asc_serial.h   |    0
 arch/mips/cpu/mips32/incaip/config.mk            |   24 +++++++++++
 arch/mips/cpu/mips32/{ => incaip}/incaip_clock.c |    0
 arch/mips/cpu/mips32/{ => incaip}/incaip_wdt.S   |    0
 boards.cfg                                       |    8 ++--
 8 files changed, 74 insertions(+), 6 deletions(-)
 create mode 100644 arch/mips/cpu/mips32/incaip/Makefile
 rename arch/mips/cpu/mips32/{ => incaip}/asc_serial.c (100%)
 rename arch/mips/cpu/mips32/{ => incaip}/asc_serial.h (100%)
 create mode 100644 arch/mips/cpu/mips32/incaip/config.mk
 rename arch/mips/cpu/mips32/{ => incaip}/incaip_clock.c (100%)
 rename arch/mips/cpu/mips32/{ => incaip}/incaip_wdt.S (100%)

index 816b76c..88e3023 100644
@@ -29,8 +29,6 @@ START	= start.o
 SOBJS-y	= cache.o
 COBJS-y	= cpu.o interrupts.o
 
-SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
-COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
 COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

similarity index 100%
rename from arch/mips/cpu/mips32/asc_serial.c
rename to arch/mips/cpu/mips32/incaip/asc_serial.c

similarity index 100%
rename from arch/mips/cpu/mips32/asc_serial.h
rename to arch/mips/cpu/mips32/incaip/asc_serial.h

new file mode 100644
index 0000000..ecfcb9c
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=4kc)

similarity index 100%
rename from arch/mips/cpu/mips32/incaip_clock.c
rename to arch/mips/cpu/mips32/incaip/incaip_clock.c

similarity index 100%
rename from arch/mips/cpu/mips32/incaip_wdt.S
rename to arch/mips/cpu/mips32/incaip/incaip_wdt.S

index 8194bb2..7844bbd 100644
@@ -223,10 +223,10 @@ dbau1500                     mips        mips32      dbau1x00            -
 dbau1550                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
 dbau1550_el                  mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
 gth2                         mips        mips32
-incaip                       mips        mips32
-incaip_100MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=100000000
-incaip_133MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=133000000
-incaip_150MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=150000000
+incaip                       mips        mips32      incaip              -              incaip
+incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
+incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
+incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
 pb1000                       mips        mips32      pb1x00              -              -           pb1x00:PB1000
 qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips32

--
1.7.4.1

Au1x00 is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization.

---
 arch/mips/cpu/mips32/Makefile                      |    2 -
 arch/mips/cpu/mips32/au1x00/Makefile               |   45 ++++++++++++++++++++
 arch/mips/cpu/mips32/{ => au1x00}/au1x00_eth.c     |    0
 arch/mips/cpu/mips32/{ => au1x00}/au1x00_serial.c  |    0
 .../mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.c |    0
 .../mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.h |    0
 arch/mips/cpu/mips32/au1x00/config.mk              |   24 ++++++++++
 boards.cfg                                         |   14 +++---
 8 files changed, 76 insertions(+), 9 deletions(-)
 create mode 100644 arch/mips/cpu/mips32/au1x00/Makefile
 rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_eth.c (100%)
 rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_serial.c (100%)
 rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.c (100%)
 rename arch/mips/cpu/mips32/{ => au1x00}/au1x00_usb_ohci.h (100%)
 create mode 100644 arch/mips/cpu/mips32/au1x00/config.mk

index 88e3023..e315c1b 100644
@@ -29,8 +29,6 @@ START	= start.o
 SOBJS-y	= cache.o
 COBJS-y	= cpu.o interrupts.o
 
-COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
-
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))

similarity index 100%
rename from arch/mips/cpu/mips32/au1x00_eth.c
rename to arch/mips/cpu/mips32/au1x00/au1x00_eth.c

similarity index 100%
rename from arch/mips/cpu/mips32/au1x00_serial.c
rename to arch/mips/cpu/mips32/au1x00/au1x00_serial.c

similarity index 100%
rename from arch/mips/cpu/mips32/au1x00_usb_ohci.c
rename to arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.c

similarity index 100%
rename from arch/mips/cpu/mips32/au1x00_usb_ohci.h
rename to arch/mips/cpu/mips32/au1x00/au1x00_usb_ohci.h

new file mode 100644
index 0000000..ecfcb9c
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += $(call cc-option,-mtune=4kc)

index 7844bbd..9a8dbb3 100644
@@ -217,17 +217,17 @@ M5282EVB                     m68k        mcf52x2     m5282evb            freesca
 M53017EVB                    m68k        mcf52x2     m53017evb           freescale
 EP2500                       m68k        mcf52x2     ep2500              Mercury
 microblaze-generic           microblaze  microblaze  microblaze-generic  xilinx
-dbau1000                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1000
-dbau1100                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1100
-dbau1500                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1500
-dbau1550                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
-dbau1550_el                  mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
-gth2                         mips        mips32
+dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
+dbau1100                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1100
+dbau1500                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1500
+dbau1550                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+dbau1550_el                  mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+gth2                         mips        mips32      -                   -              au1x00
 incaip                       mips        mips32      incaip              -              incaip
 incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
 incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
 incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
-pb1000                       mips        mips32      pb1x00              -              -           pb1x00:PB1000
+pb1000                       mips        mips32      pb1x00              -              au1x00      pb1x00:PB1000
 qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips32
 vct_premium                  mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM

--
1.7.4.1