perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
Subsystems (2)
PATCH 1/1 perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
From: Don Zickus <[email protected]>
Subject: [PATCH -tip] perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
The read of a proper MSR register was missed and instead of counter the configration register was tested (it has ARCH_P4_UNFLAGGED_BIT always cleared) leading to unknown NMI hitting the system. As result the user may obtain "Dazed and confused, but trying to continue" message. Fix it by reading a proper MSR register.
When an NMI happens on a P4, the perf nmi handler checks the configuration register to see if the overflow bit is set or not before taking appropriate action. Unfortunately, various P4 machines had a broken overflow bit, so a backup mechanism was implemented. This mechanism checked to see if the counter rolled over or not.
A previous commit that implemented this backup mechanism was broken. Instead of reading the counter register, it used the configuration register to determine if the counter rolled over or not. Reading that bit would give incorrect results.
This would lead to 'Dazed and confused' messages for the end user when using the perf tool (or if the nmi watchdog is running).
The fix is to read the counter register before determining if the counter rolled over or not.
--- arch/x86/kernel/cpu/perf_event_p4.c | 1 + 1 file changed, 1 insertion(+)
arch/x86/kernel/cpu/perf_event_p4.c +1 -0
@@ -777,6 +777,7 @@ static inline int p4_pmu_clear_cccr_ovf(* the counter has reached zero value and continued counting before * real NMI signal was received: */ +rdmsrl (hwc->event_base, v);if (!(v &ARCH_P4_UNFLAGGED_BIT ))return 1 ;
Signature · 1 line
Cyrill
Commit-ID: 242214f9c1eeaae40eca11e3b4d37bfce960a7cd Gitweb: http://git.kernel.org/tip/242214f9c1eeaae40eca11e3b4d37bfce960a7cd Author: Don Zickus <[email protected]> AuthorDate: Thu, 24 Mar 2011 23:36:25 +0300 Committer: Ingo Molnar <[email protected]> CommitDate: Thu, 24 Mar 2011 21:40:01 +0100
perf, x86: P4 PMU - Read proper MSR register to catch unflagged overflows
The read of a proper MSR register was missed and instead of counter the configration register was tested (it has ARCH_P4_UNFLAGGED_BIT always cleared) leading to unknown NMI hitting the system. As result the user may obtain "Dazed and confused, but trying to continue" message. Fix it by reading a proper MSR register.
When an NMI happens on a P4, the perf nmi handler checks the configuration register to see if the overflow bit is set or not before taking appropriate action. Unfortunately, various P4 machines had a broken overflow bit, so a backup mechanism was implemented. This mechanism checked to see if the counter rolled over or not.
A previous commit that implemented this backup mechanism was broken. Instead of reading the counter register, it used the configuration register to determine if the counter rolled over or not. Reading that bit would give incorrect results.
This would lead to 'Dazed and confused' messages for the end user when using the perf tool (or if the nmi watchdog is running).
The fix is to read the counter register before determining if the counter rolled over or not.
LKML-Reference: <[email protected]>
--- arch/x86/kernel/cpu/perf_event_p4.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/x86/kernel/cpu/perf_event_p4.c +1 -0
@@ -777,6 +777,7 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)* the counter has reached zero value and continued counting before * real NMI signal was received: */ +rdmsrl (hwc->event_base, v);if (!(v &ARCH_P4_UNFLAGGED_BIT ))return 1 ;