Skip to contentSkip to conversation

perf, x86: P4 PMU - Restore code alignment

PATCH In review Cyrill Gorcunov 1 participant 2 messages Mar 27, 2011 – Mar 29, 2011

Subsystems (2)
x86 perf events
lore
Share & tools
lore

Cyrill Gorcunov

author
#0 lore raw

PATCH 1/1 perf, x86: P4 PMU - Restore code alignment

No change on functional level. This code style nit escaped me somewhere at very first commits.

Signed-off-by Cyrill Gorcunov <[email protected]>

---

Found it while were at perf-p4 code for nmi-watchdog reason so decided to fix it just to not forget after. Note the other code already aligned this way so this snippet stabs my eyes.

 arch/x86/kernel/cpu/perf_event_p4.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/x86/kernel/cpu/perf_event_p4.c +1 -1
index c2520e1..8ff882f 100644
@@ -468,7 +468,7 @@ static struct p4_event_bind p4_event_bind_map[] = {
 		.opcode		= P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
 		.escr_emask	=
-		P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
+			P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
 		.cntr		= { {12, 13, 16}, {14, 15, 17} },
 	},
 	[P4_EVENT_X87_ASSIST] = {
Signature · 1 line
    Cyrill
author
#1 lore raw

[tip:perf/core] perf, x86: P4 PMU - clean up the code a bit

Commit-ID:  1d321881afb955bba1e0a8f50d3a04e111fcb581
Gitweb:     http://git.kernel.org/tip/1d321881afb955bba1e0a8f50d3a04e111fcb581
Author:     Cyrill Gorcunov <[email protected]>
AuthorDate: Mon, 28 Mar 2011 00:46:11 +0400
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 29 Mar 2011 09:36:33 +0200

perf, x86: P4 PMU - clean up the code a bit

No change on the functional level, just align the table properly.

Signed-off-by Cyrill Gorcunov <[email protected]>
Cc Lin Ming <[email protected]>

LKML-Reference: <[email protected]>

Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/perf_event_p4.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
arch/x86/kernel/cpu/perf_event_p4.c +1 -1
index c2520e1..8ff882f 100644
@@ -468,7 +468,7 @@ static struct p4_event_bind p4_event_bind_map[] = {
 		.opcode		= P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED),
 		.escr_msr	= { MSR_P4_CRU_ESCR0, MSR_P4_CRU_ESCR1 },
 		.escr_emask	=
-		P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
+			P4_ESCR_EMASK_BIT(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS),
 		.cntr		= { {12, 13, 16}, {14, 15, 17} },
 	},
 	[P4_EVENT_X87_ASSIST] = {