MIPS: Refactoring and cleanup of CPU and SoC code

index 4756f14..1d7e1f4 100644
@@ -919,7 +919,6 @@ Daniel Engstr
 Wolfgang Denk <[email protected]>
 
 	incaip		MIPS32 4Kc
-	purple		MIPS64 5Kc
 
 Thomas Lange <[email protected]>
 	dbau1x00	MIPS32 Au1000

index a732e6a..e1b928f 100755
@@ -507,9 +507,7 @@ LIST_mips4kc="		\
 	vct_premium_onenand_small	\
 "
 
-LIST_mips5kc="		\
-	purple		\
-"
+LIST_mips5kc=""
 
 LIST_au1xx0="		\
 	dbau1000	\

index 06df8d1..816b76c 100644
@@ -31,7 +31,6 @@ COBJS-y	= cpu.o interrupts.o
 
 SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
 COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
-COBJS-$(CONFIG_PURPLE)	+= asc_serial.o
 COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

index 4b30c89..2965938 100644
@@ -311,11 +311,7 @@ LEAF(dcache_enable)
 * RETURNS: N/A
 *
 */
-#if defined(CONFIG_PURPLE)
-# define	CACHE_LOCK_SIZE	(CONFIG_SYS_DCACHE_SIZE/2)
-#else
 # define	CACHE_LOCK_SIZE	(CONFIG_SYS_DCACHE_SIZE)
-#endif
 	.globl	mips_cache_lock
 	.ent	mips_cache_lock
 mips_cache_lock:

index d6bcef6..e661d46 100644
@@ -67,9 +67,6 @@ _start:
 #if defined(CONFIG_INCA_IP)
 	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
 	.word 0x00000000           /* phase of the flash                    */
-#elif defined(CONFIG_PURPLE)
-	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
-	.word INFINEON_EBU_BOOTCFG /* EBU init code, fetched during booting */
 #else
 	RVECENT(romReserved,2)
 #endif

@@ -203,30 +200,6 @@ _start:
 	 * 128 * 8 == 1024 == 0x400
 	 * so this is address R_VEC+0x400 == 0xbfc00400
 	 */
-#ifdef CONFIG_PURPLE
-/* 0xbfc00400 */
-	.word	0xdc870000
-	.word	0xfca70000
-	.word	0x20840008
-	.word	0x20a50008
-	.word	0x20c6ffff
-	.word	0x14c0fffa
-	.word	0x00000000
-	.word	0x03e00008
-	.word	0x00000000
-	.word	0x00000000
-/* 0xbfc00428 */
-	.word	0xdc870000
-	.word	0xfca70000
-	.word	0x20840008
-	.word	0x20a50008
-	.word	0x20c6ffff
-	.word	0x14c0fffa
-	.word	0x00000000
-	.word	0x03e00008
-	.word	0x00000000
-	.word	0x00000000
-#endif /* CONFIG_PURPLE */
 	.align 4
 reset:
 

@@ -337,17 +310,12 @@ relocate_code:
 	move	a0, t1		/* a0 <-- destination addr	*/
 	sub	a1, t2, t0	/* a1 <-- size			*/
 
-	/* On the purple board we copy the code earlier in a special way
-	 * in order to solve flash problems
-	 */
-#ifndef CONFIG_PURPLE
 1:
 	lw	t3, 0(t0)
 	sw	t3, 0(t1)
 	addu	t0, 4
 	ble	t0, t2, 1b
 	addu	t1, 4		/* delay slot			*/
-#endif
 
 	/* If caches were enabled, we would have to flush them here.
 	 */

46 lines not on this page · raw message

deleted file mode 100644
index 404c3fb..0000000
@@ -1,32 +0,0 @@
-#
-# (C) Copyright 2003
-# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# Purple board with MIPS 5Kc CPU core
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xB0000000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80100000

deleted file mode 100644
index 1bd3edb..0000000
@@ -1,36 +0,0 @@
-/*
- *  Memory sub-system initialization code for PURPLE development board.
- *
- *  Copyright (c) 2003	Wolfgang Denk <[email protected]>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <asm/regdef.h>
-
-#define MC_IOGP	0xBF800800
-
-	.globl	lowlevel_init
-lowlevel_init:
-	li	t0, MC_IOGP
-	li	t1, 0xf24
-	sw	t1, 0(t0)
-	jr	ra
-	nop

75 lines not on this page · raw message

index 45c3102..63b1cda 100644
@@ -228,7 +228,6 @@ incaip_100MHz                mips        mips        incaip              -
 incaip_133MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=133000000
 incaip_150MHz                mips        mips        incaip              -              -           incaip:CPU_CLOCK_RATE=150000000
 pb1000                       mips        mips        pb1x00              -              -           pb1x00:PB1000
-purple                       mips        mips
 qemu_mips                    mips        mips        qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips
 vct_premium                  mips        mips        vct                 micronas       -           vct:VCT_PREMIUM

84 lines not on this page · raw message

similarity index 100%
rename from arch/mips/cpu/Makefile
rename to arch/mips/cpu/mips32/Makefile

similarity index 100%
rename from arch/mips/cpu/cache.S
rename to arch/mips/cpu/mips32/cache.S

similarity index 100%
rename from arch/mips/cpu/config.mk
rename to arch/mips/cpu/mips32/config.mk

similarity index 100%
rename from arch/mips/cpu/incaip_wdt.S
rename to arch/mips/cpu/mips32/incaip_wdt.S

similarity index 100%
rename from arch/mips/cpu/start.S
rename to arch/mips/cpu/mips32/start.S

56 lines not on this page · raw message

index a173c54..4d1b273 100644
@@ -20,13 +20,14 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-v=$(shell $(AS) --version | grep 'GNU assembler' | egrep -o '2\.[0-9\.]+' | cut -d. -f2)
-MIPSFLAGS:=$(shell \
-if [ "$v" -lt "14" ]; then \
-	echo "-mcpu=4kc"; \
-else \
-	echo "-march=4kc -mtune=4kc"; \
-fi)
+
+#
+# Default optimization level for MIPS32
+#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips32r2
 
 ifneq (,$(findstring 4KCle,$(CROSS_COMPILE)))
 ENDIANNESS = -EL

index 816b76c..88e3023 100644
@@ -29,8 +29,6 @@ START	= start.o
 SOBJS-y	= cache.o
 COBJS-y	= cpu.o interrupts.o
 
-SOBJS-$(CONFIG_INCA_IP)	+= incaip_wdt.o
-COBJS-$(CONFIG_INCA_IP)	+= asc_serial.o incaip_clock.o
 COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)

46 lines not on this page · raw message

new file mode 100644
index 0000000..568f333
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -mtune=4kc

similarity index 100%
rename from arch/mips/cpu/mips32/incaip_wdt.S
rename to arch/mips/cpu/mips32/incaip/incaip_wdt.S

index 8194bb2..7844bbd 100644
@@ -223,10 +223,10 @@ dbau1500                     mips        mips32      dbau1x00            -
 dbau1550                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
 dbau1550_el                  mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
 gth2                         mips        mips32
-incaip                       mips        mips32
-incaip_100MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=100000000
-incaip_133MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=133000000
-incaip_150MHz                mips        mips32      incaip              -              -           incaip:CPU_CLOCK_RATE=150000000
+incaip                       mips        mips32      incaip              -              incaip
+incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
+incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
+incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
 pb1000                       mips        mips32      pb1x00              -              -           pb1x00:PB1000
 qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips32

index 88e3023..e315c1b 100644
@@ -29,8 +29,6 @@ START	= start.o
 SOBJS-y	= cache.o
 COBJS-y	= cpu.o interrupts.o
 
-COBJS-$(CONFIG_SOC_AU1X00) += au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
-
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))

45 lines not on this page · raw message

new file mode 100644
index 0000000..568f333
@@ -0,0 +1,24 @@
+#
+# (C) Copyright 2011
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+PLATFORM_CPPFLAGS += -mtune=4kc

index 7844bbd..9a8dbb3 100644
@@ -217,17 +217,17 @@ M5282EVB                     m68k        mcf52x2     m5282evb            freesca
 M53017EVB                    m68k        mcf52x2     m53017evb           freescale
 EP2500                       m68k        mcf52x2     ep2500              Mercury
 microblaze-generic           microblaze  microblaze  microblaze-generic  xilinx
-dbau1000                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1000
-dbau1100                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1100
-dbau1500                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1500
-dbau1550                     mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
-dbau1550_el                  mips        mips32      dbau1x00            -              -           dbau1x00:DBAU1550
-gth2                         mips        mips32
+dbau1000                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1000
+dbau1100                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1100
+dbau1500                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1500
+dbau1550                     mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+dbau1550_el                  mips        mips32      dbau1x00            -              au1x00      dbau1x00:DBAU1550
+gth2                         mips        mips32      -                   -              au1x00
 incaip                       mips        mips32      incaip              -              incaip
 incaip_100MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=100000000
 incaip_133MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=133000000
 incaip_150MHz                mips        mips32      incaip              -              incaip      incaip:CPU_CLOCK_RATE=150000000
-pb1000                       mips        mips32      pb1x00              -              -           pb1x00:PB1000
+pb1000                       mips        mips32      pb1x00              -              au1x00      pb1x00:PB1000
 qemu_mips                    mips        mips32      qemu-mips           -              -           qemu-mips
 tb0229                       mips        mips32
 vct_premium                  mips        mips32      vct                 micronas       -           vct:VCT_PREMIUM