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perf, x86: Add PERF_COUNT_HW_NMI_WATCHDOG event

RFC PATCH In review Cyrill Gorcunov 2 participants 4 messages Mar 31, 2011 – Apr 1, 2011

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#0 lore raw

RFC PATCH 1/1 perf, x86: Add PERF_COUNT_HW_NMI_WATCHDOG event

Because of Netburst HW restriction we can't move events arbitrary
between counters and this makes 'perf top' unable to run if nmi-watchdog
is running (since both uses PERF_COUNT_HW_CPU_CYCLES but such event is
bound to run on a few counters only). So as a workaround we could count that named non-sleeping ticks (as oprofile does) and both perf top and nmi-watchdog would co-exsist without conflicts but kernel needs to know about such specifics -- so PERF_COUNT_HW_NMI_WATCHDOG event is introduced. This event is an alias of PERF_COUNT_HW_CPU_CYCLES for non-P4 x86 architecture so nothing much changed I think.

Please review, I might be missing something. Also comments on idea is quite welcome since it touches ABI part.

---

Quoted 1 line

From b86ba38cb258bd309d96aee5b7b25c69945a2b60 Mon Sep 17 00:00:00 2001

From: Cyrill Gorcunov <[email protected]>
Date: Sun, 27 Mar 2011 19:58:30 +0400
Subject: [PATCH] perf, x86: Add PERF_COUNT_HW_NMI_WATCHDOG event

Due to restriction and specifics of Netburst PMU we need
a separated event for NMI watchdog. Note that on all other
than P4 PMU cpus this event is a simple alias for PERF_COUNT_HW_CPU_CYCLES.

---
 arch/x86/kernel/cpu/perf_event_amd.c   |    1 +
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 arch/x86/kernel/cpu/perf_event_p4.c    |   15 +++++++++++++++
 arch/x86/kernel/cpu/perf_event_p6.c    |    1 +
 include/linux/perf_event.h             |    1 +
 kernel/watchdog.c                      |    2 +-
 6 files changed, 20 insertions(+), 1 deletions(-)
arch/x86/kernel/cpu/perf_event_amd.c +1 -0
index 461f62b..248d8d7 100644
@@ -102,6 +102,7 @@ static const u64 amd_perfmon_event_map[] =
   [PERF_COUNT_HW_CACHE_MISSES]		= 0x0081,
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c2,
   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c3,
+  [PERF_COUNT_HW_NMI_WATCHDOG]		= 0x0076,
 };
 
 static u64 amd_pmu_event_map(int hw_event)
arch/x86/kernel/cpu/perf_event_intel.c +1 -0
index 8fc2b2c..53b4790 100644
@@ -34,6 +34,7 @@ static const u64 intel_perfmon_event_map[] =
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,
   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,
   [PERF_COUNT_HW_BUS_CYCLES]		= 0x013c,
+  [PERF_COUNT_HW_NMI_WATCHDOG]		= 0x003c,
 };
 
 static struct event_constraint intel_core_event_constraints[] =
arch/x86/kernel/cpu/perf_event_p4.c +15 -0
index 8ff882f..ef65c94 100644
@@ -557,6 +557,7 @@ static __initconst const u64 p4_hw_cache_event_ids
 };
 
 static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
+
   /* non-halted CPU clocks */
   [PERF_COUNT_HW_CPU_CYCLES] =
 	p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_GLOBAL_POWER_EVENTS)		|
@@ -607,6 +608,20 @@ static u64 p4_general_events[PERF_COUNT_HW_MAX] = {
 		P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV)		|
 		P4_ESCR_EMASK_BIT(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN))	|
 	p4_config_pack_cccr(P4_CCCR_EDGE | P4_CCCR_COMPARE),
+
+  /* we use that named non-sleeping calls */
+  [PERF_COUNT_HW_NMI_WATCHDOG] =
+	p4_config_pack_escr(P4_ESCR_EVENT(P4_EVENT_EXECUTION_EVENT)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS0)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS1)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS2)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, NBOGUS3)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS0)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS1)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS2)		|
+		P4_ESCR_EMASK_BIT(P4_EVENT_EXECUTION_EVENT, BOGUS3))		|
+	p4_config_pack_cccr(P4_CCCR_THRESHOLD(15) | P4_CCCR_COMPLEMENT		|
+		P4_CCCR_COMPARE),
 };
 
 static struct p4_event_bind *p4_config_get_bind(u64 config)
arch/x86/kernel/cpu/perf_event_p6.c +1 -0
index 20c097e..3daeb18 100644
@@ -12,6 +12,7 @@ static const u64 p6_perfmon_event_map[] =
   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x00c4,
   [PERF_COUNT_HW_BRANCH_MISSES]		= 0x00c5,
   [PERF_COUNT_HW_BUS_CYCLES]		= 0x0062,
+  [PERF_COUNT_HW_NMI_WATCHDOG]		= 0x0079,
 };
 
 static u64 p6_pmu_event_map(int hw_event)
include/linux/perf_event.h +1 -0
index 04d75a8..78da67d 100644
@@ -52,6 +52,7 @@ enum perf_hw_id {
 	PERF_COUNT_HW_BRANCH_INSTRUCTIONS	= 4,
 	PERF_COUNT_HW_BRANCH_MISSES		= 5,
 	PERF_COUNT_HW_BUS_CYCLES		= 6,
+	PERF_COUNT_HW_NMI_WATCHDOG		= 7,
 
 	PERF_COUNT_HW_MAX,			/* non-ABI */
 };
kernel/watchdog.c +1 -1
index 140dce7..46a849a 100644
@@ -191,7 +191,7 @@ static int is_softlockup(unsigned long touch_ts)
 #ifdef CONFIG_HARDLOCKUP_DETECTOR
 static struct perf_event_attr wd_hw_attr = {
 	.type		= PERF_TYPE_HARDWARE,
-	.config		= PERF_COUNT_HW_CPU_CYCLES,
+	.config		= PERF_COUNT_HW_NMI_WATCHDOG,
 	.size		= sizeof(struct perf_event_attr),
 	.pinned		= 1,
 	.disabled	= 1,
Signature · 1 line
1.7.3.3
#1 lore raw
Quoted 13 lines · Cyrill Gorcunov

Because of Netburst HW restriction we can't move events arbitrary
between counters and this makes 'perf top' unable to run if nmi-watchdog
is running (since both uses PERF_COUNT_HW_CPU_CYCLES but such event is
bound to run on a few counters only). So as a workaround we could count that named non-sleeping ticks (as oprofile does) and both perf top and nmi-watchdog would co-exsist without conflicts but kernel needs to know about such specifics -- so PERF_COUNT_HW_NMI_WATCHDOG event is introduced. This event is an alias of PERF_COUNT_HW_CPU_CYCLES for non-P4 x86 architecture so nothing much changed I think.

Please review, I might be missing something. Also comments on idea is quite welcome since it touches ABI part.

Quoted 7 lines
 arch/x86/kernel/cpu/perf_event_amd.c   |    1 +
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 arch/x86/kernel/cpu/perf_event_p4.c    |   15 +++++++++++++++
 arch/x86/kernel/cpu/perf_event_p6.c    |    1 +
 include/linux/perf_event.h             |    1 +
 kernel/watchdog.c                      |    2 +-
 6 files changed, 20 insertions(+), 1 deletions(-)

is x86 the only arch using the watchdog things?

#2 lore raw
Quoted 22 lines · Peter Zijlstra
Quoted 13 lines · Cyrill Gorcunov

Because of Netburst HW restriction we can't move events arbitrary
between counters and this makes 'perf top' unable to run if nmi-watchdog
is running (since both uses PERF_COUNT_HW_CPU_CYCLES but such event is
bound to run on a few counters only). So as a workaround we could count that named non-sleeping ticks (as oprofile does) and both perf top and nmi-watchdog would co-exsist without conflicts but kernel needs to know about such specifics -- so PERF_COUNT_HW_NMI_WATCHDOG event is introduced. This event is an alias of PERF_COUNT_HW_CPU_CYCLES for non-P4 x86 architecture so nothing much changed I think.

Please review, I might be missing something. Also comments on idea is quite welcome since it touches ABI part.

Quoted 7 lines
 arch/x86/kernel/cpu/perf_event_amd.c   |    1 +
 arch/x86/kernel/cpu/perf_event_intel.c |    1 +
 arch/x86/kernel/cpu/perf_event_p4.c    |   15 +++++++++++++++
 arch/x86/kernel/cpu/perf_event_p6.c    |    1 +
 include/linux/perf_event.h             |    1 +
 kernel/watchdog.c                      |    2 +-
 6 files changed, 20 insertions(+), 1 deletions(-)
Quoted 1 line

is x86 the only arch using the watchdog things?

Hm, good question. The powerpc, sparc, sh, arm, mips have PERF_COUNT_HW_CPU_CYCLES. Seems I've missed those archs. Thanks Peter, will take a look.

Signature · 1 line
    Cyrill
#3 lore raw

On 04/01/2011 03:05 PM, Cyrill Gorcunov wrote:
...

Quoted 6 lines
Quoted 2 lines

is x86 the only arch using the watchdog things?

Hm, good question. The powerpc, sparc, sh, arm, mips have PERF_COUNT_HW_CPU_CYCLES. Seems I've missed those archs. Thanks Peter, will take a look.

ok, as far as I see nmi-watchdog is x86 specific (only x86 refers to CONFIG_HARDLOCKUP_DETECTOR at least for now).

Signature · 1 line
    Cyrill