MTRR: clear DramModEn bit of sys_cfg MSR

diff -r 5a10b635262c -r e9ab70bf676a xen/arch/x86/cpu/mtrr/generic.c
@@ -34,11 +34,36 @@
 	rdmsrl(MTRRphysMask_MSR(index), vr->mask);
 }
 
+/*
+ * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG : 
+ * "The MtrrFixDramModEn bit should be set to 1 during BIOS initalization of 
+ * the fixed MTRRs, then cleared to 0 for operation."
+ */
+static inline void amd_check_syscfg_dram_mod_en(void)
+{
+    uint64_t syscfg;
+
+    if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+          (boot_cpu_data.x86 >= 0x0f)))
+        return;
+
+    rdmsrl(MSR_K8_SYSCFG, syscfg);
+    if (syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY) {
+        printk(KERN_ERR "MTRR: CPU %u: SYSCFG[MtrrFixDramModEn]"
+               " not cleared by BIOS, clearing this bit\n",
+               smp_processor_id());
+        syscfg &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
+        mtrr_wrmsr(MSR_K8_SYSCFG, syscfg);
+    }
+}
+
 static void
 get_fixed_ranges(mtrr_type * frs)
 {
 	uint64_t *p = (uint64_t *) frs;
 	int i;
+
+        amd_check_syscfg_dram_mod_en();
 
 	rdmsrl(MTRRfix64K_00000_MSR, p[0]);
 

@@ -116,20 +141,6 @@
 }
 
 /**
- * Enable and allow read/write of extended fixed-range MTRR bits on K8 CPUs
- * see AMD publication no. 24593, chapter 3.2.1 for more information
- */
-static inline void k8_enable_fixed_iorrs(void)
-{
-	uint64_t msr_content;
-
-	rdmsrl(MSR_K8_SYSCFG, msr_content);
-	mtrr_wrmsr(MSR_K8_SYSCFG, msr_content 
-				| K8_MTRRFIXRANGE_DRAM_ENABLE
-				| K8_MTRRFIXRANGE_DRAM_MODIFY);
-}
-
-/**
  * Checks and updates an fixed-range MTRR if it differs from the value it
  * should have. If K8 extenstions are wanted, update the K8 SYSCFG MSR also.
  * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information

@@ -145,10 +156,6 @@
 	val = ((uint64_t)msrwords[1] << 32) | msrwords[0];
 
 	if (msr_content != val) {
-		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-		    boot_cpu_data.x86 == 15 &&
-		    ((msrwords[0] | msrwords[1]) & K8_MTRR_RDMEM_WRMEM_MASK))
-			k8_enable_fixed_iorrs();
 		mtrr_wrmsr(msr, val);
 		*changed = TRUE;
 	}

@@ -211,6 +218,8 @@
 	unsigned long long *saved = (unsigned long long *) frs;
 	int changed = FALSE;
 	int block=-1, range;
+
+        amd_check_syscfg_dram_mod_en();
 
 	while (fixed_range_blocks[++block].ranges)
 	    for (range=0; range < fixed_range_blocks[block].ranges; range++)

diff -r 8957b6b3f439 -r 4a9430efe643 xen/arch/x86/cpu/amd.c
@@ -300,6 +300,32 @@
 		on_each_cpu(disable_c1e, NULL, 1);
 }
 
+/*
+ * BIOS is expected to clear MtrrFixDramModEn bit. According to AMD BKDG : 
+ * "The MtrrFixDramModEn bit should be set to 1 during BIOS initalization of 
+ * the fixed MTRRs, then cleared to 0 for operation."
+ */
+static void check_syscfg_dram_mod_en(void)
+{
+	uint64_t syscfg;
+	static int printed = 0;
+
+	if (!((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) &&
+		(boot_cpu_data.x86 >= 0x0f)))
+		return;
+
+	rdmsrl(MSR_K8_SYSCFG, syscfg);
+	if (syscfg & K8_MTRRFIXRANGE_DRAM_MODIFY) {
+		if (!printed) {
+			printed++;
+			printk(KERN_ERR "MTRR: SYSCFG[MtrrFixDramModEn] not "
+				"cleared by BIOS, clearing this bit\n");
+		}
+		syscfg &= ~K8_MTRRFIXRANGE_DRAM_MODIFY;
+		wrmsrl(MSR_K8_SYSCFG, syscfg);
+	}
+}
+
 static void __devinit init_amd(struct cpuinfo_x86 *c)
 {
 	u32 l, h;

@@ -453,6 +479,8 @@
 		disable_c1_ramping();
 
 	set_cpuidmask(c);
+
+	check_syscfg_dram_mod_en();
 }
 
 static struct cpu_dev amd_cpu_dev __cpuinitdata = {

diff -r 4a9430efe643 -r effc147d35ce xen/arch/x86/cpu/mtrr/generic.c
@@ -116,20 +116,6 @@
 }
 
 /**
- * Enable and allow read/write of extended fixed-range MTRR bits on K8 CPUs
- * see AMD publication no. 24593, chapter 3.2.1 for more information
- */
-static inline void k8_enable_fixed_iorrs(void)
-{
-	uint64_t msr_content;
-
-	rdmsrl(MSR_K8_SYSCFG, msr_content);
-	mtrr_wrmsr(MSR_K8_SYSCFG, msr_content 
-				| K8_MTRRFIXRANGE_DRAM_ENABLE
-				| K8_MTRRFIXRANGE_DRAM_MODIFY);
-}
-
-/**
  * Checks and updates an fixed-range MTRR if it differs from the value it
  * should have. If K8 extenstions are wanted, update the K8 SYSCFG MSR also.
  * see AMD publication no. 24593, chapter 7.8.1, page 233 for more information

@@ -145,10 +131,6 @@
 	val = ((uint64_t)msrwords[1] << 32) | msrwords[0];
 
 	if (msr_content != val) {
-		if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
-		    boot_cpu_data.x86 == 15 &&
-		    ((msrwords[0] | msrwords[1]) & K8_MTRR_RDMEM_WRMEM_MASK))
-			k8_enable_fixed_iorrs();
 		mtrr_wrmsr(msr, val);
 		*changed = TRUE;
 	}