mpc83xx: add config options to spd_sdram

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

2.
read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage.
Due to HRCW being being located at offset 0 we need an SPD data offset.

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

4.
CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific.

I have taken care not to increase code size and not to break existing boards.

Any comments from your side ?
Is this something you might ACK ?

On Tue, 5 Apr 2011 11:49:49 +0200
Andre Schwarz <[email protected]> wrote:

Cc'ing York Sun, who knows a little more about this stuff than I do.

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse & program the controller without requiring a new u-boot binary?

this isn't included in the below diff, right?

Quoted 5 lines

2.
read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage.
Due to HRCW being being located at offset 0 we need an SPD data offset.

and this is the SPD_EEPROM_OFFSET stuff below? hmm..

so both 1 & 2 are coagulated in my mind - ideally, this would be implemented with the new ddr code in arch/powerpc/cpu/mpc8xxx/ddr/main.c - see fsl_ddr_compute(), which has a GET_SPD step that would need to be either skipped (i.e, start_step = COMPUTE_DIMM_PARMS), or changed to be able to be overridden, or, ideally, all DIMM computations would be precomputed and stored in ROM and a direct start_step to e.g., STEP_ASSIGN_ADDRESSES were made.

Quoted 6 lines

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

board specific things like this are perfectly acceptable, of course.

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter that is needed, especially when this is all fixed in the new ddr code. So, in preparation for 83xx to eventually migrate to the new ddr code, I'd like this to be done in such a way so as to start to conform to the new code by at least defining ODT, etc. parameters in a board-specific ddr.c:fsl_ddr_board_options(). See board/freescale/{p1022ds,*}/ddr.c for example.

Quoted 4 lines

4.
CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific.

again, to be defined as popts->cpo_override in the board-specific ddr.c:fsl_ddr_board_options().

Quoted 11 lines

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

Quoted 1 line

this isn't included in the below diff, right?

Actually I have code for this already, pending for more broader testing. I use raw timing data from datasheet of DDR chips. We have an internal discussion to recommend using EEPROM to mimic SPD structure.

Quoted 6 lines

Quoted 4 lines

2.
read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage.
Due to HRCW being being located at offset 0 we need an SPD data offset.

and this is the SPD_EEPROM_OFFSET stuff below? hmm..

Quoted 7 lines

so both 1& 2 are coagulated in my mind - ideally, this would be implemented with the new ddr code in arch/powerpc/cpu/mpc8xxx/ddr/main.c - see fsl_ddr_compute(), which has a GET_SPD step that would need to be either skipped (i.e, start_step = COMPUTE_DIMM_PARMS), or changed to be able to be overridden, or, ideally, all DIMM computations would be precomputed and stored in ROM and a direct start_step to e.g., STEP_ASSIGN_ADDRESSES were made.

I don't 100% agree with the idea to put SPD-like data in HRCW.

How can you be sure the data matches DDR?

It would be equivalent to using fixed raw timing data, wouldn't it?

Quoted 7 lines

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3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

board specific things like this are perfectly acceptable, of course.

Quoted 8 lines

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter that is needed, especially when this is all fixed in the new ddr code. So, in preparation for 83xx to eventually migrate to the new ddr code, I'd like this to be done in such a way so as to start to conform to the new code by at least defining ODT, etc. parameters in a board-specific ddr.c:fsl_ddr_board_options(). See board/freescale/{p1022ds,*}/ddr.c for example.

The ODT table is implemented in options.c and it can be override by board functions. Look for the last function in options.c and ddr.c under the board folder.

Quoted 5 lines

Quoted 3 lines

4.
CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific.

again, to be defined as popts->cpo_override in the board-specific ddr.c:fsl_ddr_board_options().

I recommend to use auto calibration. If for some reason, you want to override, it belongs to board specific file, same as the above.

York,

Quoted 11 lines

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I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

Quoted 4 lines

Quoted 1 line

this isn't included in the below diff, right?

Actually I have code for this already, pending for more broader testing. I use raw timing data from datasheet of DDR chips. We have an internal discussion to recommend using EEPROM to mimic SPD structure.

sorry - I don't understand this.
Why do you want to create something new if there's a standard like SPD layout ? It is working perfectly fine and the data can be obtained from the manufacturer without further modifications.

Quoted 14 lines

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2.
read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage.
Due to HRCW being being located at offset 0 we need an SPD data offset.

and this is the SPD_EEPROM_OFFSET stuff below? hmm..

so both 1& 2 are coagulated in my mind - ideally, this would be implemented with the new ddr code in arch/powerpc/cpu/mpc8xxx/ddr/main.c - see fsl_ddr_compute(), which has a GET_SPD step that would need to be either skipped (i.e, start_step = COMPUTE_DIMM_PARMS), or changed to be able to be overridden, or, ideally, all DIMM computations would be precomputed and stored in ROM and a direct start_step to e.g., STEP_ASSIGN_ADDRESSES were made.

Quoted 1 line

I don't 100% agree with the idea to put SPD-like data in HRCW.

The SPD data has nothing to do with HRCW - it's just stored in the same PROM.

Quoted 1 line

How can you be sure the data matches DDR?

Because the SPD data gets programmed during production. We can use any SPD table *exactly* matching the soldered parts.

Quoted 1 line

It would be equivalent to using fixed raw timing data, wouldn't it?

no - it isn't.
I want the *same* U-Boot binary running on *different* memory configurations, i.e.
*no* fixed timing at all.

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3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

board specific things like this are perfectly acceptable, of course.

Quoted 8 lines

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter that is needed, especially when this is all fixed in the new ddr code. So, in preparation for 83xx to eventually migrate to the new ddr code, I'd like this to be done in such a way so as to start to conform to the new code by at least defining ODT, etc. parameters in a board-specific ddr.c:fsl_ddr_board_options(). See board/freescale/{p1022ds,*}/ddr.c for example.

Quoted 3 lines

The ODT table is implemented in options.c and it can be override by board functions. Look for the last function in options.c and ddr.c under the board folder.

To me it is a fundamental design error to rely on environment data to set up the hardware correctly. Especially something that critical as memory configuration.

Do you expect U-Boot to work with a corrupted environment, i.e. hwconfig value unavailable ?

Of course this might never happen on a reference design board - but that's not real life.

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4.
CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific.

again, to be defined as popts->cpo_override in the board-specific ddr.c:fsl_ddr_board_options().

I recommend to use auto calibration. If for some reason, you want to override, it belongs to board specific file, same as the above.

no - auto calibration is far from ideal regarding emc and power consumption.

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

this isn't included in the below diff, right?

Quoted 4 lines

2.
read SPD data also from extended adressing EEPROMS used for e.g. HRCW storage.
Due to HRCW being being located at offset 0 we need an SPD data offset.

and this is the SPD_EEPROM_OFFSET stuff below? hmm..

so both 1& 2 are coagulated in my mind - ideally, this would be implemented with the new ddr code in arch/powerpc/cpu/mpc8xxx/ddr/main.c - see fsl_ddr_compute(), which has a GET_SPD step that would need to be either skipped (i.e, start_step = COMPUTE_DIMM_PARMS), or changed to be able to be overridden, or, ideally, all DIMM computations would be precomputed and stored in ROM and a direct start_step to e.g., STEP_ASSIGN_ADDRESSES were made.

Quoted 5 lines

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

board specific things like this are perfectly acceptable, of course.

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter

that is needed, especially
when this is all fixed in the new ddr code. So, in preparation for 83xx to eventually migrate to the new ddr code,

I'd like this to be
done in such a way so as to start to conform to the new code by at least defining ODT, etc. parameters in a board-specific ddr.c:fsl_ddr_board_options(). See board/freescale/{p1022ds,*}/ddr.c for example.

Quoted 3 lines

4.
CPO values depend on internal bond wire length which has significantly high variance on MPC837x, i.e. this value also should be board specific.

again, to be defined as popts->cpo_override in the board-specific ddr.c:fsl_ddr_board_options().

Quoted 5 lines

I have taken care not to increase code size and not to break existing boards.

Any comments from your side ?
Is this something you might ACK ?

not as-is - see above, and let me know what you think.

Kim, York,

Quoted 10 lines

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

SPD data is nothing more than an I2C-EEPROM soldered on each memory module containing the physical details of the memory devices.
Since I already have an I2C-EEPROM on the board I can use it for SPD data, i.e.
the board's memory is configured using normal detection routines.

During production (exactly: board testing) the EEPROM will be programmed with an SPD
table matching the soldered memory devices. This gives some flexibility regarding size and
speed grades ... some devices have pretty short life-cycles.

Quoted 6 lines

Quoted 5 lines

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they are far from ideal.

board specific things like this are perfectly acceptable, of course.

ok.

Quoted 2 lines

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter

ok - what about this :

#if !defined(CONFIG_SYS_DDR_MODE_ODT_VALUE)
#define CONFIG_SYS_DDR_MODE_ODT_VALUE 0x40
#endif

mode_odt_enable = CONFIG_SYS_DDR_MODE_ODT_VALUE;

I really can't think of this change being a problem for anybody.

Quoted 18 lines

Kim, York,

Quoted 10 lines

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

SPD data is nothing more than an I2C-EEPROM soldered on each memory module containing the physical details of the memory devices.
Since I already have an I2C-EEPROM on the board I can use it for SPD data, i.e.
the board's memory is configured using normal detection routines.

Quoted 5 lines

During production (exactly: board testing) the EEPROM will be programmed with an SPD
table matching the soldered memory devices. This gives some flexibility regarding size and
speed grades ... some devices have pretty short life-cycles.

That's right. If you have the SPD in I2C-EEPROM, you have a real SPD as far as software concerns. Just provide the I2C address.

Quoted 13 lines

Quoted 7 lines

Quoted 6 lines

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they
are far from ideal.

board specific things like this are perfectly acceptable, of course.

ok.

Quoted 2 lines

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter

ok - what about this :

Quoted 9 lines

#if !defined(CONFIG_SYS_DDR_MODE_ODT_VALUE)
#define CONFIG_SYS_DDR_MODE_ODT_VALUE 0x40
#endif

mode_odt_enable = CONFIG_SYS_DDR_MODE_ODT_VALUE;

I really can't think of this change being a problem for anybody.

I would suggest to put it in fsl_ddr_board_options() in ddr.c under the board directory. There you can override any options, including

popts->cs_local_opts[i].odt_rd_cfg
popts->cs_local_opts[i].odt_wr_cfg
popts->cpo_override

York

--

York,
?
ok - will give it a try tomorrow.
?

?

York Sun <[email protected]> hat am 6. April 2011 um 18:37 geschrieben:

Quoted 60 lines · Andre Schwarz

Quoted 18 lines

Kim, York,

Quoted 10 lines

Quoted 6 lines

I have made some mods to spd_sdram.c for various reason:

1.
use SPD setup also for soldered RAM.
This allows DDR mounting options without U-Boot change because SPD data is written during in-circuit/boundary-scan testing.

not sure I understand this - board with soldered RAM can't physically get the SPD data from RAM, yet SPD data were somehow acquired and written into some ROM, so spd_sdram() is still needed to parse& program the controller without requiring a new u-boot binary?

SPD data is nothing more than an I2C-EEPROM soldered on each memory module containing the physical details of the memory devices.
Since I already have an I2C-EEPROM on the board I can use it for SPD data, i.e.
the board's memory is configured using normal detection routines.

Quoted 5 lines

During production (exactly: board testing) the EEPROM will be programmed with an SPD
table matching the soldered memory devices. This gives some flexibility regarding size and
speed grades ... some devices have pretty short life-cycles.

That's right. If you have the SPD in I2C-EEPROM, you have a real SPD as far as software concerns. Just provide the I2C address.

Quoted 13 lines

Quoted 7 lines

Quoted 6 lines

3.
for optimized signal integrity and power consumption we need more influence on
the on-die termination. Although the assumed default values are working they
are far from ideal.

board specific things like this are perfectly acceptable, of course.

ok.

Quoted 2 lines

however, it should not be being done by glittering old-83xx/spd_sdram with an extra #ifdef for every new parameter

ok - what about this :

Quoted 9 lines

#if !defined(CONFIG_SYS_DDR_MODE_ODT_VALUE)
#define CONFIG_SYS_DDR_MODE_ODT_VALUE 0x40
#endif

mode_odt_enable = CONFIG_SYS_DDR_MODE_ODT_VALUE;

I really can't think of this change being a problem for anybody.

I would suggest to put it in fsl_ddr_board_options() in ddr.c under the board directory. There you can override any options, including

popts->cs_local_opts[i].odt_rd_cfg
popts->cs_local_opts[i].odt_wr_cfg
popts->cpo_override

Quoted 4 lines

York

--

Gru?,
Andr? Schwarz

York,

"Schwarz,Andre" <[email protected]> hat am 6. April 2011 um 20:42 geschrieben:

Quoted 8 lines

York,

ok - will give it a try tomorrow.

hmm - having a look at the Makefile it looks like I need CONFIG_FSL_DDR2.

This seems to pull in the "new" code ... without omitting the "old" one

in arch/powerpc/cpu/mpc83xx/spd_sdram.c

The Makefile further uses ctrl_regs.c ... which fails.

having a look arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c gives :

#ifdef CONFIG_MPC85xx

  #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR

#elif defined(CONFIG_MPC86xx)

  #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR

#else

#error "Undefined _DDR_ADDR"

#endif

There's not a single sign of any 83xx within this code.

Grepping through the board configs only show 85xx and 86xx based boards using it.

Sorry, but I'm feeling like an idiot.

Are you playing some game with me or am I simply unable to understand the code ?

Please shed some light on this.

Quoted 60 lines

Quoted 8 lines

York,

ok - will give it a try tomorrow.

hmm - having a look at the Makefile it looks like I need CONFIG_FSL_DDR2.

This seems to pull in the "new" code ... without omitting the "old" one

in arch/powerpc/cpu/mpc83xx/spd_sdram.c

The Makefile further uses ctrl_regs.c ... which fails.

having a look arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c gives :

#ifdef CONFIG_MPC85xx

   #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR

#elif defined(CONFIG_MPC86xx)

   #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR

#else

#error "Undefined _DDR_ADDR"

#endif

There's not a single sign of any 83xx within this code.

Grepping through the board configs only show 85xx and 86xx based boards using it.

Sorry, but I'm feeling like an idiot.

Are you playing some game with me or am I simply unable to understand the code ?

Quoted 3 lines

Please shed some light on this.

Andre,

I am sorry I totally ignored the subject with mpc83xx. I was thinking of mpc85xx.

You are right the old code is in spd_sdram.c and it is still in use for mpc83xx. Unless to adjust the code, there is no board specific file.

Quoted 2 lines

I am sorry I totally ignored the subject with mpc83xx. I was thinking of mpc85xx.

ok - no "new" code for 83xx then.

Quoted 3 lines

You are right the old code is in spd_sdram.c and it is still in use for mpc83xx. Unless to adjust the code, there is no board specific file.

Are you willing to accept some changes to spd_sdram.c or will I have another out-of-tree board ?

What we need is :

- more configurable settings like driver strength, cpo and odt values.
- Reading SPD data from an arbitrary i2c eeprom.

What's so bad about my proposal ?
Please let me know so that I'm able to improve.

Quoted 11 lines

Quoted 2 lines

I am sorry I totally ignored the subject with mpc83xx. I was thinking of mpc85xx.

ok - no "new" code for 83xx then.

Quoted 3 lines

You are right the old code is in spd_sdram.c and it is still in use for mpc83xx. Unless to adjust the code, there is no board specific file.

Are you willing to accept some changes to spd_sdram.c or will I have another out-of-tree board ?

What we need is :

Quoted 6 lines

- more configurable settings like driver strength, cpo and odt values.
- Reading SPD data from an arbitrary i2c eeprom.

What's so bad about my proposal ?
Please let me know so that I'm able to improve.

I welcome the change to use the new code since the feature you asked is already there.

York,

Quoted 12 lines · Andre Schwarz

Quoted 11 lines

Quoted 2 lines

I am sorry I totally ignored the subject with mpc83xx. I was thinking of mpc85xx.

ok - no "new" code for 83xx then.

Quoted 3 lines

You are right the old code is in spd_sdram.c and it is still in use for mpc83xx. Unless to adjust the code, there is no board specific file.

Are you willing to accept some changes to spd_sdram.c or will I have another out-of-tree board ?

What we need is :

Quoted 8 lines

Quoted 6 lines

- more configurable settings like driver strength, cpo and odt values.
- Reading SPD data from an arbitrary i2c eeprom.

What's so bad about my proposal ?
Please let me know so that I'm able to improve.

I welcome the change to use the new code since the feature you asked is already there.

sorry, but I'm not sure if I understand this correctly.

What I need is some minor non-intrusive changes to 83xx-specific file spd_sdram.c because it is the most straightforward solution with *no* impact on code size or other existing boards. So: The feature I ask for is *not* already there.

What I definitely won't do is use the "new" fsl ddr code in mpc8xxx/ddr because it completely lacks 83xx support.
So: The feature I ask for is there but my CPU family is not supported. IMHO the "new" code is total overkill for 83xx.

Quoted 28 lines · Andre Schwarz

York,

Quoted 12 lines · Andre Schwarz

Quoted 11 lines

Quoted 2 lines

I am sorry I totally ignored the subject with mpc83xx. I was thinking of mpc85xx.

ok - no "new" code for 83xx then.

Quoted 3 lines

You are right the old code is in spd_sdram.c and it is still in use for mpc83xx. Unless to adjust the code, there is no board specific file.

Are you willing to accept some changes to spd_sdram.c or will I have another out-of-tree board ?

What we need is :

Quoted 8 lines

Quoted 6 lines

- more configurable settings like driver strength, cpo and odt values.
- Reading SPD data from an arbitrary i2c eeprom.

What's so bad about my proposal ?
Please let me know so that I'm able to improve.

I welcome the change to use the new code since the feature you asked is already there.

sorry, but I'm not sure if I understand this correctly.

What I need is some minor non-intrusive changes to 83xx-specific file spd_sdram.c because it is the most straightforward solution with *no* impact on code size or other existing boards. So: The feature I ask for is *not* already there.

Quoted 5 lines

What I definitely won't do is use the "new" fsl ddr code in mpc8xxx/ddr because it completely lacks 83xx support.
So: The feature I ask for is there but my CPU family is not supported. IMHO the "new" code is total overkill for 83xx.

It would be easier to maintain one set of code. But if the change you need is relatively small to the old code and doesn't have negative impact on other boards, go ahead to post the patch.