MX5: Keep L2 cache enabled before jump to kernel
PATCH 1/1 MX5: Keep L2 cache enabled before jump to kernel
Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel.
--- arch/arm/cpu/armv7/mx5/Makefile | 2 +- arch/arm/cpu/armv7/mx5/cache.S | 43 +++++++++++++++++++++++++++++ arch/arm/cpu/armv7/mx5/soc.c | 6 ++++ arch/arm/include/asm/arch-mx5/sys_proto.h | 2 + include/configs/mx51evk.h | 2 - include/configs/mx53evk.h | 2 - include/configs/mx53loco.h | 2 - 7 files changed, 52 insertions(+), 7 deletions(-)
arch/arm/cpu/armv7/mx5/Makefile +1 -1
@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(SOC).o COBJS = soc.o clock.o iomux.o timer.o speed.o -SOBJS = lowlevel_init.o +SOBJS = lowlevel_init.o cache.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
arch/arm/cpu/armv7/mx5/cache.S new file +43 -0
43 lines not on this page · raw message
arch/arm/cpu/armv7/mx5/soc.c +6 -0
@@ -144,3 +144,9 @@ void reset_cpu(ulong addr) {__raw_writew (4 ,WDOG1_BASE_ADDR ); } + +/*dummy function for L2 ON*/ +u32 get_device_type (void ) +{ +return 0 ; +}
arch/arm/include/asm/arch-mx5/sys_proto.h +2 -0
@@ -27,5 +27,7 @@u32 get_cpu_rev (void );#define is_soc_rev (rev) ((get_cpu_rev() & 0xFF) - rev)void sdelay (unsigned long ); +void invalidate_dcache (u32 ); +u32 get_device_type (void );#endif
include/configs/mx51evk.h +0 -2
@@ -35,8 +35,6 @@#define CONFIG_SYS_TEXT_BASE 0x97800000 -#define CONFIG_L2_OFF -#include <asm/arch/imx-regs.h> /* * Disabled for now due to build problems under Debian and a significant
include/configs/mx53evk.h +0 -2
@@ -29,8 +29,6 @@#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF -#include <asm/arch/imx-regs.h> #define CONFIG_CMDLINE_TAG 1/* enable passing of ATAGs */
include/configs/mx53loco.h +0 -2
@@ -30,8 +30,6 @@#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_L2_OFF -#include <asm/arch/imx-regs.h> #define CONFIG_CMDLINE_TAG 1/* enable passing of ATAGs */
Signature · 1 line
1.7.1
PATCH 1/1 MX5: Keep L2 cache enabled before jump to kernel
Hi Jason,
Le 13/04/2011 15:25, Jason Liu a ?crit :
Quoted 4 lines
Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel.
Do you mean that the Linux Kernel has L2 cache support except for enabling it? It would seem to me the most logical thing would be to enable the cache in Linux then, rather than expecting the bootloader to do it.
Amicalement,
Signature · 1 line
Albert.
PATCH 1/1 MX5: Keep L2 cache enabled before jump to kernel
In reply to Jason LiuOn 04/13/2011 03:25 PM, Jason Liu wrote:
Hi Jason,
Quoted 4 lines
Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel.
If the cache is not active in the kernel for MX5, this should be fixed in the kernel for this architecture. Normally, cache is activated inside the kernel itself, as I cann see for other architectures and other ARMV7 processors (omap)
However, if you plan to add cache support, why not add the functions to get the cache enabled in u-boot ?
arch/arm/cpu/armv7/mx5/cache.S line 29
Quoted 6 lines
arch/arm/cpu/armv7/mx5/cache.S new file +6
-0+ +/* + * Sine we did not enable D-cache in uboot,this is the + * Dummy function for L2 ON to make build pass. please + * Check the arch/arm/cpu/armv7/cpu.c file + */
This seems to me a workaround for a non clear problem (at least, not clear for me..) to activate the cache at the startup of the kernel. There are already processors in u-boot supporting the cache, and if we add caching functions to u-boot for i.MX5, we must implement the full support to have cache active in the bootloader.
arch/arm/cpu/armv7/mx5/cache.S line 34
Quoted 5 lines
arch/arm/cpu/armv7/mx5/cache.S new file +5
-0+invalidate_dcache: + mov pc, lr + +l2_cache_enable: + mrc p15, 0, r0, c1, c0, 1;
No registers are saved before calling this funtion ?
Best regards,
Stefano Babic
Signature · 5 lines
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PATCH 1/1 MX5: Keep L2 cache enabled before jump to kernel
Hi, Stefano,
2011/4/15 Stefano Babic <[email protected]>:
Quoted 9 lines · Jason Liu
Hi Jason,
Quoted 4 lines
Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel.
Quoted 4 lines
If the cache is not active in the kernel for MX5, this should be fixed in the kernel for this architecture. Normally, cache is activated inside the kernel itself, as I cann see for other architectures and other ARMV7 processors (omap)
Here the cache is L2 cache. I have observed that if uboot does not enable it, then L2 cache will not get enabled through current ARM linux core code.
And for the uboot itself it provide the following code in cpu.c to enable L2 cache
before jump to linux kernel, and this code maybe implemented by omap guys:
If linux kernel already enabled it, then there is no need for the L2 related code here?
int cleanup_before_linux(void)
{
unsigned int i;
/*
* this function is called just before we call linux
* it prepares the processor for linux
*
* we turn off caches etc ...
*/
disable_interrupts();
/* turn off I/D-cache */
icache_disable();
dcache_disable();
/* invalidate I-cache */
cache_flush();#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
invalidate_dcache(get_device_type());
#endif
i = 0;
/* mem barrier to sync up things */
asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i));#ifndef CONFIG_L2_OFF
l2_cache_enable();#endif
Quoted 3 lines
However, if you plan to add cache support, why not add the functions to get the cache enabled in u-boot ?
Yes, good point.
This is my to-do task but It will need much work to make the driver work when enable d-cache support.
Quoted 13 lines
arch/arm/cpu/armv7/mx5/cache.S line 29
Quoted 7 lines
arch/arm/cpu/armv7/mx5/cache.S new file +6
-0+ +/* + * Sine we did not enable D-cache in uboot,this is the + * Dummy function for L2 ON to make build pass. please + * Check the arch/arm/cpu/armv7/cpu.c file + */This seems to me a workaround for a non clear problem (at least, not clear for me..) to activate the cache at the startup of the kernel. There are already processors in u-boot supporting the cache, and if we add caching functions to u-boot for i.MX5, we must implement the full support to have cache active in the bootloader.
Here, as the comment said, since uboot does not enable L2 cache before it jump to linux kernel, so, this function is just the dummy function to pass build. Take the code from arch/arm/cpu/armv7/cpu.c:
int cleanup_before_linux(void)
{
...
#ifndef CONFIG_L2_OFF
/* turn off L2 cache */
l2_cache_disable();
/* invalidate L2 cache also */
invalidate_dcache(get_device_type());#endif
Quoted 9 lines
arch/arm/cpu/armv7/mx5/cache.S
Quoted 7 lines
arch/arm/cpu/armv7/mx5/cache.S new file +5
-0+invalidate_dcache: + ? ? mov ? ? pc, lr + +l2_cache_enable: + ? ? mrc ? ? p15, 0, r0, c1, c0, 1;No registers are saved before calling this funtion ?
I don't think it needs save any register.
Jason
Quoted 15 lines
Best regards,
Stefano Babic--
=====================================================================
DENX Software Engineering GmbH, ? ? MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 ?Email: office at denx.de
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PATCH 1/1 MX5: Keep L2 cache enabled before jump to kernel
Le 15/04/2011 17:55, Jason Liu a ?crit :
Quoted 12 lines
Hi, Stefano,
2011/4/15 Stefano Babic<[email protected]>:
Quoted 9 lines · Jason Liu
Hi Jason,
Quoted 4 lines
Currently, Linux kernel does not do any L2 cache enable Operation.So,Keep L2 cache enabled(L2EN=1) in the u-boot before Jump to the Linux Kernel and thus L2 cache can be effectively used in Linux Kernel.
Quoted 7 lines
Quoted 4 lines
If the cache is not active in the kernel for MX5, this should be fixed in the kernel for this architecture. Normally, cache is activated inside the kernel itself, as I cann see for other architectures and other ARMV7 processors (omap)
Here the cache is L2 cache. I have observed that if uboot does not enable it, then L2 cache will not get enabled through current ARM linux core code.
Which still does not tell us why Linux should depend on some bootloader for enabling L2 cache. If Linux does not enable L2 cache, there is a reason and we should not enable the L2 cache in Linux' back; conversively, if Linux wants L2 cache enabled, then let Linux do it.
Quoted 5 lines
And for the uboot itself it provide the following code in
cpu.cto enable L2 cache
before jump to linux kernel, and this code maybe implemented by omap guys:
If linux kernel already enabled it, then there is no need for the L2 related code here?
Turning caches OFF before jumping to Linux is a sane thing to do. Re-enabling it, on the other hand, bears no reason that I can discern, because Linux can do it just as well, and it is better if Linux does it because it will do it exactly where and when it is ready for it, and because this removes a dependency between Linux and the bootloader, which is a Good Thing (tm).
Amicalement,
Signature · 1 line
Albert.