ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

PATCH Superseded Macpaul Lin 4 participants 28 messages Mar 22, 2011 – May 12, 2011

Subsystems (3)

Arm (32-bit) Memory technology devices (MTD) Arm/actions semi architecture

lore

Share & tools

lore

Macpaul Lin

author

2011-03-22 05:01 UTC #0 lore raw

PATCH v2 1/4 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting
lowlevel_init

 include/faraday/ftahbc020s.h |   94 
++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

include/faraday/ftahbc020s.h new file +94 -0

new file mode 100644
index 0000000..da85582
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, n * 4, n=0~31
+ */
+#ifdef __ASSEMBLY__
+/* this section is used by lowlevel_init.S */
+#define FTAHBC020S_SLAVE_BSR_0		0x00	/* Slave n Base/Size Reg */
+#define FTAHBC020S_SLAVE_BSR_1		0x04
+#define FTAHBC020S_SLAVE_BSR_2		0x08
+#define FTAHBC020S_SLAVE_BSR_3		0x0C
+#define FTAHBC020S_SLAVE_BSR_4		0x10
+#define FTAHBC020S_SLAVE_BSR_5		0x14
+#define FTAHBC020S_SLAVE_BSR_6		0x18
+#define FTAHBC020S_SLAVE_BSR_7		0x1C
+#define FTAHBC020S_SLAVE_BSR_8		0x20
+#define FTAHBC020S_SLAVE_BSR_9		0x24
+#define FTAHBC020S_SLAVE_BSR_10		0x28
+
+#define FTAHBC020S_PCR			0x80	/* Priority Ctrl Reg */
+#define FTAHBC020S_TCRG			0x84	/* Transfer Ctrl Reg */
+#define FTAHBC020S_CR			0x88	/* Ctrl Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xFFF) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xF) << 16)
+
+#define FTAHBC020S_SLAVE_BSR_SIZE_1M	0x0
+#define FTAHBC020S_SLAVE_BSR_SIZE_2M	0x1
+#define FTAHBC020S_SLAVE_BSR_SIZE_4M	0x2
+#define FTAHBC020S_SLAVE_BSR_SIZE_8M	0x3
+#define FTAHBC020S_SLAVE_BSR_SIZE_16M	0x4
+#define FTAHBC020S_SLAVE_BSR_SIZE_32M	0x5
+#define FTAHBC020S_SLAVE_BSR_SIZE_64M	0x6
+#define FTAHBC020S_SLAVE_BSR_SIZE_128M	0x7
+#define FTAHBC020S_SLAVE_BSR_SIZE_256M	0x8
+#define FTAHBC020S_SLAVE_BSR_SIZE_512M	0x9
+#define FTAHBC020S_SLAVE_BSR_SIZE_1G	0xA
+#define FTAHBC020S_SLAVE_BSR_SIZE_2G	0xB
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_15	(1 << 15)
+#define FTAHBC020S_PCR_PLEVEL_14	(1 << 14)
+#define FTAHBC020S_PCR_PLEVEL_13	(1 << 13)
+#define FTAHBC020S_PCR_PLEVEL_12	(1 << 12)
+#define FTAHBC020S_PCR_PLEVEL_11	(1 << 11)
+#define FTAHBC020S_PCR_PLEVEL_10	(1 << 10)
+#define FTAHBC020S_PCR_PLEVEL_09	(1 << 9)
+#define FTAHBC020S_PCR_PLEVEL_08	(1 << 8)
+#define FTAHBC020S_PCR_PLEVEL_07	(1 << 7)
+#define FTAHBC020S_PCR_PLEVEL_06	(1 << 6)
+#define FTAHBC020S_PCR_PLEVEL_05	(1 << 5)
+#define FTAHBC020S_PCR_PLEVEL_04	(1 << 4)
+#define FTAHBC020S_PCR_PLEVEL_03	(1 << 3)
+#define FTAHBC020S_PCR_PLEVEL_02	(1 << 2)
+#define FTAHBC020S_PCR_PLEVEL_01	(1 << 1)
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */

Signature · 16 lines

1.7.3.5



CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally 
privileged information or information protected from disclosure. If you 
are not the intended recipient, you are hereby notified that any 
disclosure, copying, distribution, or use of the information contained 
herein is strictly prohibited. In this case, please immediately notify the 
sender by return e-mail, delete the message (and any accompanying 
documents) and destroy all printed hard copies. Thank you for your 
cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

Macpaul Lin

author

2011-03-22 05:01 UTC #1 lore raw

PATCH v2 2/4 ftsdmc021: add register definitions of ftsdmc021

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting
lowlevel_init

 include/faraday/ftsdmc021.h |  154 
+++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +34 -0

new file mode 100644
index 0000000..3ed535a
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifdef __ASSEMBLY__
+#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
+#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
+#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
+#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
+#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg

0 */
+#define FTSDMC021_OFFSET_BANK1_BSR 0x14 /* External Bank Base/Size Reg
1 */
+#define FTSDMC021_OFFSET_BANK2_BSR 0x18 /* External Bank Base/Size Reg
2 */
+#define FTSDMC021_OFFSET_BANK3_BSR 0x1C /* External Bank Base/Size Reg
3 */
+#define FTSDMC021_OFFSET_BANK4_BSR 0x20 /* External Bank Base/Size Reg
4 */
+#define FTSDMC021_OFFSET_BANK5_BSR 0x24 /* External Bank Base/Size Reg
5 */
+#define FTSDMC021_OFFSET_BANK6_BSR 0x28 /* External Bank Base/Size Reg
6 */
+#define FTSDMC021_OFFSET_BANK7_BSR 0x2C /* External Bank Base/Size Reg
7 */
+#define FTSDMC021_OFFSET_RAGR 0x30 /* Read Arbitration Group Reg */
+#define FTSDMC021_OFFSET_FRR 0x34 /* Flush Request Register */
+#define FTSDMC021_OFFSET_EBISR 0x38 /* EBI Support Register */
+#define FTSDMC021_OFFSET_CRR 0x100 /* Controller Revision Reg */
+#define FTSDMC021_OFFSET_CFR 0x104 /* Controller Feature Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x) ((x) & 0x3)
+#define FTSDMC021_TP1_TWR(x) (((x) & 0x3) << 4)
+#define FTSDMC021_TP1_TRF(x) (((x) & 0xf) << 8)
+#define FTSDMC021_TP1_TRCD(x) (((x) & 0x7) << 12)
+#define FTSDMC021_TP1_TRP(x) (((x) & 0xf) << 16)
+#define FTSDMC021_TP1_TRAS(x) (((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x) ((x) & 0xffff)
+#define FTSDMC021_TP2_INI_REFT(x) (((x) & 0xf) << 16)
+#define FTSDMC021_TP2_INI_PREC(x) (((x) & 0xf) << 20)
+
+/*
+ * Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZEF(x) ((x) & 0xf)
+#define FTSDMC021_CR1_MBW(x) (((x) & 0x3) << 4)
+#define FTSDMC021_CR1_DSZ(x) (((x) & 0x7) << 8)
+#define FTSDMC021_CR1_DDW(x) (((x) & 0x3) << 12)
+#define FTSDMC021_CR1_MA2T(x) (1 << 16) /* Double Memory Address
Cycle Enable */
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF (1 << 0)
+#define FTSDMC021_CR2_PWDN (1 << 1)
+#define FTSDMC021_CR2_ISMR (1 << 2)
+#define FTSDMC021_CR2_IREF (1 << 3)
+#define FTSDMC021_CR2_IPREC (1 << 4)
+#define FTSDMC021_CR2_REFTYPE (1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE (1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x) ((x) & 0xfff)
+
+#define FTSDMC021_BANK_SIZE_1M 0x0
+#define FTSDMC021_BANK_SIZE_2M 0x1
+#define FTSDMC021_BANK_SIZE_4M 0x2
+#define FTSDMC021_BANK_SIZE_8M 0x3
+#define FTSDMC021_BANK_SIZE_16M 0x4
+#define FTSDMC021_BANK_SIZE_32M 0x5
+#define FTSDMC021_BANK_SIZE_64M 0x6
+#define FTSDMC021_BANK_SIZE_128M 0x7
+#define FTSDMC021_BANK_SIZE_256M 0x8
+#define FTSDMC021_BANK_SIZE_512M 0x9
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x) (((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x) (((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x) (((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x) (((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x) (((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x) (((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x) (((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x) (((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x) (((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT (1 << 3)
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x) ((x) & 0xfff)
+#define FTSDMC021_EBISR_PRSMR (1 << 12)
+#define FTSDMC021_EBISR_POPREC (1 << 13)
+#define FTSDMC021_EBISR_POSMR (1 << 14)
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER (((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER (((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER (((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK (((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN (((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI (((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH (((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH (((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH (((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH (((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH (((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH (((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH (((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH (((x) >> 31) & 0x1)
+
+#endif /* __FTSDMC021_H */

Signature · 16 lines

1.7.3.5



CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally 
privileged information or information protected from disclosure. If you 
are not the intended recipient, you are hereby notified that any 
disclosure, copying, distribution, or use of the information contained 
herein is strictly prohibited. In this case, please immediately notify the 
sender by return e-mail, delete the message (and any accompanying 
documents) and destroy all printed hard copies. Thank you for your 
cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

Wolfgang Denk

2011-04-25 21:58 UTC #2 lore raw

PATCH v2 2/4 ftsdmc021: add register definitions of ftsdmc021

Dear "Macpaul Lin",

Quoted 8 lines · In message <[email protected]> you wrote:

Support registers definitions of ftsdmc021 SDRAM controller.
Signed-off-by Macpaul Lin <[email protected]>
---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting
lowlevel_init

Quoted 4 lines

 include/faraday/ftsdmc021.h |  154 
+++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

Corrupted patch (line wrapped). Please resubmit after fixing your mailer (or better use git sendmail).

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Just because your doctor has a name for your condition  doesn't  mean
he knows what it is.

Macpaul Lin

2011-04-26 06:00 UTC #3 lore raw

PATCH v2 2/4 ftsdmc021: add register definitions of ftsdmc021

Hi Wolfgang,

2011/4/26 Wolfgang Denk <[email protected]>:

Quoted 7 lines

Corrupted patch (line wrapped). ?Please resubmit after fixing your mailer (or better use git sendmail).
Best regards,
Wolfgang Denk

I did use git sent-email to send this patch.
However it seems still some problem.
I will change a mail server to resend this.

Please help on check the latest patch if the corruption still occurs.

Sorry for the bothering.

Signature · 2 lines

Best regards,
Macpaul Lin

Macpaul Lin

author

2011-04-26 05:53 UTC #4 lore raw

PATCH v2 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

In reply to Macpaul Lin

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.

Signed-off-by Macpaul Lin <[email protected]>

Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init

---
 include/faraday/ftahbc020s.h |   94 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

include/faraday/ftahbc020s.h new file +94 -0

new file mode 100644
index 0000000..da85582
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, n * 4, n=0~31
+ */
+#ifdef __ASSEMBLY__
+/* this section is used by lowlevel_init.S */
+#define FTAHBC020S_SLAVE_BSR_0		0x00	/* Slave n Base/Size Reg */
+#define FTAHBC020S_SLAVE_BSR_1		0x04
+#define FTAHBC020S_SLAVE_BSR_2		0x08
+#define FTAHBC020S_SLAVE_BSR_3		0x0C
+#define FTAHBC020S_SLAVE_BSR_4		0x10
+#define FTAHBC020S_SLAVE_BSR_5		0x14
+#define FTAHBC020S_SLAVE_BSR_6		0x18
+#define FTAHBC020S_SLAVE_BSR_7		0x1C
+#define FTAHBC020S_SLAVE_BSR_8		0x20
+#define FTAHBC020S_SLAVE_BSR_9		0x24
+#define FTAHBC020S_SLAVE_BSR_10		0x28
+
+#define FTAHBC020S_PCR			0x80	/* Priority Ctrl Reg */
+#define FTAHBC020S_TCRG			0x84	/* Transfer Ctrl Reg */
+#define FTAHBC020S_CR			0x88	/* Ctrl Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xFFF) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xF) << 16)
+
+#define FTAHBC020S_SLAVE_BSR_SIZE_1M	0x0
+#define FTAHBC020S_SLAVE_BSR_SIZE_2M	0x1
+#define FTAHBC020S_SLAVE_BSR_SIZE_4M	0x2
+#define FTAHBC020S_SLAVE_BSR_SIZE_8M	0x3
+#define FTAHBC020S_SLAVE_BSR_SIZE_16M	0x4
+#define FTAHBC020S_SLAVE_BSR_SIZE_32M	0x5
+#define FTAHBC020S_SLAVE_BSR_SIZE_64M	0x6
+#define FTAHBC020S_SLAVE_BSR_SIZE_128M	0x7
+#define FTAHBC020S_SLAVE_BSR_SIZE_256M	0x8
+#define FTAHBC020S_SLAVE_BSR_SIZE_512M	0x9
+#define FTAHBC020S_SLAVE_BSR_SIZE_1G	0xA
+#define FTAHBC020S_SLAVE_BSR_SIZE_2G	0xB
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_15	(1 << 15)
+#define FTAHBC020S_PCR_PLEVEL_14	(1 << 14)
+#define FTAHBC020S_PCR_PLEVEL_13	(1 << 13)
+#define FTAHBC020S_PCR_PLEVEL_12	(1 << 12)
+#define FTAHBC020S_PCR_PLEVEL_11	(1 << 11)
+#define FTAHBC020S_PCR_PLEVEL_10	(1 << 10)
+#define FTAHBC020S_PCR_PLEVEL_09	(1 << 9)
+#define FTAHBC020S_PCR_PLEVEL_08	(1 << 8)
+#define FTAHBC020S_PCR_PLEVEL_07	(1 << 7)
+#define FTAHBC020S_PCR_PLEVEL_06	(1 << 6)
+#define FTAHBC020S_PCR_PLEVEL_05	(1 << 5)
+#define FTAHBC020S_PCR_PLEVEL_04	(1 << 4)
+#define FTAHBC020S_PCR_PLEVEL_03	(1 << 3)
+#define FTAHBC020S_PCR_PLEVEL_02	(1 << 2)
+#define FTAHBC020S_PCR_PLEVEL_01	(1 << 1)
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */

Signature · 1 line

1.7.3.5

Macpaul Lin

author

2011-04-26 05:53 UTC #5 lore raw

PATCH v2 2/2 ftsdmc021: add register definitions of ftsdmc021

In reply to Macpaul Lin

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init

---
 include/faraday/ftsdmc021.h |  154 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +154 -0

new file mode 100644
index 0000000..3ed535a
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifdef __ASSEMBLY__
+#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
+#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
+#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
+#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
+#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg 0 */
+#define FTSDMC021_OFFSET_BANK1_BSR	0x14	/* External Bank Base/Size Reg 1 */
+#define FTSDMC021_OFFSET_BANK2_BSR	0x18	/* External Bank Base/Size Reg 2 */
+#define FTSDMC021_OFFSET_BANK3_BSR	0x1C	/* External Bank Base/Size Reg 3 */
+#define FTSDMC021_OFFSET_BANK4_BSR	0x20	/* External Bank Base/Size Reg 4 */
+#define FTSDMC021_OFFSET_BANK5_BSR	0x24	/* External Bank Base/Size Reg 5 */
+#define FTSDMC021_OFFSET_BANK6_BSR	0x28	/* External Bank Base/Size Reg 6 */
+#define FTSDMC021_OFFSET_BANK7_BSR	0x2C	/* External Bank Base/Size Reg 7 */
+#define FTSDMC021_OFFSET_RAGR		0x30	/* Read Arbitration Group Reg */
+#define FTSDMC021_OFFSET_FRR		0x34	/* Flush Request Register */
+#define FTSDMC021_OFFSET_EBISR		0x38	/* EBI Support Register */
+#define FTSDMC021_OFFSET_CRR		0x100	/* Controller Revision Reg */
+#define FTSDMC021_OFFSET_CFR		0x104	/* Controller Feature Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZEF(x)	((x) & 0xf)
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)	/* Double Memory Address Cycle Enable */
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)
+#define FTSDMC021_CR2_PWDN	(1 << 1)
+#define FTSDMC021_CR2_ISMR	(1 << 2)
+#define FTSDMC021_CR2_IREF	(1 << 3)
+#define FTSDMC021_CR2_IPREC	(1 << 4)
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+#define FTSDMC021_BANK_SIZE_1M		0x0
+#define FTSDMC021_BANK_SIZE_2M		0x1
+#define FTSDMC021_BANK_SIZE_4M		0x2
+#define FTSDMC021_BANK_SIZE_8M		0x3
+#define FTSDMC021_BANK_SIZE_16M		0x4
+#define FTSDMC021_BANK_SIZE_32M		0x5
+#define FTSDMC021_BANK_SIZE_64M		0x6
+#define FTSDMC021_BANK_SIZE_128M	0x7
+#define FTSDMC021_BANK_SIZE_256M	0x8
+#define FTSDMC021_BANK_SIZE_512M	0x9
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */

Signature · 1 line

1.7.3.5

Macpaul Lin

author

2011-04-26 06:04 UTC #6 lore raw

PATCH v3 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

In reply to Macpaul Lin

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this.

 include/faraday/ftahbc020s.h |   94 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 94 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

include/faraday/ftahbc020s.h new file +94 -0

new file mode 100644
index 0000000..da85582
@@ -0,0 +1,94 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, n * 4, n=0~31
+ */
+#ifdef __ASSEMBLY__
+/* this section is used by lowlevel_init.S */
+#define FTAHBC020S_SLAVE_BSR_0		0x00	/* Slave n Base/Size Reg */
+#define FTAHBC020S_SLAVE_BSR_1		0x04
+#define FTAHBC020S_SLAVE_BSR_2		0x08
+#define FTAHBC020S_SLAVE_BSR_3		0x0C
+#define FTAHBC020S_SLAVE_BSR_4		0x10
+#define FTAHBC020S_SLAVE_BSR_5		0x14
+#define FTAHBC020S_SLAVE_BSR_6		0x18
+#define FTAHBC020S_SLAVE_BSR_7		0x1C
+#define FTAHBC020S_SLAVE_BSR_8		0x20
+#define FTAHBC020S_SLAVE_BSR_9		0x24
+#define FTAHBC020S_SLAVE_BSR_10		0x28
+
+#define FTAHBC020S_PCR			0x80	/* Priority Ctrl Reg */
+#define FTAHBC020S_TCRG			0x84	/* Transfer Ctrl Reg */
+#define FTAHBC020S_CR			0x88	/* Ctrl Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xFFF) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xF) << 16)
+
+#define FTAHBC020S_SLAVE_BSR_SIZE_1M	0x0
+#define FTAHBC020S_SLAVE_BSR_SIZE_2M	0x1
+#define FTAHBC020S_SLAVE_BSR_SIZE_4M	0x2
+#define FTAHBC020S_SLAVE_BSR_SIZE_8M	0x3
+#define FTAHBC020S_SLAVE_BSR_SIZE_16M	0x4
+#define FTAHBC020S_SLAVE_BSR_SIZE_32M	0x5
+#define FTAHBC020S_SLAVE_BSR_SIZE_64M	0x6
+#define FTAHBC020S_SLAVE_BSR_SIZE_128M	0x7
+#define FTAHBC020S_SLAVE_BSR_SIZE_256M	0x8
+#define FTAHBC020S_SLAVE_BSR_SIZE_512M	0x9
+#define FTAHBC020S_SLAVE_BSR_SIZE_1G	0xA
+#define FTAHBC020S_SLAVE_BSR_SIZE_2G	0xB
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_15	(1 << 15)
+#define FTAHBC020S_PCR_PLEVEL_14	(1 << 14)
+#define FTAHBC020S_PCR_PLEVEL_13	(1 << 13)
+#define FTAHBC020S_PCR_PLEVEL_12	(1 << 12)
+#define FTAHBC020S_PCR_PLEVEL_11	(1 << 11)
+#define FTAHBC020S_PCR_PLEVEL_10	(1 << 10)
+#define FTAHBC020S_PCR_PLEVEL_09	(1 << 9)
+#define FTAHBC020S_PCR_PLEVEL_08	(1 << 8)
+#define FTAHBC020S_PCR_PLEVEL_07	(1 << 7)
+#define FTAHBC020S_PCR_PLEVEL_06	(1 << 6)
+#define FTAHBC020S_PCR_PLEVEL_05	(1 << 5)
+#define FTAHBC020S_PCR_PLEVEL_04	(1 << 4)
+#define FTAHBC020S_PCR_PLEVEL_03	(1 << 3)
+#define FTAHBC020S_PCR_PLEVEL_02	(1 << 2)
+#define FTAHBC020S_PCR_PLEVEL_01	(1 << 1)
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */

Signature · 1 line

1.7.3.5

Wolfgang Denk

2011-04-26 07:18 UTC #7 lore raw

PATCH v3 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

Dear Macpaul Lin,

Quoted 10 lines · In message <[email protected]> you wrote:

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.
Signed-off-by Macpaul Lin <[email protected]>
---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this.

...

include/faraday/ftahbc020s.h line 41

Quoted 12 lines

include/faraday/ftahbc020s.h new file +12 -0

+/* this section is used by lowlevel_init.S */
+#define FTAHBC020S_SLAVE_BSR_0		0x00	/* Slave n Base/Size Reg */
+#define FTAHBC020S_SLAVE_BSR_1		0x04
+#define FTAHBC020S_SLAVE_BSR_2		0x08
+#define FTAHBC020S_SLAVE_BSR_3		0x0C
+#define FTAHBC020S_SLAVE_BSR_4		0x10
+#define FTAHBC020S_SLAVE_BSR_5		0x14
+#define FTAHBC020S_SLAVE_BSR_6		0x18
+#define FTAHBC020S_SLAVE_BSR_7		0x1C
+#define FTAHBC020S_SLAVE_BSR_8		0x20
+#define FTAHBC020S_SLAVE_BSR_9		0x24
+#define FTAHBC020S_SLAVE_BSR_10		0x28

See previous comment: I think this should be done using asm-offsets instead.

Quoted 5 lines

include/faraday/ftahbc020s.h new file +5 -0

+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xFFF) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xF) << 16)
+
+#define FTAHBC020S_SLAVE_BSR_SIZE_1M	0x0
+#define FTAHBC020S_SLAVE_BSR_SIZE_2M	0x1

include/faraday/ftahbc020s.h line 65

Quoted 10 lines

include/faraday/ftahbc020s.h new file +10 -0

+#define FTAHBC020S_SLAVE_BSR_SIZE_4M	0x2
+#define FTAHBC020S_SLAVE_BSR_SIZE_8M	0x3
+#define FTAHBC020S_SLAVE_BSR_SIZE_16M	0x4
+#define FTAHBC020S_SLAVE_BSR_SIZE_32M	0x5
+#define FTAHBC020S_SLAVE_BSR_SIZE_64M	0x6
+#define FTAHBC020S_SLAVE_BSR_SIZE_128M	0x7
+#define FTAHBC020S_SLAVE_BSR_SIZE_256M	0x8
+#define FTAHBC020S_SLAVE_BSR_SIZE_512M	0x9
+#define FTAHBC020S_SLAVE_BSR_SIZE_1G	0xA
+#define FTAHBC020S_SLAVE_BSR_SIZE_2G	0xB

I recommend to use a generic macro here, as recommended for the other patch.

Quoted 8 lines

include/faraday/ftahbc020s.h new file +8 -0

+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_15	(1 << 15)
+#define FTAHBC020S_PCR_PLEVEL_14	(1 << 14)
+#define FTAHBC020S_PCR_PLEVEL_13	(1 << 13)
+#define FTAHBC020S_PCR_PLEVEL_12	(1 << 12)
+#define FTAHBC020S_PCR_PLEVEL_11	(1 << 11)

include/faraday/ftahbc020s.h line 84

Quoted 10 lines

include/faraday/ftahbc020s.h new file +10 -0

+#define FTAHBC020S_PCR_PLEVEL_10	(1 << 10)
+#define FTAHBC020S_PCR_PLEVEL_09	(1 << 9)
+#define FTAHBC020S_PCR_PLEVEL_08	(1 << 8)
+#define FTAHBC020S_PCR_PLEVEL_07	(1 << 7)
+#define FTAHBC020S_PCR_PLEVEL_06	(1 << 6)
+#define FTAHBC020S_PCR_PLEVEL_05	(1 << 5)
+#define FTAHBC020S_PCR_PLEVEL_04	(1 << 4)
+#define FTAHBC020S_PCR_PLEVEL_03	(1 << 3)
+#define FTAHBC020S_PCR_PLEVEL_02	(1 << 2)
+#define FTAHBC020S_PCR_PLEVEL_01	(1 << 1)

Ditto here. Why flooding the code with tons of (mostly) unused defines?

Use:

	#define FTAHBC020S_PCR_PLEVEL(x)	(1 << (x))

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: [email protected]
Vor allem kein Gedanke! Nichts ist kompromittierender als ein  Gedan-
ke!            - Friedrich Wilhelm Nietzsche _Der Fall Wagner_ (1888)

Macpaul Lin

author

2011-04-26 06:04 UTC #8 lore raw

PATCH v3 2/2 ftsdmc021: add register definitions of ftsdmc021

In reply to Macpaul Lin

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this.

 include/faraday/ftsdmc021.h |  154 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 154 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +154 -0

new file mode 100644
index 0000000..3ed535a
@@ -0,0 +1,154 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifdef __ASSEMBLY__
+#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
+#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
+#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
+#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
+#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg 0 */
+#define FTSDMC021_OFFSET_BANK1_BSR	0x14	/* External Bank Base/Size Reg 1 */
+#define FTSDMC021_OFFSET_BANK2_BSR	0x18	/* External Bank Base/Size Reg 2 */
+#define FTSDMC021_OFFSET_BANK3_BSR	0x1C	/* External Bank Base/Size Reg 3 */
+#define FTSDMC021_OFFSET_BANK4_BSR	0x20	/* External Bank Base/Size Reg 4 */
+#define FTSDMC021_OFFSET_BANK5_BSR	0x24	/* External Bank Base/Size Reg 5 */
+#define FTSDMC021_OFFSET_BANK6_BSR	0x28	/* External Bank Base/Size Reg 6 */
+#define FTSDMC021_OFFSET_BANK7_BSR	0x2C	/* External Bank Base/Size Reg 7 */
+#define FTSDMC021_OFFSET_RAGR		0x30	/* Read Arbitration Group Reg */
+#define FTSDMC021_OFFSET_FRR		0x34	/* Flush Request Register */
+#define FTSDMC021_OFFSET_EBISR		0x38	/* EBI Support Register */
+#define FTSDMC021_OFFSET_CRR		0x100	/* Controller Revision Reg */
+#define FTSDMC021_OFFSET_CFR		0x104	/* Controller Feature Reg */
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZEF(x)	((x) & 0xf)
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)	/* Double Memory Address Cycle Enable */
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)
+#define FTSDMC021_CR2_PWDN	(1 << 1)
+#define FTSDMC021_CR2_ISMR	(1 << 2)
+#define FTSDMC021_CR2_IREF	(1 << 3)
+#define FTSDMC021_CR2_IPREC	(1 << 4)
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+#define FTSDMC021_BANK_SIZE_1M		0x0
+#define FTSDMC021_BANK_SIZE_2M		0x1
+#define FTSDMC021_BANK_SIZE_4M		0x2
+#define FTSDMC021_BANK_SIZE_8M		0x3
+#define FTSDMC021_BANK_SIZE_16M		0x4
+#define FTSDMC021_BANK_SIZE_32M		0x5
+#define FTSDMC021_BANK_SIZE_64M		0x6
+#define FTSDMC021_BANK_SIZE_128M	0x7
+#define FTSDMC021_BANK_SIZE_256M	0x8
+#define FTSDMC021_BANK_SIZE_512M	0x9
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */

Signature · 1 line

1.7.3.5

Wolfgang Denk

2011-04-26 07:15 UTC #9 lore raw

PATCH v3 2/2 ftsdmc021: add register definitions of ftsdmc021

Dear Macpaul Lin,

Quoted 8 lines · In message <[email protected]> you wrote:

Support registers definitions of ftsdmc021 SDRAM controller.
Signed-off-by Macpaul Lin <[email protected]>
---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this.

...

include/faraday/ftsdmc021.h line 41

Quoted 13 lines

include/faraday/ftsdmc021.h new file +13 -0

+#ifdef __ASSEMBLY__
+#define FTSDMC021_OFFSET_TP1		0x00	/* SDRAM Timing Parameter 1 */
+#define FTSDMC021_OFFSET_TP2		0x04	/* SDRAM Timing Parameter 2 */
+#define FTSDMC021_OFFSET_CR1		0x08	/* SDRAM Configuration Reg 1 */
+#define FTSDMC021_OFFSET_CR2		0x0C	/* SDRAM Configuration Reg 2 */
+#define FTSDMC021_OFFSET_BANK0_BSR	0x10	/* External Bank Base/Size Reg 0 */
+#define FTSDMC021_OFFSET_BANK1_BSR	0x14	/* External Bank Base/Size Reg 1 */
+#define FTSDMC021_OFFSET_BANK2_BSR	0x18	/* External Bank Base/Size Reg 2 */
+#define FTSDMC021_OFFSET_BANK3_BSR	0x1C	/* External Bank Base/Size Reg 3 */
+#define FTSDMC021_OFFSET_BANK4_BSR	0x20	/* External Bank Base/Size Reg 4 */
+#define FTSDMC021_OFFSET_BANK5_BSR	0x24	/* External Bank Base/Size Reg 5 */
+#define FTSDMC021_OFFSET_BANK6_BSR	0x28	/* External Bank Base/Size Reg 6 */
+#define FTSDMC021_OFFSET_BANK7_BSR	0x2C	/* External Bank Base/Size Reg 7 */

Lines too long. Please fix globally.

I think it is generally wrong to manually define these offsets here. You should use a C struct instead, and auto-generate the offsets if needed using the asm-offsets approach (see top level Makefile for details).

Quoted 5 lines

include/faraday/ftsdmc021.h new file +5 -0

+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+

include/faraday/ftsdmc021.h line 104

Quoted 10 lines

include/faraday/ftsdmc021.h new file +10 -0

+#define FTSDMC021_BANK_SIZE_1M		0x0
+#define FTSDMC021_BANK_SIZE_2M		0x1
+#define FTSDMC021_BANK_SIZE_4M		0x2
+#define FTSDMC021_BANK_SIZE_8M		0x3
+#define FTSDMC021_BANK_SIZE_16M		0x4
+#define FTSDMC021_BANK_SIZE_32M		0x5
+#define FTSDMC021_BANK_SIZE_64M		0x6
+#define FTSDMC021_BANK_SIZE_128M	0x7
+#define FTSDMC021_BANK_SIZE_256M	0x8
+#define FTSDMC021_BANK_SIZE_512M	0x9

Why don't you use a generic macro here, like

	#define FTSDMC021_BANK_SIZE(sz)	(ffs(x) - 21)

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Accident: A condition in which presence of mind is good, but  absence
of body is better.

Macpaul Lin

2011-04-26 07:20 UTC #10 lore raw

PATCH v3 2/2 ftsdmc021: add register definitions of ftsdmc021

Hi Wolfgang,

2011/4/26 Wolfgang Denk <[email protected]>:

Quoted 9 lines

Dear Macpaul Lin,
Quoted 1 line
+#define FTSDMC021_OFFSET_BANK7_BSR ? 0x2C ? ?/* External Bank Base/Size Reg 7 */
Lines too long. ?Please fix globally.
I think it is generally wrong to manually define these offsets here. You should use a C struct instead, and auto-generate the offsets if needed using the asm-offsets approach (see top level Makefile for details).

Since this is a patch send before in old times, I will fix it soon and send the next patch.

Quoted 7 lines

Review
Quoted 3 lines
(quoted diff) +3 -0
+#define FTSDMC021_BANK_SIZE_128M ? ? 0x7
+#define FTSDMC021_BANK_SIZE_256M ? ? 0x8
+#define FTSDMC021_BANK_SIZE_512M ? ? 0x9
Why don't you use a generic macro here, like
? ? ? ?#define FTSDMC021_BANK_SIZE(sz) (ffs(x) - 21)

Thanks for your suggestion.

Signature · 2 lines

Best regards,
Macpaul Lin

Macpaul Lin

author

2011-04-26 10:25 UTC #11 lore raw

PATCH v4 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

In reply to Macpaul Lin

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Fix BSR according to datasheet.
- Replace offset define into structure.
- Replace the constant of power of 2 define into (ffs(x) - 1)
- Replace redundant define of PCR into simple version.

 include/faraday/ftahbc020s.h |   59 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

include/faraday/ftahbc020s.h new file +59 -0

new file mode 100644
index 0000000..c6b0c16
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, offset: n * 4, n=0~31
+ */
+#ifndef __ASSEMBLY__
+struct ftahbc02s {
+	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
+	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
+	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
+	unsigned int	cr;		/* 0x88	- Ctrl Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
+/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
+#define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */

Signature · 1 line

1.7.3.5

Macpaul Lin

author

2011-04-26 10:25 UTC #12 lore raw

PATCH v4 2/2 ftsdmc021: add register definitions of ftsdmc021

In reply to Macpaul Lin

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Cleanup.
- Replace lines over 80 chararters with proper statement.
- Add some bit-field description about important registers.
- Replace the define of constant which is power of 2 to (ffs(x - 1))

 include/faraday/ftsdmc021.h |  151 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +151 -0

new file mode 100644
index 0000000..483d991
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifndef __ASSEMBLY__
+struct ftsdmc021 {
+	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
+	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
+	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
+	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
+	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
+	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
+	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
+	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
+	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
+	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
+	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
+	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
+	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
+	unsigned int	frr;		/* 0x34 - Flush Request Register */
+	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
+	unsigned int	RSVED[25];	/* 0x3c-0x9c - Reserved		*/
+	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
+	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */
+/* b(16:19) - Initial Refresh Times */
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+/* b(20:23) - Initial Pre-Charge Times */
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * SDRAM Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */
+/* b(16) MA2T: Double Memory Address Cycle Enable */
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)
+/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
+#define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
+#define FTSDMC021_CR2_PWDN	(1 << 1)	/* Power Down Operation Mode */
+#define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
+#define FTSDMC021_CR2_IREF	(1 << 3)	/* Init Refresh Start Flag */
+#define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)	/* Flush Req Flag */
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */

Signature · 1 line

1.7.3.5

Wolfgang Denk

2011-04-26 10:48 UTC #13 lore raw

PATCH v4 2/2 ftsdmc021: add register definitions of ftsdmc021

Dear Macpaul Lin,

Quoted 60 lines · In message <[email protected]> you wrote:

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Cleanup.
- Replace lines over 80 chararters with proper statement.
- Add some bit-field description about important registers.
- Replace the define of constant which is power of 2 to (ffs(x - 1))

 include/faraday/ftsdmc021.h |  151 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +36 -0

new file mode 100644
index 0000000..483d991
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifndef __ASSEMBLY__
+struct ftsdmc021 {
+	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
+	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
+	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
+	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
+	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
+	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */

include/faraday/ftsdmc021.h line 46

Quoted 10 lines

include/faraday/ftsdmc021.h new file +10 -0

+	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
+	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
+	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
+	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
+	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
+	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
+	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
+	unsigned int	frr;		/* 0x34 - Flush Request Register */
+	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
+	unsigned int	RSVED[25];	/* 0x3c-0x9c - Reserved		*/

Sorry, but only macro definitions use ALL CAPS names. Variables names are all lower case.

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Pray to God, but keep rowing to shore. - Russian Proverb

Macpaul Lin

2011-04-26 10:57 UTC #14 lore raw

PATCH v4 2/2 ftsdmc021: add register definitions of ftsdmc021

Hi Wolfgang,

2011/4/26 Wolfgang Denk <[email protected]>:

Quoted 7 lines

Dear Macpaul Lin,
Quoted 1 line
+ ? ? unsigned int ? ?RSVED[25]; ? ? ?/* 0x3c-0x9c - Reserved ? ? ? ? */
Sorry, but only macro definitions use ALL CAPS names. ?Variables names are all lower case.

I was think of no used variable will be CAPS names to avoid typo with variable that will be used.

Will send the fix soon.

Thanks.

Signature · 2 lines

Best regards,
Macpaul Lin

Macpaul Lin

author

2011-03-22 05:01 UTC #15 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

In reply to Macpaul Lin

Move the header file "ftsdmc020.h" (SDRAM Controller) to "include/faraday" folder.

This change will let other SoC which also use ftsdmc020 could share the same header file.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Fix the include path of ftsdmc020 for a320evb.
- v1 of this patch /patch/71953/ in patchworks has been marked as
superseded.

arch/arm/include/asm/arch-a320/ftsdmc020.h |
103 ----------------------------

 board/faraday/a320evb/lowlevel_init.S      |    2 +-
 include/faraday/ftsdmc020.h                |  103 
++++++++++++++++++++++++++++
 3 files changed, 104 insertions(+), 104 deletions(-)
 delete mode 100644 arch/arm/include/asm/arch-a320/ftsdmc020.h
 create mode 100644 include/faraday/ftsdmc020.h

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-a320/ftsdmc020.h
deleted file mode 100644
index 0699772..0000000

arch/arm/include/asm/arch-a320/ftsdmc020.h deleted +0 ~~-103~~

103 lines not on this page · raw message

(quoted diff) +0 -0

b/board/faraday/a320evb/lowlevel_init.S
index 97718c0..4262c11 100644

board/faraday/a320evb/lowlevel_init.S +1 -1

@@ -21,7 +21,7 @@
 #include <version.h>
 
 #include <asm/macro.h>
-#include <asm/arch/ftsdmc020.h>
+#include <faraday/ftsdmc020.h>
 
 /*
  * parameters for the SDRAM controller

include/faraday/ftsdmc020.h new file +103 -0

103 lines not on this page · raw message

Signature · 16 lines

1.7.3.5



CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally 
privileged information or information protected from disclosure. If you 
are not the intended recipient, you are hereby notified that any 
disclosure, copying, distribution, or use of the information contained 
herein is strictly prohibited. In this case, please immediately notify the 
sender by return e-mail, delete the message (and any accompanying 
documents) and destroy all printed hard copies. Thank you for your 
cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

Albert ARIBAUD

2011-04-16 05:04 UTC #16 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

Hi MacPaul Lin,

Le 22/03/2011 06:01, Macpaul Lin a ?crit :

Quoted 13 lines

Move the header file "ftsdmc020.h" (SDRAM Controller) to "include/faraday" folder.
This change will let other SoC which also use ftsdmc020 could share the same header file.
Signed-off-by Macpaul Lin<[email protected]>
---
Changes for v2:
- Fix the include path of ftsdmc020 for a320evb.
- v1 of this patch /patch/71953/ in patchworks has been marked as
superseded.

Quoted 8 lines

arch/arm/include/asm/arch-a320/ftsdmc020.h |
103 ----------------------------
  board/faraday/a320evb/lowlevel_init.S      |    2 +-
  include/faraday/ftsdmc020.h                |  103
++++++++++++++++++++++++++++
  3 files changed, 104 insertions(+), 104 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-a320/ftsdmc020.h create mode 100644 include/faraday/ftsdmc020.h

Please use git format-patch -M or -C to get the move actually shown in the patch as a rename rather than as a delete+create.

Amicalement,

Signature · 1 line

Albert.

Macpaul Lin

2011-04-16 06:43 UTC #17 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

Hi Albert,

2011/4/16 Albert ARIBAUD <[email protected]>:

Quoted 9 lines

Hi MacPaul Lin,
Quoted 3 lines
? 3 files changed, 104 insertions(+), 104 deletions(-) ? delete mode 100644 arch/arm/include/asm/arch-a320/ftsdmc020.h ? create mode 100644 include/faraday/ftsdmc020.h
Please use git format-patch -M or -C to get the move actually shown in the patch as a rename rather than as a delete+create.

Thanks for your tip of -M or -C options.
Should I resend these two patches? Or you have already applied them into arm's master?

Signature · 2 lines

Best regards,
Macpaul Lin

Albert ARIBAUD

2011-04-16 06:50 UTC #18 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

Hi Macpaul Lin,

Le 16/04/2011 08:43, Macpaul Lin a ?crit :

Quoted 9 lines

Hi Albert,
2011/4/16 Albert ARIBAUD<[email protected]>:
Quoted 6 lines
Hi MacPaul Lin,
Quoted 3 lines
   3 files changed, 104 insertions(+), 104 deletions(-)
delete mode 100644 arch/arm/include/asm/arch-a320/ftsdmc020.h create mode 100644 include/faraday/ftsdmc020.h

Quoted 7 lines

Quoted 3 lines
Please use git format-patch -M or -C to get the move actually shown in the patch as a rename rather than as a delete+create.
Thanks for your tip of -M or -C options.
Should I resend these two patches? Or you have already applied them into arm's master?

Please resend a V3 patch set of the four patches, even if two of them are unchanged. Make sure all patches have their history updated, even the unchanged patches ('V3: no change'). I'll apply the whole set in one go.

Amicalement,

Signature · 1 line

Albert.

Macpaul Lin

2011-04-21 02:57 UTC #19 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

HI Albert,

2011/4/16 Albert ARIBAUD <[email protected]>:

Quoted 8 lines

Please resend a V3 patch set of the four patches, even if two of them are unchanged. Make sure all patches have their history updated, even the unchanged patches ('V3: no change'). I'll apply the whole set in one go.
Amicalement,
--
Albert.

Patch v3 of this set of patches has been send on 2011-04-16

Please refer to
http://patchwork.ozlabs.org/patch/91478/
http://patchwork.ozlabs.org/patch/91479/
http://patchwork.ozlabs.org/patch/91476/
http://patchwork.ozlabs.org/patch/91477/

Thanks.

Signature · 2 lines

Best regards,
Macpaul Lin

Albert ARIBAUD

2011-04-21 11:35 UTC #20 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

Hi MacPaul,

Le 21/04/2011 04:57, Macpaul Lin a ?crit :

Quoted 12 lines

HI Albert,
2011/4/16 Albert ARIBAUD<[email protected]>:
Quoted 8 lines
Please resend a V3 patch set of the four patches, even if two of them are unchanged. Make sure all patches have their history updated, even the unchanged patches ('V3: no change'). I'll apply the whole set in one go.
Amicalement,
--
Albert.

Quoted 7 lines

Patch v3 of this set of patches has been send on 2011-04-16
Please refer to
http://patchwork.ozlabs.org/patch/91478/
http://patchwork.ozlabs.org/patch/91479/
http://patchwork.ozlabs.org/patch/91476/
http://patchwork.ozlabs.org/patch/91477/

91476 and 91477 are ok, I'll apply them.

91478 and 91479, though, I don't see their point: they are adding a file that obviously no one used before it was added, but that no one uses now. These header files are dead code, and should only be added in a patch where other code changes actually make them required.

Amicalement,

Signature · 1 line

Albert.

Macpaul Lin

2011-04-21 11:53 UTC #21 lore raw

PATCH v2 3/4 ftsdmc020: move ftsdmc020.h to include/faraday

Hi Albert,

2011/4/21 Albert ARIBAUD <[email protected]>:

Quoted 9 lines

91478 and 91479, though, I don't see their point: they are adding a file that obviously no one used before it was added, but that no one uses now. These header files are dead code, and should only be added in a patch where other code changes actually make them required.
Amicalement,
--
Albert.

Roger that.
I'll resend this later with the SoC which used it is under reviewing. Thanks.

Signature · 2 lines

Best regards,
Macpaul Lin

Macpaul Lin

author

2011-03-22 05:01 UTC #22 lore raw

PATCH v2 4/4 ftsmc020: move ftsmc020 static mem controller to driver/mtd

In reply to Macpaul Lin

Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder.

This change will let other SoC which also use ftsmc020 could share the same header file.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Move the header file of ftsmc020.h to include/faraday.
- Fix the include path of ftsmc020 for a320evb.
- v1 of this patch /patch/71957/ in patchworks has been marked as
superseded.

 arch/arm/cpu/arm920t/a320/Makefile        |    1 -
 arch/arm/cpu/arm920t/a320/ftsmc020.c      |   51 ------------------
 arch/arm/include/asm/arch-a320/ftsmc020.h | 
  79 -----------------------------
 board/faraday/a320evb/a320evb.c           |    2 +-
 drivers/mtd/Makefile                      |    1 +
 drivers/mtd/ftsmc020.c                    |   51 ++++++++++++++++++
 include/configs/a320evb.h                 |    4 +-
 include/faraday/ftsmc020.h                |   79 
+++++++++++++++++++++++++++++
 8 files changed, 135 insertions(+), 133 deletions(-)
 delete mode 100644 arch/arm/cpu/arm920t/a320/ftsmc020.c
 delete mode 100644 arch/arm/include/asm/arch-a320/ftsmc020.h
 create mode 100644 drivers/mtd/ftsmc020.c
 create mode 100644 include/faraday/ftsmc020.h

(quoted diff) +0 -0

b/arch/arm/cpu/arm920t/a320/Makefile
index 31da706..50eb265 100644

arch/arm/cpu/arm920t/a320/Makefile +0 -1

@@ -27,7 +27,6 @@ LIB	= $(obj)lib$(SOC).o
 
 SOBJS	+= reset.o
 COBJS	+= timer.o
-COBJS	+= ftsmc020.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

(quoted diff) +0 -0

b/arch/arm/cpu/arm920t/a320/ftsmc020.c
deleted file mode 100644
index 7646537..0000000

arch/arm/cpu/arm920t/a320/ftsmc020.c deleted +0 ~~-34~~

@@ -1,51 +0,0 @@
-/*
- * (C) Copyright 2009 Faraday Technology
- * Po-Yu Chuang <[email protected]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/ftsmc020.h>
-
-struct ftsmc020_config {
-	unsigned int	config;
-	unsigned int	timing;
-};
-
-static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
-
-static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
-
-static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config

*cfg)
-{
- if (bank > 3) {
- printf("bank # %u invalid\n", bank);
- return;
- }
-
- writel(cfg->config, &smc->bank[bank].cr);
- writel(cfg->timing, &smc->bank[bank].tpr);
-}
-
-void ftsmc020_init(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(config); i++)
- ftsmc020_setup_bank(i, &config[i]);
-}

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-a320/ftsmc020.h
deleted file mode 100644
index 95d9500..0000000

arch/arm/include/asm/arch-a320/ftsmc020.h deleted +0 ~~-79~~

79 lines not on this page · raw message

(quoted diff) +0 -0

b/board/faraday/a320evb/a320evb.c
index b9343e4..2578be4 100644

board/faraday/a320evb/a320evb.c +1 -1

@@ -21,7 +21,7 @@
 #include <netdev.h>
 #include <asm/io.h>
 
-#include <asm/arch/ftsmc020.h>
+#include <faraday/ftsmc020.h>
 
 DECLARE_GLOBAL_DATA_PTR;

drivers/mtd/Makefile +1 -0

index 999431c..5a5ecdf 100644
@@ -32,6 +32,7 @@ COBJS-$(CONFIG_HAS_DATAFLASH) += at45.o
 COBJS-$(CONFIG_FLASH_CFI_DRIVER) += cfi_flash.o
 COBJS-$(CONFIG_FLASH_CFI_MTD) += cfi_mtd.o
 COBJS-$(CONFIG_HAS_DATAFLASH) += dataflash.o
+COBJS-$(CONFIG_FTSMC020) += ftsmc020.o
 COBJS-$(CONFIG_FLASH_CFI_LEGACY) += jedec_flash.o
 COBJS-$(CONFIG_MW_EEPROM) += mw_eeprom.o
 COBJS-$(CONFIG_SPEARSMI) += spr_smi.o

drivers/mtd/ftsmc020.c new file +34 -0

new file mode 100644
index 0000000..b027685
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <faraday/ftsmc020.h>
+
+struct ftsmc020_config {
+	unsigned int	config;
+	unsigned int	timing;
+};
+
+static struct ftsmc020_config config[] = CONFIG_SYS_FTSMC020_CONFIGS;
+
+static struct ftsmc020 *smc = (struct ftsmc020 *)CONFIG_FTSMC020_BASE;
+
+static void ftsmc020_setup_bank(unsigned int bank, struct ftsmc020_config

*cfg)
+{
+ if (bank > 3) {
+ printf("bank # %u invalid\n", bank);
+ return;
+ }
+
+ writel(cfg->config, &smc->bank[bank].cr);
+ writel(cfg->timing, &smc->bank[bank].tpr);
+}
+
+void ftsmc020_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(config); i++)
+ ftsmc020_setup_bank(i, &config[i]);
+}

include/configs/a320evb.h +3 -1

index 5373bcb..4b297f0 100644
@@ -163,7 +163,8 @@
  * Static memory controller configuration
  */
 
-#include <asm/arch/ftsmc020.h>
+#define CONFIG_FTSMC020
+#include <faraday/ftsmc020.h>
 
 #define FTSMC020_BANK0_CONFIG	(FTSMC020_BANK_ENABLE             |	\
 				 FTSMC020_BANK_BASE(PHYS_FLASH_1) |	\

@@ -196,6 +197,7 @@
 	{ FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, },	\
 	{ FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, },	\
 }
+#endif /* CONFIG_FTSMC020 */
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization

include/faraday/ftsmc020.h new file +79 -0

79 lines not on this page · raw message

Signature · 16 lines

1.7.3.5



CONFIDENTIALITY NOTICE:

This e-mail (and its attachments) may contain confidential and legally 
privileged information or information protected from disclosure. If you 
are not the intended recipient, you are hereby notified that any 
disclosure, copying, distribution, or use of the information contained 
herein is strictly prohibited. In this case, please immediately notify the 
sender by return e-mail, delete the message (and any accompanying 
documents) and destroy all printed hard copies. Thank you for your 
cooperation.

Copyright ANDES TECHNOLOGY CORPORATION - All Rights Reserved.

Albert ARIBAUD

2011-04-16 05:08 UTC #23 lore raw

PATCH v2 4/4 ftsmc020: move ftsmc020 static mem controller to driver/mtd

Hi MacMaul Lin,

Le 22/03/2011 06:01, Macpaul Lin a ?crit :

Quoted 7 lines

Move the header file and definitions of ftsmc020 static memory control unit from a320 SoC folder to "drivers/mtd" folder.
This change will let other SoC which also use ftsmc020 could share the same header file.

Quoted 7 lines

Signed-off-by Macpaul Lin<[email protected]>
---
Changes for v2:
- Move the header file of ftsmc020.h to include/faraday.
- Fix the include path of ftsmc020 for a320evb.
- v1 of this patch /patch/71957/ in patchworks has been marked as
superseded.

Please regenerate with git format-patch -C or -M to get moves to show as rename, not delete+create.

Amicalement,

Signature · 1 line

Albert.

Macpaul Lin

author

2011-04-26 11:29 UTC #24 lore raw

PATCH v5 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

In reply to Macpaul Lin

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.

Signed-off-by Macpaul Lin <[email protected]>

 include/faraday/ftahbc020s.h |   59 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

include/faraday/ftahbc020s.h new file +59 -0

new file mode 100644
index 0000000..c6b0c16
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/* FTAHBC020S - AHB Controller (Arbiter/Decoder) definitions */
+#ifndef __FTAHBC020S_H
+#define __FTAHBC202S_H
+
+/* Registers Offsets */
+
+/*
+ * AHB Slave BSR, offset: n * 4, n=0~31
+ */
+#ifndef __ASSEMBLY__
+struct ftahbc02s {
+	unsigned int	s_bsr[32];	/* 0x00-0x7c - Slave n Base/Size Reg */
+	unsigned int	pcr;		/* 0x80	- Priority Ctrl Reg */
+	unsigned int	tcrg;		/* 0x84	- Transfer Ctrl Reg */
+	unsigned int	cr;		/* 0x88	- Ctrl Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * FTAHBC020S_SLAVE_BSR - Slave n Base / Size Register
+ */
+#define FTAHBC020S_SLAVE_BSR_BASE(x)	(((x) & 0xfff) << 20)
+#define FTAHBC020S_SLAVE_BSR_SIZE(x)	(((x) & 0xf) << 16)
+/* The value of b(16:19)SLAVE_BSR_SIZE: 1M-2048M, must be power of 2 */
+#define FTAHBC020S_BSR_SIZE(x)		(ffs(x) - 1)	/* size of Addr Space */
+
+/*
+ * FTAHBC020S_PCR - Priority Control Register
+ */
+#define FTAHBC020S_PCR_PLEVEL_(x)	(1 << (x))	/* x: 1-15 */
+
+/*
+ * FTAHBC020S_CR - Interrupt Control Register
+ */
+#define FTAHBC020S_CR_INTSTS	(1 << 24)
+#define FTAHBC020S_CR_RESP(x)	(((x) & 0x3) << 20)
+#define FTAHBC020S_CR_INTSMASK	(1 << 16)
+#define FTAHBC020S_CR_REMAP	(1 << 0)
+
+#endif	/* __FTAHBC020S_H */

Signature · 1 line

1.7.3.5

Wolfgang Denk

Applied

2011-05-12 21:25 UTC #25 lore raw

PATCH v5 1/2 ftahbc020s: Faraday FTAHBC020s AHB Bus Controller

Dear Macpaul Lin,

Quoted 18 lines · In message <[email protected]> you wrote:

ftahbc020s.h provides basic definitions of this controller to help a SoC which use this AHB Controller could do scalable software settings in lowlevel_init.S.
Signed-off-by Macpaul Lin <[email protected]>
---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Fix BSR according to datasheet.
- Replace offset define into structure.
- Replace the constant of power of 2 define into (ffs(x) - 1)
- Replace redundant define of PCR into simple version.
Changes for v5:
- No Change

Quoted 3 lines

 include/faraday/ftahbc020s.h |   59 ++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 59 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftahbc020s.h

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Success in marriage is not so much finding the right person as it  is
being the right person.

Macpaul Lin

author

2011-04-26 11:29 UTC #26 lore raw

PATCH v5 2/2 ftsdmc021: add register definitions of ftsdmc021

In reply to Macpaul Lin

Support registers definitions of ftsdmc021 SDRAM controller.

Signed-off-by Macpaul Lin <[email protected]>

---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Cleanup.
- Replace lines over 80 chararters with proper statement.
- Add some bit-field description about important registers.
- Replace the define of constant which is power of 2 to (ffs(x - 1))
Changes for v5:
- Replace all CAPS variable into lower case.

 include/faraday/ftsdmc021.h |  151 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

include/faraday/ftsdmc021.h new file +151 -0

new file mode 100644
index 0000000..fa12e1a
@@ -0,0 +1,151 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang <[email protected]>
+ *
+ * (C) Copyright 2011 Andes Technology Corp
+ * Macpaul Lin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTSDMC021 - SDRAM Controller
+ */
+#ifndef __FTSDMC021_H
+#define __FTSDMC021_H
+
+#ifndef __ASSEMBLY__
+struct ftsdmc021 {
+	unsigned int	tp1;		/* 0x00 - SDRAM Timing Parameter 1 */
+	unsigned int	tp2;		/* 0x04 - SDRAM Timing Parameter 2 */
+	unsigned int	cr1;		/* 0x08 - SDRAM Configuration Reg 1 */
+	unsigned int	cr2;		/* 0x0c - SDRAM Configuration Reg 2 */
+	unsigned int	bank0_bsr;	/* 0x10 - Ext. Bank Base/Size Reg 0 */
+	unsigned int	bank1_bsr;	/* 0x14 - Ext. Bank Base/Size Reg 1 */
+	unsigned int	bank2_bsr;	/* 0x18 - Ext. Bank Base/Size Reg 2 */
+	unsigned int	bank3_bsr;	/* 0x1c - Ext. Bank Base/Size Reg 3 */
+	unsigned int	bank4_bsr;	/* 0x20 - Ext. Bank Base/Size Reg 4 */
+	unsigned int	bank5_bsr;	/* 0x24 - Ext. Bank Base/Size Reg 5 */
+	unsigned int	bank6_bsr;	/* 0x28 - Ext. Bank Base/Size Reg 6 */
+	unsigned int	bank7_bsr;	/* 0x2c - Ext. Bank Base/Size Reg 7 */
+	unsigned int	ragr;		/* 0x30 - Read Arbitration Group Reg */
+	unsigned int	frr;		/* 0x34 - Flush Request Register */
+	unsigned int	ebisr;		/* 0x38 - EBI Support Register	*/
+	unsigned int	rsved[25];	/* 0x3c-0x9c - Reserved		*/
+	unsigned int	crr;		/* 0x100 - Controller Revision Reg */
+	unsigned int	cfr;		/* 0x104 - Controller Feature Reg */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * Timing Parameter 1 Register
+ */
+#define FTSDMC021_TP1_TCL(x)	((x) & 0x3)		/* CAS Latency */
+#define FTSDMC021_TP1_TWR(x)	(((x) & 0x3) << 4)	/* W-Recovery Time */
+#define FTSDMC021_TP1_TRF(x)	(((x) & 0xf) << 8)	/* Auto-Refresh Cycle */
+#define FTSDMC021_TP1_TRCD(x)	(((x) & 0x7) << 12)	/* RAS-to-CAS Delay */
+#define FTSDMC021_TP1_TRP(x)	(((x) & 0xf) << 16)	/* Precharge Cycle */
+#define FTSDMC021_TP1_TRAS(x)	(((x) & 0xf) << 20)
+
+/*
+ * Timing Parameter 2 Register
+ */
+#define FTSDMC021_TP2_REF_INTV(x)	((x) & 0xffff)	/* Refresh interval */
+/* b(16:19) - Initial Refresh Times */
+#define FTSDMC021_TP2_INI_REFT(x)	(((x) & 0xf) << 16)
+/* b(20:23) - Initial Pre-Charge Times */
+#define FTSDMC021_TP2_INI_PREC(x)	(((x) & 0xf) << 20)
+
+/*
+ * SDRAM Configuration Register 1
+ */
+#define FTSDMC021_CR1_BNKSIZE(x)	((x) & 0xf)		/* Bank Size  */
+#define FTSDMC021_CR1_MBW(x)		(((x) & 0x3) << 4)	/* Bus Width  */
+#define FTSDMC021_CR1_DSZ(x)		(((x) & 0x7) << 8)	/* SDRAM Size */
+#define FTSDMC021_CR1_DDW(x)		(((x) & 0x3) << 12)	/* Data Width */
+/* b(16) MA2T: Double Memory Address Cycle Enable */
+#define FTSDMC021_CR1_MA2T(x)		(1 << 16)
+/* The value of b(0:3)CR1: 1M-512M, must be power of 2 */
+#define FTSDMC021_BANK_SIZE(x)		(ffs(x) - 1)
+
+/*
+ * Configuration Register 2
+ */
+#define FTSDMC021_CR2_SREF	(1 << 0)	/* Self-Refresh Mode */
+#define FTSDMC021_CR2_PWDN	(1 << 1)	/* Power Down Operation Mode */
+#define FTSDMC021_CR2_ISMR	(1 << 2)	/* Start Set-Mode-Register */
+#define FTSDMC021_CR2_IREF	(1 << 3)	/* Init Refresh Start Flag */
+#define FTSDMC021_CR2_IPREC	(1 << 4)	/* Init Pre-Charge Start Flag */
+#define FTSDMC021_CR2_REFTYPE	(1 << 5)
+
+/*
+ * SDRAM External Bank Base/Size Register
+ */
+#define FTSDMC021_BANK_ENABLE		(1 << 12)
+
+/* 12-bit base address of external bank.
+ * Default value is 0x800.
+ * The 12-bit equals to the haddr[31:20] of AHB address bus. */
+#define FTSDMC021_BANK_BASE(x)		((x) & 0xfff)
+
+/*
+ * Read Arbitration Grant Window Register
+ */
+#define FTSDMC021_RAGR_CH1GW(x)		(((x) & 0xff) << 0)
+#define FTSDMC021_RAGR_CH2GW(x)		(((x) & 0xff) << 4)
+#define FTSDMC021_RAGR_CH3GW(x)		(((x) & 0xff) << 8)
+#define FTSDMC021_RAGR_CH4GW(x)		(((x) & 0xff) << 12)
+#define FTSDMC021_RAGR_CH5GW(x)		(((x) & 0xff) << 16)
+#define FTSDMC021_RAGR_CH6GW(x)		(((x) & 0xff) << 20)
+#define FTSDMC021_RAGR_CH7GW(x)		(((x) & 0xff) << 24)
+#define FTSDMC021_RAGR_CH8GW(x)		(((x) & 0xff) << 28)
+
+/*
+ * Flush Request Register
+ */
+#define FTSDMC021_FRR_FLUSHCHN(x)	(((x) & 0x7) << 0)
+#define FTSDMC021_FRR_FLUSHCMPLT	(1 << 3)	/* Flush Req Flag */
+
+/*
+ * External Bus Interface Support Register (EBISR)
+ */
+#define FTSDMC021_EBISR_MR(x)		((x) & 0xfff)	/* Far-end mode	*/
+#define FTSDMC021_EBISR_PRSMR		(1 << 12)	/* Pre-SMR	*/
+#define FTSDMC021_EBISR_POPREC		(1 << 13)
+#define FTSDMC021_EBISR_POSMR		(1 << 14)	/* Post-SMR	*/
+
+/*
+ * Controller Revision Register (CRR, Read Only)
+ */
+#define FTSDMC021_CRR_REV_VER		(((x) >> 0) & 0xff)
+#define FTSDMC021_CRR_MINOR_VER		(((x) >> 8) & 0xff)
+#define FTSDMC021_CRR_MAJOR_VER		(((x) >> 16) & 0xff)
+
+/*
+ * Controller Feature Register (CFR, Read Only)
+ */
+#define FTSDMC021_CFR_EBNK		(((x) >> 0) & 0xf)
+#define FTSDMC021_CFR_CHN		(((x) >> 8) & 0xf)
+#define FTSDMC021_CFR_EBI		(((x) >> 16) & 0x1)
+#define FTSDMC021_CFR_CH1_FDEPTH	(((x) >> 24) & 0x1)
+#define FTSDMC021_CFR_CH2_FDEPTH	(((x) >> 25) & 0x1)
+#define FTSDMC021_CFR_CH3_FDEPTH	(((x) >> 26) & 0x1)
+#define FTSDMC021_CFR_CH4_FDEPTH	(((x) >> 27) & 0x1)
+#define FTSDMC021_CFR_CH5_FDEPTH	(((x) >> 28) & 0x1)
+#define FTSDMC021_CFR_CH6_FDEPTH	(((x) >> 29) & 0x1)
+#define FTSDMC021_CFR_CH7_FDEPTH	(((x) >> 30) & 0x1)
+#define FTSDMC021_CFR_CH8_FDEPTH	(((x) >> 31) & 0x1)
+
+#endif	/* __FTSDMC021_H */

Signature · 1 line

1.7.3.5

Wolfgang Denk

Applied

2011-05-12 21:25 UTC #27 lore raw

PATCH v5 2/2 ftsdmc021: add register definitions of ftsdmc021

Dear Macpaul Lin,

Quoted 16 lines · In message <[email protected]> you wrote:

Support registers definitions of ftsdmc021 SDRAM controller.
Signed-off-by Macpaul Lin <[email protected]>
---
Changes for v2:
- Add __ASSEMBLY__ protecton to register offset for supporting lowlevel_init
Changes for v3:
- Patch: no change. Changed a mail server to resend this patch
Changes for v4:
- Cleanup.
- Replace lines over 80 chararters with proper statement.
- Add some bit-field description about important registers.
- Replace the define of constant which is power of 2 to (ffs(x - 1))
Changes for v5:
- Replace all CAPS variable into lower case.

Quoted 3 lines

 include/faraday/ftsdmc021.h |  151 +++++++++++++++++++++++++++++++++++++++++++
 1 files changed, 151 insertions(+), 0 deletions(-)
 create mode 100644 include/faraday/ftsdmc021.h

Applied, thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Let the programmers be many and the managers few -- then all will  be
productive.               -- Geoffrey James, "The Tao of Programming"