Use chained handler entry/exit functions in platform code

This patch updates the Tegra gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

This is required for the GIC to move to fasteoi interrupt handling.

Cc Colin Cross <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
?arch/arm/mach-tegra/gpio.c | ? ?9 ++++++--- ?arch/arm/mach-tegra/irq.c ?| ? 12 ++++++------ ?2 files changed, 12 insertions(+), 9 deletions(-)

arch/arm/mach-tegra/gpio.c +0 -0

index 76a3f65..494e28f 100644
@@ -24,6 +24,8 @@

?#include <linux/io.h>
?#include <linux/gpio.h>

arch/arm/mach-tegra/gpio.c +2 -0

+#include <asm/mach/irq.h>
+

?#include <mach/iomap.h>
?#include <mach/suspend.h>

arch/arm/mach-tegra/gpio.c +2 -1

@@ -221,8 +223,9 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 ? ? ? ?int port;
 ? ? ? ?int pin;
 ? ? ? ?int unmasked = 0;
+ ? ? ? struct irq_chip *chip = irq_desc_get_chip(desc);
 
- ? ? ? desc->irq_data.chip->irq_ack(&desc->irq_data);
+ ? ? ? chained_irq_enter(chip, desc);
 
 ? ? ? ?bank = irq_get_handler_data(irq);
 

@@ -241,7 +244,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)

? ? ? ? ? ? ? ? ? ? ? ? */
? ? ? ? ? ? ? ? ? ? ? ?if (lvl & (0x100 << pin)) {
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unmasked = 1;
- ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? chained_irq_exit(chip, desc);
? ? ? ? ? ? ? ? ? ? ? ?}

? ? ? ? ? ? ? ? ? ? ? ?generic_handle_irq(gpio_to_irq(gpio + pin));

arch/arm/mach-tegra/gpio.c +1 -1

@@ -249,7 +252,7 @@ static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 ? ? ? ?}
 
 ? ? ? ?if (!unmasked)
- ? ? ? ? ? ? ? desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ ? ? ? ? ? ? ? chained_irq_exit(chip, desc);
 
 ?}
 

arch/arm/mach-tegra/irq.c +1 -1

index 4330d89..2424a3b 100644
@@ -48,7 +48,7 @@ static u32 tegra_lp0_wake_level_any;
 
 ?static void (*tegra_gic_mask_irq)(struct irq_data *d);
 ?static void (*tegra_gic_unmask_irq)(struct irq_data *d);
-static void (*tegra_gic_ack_irq)(struct irq_data *d);
+static void (*tegra_gic_eoi_irq)(struct irq_data *d);
 

?/* ensures that sufficient time is passed for a register write to ?* serialize into the 32KHz domain */

arch/arm/mach-tegra/irq.c +4 -4

@@ -113,10 +113,10 @@ static void tegra_unmask(struct irq_data *d)
 ? ? ? ?tegra_legacy_unmask_irq(d->irq);
 ?}
 
-static void tegra_ack(struct irq_data *d)
+static void tegra_eoi(struct irq_data *d)
 ?{
 ? ? ? ?tegra_legacy_force_irq_clr(d->irq);
- ? ? ? tegra_gic_ack_irq(d);
+ ? ? ? tegra_gic_eoi_irq(d);
 ?}
 
 ?static int tegra_retrigger(struct irq_data *d)

@@ -127,7 +127,7 @@ static int tegra_retrigger(struct irq_data *d)
 
 ?static struct irq_chip tegra_irq = {
 ? ? ? ?.name ? ? ? ? ? ? ? ? ? = "PPI",
- ? ? ? .irq_ack ? ? ? ? ? ? ? ?= tegra_ack,
+ ? ? ? .irq_eoi ? ? ? ? ? ? ? ?= tegra_eoi,
 ? ? ? ?.irq_mask ? ? ? ? ? ? ? = tegra_mask,
 ? ? ? ?.irq_unmask ? ? ? ? ? ? = tegra_unmask,
 ? ? ? ?.irq_retrigger ? ? ? ? ?= tegra_retrigger,

@@ -147,14 +147,14 @@ void __init tegra_init_irq(void)
 ? ? ? ?gic = irq_get_chip(29);
 ? ? ? ?tegra_gic_unmask_irq = gic->irq_unmask;
 ? ? ? ?tegra_gic_mask_irq = gic->irq_mask;
- ? ? ? tegra_gic_ack_irq = gic->irq_ack;
+ ? ? ? tegra_gic_eoi_irq = gic->irq_eoi;

?#ifdef CONFIG_SMP
? ? ? ?tegra_irq.irq_set_affinity = gic->irq_set_affinity; ?#endif

? ? ? ?for (i = 0; i < INT_MAIN_NR; i++) {
? ? ? ? ? ? ? ?irq = INT_PRI_BASE + i;
- ? ? ? ? ? ? ? irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
+ ? ? ? ? ? ? ? irq_set_chip_and_handler(irq, &tegra_irq, handle_fasteoi_irq); ? ? ? ? ? ? ? ?set_irq_flags(irq, IRQF_VALID);
? ? ? ?}
?}
--
1.7.0.4

Quoted 12 lines · Will Deacon

This patch updates the Tegra gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

This is required for the GIC to move to fasteoi interrupt handling.

Cc Colin Cross <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm/mach-tegra/gpio.c |    9 ++++++---
 arch/arm/mach-tegra/irq.c  |   12 ++++++------
 2 files changed, 12 insertions(+), 9 deletions(-)

This version of the patch contains changes to gpio.c and irq.c. If you drop the irq.c changes (which I will fix in my upcoming patch),

Acked-by Colin Cross <[email protected]>

This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Abhijeet Dharmapurikar <[email protected]>

Signed-off-by Will Deacon <[email protected]>

Quoted 6 lines · Will Deacon

This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Abhijeet Dharmapurikar <[email protected]>

Signed-off-by Will Deacon <[email protected]>

I'm okay acking this as long as Abhijeet is ok with it.

This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Abhijeet Dharmapurikar <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm/mach-msm/gpio-v2.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

arch/arm/mach-msm/gpio-v2.c +6 -1

index 56a964e..cc9c4fd 100644
@@ -27,6 +27,9 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
+
+#include <asm/mach/irq.h>
+
 #include <mach/msm_iomap.h>
 #include "gpiomux.h"
 

@@ -309,8 +312,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
  */
 static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
-	struct irq_data *data = irq_desc_get_irq_data(desc);
 	unsigned long i;
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+
+	chained_irq_enter(chip, desc);
 
 	for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
 	     i < NR_GPIO_IRQS;

Quoted 9 lines · Will Deacon

This patch updates the MSM gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Abhijeet Dharmapurikar <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm/mach-msm/gpio-v2.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)

Reviewed-by Abhijeet Dharmapurikar <[email protected]>

Tested-by Abhijeet Dharmapurikar <[email protected]>

This patch updates the Nomadik gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Rabin Vincent <[email protected]>

Signed-off-by Will Deacon <[email protected]>

+#include <asm/mach/irq.h>

- ? ? ? if (host_chip->irq_mask_ack)
- ? ? ? ? ? ? ? host_chip->irq_mask_ack(&desc->irq_data);
- ? ? ? else {
- ? ? ? ? ? ? ? host_chip->irq_mask(&desc->irq_data);
- ? ? ? ? ? ? ? if (host_chip->irq_ack)
- ? ? ? ? ? ? ? ? ? ? ? host_chip->irq_ack(&desc->irq_data);
- ? ? ? }
+ ? ? ? chained_irq_enter(host_chip, desc);

- ? ? ? host_chip->irq_unmask(&desc->irq_data);
+ ? ? ? chained_irq_exit(host_chip, desc);

2011/4/12 Will Deacon <[email protected]>:

Quoted 6 lines

This patch updates the Nomadik gpio chained IRQ handler to use the chained IRQ enter/exit functions in order to function correctly on primary controllers with different methods of flow control.

Cc Rabin Vincent <[email protected]>

Signed-off-by Will Deacon <[email protected]>

Acked-by Linus Walleij <[email protected]>

BUT I want it to go through Grants gpio tree. The reason is that I plan to consolidate this driver into drivers/gpio/* and I don't want collisions in merges.

And wait:

Quoted 10 lines

arch/arm/plat-nomadik/gpio.c +2 -7

+#include <asm/mach/irq.h>
 
-       if (host_chip->irq_mask_ack)
-               host_chip->irq_mask_ack(&desc->irq_data);
-       else {
-               host_chip->irq_mask(&desc->irq_data);
-               if (host_chip->irq_ack)
-                       host_chip->irq_ack(&desc->irq_data);
-       }
+       chained_irq_enter(host_chip, desc);

(...)

arch/arm/plat-nomadik/gpio.c static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, · line 697

Quoted 2 lines

arch/arm/plat-nomadik/gpio.c +1 -1

-       host_chip->irq_unmask(&desc->irq_data);
+       chained_irq_exit(host_chip, desc);

This looks an awful lot like this from drivers/gpio/pl061.c:

desc->irq_data.chip->irq_ack(&desc->irq_data);
(...)
desc->irq_data.chip->irq_unmask(&desc->irq_data);

It gets me wondering what the proper way is to do this. Isn't the proper place for chained_irq_[enter|exit]* in include/linux/irq.h rather? It does not really look machine or arch specific, is it, really?

Quoted 3 lines

BUT I want it to go through Grants gpio tree. The reason is that I plan to consolidate this driver into drivers/gpio/* and I don't want collisions in merges.

Ok. Will Grant just pick it up when he's happy with it?

2011/4/18 Will Deacon <[email protected]>:

Quoted 5 lines

Quoted 3 lines

BUT I want it to go through Grants gpio tree. The reason is that I plan to consolidate this driver into drivers/gpio/* and I don't want collisions in merges.

Ok. Will Grant just pick it up when he's happy with it?

If not picked up, I'll queue it on the top of my patch series when moving it to drivers/gpio...

Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Cc Abhijeet Dharmapurikar <[email protected]>

Cc Russell King - ARM Linux <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

---
 arch/arm/common/gic.c |   32 ++++++++++++++++----------------
 1 files changed, 16 insertions(+), 16 deletions(-)

arch/arm/common/gic.c +15 -15

index f70ec7d..e9c2ff8 100644
@@ -49,7 +49,7 @@ struct gic_chip_data {
  * Default make them NULL.
  */
 struct irq_chip gic_arch_extn = {
-	.irq_ack	= NULL,
+	.irq_eoi	= NULL,
 	.irq_mask	= NULL,
 	.irq_unmask	= NULL,
 	.irq_retrigger	= NULL,

@@ -84,15 +84,6 @@ static inline unsigned int gic_irq(struct irq_data *d)
 /*
  * Routines to acknowledge, disable and enable interrupts
  */
-static void gic_ack_irq(struct irq_data *d)
-{
-	spin_lock(&irq_controller_lock);
-	if (gic_arch_extn.irq_ack)
-		gic_arch_extn.irq_ack(d);
-	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
-	spin_unlock(&irq_controller_lock);
-}
-
 static void gic_mask_irq(struct irq_data *d)
 {
 	u32 mask = 1 << (d->irq % 32);

@@ -115,6 +106,17 @@ static void gic_unmask_irq(struct irq_data *d)
 	spin_unlock(&irq_controller_lock);
 }
 
+static void gic_eoi_irq(struct irq_data *d)
+{
+	if (gic_arch_extn.irq_eoi) {
+		spin_lock(&irq_controller_lock);
+		gic_arch_extn.irq_eoi(d);
+		spin_unlock(&irq_controller_lock);
+	}
+
+	writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
 static int gic_set_type(struct irq_data *d, unsigned int type)
 {
 	void __iomem *base = gic_dist_base(d);

@@ -218,8 +220,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 	unsigned int cascade_irq, gic_irq;
 	unsigned long status;
 
-	/* primary controller ack'ing */
-	chip->irq_ack(&desc->irq_data);
+	chained_irq_enter(chip, desc);
 
 	spin_lock(&irq_controller_lock);
 	status = readl(chip_data->cpu_base + GIC_CPU_INTACK);

@@ -236,15 +237,14 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 		generic_handle_irq(cascade_irq);
 
  out:
-	/* primary controller unmasking */
-	chip->irq_unmask(&desc->irq_data);
+	chained_irq_exit(chip, desc);
 }
 
 static struct irq_chip gic_chip = {
 	.name			= "GIC",
-	.irq_ack		= gic_ack_irq,
 	.irq_mask		= gic_mask_irq,
 	.irq_unmask		= gic_unmask_irq,
+	.irq_eoi		= gic_eoi_irq,
 	.irq_set_type		= gic_set_type,
 	.irq_retrigger		= gic_retrigger,
 #ifdef CONFIG_SMP

Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Cc Abhijeet Dharmapurikar<[email protected]>

Cc Russell King - ARM Linux<[email protected]>

Acked-by Catalin Marinas<[email protected]>

Signed-off-by Will Deacon<[email protected]>

---

Quoted 20 lines · Will Deacon

Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Quoted 5 lines

Cc Abhijeet Dharmapurikar<[email protected]>

Cc Russell King - ARM Linux<[email protected]>

Acked-by Catalin Marinas<[email protected]>

Signed-off-by Will Deacon<[email protected]>

---

Tested with OMAP4.

Acked-by Santosh Shilimkar <[email protected]>

Tested-by Santosh Shilimkar <[email protected]>

Hi Santosh,

Quoted 26 lines · Santosh Shilimkar

Quoted 25 lines · Will Deacon

Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Cc Abhijeet Dharmapurikar<[email protected]>

Cc Russell King - ARM Linux<[email protected]>

Acked-by Catalin Marinas<[email protected]>

Signed-off-by Will Deacon<[email protected]>

---

Quoted 3 lines

Tested with OMAP4.

Acked-by Santosh Shilimkar<[email protected]>

Tested-by Santosh Shilimkar<[email protected]>

Cheers for this. I'll add this and the tags for the OMAP-specific patch (for some reason you dropped the list when you replied with your Ack).

Currently, the gic uses handle_level_irq for handling SPIs (Shared Peripheral Interrupts), requiring active interrupts to be masked at the distributor level during IRQ handling.

On a virtualised system, only the CPU interfaces are virtualised in hardware. Accesses to the distributor must be trapped by the hypervisor, adding latency to the critical interrupt path in Linux.

This patch modifies the GIC code to use handle_fasteoi_irq for handling interrupts, which only requires us to signal EOI to the CPU interface when handling is complete. Cascaded IRQ handling is also updated to use the chained IRQ enter/exit functions to honour the flow control of the parent chip.

Note that commit 846afbd1 ("GIC: Dont disable INT in ack callback") broke cascading interrupts by forgetting to add IRQ masking. This is no longer an issue because the unmask call is now unnecessary.

Tested on Versatile Express and Realview EB (1176 w/ cascaded GICs).

Cc Abhijeet Dharmapurikar <[email protected]>

Cc Russell King - ARM Linux <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

Quoted 4 lines

Cc Abhijeet Dharmapurikar <[email protected]>

Cc Russell King - ARM Linux <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

After further testing, I'm having a problem with this patch, although I think its more of a core issue than the fault of this patch. One of my interrupts is getting stuck with the PENDING flag set, and preventing suspend. The flow that triggers this is:

level triggered irq
handle_fasteoi_irq
handle_irq_event
isr
disable_irq_nosync
schedule_work (because it takes a sleeping i2c transaction to
deassert the irq pin)

irq_eoi
same irq
handle_fasteoi_irq
mark irq pending
mask_irq
work function
causes level triggered irq to go low
enable_irq
unmask_irq
check_irq_resend (returns immediately)

At this point, the irq is unmasked, but not being asserted, and marked as pending. check_irq_resend doesn't clear the pending flag for level triggered interrupts, so the pending flag will stay set until the next time the interrupt occurs.

Should handle_fasteoi_irq mask the interrupt before eoi if it was disabled by the interrupt handler? Otherwise, every level triggered interrupt that is not deasserted by the interrupt handler will interrupt the cpu twice. There is still the case where a driver

disables the irq, the interrupt goes high, then goes low again before enable_irq is called.

Quoted 10 lines · Colin Cross

Quoted 4 lines

Cc Abhijeet Dharmapurikar <[email protected]>

Cc Russell King - ARM Linux <[email protected]>

Acked-by Catalin Marinas <[email protected]>

Signed-off-by Will Deacon <[email protected]>

After further testing, I'm having a problem with this patch, although I think its more of a core issue than the fault of this patch. ?One of my interrupts is getting stuck with the PENDING flag set, and preventing suspend. ?The flow that triggers this is:

Quoted 7 lines

level triggered irq
?handle_fasteoi_irq
? handle_irq_event
? ?isr
? ? disable_irq_nosync
? ? schedule_work (because it takes a sleeping i2c transaction to deassert the irq pin)

If you'd use a threaded irq handler the IRQ_ONESHOT mechanism would handle that problem for you. It masks the irq line before calling the handler and unmask happens after the threaded handler has run.

disable_irq_nosync from an interrupt handler plus scheduling work is the historic "threaded" interrupt handler mechanism. It's kinda murky nowadays due to the lazy irq disable mechanism.

Quoted 11 lines

? ?irq_eoi
same irq
?handle_fasteoi_irq
? mark irq pending
? mask_irq
work function
?causes level triggered irq to go low
?enable_irq
? unmask_irq
? check_irq_resend (returns immediately)

Quoted 4 lines

At this point, the irq is unmasked, but not being asserted, and marked as pending. ?check_irq_resend doesn't clear the pending flag for level triggered interrupts, so the pending flag will stay set until the next time the interrupt occurs.

Yes, that should be cleared unconditionally in check_irq_resend.

Quoted 4 lines

Should handle_fasteoi_irq mask the interrupt before eoi if it was disabled by the interrupt handler? ?Otherwise, every level triggered interrupt that is not deasserted by the interrupt handler will interrupt the cpu twice. ?There is still the case where a driver

No, we should stop doing the disable_irq_nosync from handlers and use threaded interrupts instead.

Quoted 2 lines

disables the irq, the interrupt goes high, then goes low again before enable_irq is called.

So what you're saying is:

irq ____ ? ? ? ? ? ? ? ? ?_______
? ? ? ?|________________| ? ? ? |_____________________

? ? ? ? ? ?| ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?|
? ? ? ? ISR/mask/eoi ? ? ? ? ? ? ? ?enable_irq/unmask

So after the unmask the asserted new interrupt is not delivered? That's not a software problem :)