at91: factorize soc init and switch to early platform
Subsystems (6)
cover at91: factorize soc init and switch to early platform
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
The following changes since commit b96406f91da18e62afe7f78ef3ef4f5804df6d2a:
clkdev: add support to lookup for early platform device (2011-04-26 01:10:47 +0800)
are available in the git repository at:
et ..BRANCH.NOT.VERIFIED..
Jean-Christophe PLAGNIOL-VILLARD (13):
at91rm9200: introduce at91rm9200_set_type to specficy cpu package
at91: introduce commom AT91_BASE_SYS
at91: factorize at91 interrupts init to soc
at91: use structure to store the current soc
at91: switch to CLKDEV_LOOKUP
at91: switch gpio to early platfrom device
at91: move gpio to drivers/gpio
at91: switch pit timer to early platform devices
at91: switch st timer to early platform devices
at91: move pit timer to drivers/clocksource
at91: move st timer to drivers/clocksource
at91: move register clocks to soc generic init
at91: move clock subsystem init to soc generic init
Nico Erfurth (1):
at91: merge board usb-a9260 and usb-a9263 together
MAINTAINERS | 2 +
arch/arm/Kconfig | 1 +
arch/arm/mach-at91/Kconfig | 8 +
arch/arm/mach-at91/Makefile | 26 +-
arch/arm/mach-at91/at572d940hf.c | 124 +++++---
arch/arm/mach-at91/at572d940hf_devices.c | 22 +-
arch/arm/mach-at91/at91cap9.c | 125 +++++---
arch/arm/mach-at91/at91cap9_devices.c | 28 +-
arch/arm/mach-at91/at91rm9200.c | 121 +++++---
arch/arm/mach-at91/at91rm9200_devices.c | 28 +-
arch/arm/mach-at91/at91rm9200_time.c | 209 ------------
arch/arm/mach-at91/at91sam9260.c | 116 +++++---
arch/arm/mach-at91/at91sam9260_devices.c | 31 +--
arch/arm/mach-at91/at91sam9261.c | 119 +++++---
arch/arm/mach-at91/at91sam9261_devices.c | 26 +-
arch/arm/mach-at91/at91sam9263.c | 125 +++++---
arch/arm/mach-at91/at91sam9263_devices.c | 24 +-
arch/arm/mach-at91/at91sam926x_time.c | 188 -----------
arch/arm/mach-at91/at91sam9g45.c | 154 ++++++----
arch/arm/mach-at91/at91sam9g45_devices.c | 31 +--
arch/arm/mach-at91/at91sam9rl.c | 121 +++++---
arch/arm/mach-at91/at91sam9rl_devices.c | 27 +-
arch/arm/mach-at91/at91x40.c | 5 -
arch/arm/mach-at91/board-1arm.c | 10 +-
arch/arm/mach-at91/board-afeb-9260v1.c | 6 +-
arch/arm/mach-at91/board-at572d940hf_ek.c | 6 +-
arch/arm/mach-at91/board-cam60.c | 6 +-
arch/arm/mach-at91/board-cap9adk.c | 6 +-
arch/arm/mach-at91/board-carmeva.c | 6 +-
arch/arm/mach-at91/board-cpu9krea.c | 6 +-
arch/arm/mach-at91/board-cpuat91.c | 10 +-
arch/arm/mach-at91/board-csb337.c | 6 +-
arch/arm/mach-at91/board-csb637.c | 6 +-
arch/arm/mach-at91/board-eb9200.c | 6 +-
arch/arm/mach-at91/board-ecbat91.c | 10 +-
arch/arm/mach-at91/board-eco920.c | 11 +-
arch/arm/mach-at91/board-flexibity.c | 6 +-
arch/arm/mach-at91/board-foxg20.c | 6 +-
arch/arm/mach-at91/board-gsia18s.c | 4 +-
arch/arm/mach-at91/board-kafa.c | 10 +-
arch/arm/mach-at91/board-kb9202.c | 11 +-
arch/arm/mach-at91/board-neocore926.c | 6 +-
arch/arm/mach-at91/board-pcontrol-g20.c | 4 +-
arch/arm/mach-at91/board-picotux200.c | 6 +-
arch/arm/mach-at91/board-qil-a9260.c | 6 +-
arch/arm/mach-at91/board-rm9200dk.c | 6 +-
arch/arm/mach-at91/board-rm9200ek.c | 6 +-
arch/arm/mach-at91/board-sam9-l9260.c | 6 +-
arch/arm/mach-at91/board-sam9260ek.c | 6 +-
arch/arm/mach-at91/board-sam9261ek.c | 6 +-
arch/arm/mach-at91/board-sam9263ek.c | 6 +-
arch/arm/mach-at91/board-sam9g20ek.c | 8 +-
arch/arm/mach-at91/board-sam9m10g45ek.c | 6 +-
arch/arm/mach-at91/board-sam9rlek.c | 6 +-
arch/arm/mach-at91/board-snapper9260.c | 6 +-
arch/arm/mach-at91/board-stamp9g20.c | 8 +-
arch/arm/mach-at91/board-usb-a9260.c | 236 --------------
.../{board-usb-a9263.c => board-usb-a926x.c} | 62 +++-
arch/arm/mach-at91/board-yl-9200.c | 10 +-
arch/arm/mach-at91/clock.c | 54 +---
arch/arm/mach-at91/clock.h | 25 ++-
arch/arm/mach-at91/cpu.h | 181 +++++++++++
arch/arm/mach-at91/devices.c | 15 +
arch/arm/mach-at91/devices.h | 55 ++++
arch/arm/mach-at91/generic.h | 41 +--
arch/arm/mach-at91/include/mach/at572d940hf.h | 1 -
arch/arm/mach-at91/include/mach/at91_pit.h | 8 +-
arch/arm/mach-at91/include/mach/at91_st.h | 20 +-
arch/arm/mach-at91/include/mach/at91cap9.h | 1 -
arch/arm/mach-at91/include/mach/at91rm9200.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9260.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9261.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9263.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 -
arch/arm/mach-at91/include/mach/at91sam9rl.h | 1 -
arch/arm/mach-at91/include/mach/clkdev.h | 7 +
arch/arm/mach-at91/include/mach/cpu.h | 180 ++++-------
arch/arm/mach-at91/include/mach/hardware.h | 14 +
arch/arm/mach-at91/soc.c | 281 +++++++++++++++++
arch/arm/mach-at91/soc.h | 31 ++
drivers/clocksource/Makefile | 2 +
drivers/clocksource/at91_pit.c | 333 ++++++++++++++++++++
drivers/gpio/Makefile | 1 +
.../mach-at91/gpio.c => drivers/gpio/at91_gpio.c | 78 +++--
84 files changed, 2078 insertions(+), 1449 deletions(-)
delete mode 100644 arch/arm/mach-at91/at91rm9200_time.c
delete mode 100644 arch/arm/mach-at91/at91sam926x_time.c
delete mode 100644 arch/arm/mach-at91/board-usb-a9260.c
rename arch/arm/mach-at91/{board-usb-a9263.c => board-usb-a926x.c} (83%)
create mode 100644 arch/arm/mach-at91/cpu.h
create mode 100644 arch/arm/mach-at91/devices.c
create mode 100644 arch/arm/mach-at91/devices.h
create mode 100644 arch/arm/mach-at91/include/mach/clkdev.h
create mode 100644 arch/arm/mach-at91/soc.c
create mode 100644 arch/arm/mach-at91/soc.h
create mode 100644 drivers/clocksource/at91_pit.c
rename arch/arm/mach-at91/gpio.c => drivers/gpio/at91_gpio.c (90%)Best Regards,
J.
PATCH 1/14 at91rm9200: introduce at91rm9200_set_type to specficy cpu package
as we can not detect it
by defaut the type will be bga
introduce cpu_is_at91rm9200_bga and cpu_is_at91rm9200_pqfp
--- arch/arm/mach-at91/at91rm9200.c | 13 +++++++++++-- arch/arm/mach-at91/board-1arm.c | 6 +++++- arch/arm/mach-at91/board-carmeva.c | 2 +- arch/arm/mach-at91/board-cpuat91.c | 6 +++++- arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 2 +- arch/arm/mach-at91/board-eb9200.c | 2 +- arch/arm/mach-at91/board-ecbat91.c | 6 +++++- arch/arm/mach-at91/board-eco920.c | 7 ++++++- arch/arm/mach-at91/board-kafa.c | 6 +++++- arch/arm/mach-at91/board-kb9202.c | 7 +++++-- arch/arm/mach-at91/board-picotux200.c | 2 +- arch/arm/mach-at91/board-rm9200dk.c | 2 +- arch/arm/mach-at91/board-rm9200ek.c | 2 +- arch/arm/mach-at91/board-yl-9200.c | 6 +++++- arch/arm/mach-at91/generic.h | 3 ++- arch/arm/mach-at91/include/mach/cpu.h | 7 +++++++ 17 files changed, 63 insertions(+), 18 deletions(-)
arch/arm/mach-at91/at91rm9200.c +11 -2
@@ -18,6 +18,7 @@#include <mach/at91rm9200.h> #include <mach/at91_pmc.h> #include <mach/at91_st.h> +#include <mach/cpu.h> #include "generic.h" #include "clock.h"
@@ -266,11 +267,18 @@ static void at91rm9200_reset(void)at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); } +int rm9200_type; +EXPORT_SYMBOL (rm9200_type); + +void __init at91rm9200_set_type (int type) +{ + rm9200_type = type; +}/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -void __init at91rm9200_initialize (unsigned long main_clock,unsigned short banks) +void __init at91rm9200_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at91rm9200_io_desc,ARRAY_SIZE (at91rm9200_io_desc));
@@ -288,7 +296,8 @@ void __init at91rm9200_initialize(unsigned long main_clock, unsigned short banksat91rm9200_register_clocks ();/* Initialize GPIO subsystem */ -at91_gpio_init (at91rm9200_gpio, banks); +at91_gpio_init (at91rm9200_gpio, +cpu_is_at91rm9200_bga () ?AT91RM9200_BGA :AT91RM9200_PQFP ); }
arch/arm/mach-at91/board-1arm.c +5 -1
@@ -35,14 +35,18 @@#include <mach/board.h> #include <mach/gpio.h> +#include <mach/cpu.h> #include "generic.h" static void __init onearm_map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-carmeva.c +1 -1
@@ -43,7 +43,7 @@static void __init carmeva_map_io (void ) {/* Initialize processor: 20.000 MHz crystal */ -at91rm9200_initialize (20000000 ,AT91RM9200_BGA ); +at91rm9200_initialize (20000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-cpuat91.c +5 -1
@@ -38,6 +38,7 @@#include <mach/board.h> #include <mach/gpio.h> #include <mach/at91rm9200_mc.h> +#include <mach/cpu.h> #include "generic.h"
@@ -52,8 +53,11 @@ static struct gpio_led cpuat91_leds[] = {static void __init cpuat91_map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-csb337.c +1 -1
@@ -46,7 +46,7 @@static void __init csb337_map_io (void ) {/* Initialize processor: 3.6864 MHz crystal */ -at91rm9200_initialize (3686400 ,AT91RM9200_BGA ); +at91rm9200_initialize (3686400 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB0 ,AT91_PIN_PB1 );
arch/arm/mach-at91/board-csb637.c +1 -1
@@ -43,7 +43,7 @@static void __init csb637_map_io (void ) {/* Initialize processor: 3.6864 MHz crystal */ -at91rm9200_initialize (3686400 ,AT91RM9200_BGA ); +at91rm9200_initialize (3686400 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-eb9200.c +1 -1
@@ -43,7 +43,7 @@static void __init eb9200_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_BGA ); +at91rm9200_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-ecbat91.c +5 -1
@@ -38,14 +38,18 @@#include <mach/board.h> #include <mach/gpio.h> +#include <mach/cpu.h> #include "generic.h" static void __init ecb_at91map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PC7 ,AT91_PIN_PC7 );
arch/arm/mach-at91/board-eco920.c +6 -1
@@ -26,11 +26,16 @@#include <mach/board.h> #include <mach/at91rm9200_mc.h> +#include <mach/cpu.h> +#include "generic.h" static void __init eco920_map_io (void ) { -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); + +at91rm9200_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB0 ,AT91_PIN_PB1 );
arch/arm/mach-at91/board-kafa.c +5 -1
@@ -35,14 +35,18 @@#include <mach/board.h> #include <mach/gpio.h> +#include <mach/cpu.h> #include "generic.h" static void __init kafa_map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (18432000 );/* Set up the LEDs */ at91_init_leds (AT91_PIN_PB4 ,AT91_PIN_PB4 );
arch/arm/mach-at91/board-kb9202.c +5 -2
@@ -36,7 +36,7 @@#include <mach/board.h> #include <mach/gpio.h> - +#include <mach/cpu.h> #include <mach/at91rm9200_mc.h> #include "generic.h"
@@ -44,8 +44,11 @@static void __init kb9202_map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 10 MHz crystal */ -at91rm9200_initialize (10000000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (10000000 );/* Set up the LEDs */ at91_init_leds (AT91_PIN_PC19 ,AT91_PIN_PC18 );
arch/arm/mach-at91/board-picotux200.c +1 -1
@@ -46,7 +46,7 @@static void __init picotux200_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_BGA ); +at91rm9200_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-rm9200dk.c +1 -1
@@ -48,7 +48,7 @@static void __init dk_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_BGA ); +at91rm9200_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB2 ,AT91_PIN_PB2 );
arch/arm/mach-at91/board-rm9200ek.c +1 -1
@@ -48,7 +48,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_BGA ); +at91rm9200_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB1 ,AT91_PIN_PB2 );
arch/arm/mach-at91/board-yl-9200.c +5 -1
@@ -45,14 +45,18 @@#include <mach/board.h> #include <mach/gpio.h> #include <mach/at91rm9200_mc.h> +#include <mach/cpu.h> #include "generic.h" static void __init yl9200_map_io (void ) { +/* Set cpu type: PQFP */ +at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); +/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ,AT91RM9200_PQFP ); +at91rm9200_initialize (18432000 );/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ at91_init_leds (AT91_PIN_PB16 ,AT91_PIN_PB17 );
arch/arm/mach-at91/generic.h +2 -1
@@ -9,7 +9,8 @@*/ /* Processors */ -extern void __init at91rm9200_initialize (unsigned long main_clock,unsigned short banks); +extern void __init at91rm9200_set_type (int type); +extern void __init at91rm9200_initialize (unsigned long main_clock);extern void __init at91sam9260_initialize (unsigned long main_clock);extern void __init at91sam9261_initialize (unsigned long main_clock);extern void __init at91sam9263_initialize (unsigned long main_clock);
arch/arm/mach-at91/include/mach/cpu.h +7 -0
@@ -90,9 +90,16 @@ static inline unsigned long at91cap9_rev_identify(void)#endif #ifdef CONFIG_ARCH_AT91RM9200 +extern int rm9200_type; +#define ARCH_REVISON_9200_BGA (0 << 0) +#define ARCH_REVISON_9200_PQFP (1 << 0)#define cpu_is_at91rm9200 () (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#define cpu_is_at91rm9200_bga () (!cpu_is_at91rm9200_pqfp()) +#define cpu_is_at91rm9200_pqfp () (cpu_is_at91rm9200() && rm9200_type & ARCH_REVISON_9200_PQFP)#else #define cpu_is_at91rm9200 () (0) +#define cpu_is_at91rm9200_bga () (0) +#define cpu_is_at91rm9200_pqfp () (0)#endif #ifdef CONFIG_ARCH_AT91SAM9260
Signature · 1 line
1.7.4.1
PATCH 2/14 at91: introduce commom AT91_BASE_SYS
In reply to Jean-Christophe PLAGNIOL-VILLARDon all at91 except rm9200 and x40 have the System Controller start in reallity at 0xffffc000 of 16KiB
on rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting at 0xfffff000
so we will use a common AT91_BASE_SYS at 0xffffc000 of 16KiB and map the same memory space
--- arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/at572d940hf.c | 12 +++--- arch/arm/mach-at91/at91cap9.c | 13 +++--- arch/arm/mach-at91/at91rm9200.c | 13 +++--- arch/arm/mach-at91/at91sam9260.c | 18 +++----- arch/arm/mach-at91/at91sam9261.c | 18 +++----- arch/arm/mach-at91/at91sam9263.c | 13 +++--- arch/arm/mach-at91/at91sam9g45.c | 13 +++--- arch/arm/mach-at91/at91sam9rl.c | 18 +++----- arch/arm/mach-at91/board-1arm.c | 2 +- arch/arm/mach-at91/board-afeb-9260v1.c | 2 +- arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- arch/arm/mach-at91/board-cam60.c | 2 +- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-carmeva.c | 2 +- arch/arm/mach-at91/board-cpu9krea.c | 2 +- arch/arm/mach-at91/board-cpuat91.c | 2 +- arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 2 +- arch/arm/mach-at91/board-eb9200.c | 2 +- arch/arm/mach-at91/board-ecbat91.c | 2 +- arch/arm/mach-at91/board-eco920.c | 2 +- arch/arm/mach-at91/board-flexibity.c | 2 +- arch/arm/mach-at91/board-foxg20.c | 2 +- arch/arm/mach-at91/board-kafa.c | 2 +- arch/arm/mach-at91/board-kb9202.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-picotux200.c | 2 +- arch/arm/mach-at91/board-qil-a9260.c | 2 +- arch/arm/mach-at91/board-rm9200dk.c | 2 +- arch/arm/mach-at91/board-rm9200ek.c | 2 +- arch/arm/mach-at91/board-sam9-l9260.c | 2 +- arch/arm/mach-at91/board-sam9260ek.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 2 +- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9g20ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- arch/arm/mach-at91/board-snapper9260.c | 2 +- arch/arm/mach-at91/board-stamp9g20.c | 2 +- arch/arm/mach-at91/board-usb-a9260.c | 2 +- arch/arm/mach-at91/board-usb-a9263.c | 2 +- arch/arm/mach-at91/board-yl-9200.c | 2 +- arch/arm/mach-at91/generic.h | 9 +---- arch/arm/mach-at91/include/mach/at572d940hf.h | 1 - arch/arm/mach-at91/include/mach/at91cap9.h | 1 - arch/arm/mach-at91/include/mach/at91rm9200.h | 1 - arch/arm/mach-at91/include/mach/at91sam9260.h | 1 - arch/arm/mach-at91/include/mach/at91sam9261.h | 1 - arch/arm/mach-at91/include/mach/at91sam9263.h | 1 - arch/arm/mach-at91/include/mach/at91sam9g45.h | 1 - arch/arm/mach-at91/include/mach/at91sam9rl.h | 1 - arch/arm/mach-at91/include/mach/hardware.h | 14 ++++++ arch/arm/mach-at91/soc.c | 57 +++++++++++++++++++++++++ arch/arm/mach-at91/soc.h | 22 ++++++++++ 55 files changed, 184 insertions(+), 114 deletions(-) create mode 100644 arch/arm/mach-at91/soc.c create mode 100644 arch/arm/mach-at91/soc.h
arch/arm/mach-at91/Makefile +1 -1
@@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o gpio.o +obj-y := irq.o gpio.o soc.o obj-m := obj-n := obj- :=
arch/arm/mach-at91/at572d940hf.c +6 -6
@@ -31,16 +31,12 @@#include <mach/at91_pmc.h> #include <mach/at91_rstc.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at572d940hf_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, { .virtual =AT91_IO_VIRT_BASE -AT572D940HF_SRAM_SIZE , .pfn =__phys_to_pfn (AT572D940HF_SRAM_BASE ), .length =AT572D940HF_SRAM_SIZE ,
@@ -302,7 +298,7 @@ static void at572d940hf_reset(void)* AT572D940HF processor initialization * -------------------------------------------------------------------- */ -void __init at572d940hf_initialize (unsigned long main_clock) +static void __init at572d940hf_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at572d940hf_io_desc,ARRAY_SIZE (at572d940hf_io_desc));
@@ -375,3 +371,7 @@ void __init at572d940hf_init_interrupts(unsigned int priority[NR_AIC_IRQS])at91_gpio_irq_setup (); } +struct at91_soc __initdata at572d940hf_soc = { + .name ="at572d940hf" , + .init = at572d940hf_initialize, +};
arch/arm/mach-at91/at91cap9.c +7 -6
@@ -25,16 +25,12 @@#include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at91cap9_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, { .virtual =AT91_IO_VIRT_BASE -AT91CAP9_SRAM_SIZE , .pfn =__phys_to_pfn (AT91CAP9_SRAM_BASE ), .length =AT91CAP9_SRAM_SIZE ,
@@ -303,7 +299,7 @@ static void at91cap9_poweroff(void)* AT91CAP9 processor initialization * -------------------------------------------------------------------- */ -void __init at91cap9_initialize (unsigned long main_clock) +static void __init at91cap9_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at91cap9_io_desc,ARRAY_SIZE (at91cap9_io_desc));
@@ -381,3 +377,8 @@ void __init at91cap9_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91cap9_soc = { + .name ="at91cap9" , + .init = at91cap9_initialize, +};
arch/arm/mach-at91/at91rm9200.c +7 -6
@@ -20,16 +20,12 @@#include <mach/at91_st.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at91rm9200_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_4K , - .type =MT_DEVICE , - }, { .virtual =AT91_VA_BASE_EMAC , .pfn =__phys_to_pfn (AT91RM9200_BASE_EMAC ), .length =SZ_16K ,
@@ -278,7 +274,7 @@ void __init at91rm9200_set_type(int type)/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -void __init at91rm9200_initialize (unsigned long main_clock) +static void __init at91rm9200_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at91rm9200_io_desc,ARRAY_SIZE (at91rm9200_io_desc));
@@ -354,3 +350,8 @@ void __init at91rm9200_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91rm9200_soc = { + .name ="at91rm9200" , + .init = at91rm9200_initialize, +};
arch/arm/mach-at91/at91sam9260.c +7 -11
@@ -22,18 +22,10 @@#include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9260_io_desc[]__initdata = { - { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - } -}; -static struct map_desc at91sam9260_sram_desc[]__initdata = { { .virtual =AT91_IO_VIRT_BASE -AT91SAM9260_SRAM_SIZE ,
@@ -300,10 +292,9 @@ static void __init at91sam9xe_initialize(void)iotable_init (at91sam9xe_sram_desc,ARRAY_SIZE (at91sam9xe_sram_desc)); } -void __init at91sam9260_initialize (unsigned long main_clock) +static void __init at91sam9260_initialize (unsigned long main_clock) {/* Map peripherals */ -iotable_init (at91sam9260_io_desc,ARRAY_SIZE (at91sam9260_io_desc));if (cpu_is_at91sam9xe ())at91sam9xe_initialize ();
@@ -380,3 +371,8 @@ void __init at91sam9260_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91sam9260_soc = { + .name ="at91sam9260" , + .init = at91sam9260_initialize, +};
arch/arm/mach-at91/at91sam9261.c +7 -11
@@ -22,18 +22,10 @@#include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9261_io_desc[]__initdata = { - { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, -}; -static struct map_desc at91sam9261_sram_desc[]__initdata = { { .virtual =AT91_IO_VIRT_BASE -AT91SAM9261_SRAM_SIZE ,
@@ -267,10 +259,9 @@ static void at91sam9261_poweroff(void)* AT91SAM9261 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9261_initialize (unsigned long main_clock) +static void __init at91sam9261_initialize (unsigned long main_clock) {/* Map peripherals */ -iotable_init (at91sam9261_io_desc,ARRAY_SIZE (at91sam9261_io_desc));if (cpu_is_at91sam9g10 ())iotable_init (at91sam9g10_sram_desc,ARRAY_SIZE (at91sam9g10_sram_desc));
@@ -346,3 +337,8 @@ void __init at91sam9261_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91sam9261_soc = { + .name ="at91sam9261" , + .init = at91sam9261_initialize, +};
arch/arm/mach-at91/at91sam9263.c +7 -6
@@ -21,16 +21,12 @@#include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at91sam9263_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, { .virtual =AT91_IO_VIRT_BASE -AT91SAM9263_SRAM0_SIZE , .pfn =__phys_to_pfn (AT91SAM9263_SRAM0_BASE ), .length =AT91SAM9263_SRAM0_SIZE ,
@@ -279,7 +275,7 @@ static void at91sam9263_poweroff(void)* AT91SAM9263 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9263_initialize (unsigned long main_clock) +static void __init at91sam9263_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at91sam9263_io_desc,ARRAY_SIZE (at91sam9263_io_desc));
@@ -351,3 +347,8 @@ void __init at91sam9263_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91sam9263_soc = { + .name ="at91sam9263" , + .init = at91sam9263_initialize, +};
arch/arm/mach-at91/at91sam9g45.c +7 -6
@@ -22,16 +22,12 @@#include <mach/at91_shdwc.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h" static struct map_desc at91sam9g45_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, { .virtual =AT91_IO_VIRT_BASE -AT91SAM9G45_SRAM_SIZE , .pfn =__phys_to_pfn (AT91SAM9G45_SRAM_BASE ), .length =AT91SAM9G45_SRAM_SIZE ,
@@ -306,7 +302,7 @@ static void at91sam9g45_poweroff(void)* AT91SAM9G45 processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9g45_initialize (unsigned long main_clock) +static void __init at91sam9g45_initialize (unsigned long main_clock) {/* Map peripherals */ iotable_init (at91sam9g45_io_desc,ARRAY_SIZE (at91sam9g45_io_desc));
@@ -378,3 +374,8 @@ void __init at91sam9g45_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91sam9g45_soc = { + .name ="at91sam9g45" , + .init = at91sam9g45_initialize, +};
arch/arm/mach-at91/at91sam9rl.c +7 -11
@@ -21,18 +21,10 @@#include <mach/at91_rstc.h> #include <mach/at91_shdwc.h> +#include "soc.h" #include "generic.h" #include "clock.h" -static struct map_desc at91sam9rl_io_desc[]__initdata = { - { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_16K , - .type =MT_DEVICE , - }, -}; -static struct map_desc at91sam9rl_sram_desc[]__initdata = { { .pfn =__phys_to_pfn (AT91SAM9RL_SRAM_BASE ),
@@ -252,12 +244,11 @@ static void at91sam9rl_poweroff(void)* AT91SAM9RL processor initialization * -------------------------------------------------------------------- */ -void __init at91sam9rl_initialize (unsigned long main_clock) +static void __init at91sam9rl_initialize (unsigned long main_clock) {unsigned long cidr, sram_size;/* Map peripherals */ -iotable_init (at91sam9rl_io_desc,ARRAY_SIZE (at91sam9rl_io_desc)); cidr =at91_sys_read (AT91_DBGU_CIDR );
@@ -343,3 +334,8 @@ void __init at91sam9rl_init_interrupts(unsigned int priority[NR_AIC_IRQS])/* Enable GPIO interrupts */ at91_gpio_irq_setup (); } + +struct at91_soc __initdata at91sam9rl_soc = { + .name ="at91sam9rl" , + .init = at91sam9rl_initialize, +};
arch/arm/mach-at91/board-1arm.c +1 -1
@@ -46,7 +46,7 @@ static void __init onearm_map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-afeb-9260v1.c +1 -1
@@ -51,7 +51,7 @@static void __init afeb9260_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-at572d940hf_ek.c +1 -1
@@ -50,7 +50,7 @@static void __init eb_map_io (void ) {/* Initialize processor: 12.500 MHz crystal */ -at572d940hf_initialize (12000000 ); +at91_initialize (12000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-cam60.c +1 -1
@@ -48,7 +48,7 @@static void __init cam60_map_io (void ) {/* Initialize processor: 10 MHz crystal */ -at91sam9260_initialize (10000000 ); +at91_initialize (10000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-cap9adk.c +1 -1
@@ -53,7 +53,7 @@static void __init cap9adk_map_io (void ) {/* Initialize processor: 12 MHz crystal */ -at91cap9_initialize (12000000 ); +at91_initialize (12000000 );/* Setup the LEDs: USER1 and USER2 LED for cpu/timer... */ at91_init_leds (AT91_PIN_PA10 ,AT91_PIN_PA11 );
arch/arm/mach-at91/board-carmeva.c +1 -1
@@ -43,7 +43,7 @@static void __init carmeva_map_io (void ) {/* Initialize processor: 20.000 MHz crystal */ -at91rm9200_initialize (20000000 ); +at91_initialize (20000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-cpu9krea.c +1 -1
@@ -50,7 +50,7 @@static void __init cpu9krea_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-cpuat91.c +1 -1
@@ -57,7 +57,7 @@ static void __init cpuat91_map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-csb337.c +1 -1
@@ -46,7 +46,7 @@static void __init csb337_map_io (void ) {/* Initialize processor: 3.6864 MHz crystal */ -at91rm9200_initialize (3686400 ); +at91_initialize (3686400 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB0 ,AT91_PIN_PB1 );
arch/arm/mach-at91/board-csb637.c +1 -1
@@ -43,7 +43,7 @@static void __init csb637_map_io (void ) {/* Initialize processor: 3.6864 MHz crystal */ -at91rm9200_initialize (3686400 ); +at91_initialize (3686400 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-eb9200.c +1 -1
@@ -43,7 +43,7 @@static void __init eb9200_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-ecbat91.c +1 -1
@@ -49,7 +49,7 @@ static void __init ecb_at91map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PC7 ,AT91_PIN_PC7 );
arch/arm/mach-at91/board-eco920.c +1 -1
@@ -35,7 +35,7 @@ static void __init eco920_map_io(void)/* Set cpu type: PQFP */ at91rm9200_set_type (ARCH_REVISON_9200_PQFP ); -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB0 ,AT91_PIN_PB1 );
arch/arm/mach-at91/board-flexibity.c +1 -1
@@ -40,7 +40,7 @@static void __init flexibity_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-foxg20.c +1 -1
@@ -60,7 +60,7 @@static void __init foxg20_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-kafa.c +1 -1
@@ -46,7 +46,7 @@ static void __init kafa_map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Set up the LEDs */ at91_init_leds (AT91_PIN_PB4 ,AT91_PIN_PB4 );
arch/arm/mach-at91/board-kb9202.c +1 -1
@@ -48,7 +48,7 @@ static void __init kb9202_map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 10 MHz crystal */ -at91rm9200_initialize (10000000 ); +at91_initialize (10000000 );/* Set up the LEDs */ at91_init_leds (AT91_PIN_PC19 ,AT91_PIN_PC18 );
arch/arm/mach-at91/board-neocore926.c +1 -1
@@ -54,7 +54,7 @@static void __init neocore926_map_io (void ) {/* Initialize processor: 20 MHz crystal */ -at91sam9263_initialize (20000000 ); +at91_initialize (20000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-picotux200.c +1 -1
@@ -46,7 +46,7 @@static void __init picotux200_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-qil-a9260.c +1 -1
@@ -51,7 +51,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 12.000 MHz crystal */ -at91sam9260_initialize (12000000 ); +at91_initialize (12000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-rm9200dk.c +1 -1
@@ -48,7 +48,7 @@static void __init dk_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB2 ,AT91_PIN_PB2 );
arch/arm/mach-at91/board-rm9200ek.c +1 -1
@@ -48,7 +48,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PB1 ,AT91_PIN_PB2 );
arch/arm/mach-at91/board-sam9-l9260.c +1 -1
@@ -47,7 +47,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PA9 ,AT91_PIN_PA6 );
arch/arm/mach-at91/board-sam9260ek.c +1 -1
@@ -53,7 +53,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-sam9261ek.c +1 -1
@@ -57,7 +57,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9261_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs */ at91_init_leds (AT91_PIN_PA13 ,AT91_PIN_PA14 );
arch/arm/mach-at91/board-sam9263ek.c +1 -1
@@ -56,7 +56,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 16.367 MHz crystal */ -at91sam9263_initialize (16367660 ); +at91_initialize (16367660 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-sam9g20ek.c +1 -1
@@ -64,7 +64,7 @@ static int inline ek_have_2mmc(void)static void __init ek_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-sam9m10g45ek.c +1 -1
@@ -50,7 +50,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 12.000 MHz crystal */ -at91sam9g45_initialize (12000000 ); +at91_initialize (12000000 );/* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-sam9rlek.c +1 -1
@@ -41,7 +41,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 12.000 MHz crystal */ -at91sam9rl_initialize (12000000 ); +at91_initialize (12000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-snapper9260.c +1 -1
@@ -42,7 +42,7 @@static void __init snapper9260_map_io (void ) { -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* Debug on ttyS0 */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-stamp9g20.c +1 -1
@@ -35,7 +35,7 @@void __init stamp9g20_map_io (void ) {/* Initialize processor: 18.432 MHz crystal */ -at91sam9260_initialize (18432000 ); +at91_initialize (18432000 );/* DGBU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-usb-a9260.c +1 -1
@@ -51,7 +51,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 12.000 MHz crystal */ -at91sam9260_initialize (12000000 ); +at91_initialize (12000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-usb-a9263.c +1 -1
@@ -50,7 +50,7 @@static void __init ek_map_io (void ) {/* Initialize processor: 12.00 MHz crystal */ -at91sam9263_initialize (12000000 ); +at91_initialize (12000000 );/* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart (0 ,0 ,0 );
arch/arm/mach-at91/board-yl-9200.c +1 -1
@@ -56,7 +56,7 @@ static void __init yl9200_map_io(void)at91rm9200_set_type (ARCH_REVISON_9200_PQFP );/* Initialize processor: 18.432 MHz crystal */ -at91rm9200_initialize (18432000 ); +at91_initialize (18432000 );/* Setup the LEDs D2=PB17 (timer), D3=PB16 (cpu) */ at91_init_leds (AT91_PIN_PB16 ,AT91_PIN_PB17 );
arch/arm/mach-at91/generic.h +1 -8
@@ -10,15 +10,8 @@/* Processors */ extern void __init at91rm9200_set_type (int type); -extern void __init at91rm9200_initialize (unsigned long main_clock); -extern void __init at91sam9260_initialize (unsigned long main_clock); -extern void __init at91sam9261_initialize (unsigned long main_clock); -extern void __init at91sam9263_initialize (unsigned long main_clock); -extern void __init at91sam9rl_initialize (unsigned long main_clock); -extern void __init at91sam9g45_initialize (unsigned long main_clock); +extern void __init at91_initialize (unsigned long main_clock);extern void __init at91x40_initialize (unsigned long main_clock); -extern void __init at91cap9_initialize (unsigned long main_clock); -extern void __init at572d940hf_initialize (unsigned long main_clock);/* Interrupts */ extern void __init at91rm9200_init_interrupts (unsigned int priority[]);
arch/arm/mach-at91/include/mach/at572d940hf.h +0 -1
@@ -83,7 +83,6 @@#define AT572D940HF_BASE_EMAC 0xfffd8000#define AT572D940HF_BASE_CAN0 0xfffdc000#define AT572D940HF_BASE_CAN1 0xfffe0000 -#define AT91_BASE_SYS 0xffffea00/*
arch/arm/mach-at91/include/mach/at91cap9.h +0 -1
@@ -77,7 +77,6 @@#define AT91CAP9_BASE_EMAC 0xfffbc000#define AT91CAP9_BASE_ADC 0xfffc0000#define AT91CAP9_BASE_ISI 0xfffc4000 -#define AT91_BASE_SYS 0xffffe200/* * System Peripherals (offset from AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91rm9200.h +0 -1
@@ -76,7 +76,6 @@#define AT91RM9200_BASE_SSC1 0xfffd4000#define AT91RM9200_BASE_SSC2 0xfffd8000#define AT91RM9200_BASE_SPI 0xfffe0000 -#define AT91_BASE_SYS 0xfffff000/*
arch/arm/mach-at91/include/mach/at91sam9260.h +0 -1
@@ -78,7 +78,6 @@#define AT91SAM9260_BASE_TC4 0xfffdc040#define AT91SAM9260_BASE_TC5 0xfffdc080#define AT91SAM9260_BASE_ADC 0xfffe0000 -#define AT91_BASE_SYS 0xffffe800/* * System Peripherals (offset from AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9261.h +0 -1
@@ -62,7 +62,6 @@#define AT91SAM9261_BASE_SSC2 0xfffc4000#define AT91SAM9261_BASE_SPI0 0xfffc8000#define AT91SAM9261_BASE_SPI1 0xfffcc000 -#define AT91_BASE_SYS 0xffffea00/*
arch/arm/mach-at91/include/mach/at91sam9263.h +0 -1
@@ -72,7 +72,6 @@#define AT91SAM9263_BASE_EMAC 0xfffbc000#define AT91SAM9263_BASE_ISI 0xfffc4000#define AT91SAM9263_BASE_2DGE 0xfffc8000 -#define AT91_BASE_SYS 0xffffe000/* * System Peripherals (offset from AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9g45.h +0 -1
@@ -84,7 +84,6 @@#define AT91SAM9G45_BASE_TC3 0xfffd4000#define AT91SAM9G45_BASE_TC4 0xfffd4040#define AT91SAM9G45_BASE_TC5 0xfffd4080 -#define AT91_BASE_SYS 0xffffe200/* * System Peripherals (offset from AT91_BASE_SYS)
arch/arm/mach-at91/include/mach/at91sam9rl.h +0 -1
@@ -66,7 +66,6 @@#define AT91SAM9RL_BASE_TSC 0xfffd0000#define AT91SAM9RL_BASE_UDPHS 0xfffd4000#define AT91SAM9RL_BASE_AC97C 0xfffd8000 -#define AT91_BASE_SYS 0xffffc000/*
arch/arm/mach-at91/include/mach/hardware.h +14 -0
@@ -16,6 +16,20 @@#include <asm/sizes.h> +#if !defined(CONFIG_ARCH_AT91X40 ) +/* +* on all at91 except rm9200 and x40 have the System Controller start in reallity +* at 0xffffc000 of 16KiB +* +* on rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting +* at 0xfffff000 +* +* so we will use a common AT91_BASE_SYS at 0xffffc000 of 16KiB +* and map the same memory space +*/ +#define AT91_BASE_SYS 0xffffc000 +#endif +#if defined(CONFIG_ARCH_AT91RM9200 )#include <mach/at91rm9200.h> #elif defined(CONFIG_ARCH_AT91SAM9260 ) || defined(CONFIG_ARCH_AT91SAM9G20 )
arch/arm/mach-at91/soc.c new file +57 -0
57 lines not on this page · raw message
arch/arm/mach-at91/soc.h new file +22 -0
@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2007 Atmel Corporation. +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +* +*/ + +struct at91_soc { +char *name; + +void (*init)(unsigned long main_clock); +}; + +extern struct at91_soc at91rm9200_soc; +extern struct at91_soc at91sam9260_soc; +extern struct at91_soc at91sam9261_soc; +extern struct at91_soc at91sam9263_soc; +extern struct at91_soc at91sam9rl_soc; +extern struct at91_soc at91sam9g45_soc; +extern struct at91_soc at91cap9_soc; +extern struct at91_soc at572d940hf_soc;
Signature · 1 line
1.7.4.1
PATCH 2/14 at91: introduce commom AT91_BASE_SYS
Quoted 2 lines · Jean-Christophe PLAGNIOL-VILLARD
on all at91 except rm9200 and x40 have the System Controller start in reallity at
0xffffc000of 16KiB
Hi Jean,
I think this should be reworded as something like:
"On all AT91 variants except the RM9200 and x40 the system controller starts at address 0xffffc000 and has a size of 16KiB."
Quoted 3 lines
on rm9200 it's start at
0xfffe4000of 111KiB with non reserved data starting at0xfffff000
This bit is okay.
Quoted 2 lines
so we will use a common
AT91_BASE_SYSat0xffffc000of 16KiB and map the same memory space
"This patch removes the individual definitions of AT91_BASE_SYS and replaces them with a common version at base 0xfffffc000 and size 16KiB".
<snip>
Quoted 9 lines
arch/arm/mach-at91/at91rm9200.c +1
-0@@ -20,16 +20,12 @@#include <mach/at91_st.h> #include <mach/cpu.h> +#include "soc.h"
arch/arm/mach-at91/at91rm9200.c line 32
Quoted 10 lines
arch/arm/mach-at91/at91rm9200.c +0
-5#include "generic.h" #include "clock.h" static struct map_desc at91rm9200_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_4K , - .type =MT_DEVICE , - }, {
If the RM9200 system controller is not at the same base address as the other variants then how does the common AT91_BASE_SYS work correctly? I can't see an offseting code. What am I missing?
<snip>
Quoted 8 lines
arch/arm/mach-at91/include/mach/hardware.h +0
-0@@ -16,6 +16,20 @@#include <asm/sizes.h>
arch/arm/mach-at91/include/mach/hardware.h line 28
Quoted 10 lines
arch/arm/mach-at91/include/mach/hardware.h +10
-0+#if !defined(CONFIG_ARCH_AT91X40 ) +/* +* on all at91 except rm9200 and x40 have the System Controller start in reallity +* at 0xffffc000 of 16KiB +* +* on rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting +* at 0xfffff000 +* +* so we will use a common AT91_BASE_SYS at 0xffffc000 of 16KiB +* and map the same memory space
Please reword this as suggested for the changelog.
<snip>
Quoted 6 lines
arch/arm/mach-at91/soc.h new file +0
-0
arch/arm/mach-at91/soc.h line 10
Quoted 10 lines
arch/arm/mach-at91/soc.h new file +10
-0@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2007 Atmel Corporation. +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +* +*/ + +struct at91_soc { +char *name;
Should be const. Do we really need the name of the AT91 variant? We could just export the initialize function and get rid of this new struct which would further reduce the line count?
arch/arm/mach-at91/soc.h line 22
Quoted 12 lines
arch/arm/mach-at91/soc.h new file +12
-0+ +void (*init)(unsigned long main_clock); +}; + +extern struct at91_soc at91rm9200_soc; +extern struct at91_soc at91sam9260_soc; +extern struct at91_soc at91sam9261_soc; +extern struct at91_soc at91sam9263_soc; +extern struct at91_soc at91sam9rl_soc; +extern struct at91_soc at91sam9g45_soc; +extern struct at91_soc at91cap9_soc; +extern struct at91_soc at572d940hf_soc;
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 2/14 at91: introduce commom AT91_BASE_SYS
Quoted 12 lines
Quoted 12 lines
arch/arm/mach-at91/at91rm9200.c +1
-0@@ -20,16 +20,12 @@#include <mach/at91_st.h> #include <mach/cpu.h> +#include "soc.h" #include "generic.h" #include "clock.h"
Quoted 11 lines
arch/arm/mach-at91/at91rm9200.c line 32
Quoted 7 lines
arch/arm/mach-at91/at91rm9200.c +0
-5static struct map_desc at91rm9200_io_desc[]__initdata = { { - .virtual =AT91_VA_BASE_SYS , - .pfn =__phys_to_pfn (AT91_BASE_SYS ), - .length =SZ_4K , - .type =MT_DEVICE , - }, {If the RM9200 system controller is not at the same base address as the other variants then how does the common
AT91_BASE_SYSwork correctly? I can't see an offseting code. What am I missing?
you have reserved memory and the then we map it in memory cf hardware.h
Quoted 38 lines
<snip>
Quoted 8 lines
arch/arm/mach-at91/include/mach/hardware.h +0
-0@@ -16,6 +16,20 @@#include <asm/sizes.h> arch/arm/mach-at91/include/mach/hardware.h line 28
Quoted 10 lines
arch/arm/mach-at91/include/mach/hardware.h +10
-0+#if !defined(CONFIG_ARCH_AT91X40 ) +/* +* on all at91 except rm9200 and x40 have the System Controller start in reallity +* at 0xffffc000 of 16KiB +* +* on rm9200 it's start at 0xfffe4000 of 111KiB with non reserved data starting +* at 0xfffff000 +* +* so we will use a common AT91_BASE_SYS at 0xffffc000 of 16KiB +* and map the same memory space Please reword this as suggested for the changelog.
<snip>
Quoted 12 lines
arch/arm/mach-at91/soc.h new file +6
-0@@ -0,0 +1,22 @@ +/* +* Copyright (C) 2007 Atmel Corporation. +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +*
Quoted 8 lines
arch/arm/mach-at91/soc.h line 10
Quoted 4 lines
arch/arm/mach-at91/soc.h new file +4
-0+*/ + +struct at91_soc { +char *name;Should be const. Do we really need the name of the AT91 variant? We could just export the initialize function and get rid of this new struct which would further reduce the line count?
yeah some board can have different soc so print is usefull
I do not want to export 1000 of functions as done today the struct is here for this
Best Regards,
J.
PATCH 3/14 at91: factorize at91 interrupts init to soc
In reply to Jean-Christophe PLAGNIOL-VILLARDthey are the same except the default priority
--- arch/arm/mach-at91/at572d940hf.c | 13 +------------ arch/arm/mach-at91/at91cap9.c | 13 +------------ arch/arm/mach-at91/at91rm9200.c | 13 +------------ arch/arm/mach-at91/at91sam9260.c | 13 +------------ arch/arm/mach-at91/at91sam9261.c | 13 +------------ arch/arm/mach-at91/at91sam9263.c | 13 +------------ arch/arm/mach-at91/at91sam9g45.c | 13 +------------ arch/arm/mach-at91/at91sam9rl.c | 13 +------------ arch/arm/mach-at91/board-1arm.c | 2 +- arch/arm/mach-at91/board-afeb-9260v1.c | 2 +- arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- arch/arm/mach-at91/board-cam60.c | 2 +- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-carmeva.c | 2 +- arch/arm/mach-at91/board-cpu9krea.c | 2 +- arch/arm/mach-at91/board-cpuat91.c | 2 +- arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 2 +- arch/arm/mach-at91/board-eb9200.c | 2 +- arch/arm/mach-at91/board-ecbat91.c | 2 +- arch/arm/mach-at91/board-eco920.c | 2 +- arch/arm/mach-at91/board-flexibity.c | 2 +- arch/arm/mach-at91/board-foxg20.c | 2 +- arch/arm/mach-at91/board-gsia18s.c | 2 +- arch/arm/mach-at91/board-kafa.c | 2 +- arch/arm/mach-at91/board-kb9202.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-pcontrol-g20.c | 2 +- arch/arm/mach-at91/board-picotux200.c | 2 +- arch/arm/mach-at91/board-qil-a9260.c | 2 +- arch/arm/mach-at91/board-rm9200dk.c | 2 +- arch/arm/mach-at91/board-rm9200ek.c | 2 +- arch/arm/mach-at91/board-sam9-l9260.c | 2 +- arch/arm/mach-at91/board-sam9260ek.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 2 +- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9g20ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- arch/arm/mach-at91/board-snapper9260.c | 2 +- arch/arm/mach-at91/board-stamp9g20.c | 2 +- arch/arm/mach-at91/board-usb-a9260.c | 2 +- arch/arm/mach-at91/board-usb-a9263.c | 2 +- arch/arm/mach-at91/board-yl-9200.c | 2 +- arch/arm/mach-at91/generic.h | 9 +-------- arch/arm/mach-at91/soc.c | 12 ++++++++++++ arch/arm/mach-at91/soc.h | 1 + 47 files changed, 58 insertions(+), 140 deletions(-)
arch/arm/mach-at91/at572d940hf.c +1 -12
@@ -359,19 +359,8 @@ static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at572d940hf_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at572d940hf_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at572d940hf_soc = { .name ="at572d940hf" , + .default_irq_priority = at572d940hf_default_irq_priority, .init = at572d940hf_initialize, };
arch/arm/mach-at91/at91cap9.c +1 -12
@@ -366,19 +366,8 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91cap9_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91cap9_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91cap9_soc = { .name ="at91cap9" , + .default_irq_priority = at91cap9_default_irq_priority, .init = at91cap9_initialize, };
arch/arm/mach-at91/at91rm9200.c +1 -12
@@ -339,19 +339,8 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 0 /* Advanced Interrupt Controller (IRQ6) */ }; -void __init at91rm9200_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91rm9200_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91rm9200_soc = { .name ="at91rm9200" , + .default_irq_priority = at91rm9200_default_irq_priority, .init = at91rm9200_initialize, };
arch/arm/mach-at91/at91sam9260.c +1 -12
@@ -360,19 +360,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9260_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9260_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9260_soc = { .name ="at91sam9260" , + .default_irq_priority = at91sam9260_default_irq_priority, .init = at91sam9260_initialize, };
arch/arm/mach-at91/at91sam9261.c +1 -12
@@ -326,19 +326,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9261_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9261_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9261_soc = { .name ="at91sam9261" , + .default_irq_priority = at91sam9261_default_irq_priority, .init = at91sam9261_initialize, };
arch/arm/mach-at91/at91sam9263.c +1 -12
@@ -336,19 +336,8 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91sam9263_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9263_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9263_soc = { .name ="at91sam9263" , + .default_irq_priority = at91sam9263_default_irq_priority, .init = at91sam9263_initialize, };
arch/arm/mach-at91/at91sam9g45.c +1 -12
@@ -363,19 +363,8 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ0) */ }; -void __init at91sam9g45_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9g45_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9g45_soc = { .name ="at91sam9g45" , + .default_irq_priority = at91sam9g45_default_irq_priority, .init = at91sam9g45_initialize, };
arch/arm/mach-at91/at91sam9rl.c +1 -12
@@ -323,19 +323,8 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9rl_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9rl_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9rl_soc = { .name ="at91sam9rl" , + .default_irq_priority = at91sam9rl_default_irq_priority, .init = at91sam9rl_initialize, };
arch/arm/mach-at91/board-1arm.c +1 -1
@@ -65,7 +65,7 @@ static void __init onearm_map_io(void)static void __init onearm_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata onearm_eth_data = {
arch/arm/mach-at91/board-afeb-9260v1.c +1 -1
@@ -72,7 +72,7 @@ static void __init afeb9260_map_io(void)static void __init afeb9260_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-at572d940hf_ek.c +1 -1
@@ -70,7 +70,7 @@ static void __init eb_map_io(void)static void __init eb_init_irq (void ) { -at572d940hf_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-cam60.c +1 -1
@@ -59,7 +59,7 @@ static void __init cam60_map_io(void)static void __init cam60_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-cap9adk.c +1 -1
@@ -67,7 +67,7 @@ static void __init cap9adk_map_io(void)static void __init cap9adk_init_irq (void ) { -at91cap9_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-carmeva.c +1 -1
@@ -59,7 +59,7 @@ static void __init carmeva_map_io(void)static void __init carmeva_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata carmeva_eth_data = {
arch/arm/mach-at91/board-cpu9krea.c +1 -1
@@ -83,7 +83,7 @@ static void __init cpu9krea_map_io(void)static void __init cpu9krea_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/*
arch/arm/mach-at91/board-cpuat91.c +1 -1
@@ -84,7 +84,7 @@ static void __init cpuat91_map_io(void)static void __init cpuat91_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata cpuat91_eth_data = {
arch/arm/mach-at91/board-csb337.c +1 -1
@@ -60,7 +60,7 @@ static void __init csb337_map_io(void)static void __init csb337_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata csb337_eth_data = {
arch/arm/mach-at91/board-csb637.c +1 -1
@@ -54,7 +54,7 @@ static void __init csb637_map_io(void)static void __init csb637_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata csb637_eth_data = {
arch/arm/mach-at91/board-eb9200.c +1 -1
@@ -62,7 +62,7 @@ static void __init eb9200_map_io(void)static void __init eb9200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata eb9200_eth_data = {
arch/arm/mach-at91/board-ecbat91.c +1 -1
@@ -66,7 +66,7 @@ static void __init ecb_at91map_io(void)static void __init ecb_at91init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata ecb_at91eth_data = {
arch/arm/mach-at91/board-eco920.c +1 -1
@@ -49,7 +49,7 @@ static void __init eco920_map_io(void)static void __init eco920_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata eco920_eth_data = {
arch/arm/mach-at91/board-flexibity.c +1 -1
@@ -51,7 +51,7 @@ static void __init flexibity_map_io(void)static void __init flexibity_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/* USB Host port */
arch/arm/mach-at91/board-foxg20.c +1 -1
@@ -103,7 +103,7 @@ static void __init foxg20_map_io(void)static void __init foxg20_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-gsia18s.c +1 -1
@@ -77,7 +77,7 @@ static void __init gsia18s_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/*
arch/arm/mach-at91/board-kafa.c +1 -1
@@ -63,7 +63,7 @@ static void __init kafa_map_io(void)static void __init kafa_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata kafa_eth_data = {
arch/arm/mach-at91/board-kb9202.c +1 -1
@@ -71,7 +71,7 @@ static void __init kb9202_map_io(void)static void __init kb9202_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata kb9202_eth_data = {
arch/arm/mach-at91/board-neocore926.c +1 -1
@@ -68,7 +68,7 @@ static void __init neocore926_map_io(void)static void __init neocore926_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-pcontrol-g20.c +1 -1
@@ -56,7 +56,7 @@ static void __init pcontrol_g20_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-picotux200.c +1 -1
@@ -62,7 +62,7 @@ static void __init picotux200_map_io(void)static void __init picotux200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata picotux200_eth_data = {
arch/arm/mach-at91/board-qil-a9260.c +1 -1
@@ -74,7 +74,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-rm9200dk.c +1 -1
@@ -67,7 +67,7 @@ static void __init dk_map_io(void)static void __init dk_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata dk_eth_data = {
arch/arm/mach-at91/board-rm9200ek.c +1 -1
@@ -67,7 +67,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata ek_eth_data = {
arch/arm/mach-at91/board-sam9-l9260.c +1 -1
@@ -69,7 +69,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9260ek.c +1 -1
@@ -72,7 +72,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9261ek.c +1 -1
@@ -71,7 +71,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9261_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9263ek.c +1 -1
@@ -70,7 +70,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9g20ek.c +1 -1
@@ -83,7 +83,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9m10g45ek.c +1 -1
@@ -65,7 +65,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9g45_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-sam9rlek.c +1 -1
@@ -55,7 +55,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9rl_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-snapper9260.c +1 -1
@@ -57,7 +57,7 @@ static void __init snapper9260_map_io(void)static void __init snapper9260_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_usbh_data __initdata snapper9260_usbh_data = {
arch/arm/mach-at91/board-stamp9g20.c +1 -1
@@ -78,7 +78,7 @@ static void __init portuxg20_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-usb-a9260.c +1 -1
@@ -62,7 +62,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-usb-a9263.c +1 -1
@@ -61,7 +61,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/board-yl-9200.c +1 -1
@@ -81,7 +81,7 @@ static void __init yl9200_map_io(void)static void __init yl9200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
arch/arm/mach-at91/generic.h +1 -8
@@ -14,15 +14,8 @@ extern void __init at91_initialize(unsigned long main_clock);extern void __init at91x40_initialize (unsigned long main_clock);/* Interrupts */ -extern void __init at91rm9200_init_interrupts (unsigned int priority[]); -extern void __init at91sam9260_init_interrupts (unsigned int priority[]); -extern void __init at91sam9261_init_interrupts (unsigned int priority[]); -extern void __init at91sam9263_init_interrupts (unsigned int priority[]); -extern void __init at91sam9rl_init_interrupts (unsigned int priority[]); -extern void __init at91sam9g45_init_interrupts (unsigned int priority[]); +extern void __init at91_init_interrupts (unsigned int priority[]);extern void __init at91x40_init_interrupts (unsigned int priority[]); -extern void __init at91cap9_init_interrupts (unsigned int priority[]); -extern void __init at572d940hf_init_interrupts (unsigned int priority[]);extern void __init at91_aic_init (unsigned int priority[]);/* Timer */
arch/arm/mach-at91/soc.c +12 -0
@@ -20,6 +20,18 @@static struct at91_soc __initdata current_soc; +void __init at91_init_interrupts (unsigned int *priority) +{ +if (!priority) + priority = current_soc.default_irq_priority; + +/* Initialize the AIC interrupt controller */ +at91_aic_init (priority); + +/* Enable GPIO interrupts */ +at91_gpio_irq_setup (); +} +static struct map_desc at91_io_desc__initdata = { .virtual =AT91_VA_BASE_SYS , .pfn =__phys_to_pfn (AT91_BASE_SYS ),
arch/arm/mach-at91/soc.h +1 -0
@@ -8,6 +8,7 @@struct at91_soc {char *name; +unsigned int *default_irq_priority;void (*init)(unsigned long main_clock); };
Signature · 1 line
1.7.4.1
PATCH 3/14 at91: factorize at91 interrupts init to soc
Quoted 5 lines · Jean-Christophe PLAGNIOL-VILLARD
they are the same except the default priority
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>
Looks good.
Quoted 774 lines
--- arch/arm/mach-at91/at572d940hf.c | 13 +------------ arch/arm/mach-at91/at91cap9.c | 13 +------------ arch/arm/mach-at91/at91rm9200.c | 13 +------------ arch/arm/mach-at91/at91sam9260.c | 13 +------------ arch/arm/mach-at91/at91sam9261.c | 13 +------------ arch/arm/mach-at91/at91sam9263.c | 13 +------------ arch/arm/mach-at91/at91sam9g45.c | 13 +------------ arch/arm/mach-at91/at91sam9rl.c | 13 +------------ arch/arm/mach-at91/board-1arm.c | 2 +- arch/arm/mach-at91/board-afeb-9260v1.c | 2 +- arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- arch/arm/mach-at91/board-cam60.c | 2 +- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-carmeva.c | 2 +- arch/arm/mach-at91/board-cpu9krea.c | 2 +- arch/arm/mach-at91/board-cpuat91.c | 2 +- arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 2 +- arch/arm/mach-at91/board-eb9200.c | 2 +- arch/arm/mach-at91/board-ecbat91.c | 2 +- arch/arm/mach-at91/board-eco920.c | 2 +- arch/arm/mach-at91/board-flexibity.c | 2 +- arch/arm/mach-at91/board-foxg20.c | 2 +- arch/arm/mach-at91/board-gsia18s.c | 2 +- arch/arm/mach-at91/board-kafa.c | 2 +- arch/arm/mach-at91/board-kb9202.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-pcontrol-g20.c | 2 +- arch/arm/mach-at91/board-picotux200.c | 2 +- arch/arm/mach-at91/board-qil-a9260.c | 2 +- arch/arm/mach-at91/board-rm9200dk.c | 2 +- arch/arm/mach-at91/board-rm9200ek.c | 2 +- arch/arm/mach-at91/board-sam9-l9260.c | 2 +- arch/arm/mach-at91/board-sam9260ek.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 2 +- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9g20ek.c | 2 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- arch/arm/mach-at91/board-snapper9260.c | 2 +- arch/arm/mach-at91/board-stamp9g20.c | 2 +- arch/arm/mach-at91/board-usb-a9260.c | 2 +- arch/arm/mach-at91/board-usb-a9263.c | 2 +- arch/arm/mach-at91/board-yl-9200.c | 2 +- arch/arm/mach-at91/generic.h | 9 +-------- arch/arm/mach-at91/soc.c | 12 ++++++++++++ arch/arm/mach-at91/soc.h | 1 + 47 files changed, 58 insertions(+), 140 deletions(-)arch/arm/mach-at91/at572d940hf.c +1
-12@@ -359,19 +359,8 @@ static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at572d940hf_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at572d940hf_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at572d940hf_soc = { .name ="at572d940hf" , + .default_irq_priority = at572d940hf_default_irq_priority, .init = at572d940hf_initialize, };arch/arm/mach-at91/at91cap9.c +1
-12@@ -366,19 +366,8 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91cap9_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91cap9_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91cap9_soc = { .name ="at91cap9" , + .default_irq_priority = at91cap9_default_irq_priority, .init = at91cap9_initialize, };arch/arm/mach-at91/at91rm9200.c +1
-12@@ -339,19 +339,8 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = { 0 /* Advanced Interrupt Controller (IRQ6) */ }; -void __init at91rm9200_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91rm9200_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91rm9200_soc = { .name ="at91rm9200" , + .default_irq_priority = at91rm9200_default_irq_priority, .init = at91rm9200_initialize, };arch/arm/mach-at91/at91sam9260.c +1
-12@@ -360,19 +360,8 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9260_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9260_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9260_soc = { .name ="at91sam9260" , + .default_irq_priority = at91sam9260_default_irq_priority, .init = at91sam9260_initialize, };arch/arm/mach-at91/at91sam9261.c +1
-12@@ -326,19 +326,8 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9261_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9261_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9261_soc = { .name ="at91sam9261" , + .default_irq_priority = at91sam9261_default_irq_priority, .init = at91sam9261_initialize, };arch/arm/mach-at91/at91sam9263.c +1
-12@@ -336,19 +336,8 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; -void __init at91sam9263_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9263_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9263_soc = { .name ="at91sam9263" , + .default_irq_priority = at91sam9263_default_irq_priority, .init = at91sam9263_initialize, };arch/arm/mach-at91/at91sam9g45.c +1
-12@@ -363,19 +363,8 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ0) */ }; -void __init at91sam9g45_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9g45_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9g45_soc = { .name ="at91sam9g45" , + .default_irq_priority = at91sam9g45_default_irq_priority, .init = at91sam9g45_initialize, };arch/arm/mach-at91/at91sam9rl.c +1
-12@@ -323,19 +323,8 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; -void __init at91sam9rl_init_interrupts (unsigned int priority[NR_AIC_IRQS ]) -{ -if (!priority) - priority = at91sam9rl_default_irq_priority; - -/* Initialize the AIC interrupt controller */ -at91_aic_init (priority); - -/* Enable GPIO interrupts */ -at91_gpio_irq_setup (); -} -struct at91_soc __initdata at91sam9rl_soc = { .name ="at91sam9rl" , + .default_irq_priority = at91sam9rl_default_irq_priority, .init = at91sam9rl_initialize, };arch/arm/mach-at91/board-1arm.c +1
-1@@ -65,7 +65,7 @@ static void __init onearm_map_io(void)static void __init onearm_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata onearm_eth_data = {arch/arm/mach-at91/board-afeb-9260v1.c +1
-1@@ -72,7 +72,7 @@ static void __init afeb9260_map_io(void)static void __init afeb9260_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-at572d940hf_ek.c +1
-1@@ -70,7 +70,7 @@ static void __init eb_map_io(void)static void __init eb_init_irq (void ) { -at572d940hf_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-cam60.c +1
-1@@ -59,7 +59,7 @@ static void __init cam60_map_io(void)static void __init cam60_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-cap9adk.c +1
-1@@ -67,7 +67,7 @@ static void __init cap9adk_map_io(void)static void __init cap9adk_init_irq (void ) { -at91cap9_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-carmeva.c +1
-1@@ -59,7 +59,7 @@ static void __init carmeva_map_io(void)static void __init carmeva_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata carmeva_eth_data = {arch/arm/mach-at91/board-cpu9krea.c +1
-1@@ -83,7 +83,7 @@ static void __init cpu9krea_map_io(void)static void __init cpu9krea_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/* arch/arm/mach-at91/board-cpuat91.c +1
-1@@ -84,7 +84,7 @@ static void __init cpuat91_map_io(void)static void __init cpuat91_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata cpuat91_eth_data = {arch/arm/mach-at91/board-csb337.c +1
-1@@ -60,7 +60,7 @@ static void __init csb337_map_io(void)static void __init csb337_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata csb337_eth_data = {arch/arm/mach-at91/board-csb637.c +1
-1@@ -54,7 +54,7 @@ static void __init csb637_map_io(void)static void __init csb637_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata csb637_eth_data = {arch/arm/mach-at91/board-eb9200.c +1
-1@@ -62,7 +62,7 @@ static void __init eb9200_map_io(void)static void __init eb9200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata eb9200_eth_data = {arch/arm/mach-at91/board-ecbat91.c +1
-1@@ -66,7 +66,7 @@ static void __init ecb_at91map_io(void)static void __init ecb_at91init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata ecb_at91eth_data = {arch/arm/mach-at91/board-eco920.c +1
-1@@ -49,7 +49,7 @@ static void __init eco920_map_io(void)static void __init eco920_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata eco920_eth_data = {arch/arm/mach-at91/board-flexibity.c +1
-1@@ -51,7 +51,7 @@ static void __init flexibity_map_io(void)static void __init flexibity_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/* USB Host port */ arch/arm/mach-at91/board-foxg20.c +1
-1@@ -103,7 +103,7 @@ static void __init foxg20_map_io(void)static void __init foxg20_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-gsia18s.c +1
-1@@ -77,7 +77,7 @@ static void __init gsia18s_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }/* arch/arm/mach-at91/board-kafa.c +1
-1@@ -63,7 +63,7 @@ static void __init kafa_map_io(void)static void __init kafa_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata kafa_eth_data = {arch/arm/mach-at91/board-kb9202.c +1
-1@@ -71,7 +71,7 @@ static void __init kb9202_map_io(void)static void __init kb9202_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata kb9202_eth_data = {arch/arm/mach-at91/board-neocore926.c +1
-1@@ -68,7 +68,7 @@ static void __init neocore926_map_io(void)static void __init neocore926_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-pcontrol-g20.c +1
-1@@ -56,7 +56,7 @@ static void __init pcontrol_g20_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-picotux200.c +1
-1@@ -62,7 +62,7 @@ static void __init picotux200_map_io(void)static void __init picotux200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata picotux200_eth_data = {arch/arm/mach-at91/board-qil-a9260.c +1
-1@@ -74,7 +74,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-rm9200dk.c +1
-1@@ -67,7 +67,7 @@ static void __init dk_map_io(void)static void __init dk_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata dk_eth_data = {arch/arm/mach-at91/board-rm9200ek.c +1
-1@@ -67,7 +67,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_eth_data __initdata ek_eth_data = {arch/arm/mach-at91/board-sam9-l9260.c +1
-1@@ -69,7 +69,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9260ek.c +1
-1@@ -72,7 +72,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9261ek.c +1
-1@@ -71,7 +71,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9261_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9263ek.c +1
-1@@ -70,7 +70,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9g20ek.c +1
-1@@ -83,7 +83,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9m10g45ek.c +1
-1@@ -65,7 +65,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9g45_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-sam9rlek.c +1
-1@@ -55,7 +55,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9rl_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-snapper9260.c +1
-1@@ -57,7 +57,7 @@ static void __init snapper9260_map_io(void)static void __init snapper9260_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }static struct at91_usbh_data __initdata snapper9260_usbh_data = {arch/arm/mach-at91/board-stamp9g20.c +1
-1@@ -78,7 +78,7 @@ static void __init portuxg20_map_io(void)static void __init init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-usb-a9260.c +1
-1@@ -62,7 +62,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9260_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-usb-a9263.c +1
-1@@ -61,7 +61,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/board-yl-9200.c +1
-1@@ -81,7 +81,7 @@ static void __init yl9200_map_io(void)static void __init yl9200_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }arch/arm/mach-at91/generic.h +1
-8@@ -14,15 +14,8 @@ extern void __init at91_initialize(unsigned long main_clock);extern void __init at91x40_initialize (unsigned long main_clock);/* Interrupts */ -extern void __init at91rm9200_init_interrupts (unsigned int priority[]); -extern void __init at91sam9260_init_interrupts (unsigned int priority[]); -extern void __init at91sam9261_init_interrupts (unsigned int priority[]); -extern void __init at91sam9263_init_interrupts (unsigned int priority[]); -extern void __init at91sam9rl_init_interrupts (unsigned int priority[]); -extern void __init at91sam9g45_init_interrupts (unsigned int priority[]); +extern void __init at91_init_interrupts (unsigned int priority[]);extern void __init at91x40_init_interrupts (unsigned int priority[]); -extern void __init at91cap9_init_interrupts (unsigned int priority[]); -extern void __init at572d940hf_init_interrupts (unsigned int priority[]);extern void __init at91_aic_init (unsigned int priority[]);/* Timer */ arch/arm/mach-at91/soc.c +12
-0@@ -20,6 +20,18 @@static struct at91_soc __initdata current_soc; +void __init at91_init_interrupts (unsigned int *priority) +{ +if (!priority) + priority = current_soc.default_irq_priority; + +/* Initialize the AIC interrupt controller */ +at91_aic_init (priority); + +/* Enable GPIO interrupts */ +at91_gpio_irq_setup (); +} +static struct map_desc at91_io_desc__initdata = { .virtual =AT91_VA_BASE_SYS , .pfn =__phys_to_pfn (AT91_BASE_SYS ),arch/arm/mach-at91/soc.h +1
-0@@ -8,6 +8,7 @@struct at91_soc {char *name; +unsigned int *default_irq_priority;void (*init)(unsigned long main_clock); };
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 3/14 at91: factorize at91 interrupts init to soc
In reply to Jean-Christophe PLAGNIOL-VILLARDQuoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
they are the same except the default priority
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>
[snip]
Quoted 11 lines
arch/arm/mach-at91/board-1arm.c +1
-1@@ -65,7 +65,7 @@ static void __init onearm_map_io(void)static void __init onearm_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
[snip]
Quoted 10 lines
arch/arm/mach-at91/soc.c +2
-0@@ -20,6 +20,18 @@static struct at91_soc __initdata current_soc; +void __init at91_init_interrupts (unsigned int *priority) +{
arch/arm/mach-at91/soc.c line 34
Quoted 10 lines
arch/arm/mach-at91/soc.c +10
-0+if (!priority) + priority = current_soc.default_irq_priority; + +/* Initialize the AIC interrupt controller */ +at91_aic_init (priority); + +/* Enable GPIO interrupts */ +at91_gpio_irq_setup (); +} +
All the board files call at91_init_interrupts with a NULL priority. Why not just remove the parameter entirely, make MACHINE_START.init_irq = at91_init_interrupts, and then remove all the {board}_init_irq functions.
Regards,
Hartley
PATCH 3/14 at91: factorize at91 interrupts init to soc
Quoted 32 lines · H Hartley Sweeten
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
they are the same except the default priority
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>[snip]
Quoted 11 lines
arch/arm/mach-at91/board-1arm.c +1
-1@@ -65,7 +65,7 @@ static void __init onearm_map_io(void)static void __init onearm_init_irq (void ) { -at91rm9200_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }[snip]
Quoted 8 lines
arch/arm/mach-at91/soc.c +0
-0@@ -20,6 +20,18 @@static struct at91_soc __initdata current_soc;
Quoted 16 lines
arch/arm/mach-at91/soc.c line 34
Quoted 12 lines
arch/arm/mach-at91/soc.c +12
-0+void __init at91_init_interrupts (unsigned int *priority) +{ +if (!priority) + priority = current_soc.default_irq_priority; + +/* Initialize the AIC interrupt controller */ +at91_aic_init (priority); + +/* Enable GPIO interrupts */ +at91_gpio_irq_setup (); +} +All the board files call
at91_init_interruptswith a NULL priority. Why not just remove the parameter entirely, make MACHINE_START.init_irq =at91_init_interrupts, and then remove all the {board}_init_irq functions.
keep it is important as the irq priority can be board specific as we have nearly no fifo on at91
agreed to too have a a generic function
Best Regards,
J.
PATCH 3/14 at91: factorize at91 interrupts init to soc
hi,
Quoted 7 lines
Quoted 3 lines
All the board files call
at91_init_interruptswith a NULL priority. ?Why not just remove the parameter entirely, make MACHINE_START.init_irq =at91_init_interrupts, and then remove all the {board}_init_irq functions.keep it is important as the irq priority can be board specific as we have nearly no fifo on at91
agreed to too have a a generic function
As of this patch:
http://git.kernel.org/?p=linux/kernel/git/stable/linux-2.6.35.y.git;a=commit;h=e58aa3d2d0cc01ad8d6f7f640a0670433f794922
interrupt priority / nesting were disabled in the core IRQ code. So even though we configure the AT91's AIC controller for priority levels, it won't as make much difference as before. Only if you have multiple pending interrupts, will the one with the highest priority be serviced first.
Also, you might want to look into changing the AIC's handler from handle_level_irq() to the handle_fasteoi_irq().
Then the irq_finish() can be removed from the low-level ARM asm_do_IRQ() handler.
Regards,
Andrew Victor
PATCH 3/14 at91: factorize at91 interrupts init to soc
Quoted 10 lines · Andrew Victor
hi,
Quoted 7 lines
Quoted 3 lines
All the board files call
at91_init_interruptswith a NULL priority. ?Why not just remove the parameter entirely, make MACHINE_START.init_irq =at91_init_interrupts, and then remove all the {board}_init_irq functions.keep it is important as the irq priority can be board specific as we have nearly no fifo on at91
agreed to too have a a generic function
Quoted 7 lines
As of this patch:
http://git.kernel.org/?p=linux/kernel/git/stable/linux-2.6.35.y.git;a=commit;h=e58aa3d2d0cc01ad8d6f7f640a0670433f794922
interrupt priority / nesting were disabled in the core IRQ code. So even though we configure the AT91's AIC controller for priority levels, it won't as make much difference as before. Only if you have multiple pending interrupts, will the one with the highest priority be serviced first.
I'm aware of it yes but the priority can be programed for each board and f if we use the preempt to will be true again
Quoted 5 lines
Also, you might want to look into changing the AIC's handler from
handle_level_irq()to thehandle_fasteoi_irq().
Then theirq_finish()can be removed from the low-level ARMasm_do_IRQ()handler.
I plan to rework the interrupt drivers
Best Regards,
J.
PATCH 3/14 at91: factorize at91 interrupts init to soc
In reply to Jean-Christophe PLAGNIOL-VILLARDQuoted 1 line · Jean-Christophe PLAGNIOL-VILLARD
they are the same except the default priority
No one uses anything but the default priority. So let's have a version of this patch which simplifies this further:
arch/arm/mach-at91/board-usb-a9263.c static void __init ek_map_io(void) · line 65
Quoted 11 lines
arch/arm/mach-at91/board-usb-a9263.c +1
-1@@ -61,7 +61,7 @@ static void __init ek_map_io(void)static void __init ek_init_irq (void ) { -at91sam9263_init_interrupts (NULL ); +at91_init_interrupts (NULL ); }
by replacing every instance of the above with a call in their machine record to at91_init_irq_default(), and:
arch/arm/mach-at91/board-usb-a9263.c static void __init ek_map_io(void)
Quoted 11 lines
arch/arm/mach-at91/board-usb-a9263.c +11
-0+void __init at91_init_interrupts (unsigned int *priority) +{ +if (!priority) + priority = current_soc.default_irq_priority; + +/* Initialize the AIC interrupt controller */ +at91_aic_init (priority); + +/* Enable GPIO interrupts */ +at91_gpio_irq_setup (); +}
void __init at91_init_interrupts(unsigned int *priority)
{
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* Enable GPIO interrupts */
at91_gpio_irq_setup();
}void __init at91_init_irq_default(void)
{
at91_init_interrupts(current_soc.default_irq_priority);
}If people wish to change from the default priority, they can provide their own init_irq function, and call at91_init_interrupts with their desired priority array.
arch/arm/mach-at91/soc.h line 10
Quoted 8 lines
arch/arm/mach-at91/soc.h +0
-0@@ -8,6 +8,7 @@struct at91_soc {char *name;
btw, this should be const (which should of course be a separate patch).
PATCH v2 4/14 at91: merge board usb-a9260 and usb-a9263 together
In reply to Jean-Christophe PLAGNIOL-VILLARDFrom: Nico Erfurth <[email protected]>
as the are nearly the same
---
v2:
update against new common init
we must use it as we can detect the cpu type only after mapping the system controler
Best Regards,
J.
arch/arm/mach-at91/Makefile | 4 +-
arch/arm/mach-at91/board-usb-a9260.c | 236 --------------------
.../{board-usb-a9263.c => board-usb-a926x.c} | 56 ++++-
arch/arm/mach-at91/soc.c | 16 +-
arch/arm/mach-at91/soc.h | 7 +-
5 files changed, 65 insertions(+), 254 deletions(-)
delete mode 100644 arch/arm/mach-at91/board-usb-a9260.c
rename arch/arm/mach-at91/{board-usb-a9263.c => board-usb-a926x.c} (85%)arch/arm/mach-at91/Makefile +2 -2
@@ -42,7 +42,7 @@ obj-$(CONFIG_MACH_ECO920) += board-eco920.o obj-$(CONFIG_MACH_AT91SAM9260EK) += board-sam9260ek.o obj-$(CONFIG_MACH_CAM60) += board-cam60.o obj-$(CONFIG_MACH_SAM9_L9260) += board-sam9-l9260.o -obj-$(CONFIG_MACH_USB_A9260) += board-usb-a9260.o +obj-$(CONFIG_MACH_USB_A9260) += board-usb-a926x.o obj-$(CONFIG_MACH_QIL_A9260) += board-qil-a9260.o obj-$(CONFIG_MACH_AFEB9260) += board-afeb-9260v1.o obj-$(CONFIG_MACH_CPU9260) += board-cpu9krea.o
@@ -54,7 +54,7 @@ obj-$(CONFIG_MACH_AT91SAM9G10EK) += board-sam9261ek.o # AT91SAM9263 board-specific support obj-$(CONFIG_MACH_AT91SAM9263EK) += board-sam9263ek.o -obj-$(CONFIG_MACH_USB_A9263) += board-usb-a9263.o +obj-$(CONFIG_MACH_USB_A9263) += board-usb-a926x.o obj-$(CONFIG_MACH_NEOCORE926) += board-neocore926.o # AT91SAM9RL board-specific support
arch/arm/mach-at91/board-usb-a9260.c deleted +0 -236
236 lines not on this page · raw message
arch/arm/mach-at91/board-usb-a926x.c renamed from arch/arm/mach-at91/board-usb-a9263.c +50 -6
112 lines not on this page · raw message
arch/arm/mach-at91/soc.c +9 -7
@@ -44,7 +44,11 @@ void __init at91_initialize(unsigned long main_clock)/* Map peripherals */ iotable_init (&at91_io_desc,1 ); -if (cpu_is_at91rm9200 ()) +if (cpu_is_at572d940hf ()) + current_soc = at572d940hf_soc; +else if (cpu_is_at91cap9 ()) + current_soc = at91cap9_soc; +else if (cpu_is_at91rm9200 ()) current_soc = at91rm9200_soc;else if (cpu_is_at91sam9260 ()) current_soc = at91sam9260_soc;
@@ -52,14 +56,12 @@ void __init at91_initialize(unsigned long main_clock) current_soc = at91sam9261_soc; else if (cpu_is_at91sam9263()) current_soc = at91sam9263_soc; - else if (cpu_is_at91sam9rl()) - current_soc = at91sam9rl_soc; else if (cpu_is_at91sam9g45()) current_soc = at91sam9g45_soc; - else if (cpu_is_at91cap9()) - current_soc = at91cap9_soc; - else if (cpu_is_at572d940hf()) - current_soc = at572d940hf_soc; + else if (cpu_is_at91sam9rl()) + current_soc = at91sam9rl_soc; + else if (cpu_is_at91sam9x5()) + current_soc = at91sam9x5_soc; else panic("Impossible to detect the CPU type");
arch/arm/mach-at91/soc.h +4 -3
@@ -13,11 +13,12 @@ struct at91_soc {void (*init)(unsigned long main_clock); }; +extern struct at91_soc at572d940hf_soc; +extern struct at91_soc at91cap9_soc;extern struct at91_soc at91rm9200_soc;extern struct at91_soc at91sam9260_soc;extern struct at91_soc at91sam9261_soc;extern struct at91_soc at91sam9263_soc; -extern struct at91_soc at91sam9rl_soc;extern struct at91_soc at91sam9g45_soc; -extern struct at91_soc at91cap9_soc; -extern struct at91_soc at572d940hf_soc; +extern struct at91_soc at91sam9rl_soc; +extern struct at91_soc at91sam9x5_soc;
Signature · 1 line
1.7.4.1
PATCH 5/14 at91: use structure to store the current soc
In reply to Jean-Christophe PLAGNIOL-VILLARDinstead of reading the registers everytime
--- arch/arm/mach-at91/at91rm9200.c | 8 - arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9rl.c | 1 + arch/arm/mach-at91/cpu.h | 181 +++++++++++++++++ arch/arm/mach-at91/include/mach/cpu.h | 355 ++++++++++++++------------------- arch/arm/mach-at91/soc.c | 66 +++++- 6 files changed, 391 insertions(+), 221 deletions(-) create mode 100644 arch/arm/mach-at91/cpu.h
rewrite arch/arm/mach-at91/include/mach/cpu.h (71%)
arch/arm/mach-at91/at91rm9200.c +0 -8
@@ -263,14 +263,6 @@ static void at91rm9200_reset(void)at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); } -int rm9200_type; -EXPORT_SYMBOL (rm9200_type); - -void __init at91rm9200_set_type (int type) -{ - rm9200_type = type; -} -/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */
arch/arm/mach-at91/at91sam9260.c +1 -0
@@ -17,6 +17,7 @@#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/cpu.h> +#include <mach/at91_dbgu.h> #include <mach/at91sam9260.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h>
arch/arm/mach-at91/at91sam9rl.c +1 -0
@@ -16,6 +16,7 @@#include <asm/mach/arch.h> #include <asm/mach/map.h> #include <mach/cpu.h> +#include <mach/at91_dbgu.h> #include <mach/at91sam9rl.h> #include <mach/at91_pmc.h> #include <mach/at91_rstc.h>
arch/arm/mach-at91/cpu.h new file +181 -0
181 lines not on this page · raw message
arch/arm/mach-at91/include/mach/cpu.h +152 -203
355 lines not on this page · raw message
arch/arm/mach-at91/soc.c +56 -10
93 lines not on this page · raw message
Signature · 1 line
1.7.4.1
PATCH 5/14 at91: use structure to store the current soc
Quoted 1 line · Jean-Christophe PLAGNIOL-VILLARD
instead of reading the registers everytime
Hi Jean, a couple of comments below.
Quoted 20 lines
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>--- arch/arm/mach-at91/at91rm9200.c | 8 - arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9rl.c | 1 + arch/arm/mach-at91/cpu.h | 181 +++++++++++++++++ arch/arm/mach-at91/include/mach/cpu.h | 355 ++++++++++++++------------------- arch/arm/mach-at91/soc.c | 66 +++++- 6 files changed, 391 insertions(+), 221 deletions(-) create mode 100644 arch/arm/mach-at91/cpu.hrewrite
arch/arm/mach-at91/include/mach/cpu.h(71%)arch/arm/mach-at91/at91rm9200.c +0
-0@@ -263,14 +263,6 @@ static void at91rm9200_reset(void)at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST );
arch/arm/mach-at91/at91rm9200.c static void at91rm9200_reset(void) · line 273
Quoted 10 lines
arch/arm/mach-at91/at91rm9200.c +0
-8} -int rm9200_type; -EXPORT_SYMBOL (rm9200_type); - -void __init at91rm9200_set_type (int type) -{ - rm9200_type = type; -} -
This only got introduce a couple of patches ago. I'm aware its a stop-gap solution, but is it possible to rework/reorder the patches so that this doesn't need to be temporarily introduced?
<snip>
arch/arm/mach-at91/at91rm9200.c static void at91rm9200_reset(void)
Quoted 6 lines
arch/arm/mach-at91/at91rm9200.c +6
-0+ +#ifdef CONFIG_ARCH_AT91RM9200 +#define __cpu_is_at91rm9200 () (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#else +#define __cpu_is_at91rm9200 () (0) +#endif
I haven't looked at the subsequent patches yet to see if this patch simplifies things later but it seems that this just adds more lines of code by having two copies of the each of the cpu_is_xxx macros (the __cpu_is_xxx version which reads the register, and the cpu_is_xxx version which reads the shadow value)?
What is the reasoning behind shadowing the cpu type rather than reading the registers? The cpu detection macros are mostly used at initialisation and device probe time, so they don't necessarily need to be fast.
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 27 lines · Ryan Mallon
Quoted 1 line · Jean-Christophe PLAGNIOL-VILLARD
instead of reading the registers everytime
Hi Jean, a couple of comments below.
Quoted 22 lines
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>--- arch/arm/mach-at91/at91rm9200.c | 8 - arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9rl.c | 1 + arch/arm/mach-at91/cpu.h | 181 +++++++++++++++++ arch/arm/mach-at91/include/mach/cpu.h | 355 ++++++++++++++------------------- arch/arm/mach-at91/soc.c | 66 +++++- 6 files changed, 391 insertions(+), 221 deletions(-) create mode 100644 arch/arm/mach-at91/cpu.hrewrite
arch/arm/mach-at91/include/mach/cpu.h(71%)arch/arm/mach-at91/at91rm9200.c +0
-0@@ -263,14 +263,6 @@ static void at91rm9200_reset(void)at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); }
Quoted 12 lines
arch/arm/mach-at91/at91rm9200.c static void at91rm9200_reset(void) · line 273
Quoted 8 lines
arch/arm/mach-at91/at91rm9200.c +0
-8-int rm9200_type; -EXPORT_SYMBOL (rm9200_type); - -void __init at91rm9200_set_type (int type) -{ - rm9200_type = type; -} -This only got introduce a couple of patches ago. I'm aware its a stop-gap solution, but is it possible to rework/reorder the patches so that this doesn't need to be temporarily introduced?
the is to do not touch the other soc init api so I keep the changes local and prepare the soc to have the same init API so we can factorize them
I prefer to do small changes to be able to bisect them if needed
Quoted 16 lines
<snip>
arch/arm/mach-at91/at91rm9200.c
Quoted 6 lines
arch/arm/mach-at91/at91rm9200.c +6
-0+ +#ifdef CONFIG_ARCH_AT91RM9200 +#define __cpu_is_at91rm9200 () (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#else +#define __cpu_is_at91rm9200 () (0) +#endif I haven't looked at the subsequent patches yet to see if this patch simplifies things later but it seems that this just adds more lines of code by having two copies of the each of the
cpu_is_xxxmacros (the__cpu_is_xxxversion which reads the register, and thecpu_is_xxxversion which reads the shadow value)?
Quoted 7 lines
What is the reasoning behind shadowing the cpu type rather than reading the registers? The cpu detection macros are mostly used at initialisation and device probe time, so they don't necessarily need to be fast.
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between __cpu_is and cpu_is is necessarly
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 65 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 27 lines · Ryan Mallon
Quoted 1 line · Jean-Christophe PLAGNIOL-VILLARD
instead of reading the registers everytime
Hi Jean, a couple of comments below.
Quoted 22 lines
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>--- arch/arm/mach-at91/at91rm9200.c | 8 - arch/arm/mach-at91/at91sam9260.c | 1 + arch/arm/mach-at91/at91sam9rl.c | 1 + arch/arm/mach-at91/cpu.h | 181 +++++++++++++++++ arch/arm/mach-at91/include/mach/cpu.h | 355 ++++++++++++++------------------- arch/arm/mach-at91/soc.c | 66 +++++- 6 files changed, 391 insertions(+), 221 deletions(-) create mode 100644 arch/arm/mach-at91/cpu.hrewrite
arch/arm/mach-at91/include/mach/cpu.h(71%)arch/arm/mach-at91/at91rm9200.c +0
-0@@ -263,14 +263,6 @@ static void at91rm9200_reset(void)at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); }Quoted 12 lines
arch/arm/mach-at91/at91rm9200.c static void at91rm9200_reset(void) · line 273
Quoted 8 lines
arch/arm/mach-at91/at91rm9200.c +0
-8-int rm9200_type; -EXPORT_SYMBOL (rm9200_type); - -void __init at91rm9200_set_type (int type) -{ - rm9200_type = type; -} -This only got introduce a couple of patches ago. I'm aware its a stop-gap solution, but is it possible to rework/reorder the patches so that this doesn't need to be temporarily introduced?
the is to do not touch the other soc init api so I keep the changes local and prepare the soc to have the same init API so we can factorize them
I prefer to do small changes to be able to bisect them if needed
Quoted 21 lines
<snip>
arch/arm/mach-at91/at91rm9200.c
Quoted 6 lines
arch/arm/mach-at91/at91rm9200.c +6
-0+ +#ifdef CONFIG_ARCH_AT91RM9200 +#define __cpu_is_at91rm9200 () (at91_cpu_identify() == ARCH_ID_AT91RM9200) +#else +#define __cpu_is_at91rm9200 () (0) +#endif I haven't looked at the subsequent patches yet to see if this patch simplifies things later but it seems that this just adds more lines of code by having two copies of the each of the
cpu_is_xxxmacros (the__cpu_is_xxxversion which reads the register, and thecpu_is_xxxversion which reads the shadow value)?What is the reasoning behind shadowing the cpu type rather than reading the registers? The cpu detection macros are mostly used at initialisation and device probe time, so they don't necessarily need to be fast.
Quoted 7 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarly
I don't understand. The at91_initialize function sets cpu_id using the __cpu_is macros, and the cpu_is macros check cpu_id to determine the cpu type. So the __cpu_is and cpu_is macros are functionally equivalent except that the former uses register reads and the latter reads a shadow value. i.e. the cpu_is macros are just indirectly using the __cpu_is macros.
If the register offsets are different between the various platforms then this won't work anyway since the __cpu_is macros cannot be generic.
Quoted 2 lines
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
If the __cpu_is macros, which read the registers directly, remain then I don't see how this can be generic between the various SoCs?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 19 lines
Quoted 11 lines
Quoted 11 lines
I haven't looked at the subsequent patches yet to see if this patch simplifies things later but it seems that this just adds more lines of code by having two copies of the each of the
cpu_is_xxxmacros (the__cpu_is_xxxversion which reads the register, and thecpu_is_xxxversion which reads the shadow value)?What is the reasoning behind shadowing the cpu type rather than reading the registers? The cpu detection macros are mostly used at initialisation and device probe time, so they don't necessarily need to be fast.
Quoted 7 lines
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If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarly
Quoted 8 lines
I don't understand. The
at91_initializefunction setscpu_idusing the__cpu_ismacros, and thecpu_ismacros checkcpu_idto determine the cpu type. So the__cpu_isandcpu_ismacros are functionally equivalent except that the former uses register reads and the latter reads a shadow value. i.e. thecpu_ismacros are just indirectly using the__cpu_ismacros.If the register offsets are different between the various platforms then this won't work anyway since the
__cpu_ismacros cannot be generic.
yes it's for now we can use one soc at a time I'm working to remove those issue and make then soc specific
before doint this I need to fix pm, interrupt, earlyprintk, ll_debug, etc...
for gpio and timers it's already fix so one by one and it will be clean in those 2 we can now specify on the soc the resource so we do not need to have the same AT91_PIOx, AT91_ST and AT91_PIT for all soc
they can have their own.
When this cleanup will be finished we will have AT91SAM9263_PIOx AT91SAM9263_PIT etc... and only common define when they are really common
Quoted 6 lines
Quoted 3 lines
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
If the
__cpu_ismacros, which read the registers directly, remain then I don't see how this can be generic between the various SoCs?
because they will be use only at the begenning before any drivers or other ip enable so we can use them later it will not be the case anymore
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 40 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 18 lines
Quoted 11 lines
Quoted 11 lines
I haven't looked at the subsequent patches yet to see if this patch simplifies things later but it seems that this just adds more lines of code by having two copies of the each of the
cpu_is_xxxmacros (the__cpu_is_xxxversion which reads the register, and thecpu_is_xxxversion which reads the shadow value)?What is the reasoning behind shadowing the cpu type rather than reading the registers? The cpu detection macros are mostly used at initialisation and device probe time, so they don't necessarily need to be fast.
Quoted 7 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyQuoted 8 lines
I don't understand. The
at91_initializefunction setscpu_idusing the__cpu_ismacros, and thecpu_ismacros checkcpu_idto determine the cpu type. So the__cpu_isandcpu_ismacros are functionally equivalent except that the former uses register reads and the latter reads a shadow value. i.e. thecpu_ismacros are just indirectly using the__cpu_ismacros.If the register offsets are different between the various platforms then this won't work anyway since the
__cpu_ismacros cannot be generic.yes it's for now we can use one soc at a time I'm working to remove those issue and make then soc specific
before doint this I need to fix pm, interrupt, earlyprintk,ll_debug, etc...for gpio and timers it's already fix so one by one and it will be clean in those 2 we can now specify on the soc the resource so we do not need to have the same
AT91_PIOx,AT91_STandAT91_PITfor all soc
they can have their own.When this cleanup will be finished we will have
AT91SAM9263_PIOxAT91SAM9263_PITetc... and only common define when they are really commonQuoted 2 lines
Quoted 2 lines
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
Quoted 7 lines
Quoted 2 lines
If the
__cpu_ismacros, which read the registers directly, remain then I don't see how this can be generic between the various SoCs?because they will be use only at the begenning before any drivers or other ip enable so we can use them later it will not be the case anymore
Best Regards,
J.
I think that a better approach is to have only the cpu_is_ macros which read the shadow value and then have at91_initialize (or some other function which is init called before anything needs the cpu_is_ macros) which just directly reads the cpu id registers and fills in the structure. You won't need a structure that way either, just an id. Something like:
/* include/mach/cpu.h */
/* Base SoC types */
#define AT91_SOC_AT91RM9200 0x1
#define AT91_SOC_AT91SAM9260 0x2
/* Extended SoC types */
#define AT91_SOC_AT91SAM9XE (0x1 << 16)
/* Accessor macros */
#define AT91_SOC_TYPE(x) ((x) & 0xffff)
#define AT91_SOC_EXT_TYPE(x) (((x) >> 16) & 0xffff)
extern unsigned long at91_soc_id;
#define cpu_is_at91rm9200() (AT91_SOC_TYPE(at91_soc_id) == AT91_SOC_AT91RM9200)
#define cpu_is_at91sam9260() (AT91_SOC_TYPE(at91_soc_id) == AT91_SOC_AT91SAM9260)
#define cpu_is_at91sam9xe() (AT91_SOC_EXT_TYPE(at91_soc_id) == AT91_SOC_AT91SAM9XE)
/* soc.c */
unsigned long at91_soc_id = 0;
static void at91_detect_cpu(void)
{
unsigned long cpu_id, full_id, arch_id, exid;
full_id = at91_sys_read(AT91_DBGU_CIDR);
cpu_id = full_id & !AT91_CIDR_VERSION);
arch_id = full_id & AT91_CIDR_ARCH;
exid = at91_sys_read(AT91_DBGU_EXID);
switch (cpu_id) {
case ARCH_ID_AT91RM9200:
at91_soc_id = AT91_SOC_AT91RM9200;
current_soc = at91rm9200_soc;
break;
case ARCH_ID_AT91SAM9260:
at91_soc_id = AT91_SOC_AT91SAM9260;
if (arch_id == ARCH_FAMILY_AT91SAM9XE)
at91_soc_id |= AT91_SOC_AT91SAM9XE;
current_soc = at91sam9260_soc;
break;
...
default:
panic("Unknown AT91 SoC type\n");
}
} This way the cpu detection code is much clearer and easier to read and only one set of __cpu_is macros are needed. The values for ARCH_ID_AT91RM9200, etc can be moved into soc.c since they are not needed elsewhere.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 81 lines
Quoted 14 lines
yes it's for now we can use one soc at a time I'm working to remove those issue and make then soc specific
before doint this I need to fix pm, interrupt, earlyprintk,ll_debug, etc...for gpio and timers it's already fix so one by one and it will be clean in those 2 we can now specify on the soc the resource so we do not need to have the same
AT91_PIOx,AT91_STandAT91_PITfor all soc
they can have their own.When this cleanup will be finished we will have
AT91SAM9263_PIOxAT91SAM9263_PITetc... and only common define when they are really commonQuoted 2 lines
Quoted 2 lines
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
Quoted 7 lines
Quoted 2 lines
If the
__cpu_ismacros, which read the registers directly, remain then I don't see how this can be generic between the various SoCs?because they will be use only at the begenning before any drivers or other ip enable so we can use them later it will not be the case anymore
Best Regards,
J.I think that a better approach is to have only the
cpu_is_macros which read the shadow value and then haveat91_initialize(or some other function which is init called before anything needs thecpu_is_macros) which just directly reads the cpu id registers and fills in the structure. You won't need a structure that way either, just an id. Something like:/*
include/mach/cpu.h*//* Base SoC types */
#define
AT91_SOC_AT91RM92000x1
#defineAT91_SOC_AT91SAM92600x2/* Extended SoC types */
#defineAT91_SOC_AT91SAM9XE(0x1<< 16)/* Accessor macros */
#defineAT91_SOC_TYPE(x)((x) &0xffff)
#defineAT91_SOC_EXT_TYPE(x)(((x) >> 16) &0xffff)extern unsigned long
at91_soc_id;#define
cpu_is_at91rm9200()(AT91_SOC_TYPE(at91_soc_id)==AT91_SOC_AT91RM9200)
#definecpu_is_at91sam9260()(AT91_SOC_TYPE(at91_soc_id)==AT91_SOC_AT91SAM9260)
#definecpu_is_at91sam9xe()(AT91_SOC_EXT_TYPE(at91_soc_id)==AT91_SOC_AT91SAM9XE)/*
soc.c*/
unsigned longat91_soc_id= 0;static void
at91_detect_cpu(void){ unsigned long cpu_id, full_id, arch_id, exid; full_id = at91_sys_read(AT91_DBGU_CIDR); cpu_id = full_id & !AT91_CIDR_VERSION); arch_id = full_id & AT91_CIDR_ARCH; exid = at91_sys_read(AT91_DBGU_EXID); switch (cpu_id) { case ARCH_ID_AT91RM9200: at91_soc_id = AT91_SOC_AT91RM9200; current_soc = at91rm9200_soc; break; case ARCH_ID_AT91SAM9260: at91_soc_id = AT91_SOC_AT91SAM9260; if (arch_id == ARCH_FAMILY_AT91SAM9XE) at91_soc_id |= AT91_SOC_AT91SAM9XE; current_soc = at91sam9260_soc; break; ... default: panic("Unknown AT91 SoC type\n"); } }
Quoted 4 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.
This will never work you do not listen
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by one
I keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 87 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 81 lines
Quoted 14 lines
yes it's for now we can use one soc at a time I'm working to remove those issue and make then soc specific
before doint this I need to fix pm, interrupt, earlyprintk,ll_debug, etc...for gpio and timers it's already fix so one by one and it will be clean in those 2 we can now specify on the soc the resource so we do not need to have the same
AT91_PIOx,AT91_STandAT91_PITfor all soc
they can have their own.When this cleanup will be finished we will have
AT91SAM9263_PIOxAT91SAM9263_PITetc... and only common define when they are really commonQuoted 2 lines
Quoted 2 lines
all of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
Quoted 7 lines
Quoted 2 lines
If the
__cpu_ismacros, which read the registers directly, remain then I don't see how this can be generic between the various SoCs?because they will be use only at the begenning before any drivers or other ip enable so we can use them later it will not be the case anymore
Best Regards,
J.I think that a better approach is to have only the
cpu_is_macros which read the shadow value and then haveat91_initialize(or some other function which is init called before anything needs thecpu_is_macros) which just directly reads the cpu id registers and fills in the structure. You won't need a structure that way either, just an id. Something like:/*
include/mach/cpu.h*//* Base SoC types */
#define
AT91_SOC_AT91RM92000x1
#defineAT91_SOC_AT91SAM92600x2/* Extended SoC types */
#defineAT91_SOC_AT91SAM9XE(0x1<< 16)/* Accessor macros */
#defineAT91_SOC_TYPE(x)((x) &0xffff)
#defineAT91_SOC_EXT_TYPE(x)(((x) >> 16) &0xffff)extern unsigned long
at91_soc_id;#define
cpu_is_at91rm9200()(AT91_SOC_TYPE(at91_soc_id)==AT91_SOC_AT91RM9200)
#definecpu_is_at91sam9260()(AT91_SOC_TYPE(at91_soc_id)==AT91_SOC_AT91SAM9260)
#definecpu_is_at91sam9xe()(AT91_SOC_EXT_TYPE(at91_soc_id)==AT91_SOC_AT91SAM9XE)/*
soc.c*/
unsigned longat91_soc_id= 0;static void
at91_detect_cpu(void){ unsigned long cpu_id, full_id, arch_id, exid; full_id = at91_sys_read(AT91_DBGU_CIDR); cpu_id = full_id & !AT91_CIDR_VERSION); arch_id = full_id & AT91_CIDR_ARCH; exid = at91_sys_read(AT91_DBGU_EXID); switch (cpu_id) { case ARCH_ID_AT91RM9200: at91_soc_id = AT91_SOC_AT91RM9200; current_soc = at91rm9200_soc; break; case ARCH_ID_AT91SAM9260: at91_soc_id = AT91_SOC_AT91SAM9260; if (arch_id == ARCH_FAMILY_AT91SAM9XE) at91_soc_id |= AT91_SOC_AT91SAM9XE; current_soc = at91sam9260_soc; break; ... default: panic("Unknown AT91 SoC type\n"); } }Quoted 4 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.This will never work you do not listen
Quoted 8 lines
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by oneI keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Best Regards,
J.
You can only be running one machine at a time. Are you implying that this change breaks at91_sys_read in such a way that it reads the wrong registers? If so, then its definitely a NAK.
Your patch does this:
static inline unsigned long at91_cpu_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
}...
#ifdef CONFIG_ARCH_AT91RM9200
#define __cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
#else
#define __cpu_is_at91rm9200() (0)
#endif
...
void __init at91_initialize(unsigned long main_clock)
{
...
if (__cpu_is_at91rm9200()) {
cpu_id.is_at91rm9200_soc;
current_soc = at91rm9200_soc;
}
...
}So at91_initialize calls the __cpu_is macros, which in turn read the AT91_DBGU registers via at91_sys_read. What I am proposing above is to replace the massive collection of if statements with a simpler switch statement and replacing the __cpu_is macros with direct register reads via at91_sys_read, which results in far less code and more readable code. If your version works, then how can mine not?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 10 lines
Quoted 10 lines
Quoted 5 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.This will never work you do not listen
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by one
Quoted 8 lines
Quoted 5 lines
I keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Best Regards,
J.You can only be running one machine at a time. Are you implying that this change breaks
at91_sys_readin such a way that it reads the wrong registers? If so, then its definitely a NAK.
Certernly not ALL of the current work is too allow in a UNIQUE kernel to have all the atmel inside and other vendors and boards in the same kernel
and for at91_sys_read it's not a big deal as I'm going to drop it at the end the timers does not use it anymore and the other drivers will update also one by one
Quoted 8 lines
Your patch does this:
static inline unsigned long
at91_cpu_identify(void){ return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); }
Yeah as I said already I need to fix a lots of place and I do it step by step so for now on I do not update the at91_cpu_identify & co but I will in time
Quoted 21 lines
...
#ifdef
CONFIG_ARCH_AT91RM9200
#define__cpu_is_at91rm9200()(at91_cpu_identify()==ARCH_ID_AT91RM9200)
#else
#define__cpu_is_at91rm9200()(0)
#endif...
void
__initat91_initialize(unsigned long main_clock){ ... if (__cpu_is_at91rm9200()) { cpu_id.is_at91rm9200_soc; current_soc = at91rm9200_soc; } ... }
Quoted 6 lines
So
at91_initializecalls the__cpu_ismacros, which in turn read theAT91_DBGUregisters viaat91_sys_read. What I am proposing above is to replace the massive collection of if statements with a simpler switch statement and replacing the__cpu_ismacros with direct register reads viaat91_sys_read, which results in far less code and more readable code. If your version works, then how can mine not?
Because It will never allow you to have a __cpu_is_ soc specific which is the goal here
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 13 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 13 lines
Quoted 13 lines
Quoted 5 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.This will never work you do not listen
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by oneI keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Quoted 7 lines
Quoted 5 lines
Quoted 2 lines
Best Regards,
J.You can only be running one machine at a time. Are you implying that this change breaks
at91_sys_readin such a way that it reads the wrong registers? If so, then its definitely a NAK.Certernly not ALL of the current work is too allow in a UNIQUE kernel to have all the atmel inside and other vendors and boards in the same kernel
Agreed. At the moment we still have a situation where we can only compile one at91 SoC variant into the kernel. So, at the moment, we do not need to deal with the fact that the DBGU exists at different locations, we can just read it for the board that we are booting on.
What I am objecting to is adding two entire sets of cpu_is macros which is just needless extra code with no benefit. We should determine the cpu/SoC type _once_ inside a single function (at91_initialize) and the the cpu_is macros should just read the shadow value. There is no reason to have two sets of macros.
Quoted 3 lines
and for
at91_sys_readit's not a big deal as I'm going to drop it at the end the timers does not use it anymore and the other drivers will update also one by one
Okay. But it shouldn't get broken now.
Quoted 9 lines
Quoted 7 lines
Your patch does this:
static inline unsigned long
at91_cpu_identify(void){ return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION); }Yeah as I said already I need to fix a lots of place and I do it step by step so for now on I do not update the
at91_cpu_identify& co but I will in time
Right. But the point is, if __cpu_is_at91rm9200 calls at91_cpu_identify, then why can't we drop the __cpu_is_at91rm9200 call entirely and just work out the cpu/SoC type in a big switch statement?
In short, what is the benefit of the __cpu_is macros if they are never used outside of at91_initialize?
Quoted 21 lines
Quoted 21 lines
...
#ifdef
CONFIG_ARCH_AT91RM9200
#define__cpu_is_at91rm9200()(at91_cpu_identify()==ARCH_ID_AT91RM9200)
#else
#define__cpu_is_at91rm9200()(0)
#endif...
void
__initat91_initialize(unsigned long main_clock){ ... if (__cpu_is_at91rm9200()) { cpu_id.is_at91rm9200_soc; current_soc = at91rm9200_soc; } ... }
Quoted 8 lines
Quoted 6 lines
So
at91_initializecalls the__cpu_ismacros, which in turn read theAT91_DBGUregisters viaat91_sys_read. What I am proposing above is to replace the massive collection of if statements with a simpler switch statement and replacing the__cpu_ismacros with direct register reads viaat91_sys_read, which results in far less code and more readable code. If your version works, then how can mine not?Because It will never allow you to have a
__cpu_is_soc specific which is the goal here
You already have the existing cpu_is versions (which would now use the shadowed value rather than register reads). After at91_initialize has determined the cpu/SoC type the __cpu_is macros are no longer used right?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 19 lines · Ryan Mallon
Quoted 18 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 18 lines
Quoted 7 lines
Quoted 5 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.This will never work you do not listen
Quoted 8 lines
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by oneI keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Best Regards,
J.You can only be running one machine at a time. Are you implying that this change breaks
at91_sys_readin such a way that it reads the wrong registers? If so, then its definitely a NAK.
Quoted 7 lines
Quoted 2 lines
Certernly not ALL of the current work is too allow in a UNIQUE kernel to have all the atmel inside and other vendors and boards in the same kernel
Agreed. At the moment we still have a situation where we can only compile one at91 SoC variant into the kernel. So, at the moment, we do not need to deal with the fact that the DBGU exists at different locations, we can just read it for the board that we are booting on.
This patch series goal is to allow to have a UNIQUE kernel so all the drivers and new code are write with this requirement
so no the double implementation is needed
no new code will accepted if it's does have this in considaration
Quoted 6 lines
What I am objecting to is adding two entire sets of
cpu_ismacros which is just needless extra code with no benefit. We should determine the cpu/SoC type _once_ inside a single function (at91_initialize) and the thecpu_ismacros should just read the shadow value. There is no reason to have two sets of macros.
Those two macro set does not have the same constrains
cpu_is is to be soc agnostic__cpu_is is to be soc specific
so yes they are needed
and I'll update the __cpu_is soon so they will not use at91_sys_read anymore
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 27 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 19 lines · Ryan Mallon
Quoted 18 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 18 lines
Quoted 7 lines
Quoted 5 lines
This way the cpu detection code is much clearer and easier to read and only one set of
__cpu_ismacros are needed. The values forARCH_ID_AT91RM9200, etc can be moved intosoc.csince they are not needed elsewhere.This will never work you do not listen
Quoted 8 lines
the DBUG is at DIFFERENT base address on the AT91
you need to check them one by oneI keep the structure to keep more imformation inside and do not want to be limited by a 32bit and complex encoding to maintain
Best Regards,
J.You can only be running one machine at a time. Are you implying that this change breaks
at91_sys_readin such a way that it reads the wrong registers? If so, then its definitely a NAK.Quoted 7 lines
Quoted 2 lines
Certernly not ALL of the current work is too allow in a UNIQUE kernel to have all the atmel inside and other vendors and boards in the same kernel
Agreed. At the moment we still have a situation where we can only compile one at91 SoC variant into the kernel. So, at the moment, we do not need to deal with the fact that the DBGU exists at different locations, we can just read it for the board that we are booting on.
Quoted 6 lines
This patch series goal is to allow to have a UNIQUE kernel so all the drivers and new code are write with this requirement
so no the double implementation is needed
no new code will accepted if it's does have this in considaration
I understand that the goal is to get a single kernel supporting all of the at91 soc variants. This is one of the goals for the devices patch series I posted also.
I am objecting to the implementation, not the goal. I believe there is a better, cleaner way to handle this.
Quoted 9 lines
Quoted 5 lines
What I am objecting to is adding two entire sets of
cpu_ismacros which is just needless extra code with no benefit. We should determine the cpu/SoC type _once_ inside a single function (at91_initialize) and the thecpu_ismacros should just read the shadow value. There is no reason to have two sets of macros.Those two macro set does not have the same constrains
cpu_isis to be soc agnostic__cpu_isis to be soc specific
Yes. But if the __cpu_is versions are not needed outside of the at91_initialize function (in order to first determine the cpu/soc type) then why not move all of the code into at91_initialize (i.e. the switch statement I proposed) and do away with the __cpu_is macros. This would be functionally the same but doesn't add a second copy of the cpu_is macros.
Quoted 1 line
so yes they are needed
The code _inside_ them is needed, but does not need to be in the form of the __cpu_is macros, it can be moved directly into at91_initialize which is cleaner and simpler.
Quoted 1 line
and I'll update the
__cpu_issoon so they will not useat91_sys_readanymore
When will users ever need to use the __cpu_is macros and how will they know when to use cpu_is and when to use __cpu_is?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
In reply to Jean-Christophe PLAGNIOL-VILLARDhi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The cpu_is() or__cpu_is() perform a at91_sys_read() of one of the DBGU registers.
But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.
While having a single kernel image that supports AT91 processors is a good goal, the soc.h is a totally unnecessary complication. I can't think of any situation where an AT91 board.c file doesn't know what processor it has.
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection -->at91XX_initialize()
just do:
boardXYZ-init -> at91XX_initialize()
And soc.c's not really removing much code duplication... most of the code in there is the newly-added early_platform_devices.
Regards,
Andrew Victor
PATCH 5/14 at91: use structure to store the current soc
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.
Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 43 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()
Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The init_machine callback can be separated in this case so that both of the boards initialise the correct cpu type.
For cases such as the Snapper 9260/9G20, where a single mach-type is used for two boards, we can then read the DBGU registers because the location is the same for the 9260 and 9G20 (same sub-family). I don't think there are any boards in the kernel which share a mach-type, but have different sub-families and therefore different locations for DBGU.
If we took the approach that the boards must explicitly specify (as closely as possible) their cpu/soc type then we could remove much of the cpu detection code. We will still need the sub-family detection (e.g. 9260/9G20, CAP9 revision, etc) to distinguish some boards.
As Andrew says, cpu detection will not reliably work if we have a kernel where all boards are compiled in. We have a chicken and egg problem in that we need to know the cpu type in order to know where the DBGU registers are, and we need to read the DBGU registers in order to determine the cpu type. Catch 22.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 52 lines · Ryan Mallon
Quoted 43 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 58 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 52 lines · Ryan Mallon
Quoted 43 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.
Quoted 7 lines
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
How? It has been pointed out that there is no way that this can be reliably done if you have all of the at91 socs built into a single kernel. You cannot know where the DBGU registers are to read determine the cpu/soc type.
The most reliable way to do this, which also requires the least code, is to have the boards explicitly specify which cpu/soc type they are. In this case most of the cpu detection code can be removed. Only the minor variant (i.e. 9260/9G20) detection code would need to remain.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 72 lines · Ryan Mallon
Quoted 58 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 52 lines · Ryan Mallon
Quoted 43 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.Quoted 7 lines
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
How? It has been pointed out that there is no way that this can be reliably done if you have all of the at91 socs built into a single kernel. You cannot know where the DBGU registers are to read determine the cpu/soc type.
Quoted 4 lines
The most reliable way to do this, which also requires the least code, is to have the boards explicitly specify which cpu/soc type they are. In this case most of the cpu detection code can be removed. Only the minor variant (i.e. 9260/9G20) detection code would need to remain.
Having another look at this, the cpu detection is already fine. For example, board-snapper9260.c calls at91sam9260_initialize, which in turn determines whether the soc is a 9xe, 9260, or 9g20 and does the appropriate intialisation. This all works fine because the three socs have the same DBGU location.
There are other obstacles to having a single kernel for all of AT91, in particular the big ifdef switch in include/mach/hardware.h and the whole AT91_BASE_SYS thing, but the cpu/soc detection should not actually need to be modified.
Lets fix the other problems first.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 84 lines · Ryan Mallon
Quoted 72 lines · Ryan Mallon
Quoted 58 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 52 lines · Ryan Mallon
Quoted 43 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 37 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.Quoted 7 lines
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
How? It has been pointed out that there is no way that this can be reliably done if you have all of the at91 socs built into a single kernel. You cannot know where the DBGU registers are to read determine the cpu/soc type.
Quoted 4 lines
The most reliable way to do this, which also requires the least code, is to have the boards explicitly specify which cpu/soc type they are. In this case most of the cpu detection code can be removed. Only the minor variant (i.e. 9260/9G20) detection code would need to remain.
Having another look at this, the cpu detection is already fine. For example,
board-snapper9260.ccallsat91sam9260_initialize, which in turn determines whether the soc is a 9xe, 9260, or 9g20 and does the appropriate intialisation. This all works fine because the three socs have the same DBGU location.
Quoted 6 lines
There are other obstacles to having a single kernel for all of AT91, in particular the big ifdef switch in
include/mach/hardware.hand the wholeAT91_BASE_SYSthing, but the cpu/soc detection should not actually need to be modified.Lets fix the other problems first.
I known one by one please it's plan to get rid of this
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
In reply to Ryan MallonQuoted 41 lines
Quoted 28 lines
Quoted 23 lines
Quoted 15 lines
Quoted 10 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.Quoted 7 lines
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
How? It has been pointed out that there is no way that this can be reliably done if you have all of the at91 socs built into a single kernel. You cannot know where the DBGU registers are to read determine the cpu/soc type.
Quoted 4 lines
The most reliable way to do this, which also requires the least code, is to have the boards explicitly specify which cpu/soc type they are. In this case most of the cpu detection code can be removed. Only the minor variant (i.e. 9260/9G20) detection code would need to remain.
Except the idea here to do not do so
as I point some board will have different soc for the cpu module a big real case on AT91
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 41 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 41 lines
Quoted 28 lines
Quoted 23 lines
Quoted 15 lines
Quoted 10 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.While having a single kernel image that supports AT91 processors is a good goal, the
soc.his a totally unnecessary complication. I can't think of any situation where an AT91board.cfile doesn't know what processor it has.Quoted 5 lines
So instead of :
boardXYZ-init -> at91_initialize() --> magic-cpu-detection --> at91XX_initialize() just do: boardXYZ-init -> at91XX_initialize()Quoted 7 lines
except there is no need to known it and board seach as the usb-926x are the same nearly and do not need to known on which soc they are
ditto for other boards you do not need to known the soc we are on. And when you work on CPU module the board is the same but not the cpu on the module so detect the SOC allow to have one kernel for all and not multiple machine ID for each module and board combination
Quoted 5 lines
I Agree with Andrew. When can determine everything we need from the mach-type. For boards such as the usb-926x we have two separate mach-types for the 9263 and the 9260 variants. The
init_machinecallback can be separated in this case so that both of the boards initialise the correct cpu type.Quoted 7 lines
I do work on board where is the case and I do not want to keep the limitation and yes I'll put them mainline
And Russell will not accept I'll create 10 or 20 machine ID for board / cpu module combinaison just because of different I do not detect the SOC type
so I'll continue to detect the soc
How? It has been pointed out that there is no way that this can be reliably done if you have all of the at91 socs built into a single kernel. You cannot know where the DBGU registers are to read determine the cpu/soc type.
Quoted 8 lines
Quoted 4 lines
The most reliable way to do this, which also requires the least code, is to have the boards explicitly specify which cpu/soc type they are. In this case most of the cpu detection code can be removed. Only the minor variant (i.e. 9260/9G20) detection code would need to remain.
Except the idea here to do not do so
as I point some board will have different soc for the cpu module a big real case on AT91
Can you give an example of a situation where we have the same mach-type for two boards, where the DBGU is at a different location and therefore not possible to differentiate between the boards?
You still haven't answered how your proposed cpu detection code would work if all of the at91 socs were compiled into a single kernel, where the DBGU registers are at different locations.
The current approach of boards explicitly specifying their cpu/soc type will actually work correctly if all at91 socs are compiled into a single kernel. Your patch set will actively break this.
~Ryan
PATCH 5/14 at91: use structure to store the current soc
In reply to Andrew VictorQuoted 27 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.
we have 2 different register 0xfffff200 and 0xffffee00 which are the DBGU or the PIOA
and on the PIOA at the offset 0x40 if you try to read the cpu will always return 0x0, and have no effect on the soc
so I do not think there is a big issue to read 2 register to detect the soc automatically
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 31 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 27 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 2 lines
If this eventually reduces code size then I think it is useful, but otherwise I'm not sure I see the point?
It's on purpose as the dbgu physical address is not at the same place so read the other register really does not impact the chip but if we do it later duting the boot or the life to the kernel it's an other story
so the split between
__cpu_isandcpu_isis necessarlyall of this work is in preparation to allow multiple soc in the same kernel that's also why I map the system controller the same way on all at91 arm9
The
cpu_is()or__cpu_is()perform aat91_sys_read()of one of the DBGU registers.But the address of the DBGU differs between CPUs regardless if you map the system controller the same:
at572d940hf.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91cap9.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91rm9200.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9260.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9261.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) at91sam9263.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9g45.h:#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS) at91sam9rl.h:#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.
Quoted 8 lines
we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
And it's not random address it's specific 2 address with specific value per soc
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 17 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 7 lines
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
You haven't named such a piece of hardware yet. We have boards like our own Snapper 9260/9G20 where the same mach-type is used for two boards, one with a SAM9260 and the other with a SAM9G20. Because these are variants of the same soc we know that the DBGU is at the same address on both and so we can read the cpuid registers to determine which board it is.
Can you give me an example of a mach-type which is used for two or more boards that cannot be differentiated this way?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 26 lines · Ryan Mallon
Quoted 17 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 7 lines
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
Quoted 5 lines
You haven't named such a piece of hardware yet. We have boards like our own Snapper 9260/9G20 where the same mach-type is used for two boards, one with a SAM9260 and the other with a SAM9G20. Because these are variants of the same soc we know that the DBGU is at the same address on both and so we can read the cpuid registers to determine which board it is.
take a look on the Ronetix
http://www.ronetix.at/
and this is just one the example
Quoted 3 lines
Can you give me an example of a mach-type which is used for two or more boards that cannot be differentiated this way?
today we can not do so, so people multiplicate the machine ID which is wrong and please do not only see the Snapper there is much more hardware provider
This is more and more common as when you design the cpu module you will use a 4 or 6 layers pcb and for the main board just 2 layers
This allow you the reduce the cost and be more flexible
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 32 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 26 lines · Ryan Mallon
Quoted 17 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 7 lines
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
Quoted 5 lines
You haven't named such a piece of hardware yet. We have boards like our own Snapper 9260/9G20 where the same mach-type is used for two boards, one with a SAM9260 and the other with a SAM9G20. Because these are variants of the same soc we know that the DBGU is at the same address on both and so we can read the cpuid registers to determine which board it is.
Quoted 4 lines
take a look on the Ronetix
http://www.ronetix.at/and this is just one the example
Why would each of those three modules not have their own mach-type? They could be implemented as a single board file, with three MACHINE_START sections at the bottom of the file. All three could be compiled into a single kernel and the cpu_is macros can be used for the soc specific stuff.
Quoted 4 lines
Quoted 2 lines
Can you give me an example of a mach-type which is used for two or more boards that cannot be differentiated this way?
today we can not do so, so people multiplicate the machine ID which is wrong and please do not only see the Snapper there is much more hardware provider
I think that these boards are different enough (they have cpus with different memory layouts) that they should be specified by their own mach-type.
Russell, what is your opinion on this? Should we use individual mach-types for the above boards and have them explicitly specify their cpu/soc type, or should we be aiming to have a single mach-type for all of them and determine the cpu/soc type in code?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 48 lines · Ryan Mallon
Quoted 32 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 26 lines · Ryan Mallon
Quoted 17 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 7 lines
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
Quoted 5 lines
You haven't named such a piece of hardware yet. We have boards like our own Snapper 9260/9G20 where the same mach-type is used for two boards, one with a SAM9260 and the other with a SAM9G20. Because these are variants of the same soc we know that the DBGU is at the same address on both and so we can read the cpuid registers to determine which board it is.
Quoted 4 lines
take a look on the Ronetix
http://www.ronetix.at/and this is just one the example
Why would each of those three modules not have their own mach-type? They could be implemented as a single board file, with three
MACHINE_STARTsections at the bottom of the file. All three could be compiled into a single kernel and thecpu_ismacros can be used for the soc specific stuff.Quoted 4 lines
Quoted 2 lines
Can you give me an example of a mach-type which is used for two or more boards that cannot be differentiated this way?
today we can not do so, so people multiplicate the machine ID which is wrong and please do not only see the Snapper there is much more hardware provider
Quoted 8 lines
I think that these boards are different enough (they have cpus with different memory layouts) that they should be specified by their own mach-type.
Russell, what is your opinion on this? Should we use individual mach-types for the above boards and have them explicitly specify their cpu/soc type, or should we be aiming to have a single mach-type for all of them and determine the cpu/soc type in code?
so which means when we will have multiple board that use the SAME cpu module we will add X * Y boards machine ID
really not good just to avoid to read 2 registers common it's non-sense
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 53 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 52 lines · Ryan Mallon
Quoted 32 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 26 lines · Ryan Mallon
Quoted 17 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 17 lines
Quoted 11 lines
Quoted 3 lines
So I don't see how you can "detect" the CPU without first knowing which CPU and therefore where the DBGU register is anyway.
And probing different addresses for a value is not an acceptable solution.we have 2 different register
0xfffff200and0xffffee00which are the DBGU or the PIOAand on the PIOA at the offset
0x40if you try to read the cpu will always return0x0, and have no effect on the socso I do not think there is a big issue to read 2 register to detect the soc automatically
This does rely on Atmel not making another soc which has the DBGU at an address which does cause a conflict (low possibility, but would be very annoying). It's also really ugly to read random registers until we get the one we want.
Quoted 7 lines
Quoted 4 lines
However, I still do not see what is wrong with the current approach of the boards explicitly specifying the soc type. The correct soc/cpu type can already be determined without changing the code. So why are we changing the code?
Because some hardware design architecture such as CPU module do allow to have the SAME board with different SOC. So have one machine ID per combinaison because we just change the soc is a non-sense.
Quoted 5 lines
You haven't named such a piece of hardware yet. We have boards like our own Snapper 9260/9G20 where the same mach-type is used for two boards, one with a SAM9260 and the other with a SAM9G20. Because these are variants of the same soc we know that the DBGU is at the same address on both and so we can read the cpuid registers to determine which board it is.
Quoted 4 lines
take a look on the Ronetix
http://www.ronetix.at/and this is just one the example
Why would each of those three modules not have their own mach-type? They could be implemented as a single board file, with three
MACHINE_STARTsections at the bottom of the file. All three could be compiled into a single kernel and thecpu_ismacros can be used for the soc specific stuff.Quoted 4 lines
Quoted 2 lines
Can you give me an example of a mach-type which is used for two or more boards that cannot be differentiated this way?
today we can not do so, so people multiplicate the machine ID which is wrong and please do not only see the Snapper there is much more hardware provider
I think that these boards are different enough (they have cpus with different memory layouts) that they should be specified by their own mach-type.
Quoted 8 lines
Quoted 4 lines
Russell, what is your opinion on this? Should we use individual mach-types for the above boards and have them explicitly specify their cpu/soc type, or should we be aiming to have a single mach-type for all of them and determine the cpu/soc type in code?
so which means when we will have multiple board that use the SAME cpu module we will add X * Y boards machine ID
really not good just to avoid to read 2 registers common it's non-sense
The boards are different. They have a common base pinout, but their peripheral pinouts are different. Multiple mach-types cost nothing and are a well understood part of ARM Linux. Your proposed cpu detection code adds complexity and code, and has zero benefit for any of the boards currently in mainline.
Carrier boards are a separate issue, and there has not really been a consensus on what the best way to solve the issue of combining system on modules (SoMs) with carrier boards. Should the mach-type belong to the SoM or to the system as a whole (SoM + carrier board)? There is currently a push to get ARM to consolidate on things rather than each sub-architecture doing things its own way. So if you want a way to differentiate carrier boards, then I think that needs to be discussed with other sub-architecture maintainers so that a common approach can be devised. I don't think that cpu detection is a robust solution. Device tree is probably the long-term solution to this.
In short, your soc detection patches add additional complexity, but have zero effect on the possibility of supporting all of the current mainline at91 platforms in a single kernel. We need to fix the other barriers to this support first (such as the work Andrew Victor is doing).
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 5 lines
The boards are different. They have a common base pinout, but their peripheral pinouts are different. Multiple mach-types cost nothing and are a well understood part of ARM Linux. Your proposed cpu detection code adds complexity and code, and has zero benefit for any of the boards currently in mainline.
So we will do an other re-architecture in the few months
Linus is going to said no
We do need to stop to do changset again and again just because we don't solve the issue at the beginning
Quoted 7 lines
Carrier boards are a separate issue, and there has not really been a consensus on what the best way to solve the issue of combining system on modules (SoMs) with carrier boards. Should the mach-type belong to the SoM or to the system as a whole (SoM + carrier board)? There is currently a push to get ARM to consolidate on things rather than each sub-architecture doing things its own way.
Sorry but cpu detection is soc specific
hardcode it via machine ID is not good
Quoted 10 lines
So if you want a way to
differentiate carrier boards, then I think that needs to be discussed with other sub-architecture maintainers so that a common approach can be devised. I don't think that cpu detection is a robust solution. Device tree is probably the long-term solution to this.In short, your soc detection patches add additional complexity, but have zero effect on the possibility of supporting all of the current mainline at91 platforms in a single kernel. We need to fix the other barriers to this support first (such as the work Andrew Victor is doing).
Which can be also simply be knowning the CPU you are on
If you take a look on other arch they do cpu detection and there is nothing wrong about it. And device tree is not the solution to everything If you have work on it on PowerPC or other arch, you will known that it's also have its own issue
such as bootloader/kernel incompatibilty
so detect cpu type at runtine in the kernel is good to do not realy blindly on DT
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines
The boards are different. They have a common base pinout, but their peripheral pinouts are different. Multiple mach-types cost nothing and are a well understood part of ARM Linux. Your proposed cpu detection code adds complexity and code, and has zero benefit for any of the boards currently in mainline.
So we will do an other re-architecture in the few months
Linus is going to said no
We do need to stop to do changset again and again just because we don't solve the issue at the beginning
Agreed. That is why I am saying that we should focusing on reducing the size and complexity of AT91 and getting a single kernel working for all of the at91 boards which are currently in mainline.
Quoted 7 lines
Quoted 6 lines
Carrier boards are a separate issue, and there has not really been a consensus on what the best way to solve the issue of combining system on modules (SoMs) with carrier boards. Should the mach-type belong to the SoM or to the system as a whole (SoM + carrier board)? There is currently a push to get ARM to consolidate on things rather than each sub-architecture doing things its own way.
Sorry but cpu detection is soc specific
The method for specifying the setup of a system including SoM and carrier board(s) is not cpu/soc specific and does not necessarily need to be done via cpu detection. In fact, I think cpu detection is a bad way to do it.
Quoted 7 lines
hardcode it via machine ID is not good
Quoted 6 lines
So if you want a way to
differentiate carrier boards, then I think that needs to be discussed with other sub-architecture maintainers so that a common approach can be devised. I don't think that cpu detection is a robust solution. Device tree is probably the long-term solution to this.
Quoted 8 lines
Quoted 4 lines
In short, your soc detection patches add additional complexity, but have zero effect on the possibility of supporting all of the current mainline at91 platforms in a single kernel. We need to fix the other barriers to this support first (such as the work Andrew Victor is doing).
Which can be also simply be knowning the CPU you are on
If you take a look on other arch they do cpu detection and there is nothing wrong about it.
There is nothing wrong with the current solution for at91, yet you are trying to add code which is confusing (two sets of cpu_is macros) and adds more lines for something which _already works_.
This argument is getting frustrating. My current objections to this patch are:
- The current solution (explicitly specifying the soc type) works for all of the at91 boards currently in mainline.
- It adds two sets of cpu_is macros (second set with __ prefix), which is confusing and pointless.
- You have implied that the __cpu_is macros will be removed at a later date. Since they are basically useless now, this is just more code churn when we are trying to reduce it on ARM.
- The patch as it stands won't work in a unified at91 kernel because the address of the DBGU registers is different on some at91 platforms.
- By itself this patch adds complexity without fixing anything and without introducing any functional change.
- There are other barriers to having a unified at91 kernel which need to be solved first. This patch is trying to jump ahead and solve problems that don't exist yet.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 5/14 at91: use structure to store the current soc
Quoted 48 lines · Ryan Mallon
Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 5 lines
The boards are different. They have a common base pinout, but their peripheral pinouts are different. Multiple mach-types cost nothing and are a well understood part of ARM Linux. Your proposed cpu detection code adds complexity and code, and has zero benefit for any of the boards currently in mainline.
So we will do an other re-architecture in the few months
Linus is going to said no
We do need to stop to do changset again and again just because we don't solve the issue at the beginningAgreed. That is why I am saying that we should focusing on reducing the size and complexity of AT91 and getting a single kernel working for all of the at91 boards which are currently in mainline.
Quoted 7 lines
Quoted 6 lines
Carrier boards are a separate issue, and there has not really been a consensus on what the best way to solve the issue of combining system on modules (SoMs) with carrier boards. Should the mach-type belong to the SoM or to the system as a whole (SoM + carrier board)? There is currently a push to get ARM to consolidate on things rather than each sub-architecture doing things its own way.
Sorry but cpu detection is soc specific
The method for specifying the setup of a system including SoM and carrier board(s) is not cpu/soc specific and does not necessarily need to be done via cpu detection. In fact, I think cpu detection is a bad way to do it.
Quoted 7 lines
hardcode it via machine ID is not good
Quoted 6 lines
So if you want a way to
differentiate carrier boards, then I think that needs to be discussed with other sub-architecture maintainers so that a common approach can be devised. I don't think that cpu detection is a robust solution. Device tree is probably the long-term solution to this.Quoted 8 lines
Quoted 4 lines
In short, your soc detection patches add additional complexity, but have zero effect on the possibility of supporting all of the current mainline at91 platforms in a single kernel. We need to fix the other barriers to this support first (such as the work Andrew Victor is doing).
Which can be also simply be knowning the CPU you are on
If you take a look on other arch they do cpu detection and there is nothing wrong about it.
There is nothing wrong with the current solution for at91, yet you are trying to add code which is confusing (two sets of
cpu_ismacros) and adds more lines for something which_alreadyworks_.
Quoted 5 lines
This argument is getting frustrating. My current objections to this patch are:
- The current solution (explicitly specifying the soc type) works for all of the at91 boards currently in mainline.
why do you we redisign the 5series are based on som so when we will add the cpu from Atmel we will have to solve this again wow great
Quoted 5 lines
- It adds two sets of
cpu_ismacros (second set with __ prefix), which is confusing and pointless.
- You have implied that the__cpu_ismacros will be removed at a later date. Since they are basically useless now, this is just more code churn when we are trying to reduce it on ARM.
so we will re-add it later no-way
Quoted 2 lines
- The patch as it stands won't work in a unified at91 kernel because the address of the DBGU registers is different on some at91 platforms.
we just have 2 diffents register common stop it
it's not the case we have one for each soc
Quoted 2 lines
- By itself this patch adds complexity without fixing anything and without introducing any functional change.
except you propose to add 100s of new function for each soc when the soc init is exactly the same same add copy paste for nothing
Quoted 3 lines
- There are other barriers to having a unified at91 kernel which need to be solved first. This patch is trying to jump ahead and solve problems that don't exist yet.
except the swtich to the common AT91_BASE_SYS, switch of the timers, gpio to platfrom_device, clkdev do fix it
Best Regards,
J.
PATCH 5/14 at91: use structure to store the current soc
In reply to Ryan MallonQuoted 4 lines · Ryan Mallon
Russell, what is your opinion on this? Should we use individual mach-types for the above boards and have them explicitly specify their cpu/soc type, or should we be aiming to have a single mach-type for all of them and determine the cpu/soc type in code?
I don't like answering these questions because it requires understanding the differences between the various individual SoCs to determine what's possible.
You are correct that CPU type is determined at run-time by the kernel, and whether its an 920T or 926T CPU is neither here or there to the kernel. It's really the SoC type that's the problem, and we don't have a very good way of specifying that (partly as there is no standard way to tell what sort of SoC we have.)
So, really, it's a platform specific question. If there is some way that the SoC type can be detected from the hardware, that may be an appropriate way to deal with that issue. If not, then the mach-type approach (which I assume is what AT91 currently does) is probably as good as any other until we have something like DT.
PATCH 5/14 at91: use structure to store the current soc
Quoted 16 lines · Russell King - ARM Linux
Quoted 4 lines · Ryan Mallon
Russell, what is your opinion on this? Should we use individual mach-types for the above boards and have them explicitly specify their cpu/soc type, or should we be aiming to have a single mach-type for all of them and determine the cpu/soc type in code?
I don't like answering these questions because it requires understanding the differences between the various individual SoCs to determine what's possible.
You are correct that CPU type is determined at run-time by the kernel, and whether its an 920T or 926T CPU is neither here or there to the kernel. It's really the SoC type that's the problem, and we don't have a very good way of specifying that (partly as there is no standard way to tell what sort of SoC we have.)
Quoted 5 lines
So, really, it's a platform specific question. If there is some way that the SoC type can be detected from the hardware, that may be an appropriate way to deal with that issue. If not, then the mach-type approach (which I assume is what AT91 currently does) is probably as good as any other until we have something like DT.
Except we have Russell it's we need to read 2 registers differents
which is 0x0 if does not containt a cpu id
or or the cpu id of the current chip
So I do not see the big deal
Best Regards,
J.
PATCH v3 6/14 at91: switch to CLKDEV_LOOKUP
In reply to Jean-Christophe PLAGNIOL-VILLARDwe do not change the clock naming convention so does not need to switch the AVR32 yet
---
v3:
udpate at91x40
Best Regards,
J.
arch/arm/Kconfig | 1 + arch/arm/mach-at91/at572d940hf.c | 64 +++++++++++++++++++++++ arch/arm/mach-at91/at572d940hf_devices.c | 22 ++++---- arch/arm/mach-at91/at91cap9.c | 58 ++++++++++++++++++++ arch/arm/mach-at91/at91cap9_devices.c | 28 ++++------ arch/arm/mach-at91/at91rm9200.c | 50 ++++++++++++++++++ arch/arm/mach-at91/at91rm9200_devices.c | 28 ++++------ arch/arm/mach-at91/at91sam9260.c | 51 ++++++++++++++++++ arch/arm/mach-at91/at91sam9260_devices.c | 31 ++++------- arch/arm/mach-at91/at91sam9261.c | 55 +++++++++++++++++++ arch/arm/mach-at91/at91sam9261_devices.c | 26 ++++----- arch/arm/mach-at91/at91sam9263.c | 54 +++++++++++++++++++ arch/arm/mach-at91/at91sam9263_devices.c | 24 ++++---- arch/arm/mach-at91/at91sam9g45.c | 84 +++++++++++++++++++++++------- arch/arm/mach-at91/at91sam9g45_devices.c | 31 ++++------- arch/arm/mach-at91/at91sam9rl.c | 51 ++++++++++++++++++ arch/arm/mach-at91/at91sam9rl_devices.c | 27 ++++----- arch/arm/mach-at91/at91x40.c | 5 -- arch/arm/mach-at91/clock.c | 54 +++++-------------- arch/arm/mach-at91/clock.h | 19 ++++++- arch/arm/mach-at91/generic.h | 12 ++++- arch/arm/mach-at91/include/mach/clkdev.h | 7 +++ 22 files changed, 595 insertions(+), 187 deletions(-) create mode 100644 arch/arm/mach-at91/include/mach/clkdev.h
arch/arm/Kconfig +1 -0
@@ -288,6 +288,7 @@ config ARCH_AT91 bool "Atmel AT91" select ARCH_REQUIRE_GPIOLIB select HAVE_CLK + select CLKDEV_LOOKUP help This enables support for systems based on the Atmel AT91RM9200, AT91SAM9 and AT91CAP9 processors.
arch/arm/mach-at91/at572d940hf.c +64 -0
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arch/arm/mach-at91/at572d940hf_devices.c +12 -10
@@ -532,7 +532,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PA1 ,0 );/* SPI0_MOSI */ at91_set_A_periph (AT91_PIN_PA2 ,0 );/* SPI0_SPCK */ -at91_clock_associate ("spi0_clk" , &at572d940hf_spi0_device.dev,"spi_clk" );platform_device_register (&at572d940hf_spi0_device); }if (enable_spi1) {
@@ -540,7 +539,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PC1 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PC2 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at572d940hf_spi1_device.dev,"spi_clk" );platform_device_register (&at572d940hf_spi1_device); } }
@@ -588,9 +586,6 @@ static struct platform_device at572d940hf_tcb_device = {static void __init at91_add_device_tc (void ) {/* this chip has a separate clock and irq for each TC channel */ -at91_clock_associate ("tc0_clk" , &at572d940hf_tcb_device.dev,"t0_clk" ); -at91_clock_associate ("tc1_clk" , &at572d940hf_tcb_device.dev,"t1_clk" ); -at91_clock_associate ("tc2_clk" , &at572d940hf_tcb_device.dev,"t2_clk" );platform_device_register (&at572d940hf_tcb_device); }#else
@@ -828,22 +823,18 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at572d940hf_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT572D940HF_ID_US0 : pdev = &at572d940hf_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT572D940HF_ID_US1 : pdev = &at572d940hf_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT572D940HF_ID_US2 : pdev = &at572d940hf_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -855,10 +846,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at572d940hf_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91cap9.c +58 -0
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arch/arm/mach-at91/at91cap9_devices.c +12 -16
@@ -181,10 +181,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)/* Pullup pin is handled internally by USB device peripheral */ -/* Clocks */ -at91_clock_associate ("utmi_clk" , &at91_usba_udc_device.dev,"hclk" ); -at91_clock_associate ("udphs_clk" , &at91_usba_udc_device.dev,"pclk" ); - platform_device_register(&at91_usba_udc_device); }#else
@@ -355,7 +351,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc0_data = *data; -at91_clock_associate ("mci0_clk" , &at91cap9_mmc0_device.dev,"mci_clk" );platform_device_register (&at91cap9_mmc0_device); }else {/* MCI1 */ /* CLK */
@@ -373,7 +368,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc1_data = *data; -at91_clock_associate ("mci1_clk" , &at91cap9_mmc1_device.dev,"mci_clk" );platform_device_register (&at91cap9_mmc1_device); } }
@@ -614,7 +608,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_B_periph (AT91_PIN_PA1 ,0 );/* SPI0_MOSI */ at91_set_B_periph (AT91_PIN_PA2 ,0 );/* SPI0_SPCK */ -at91_clock_associate ("spi0_clk" , &at91cap9_spi0_device.dev,"spi_clk" );platform_device_register (&at91cap9_spi0_device); }if (enable_spi1) {
@@ -622,7 +615,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB13 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PB14 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at91cap9_spi1_device.dev,"spi_clk" );platform_device_register (&at91cap9_spi1_device); } }
@@ -660,7 +652,6 @@ static struct platform_device at91cap9_tcb_device = {static void __init at91_add_device_tc (void ) {/* this chip has one clock and irq for all three TC channels */ -at91_clock_associate ("tcb_clk" , &at91cap9_tcb_device.dev,"t0_clk" );platform_device_register (&at91cap9_tcb_device); }#else
@@ -1001,12 +992,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91CAP9_ID_SSC0 : pdev = &at91cap9_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"ssc" );break ;case AT91CAP9_ID_SSC1 : pdev = &at91cap9_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"ssc" );break ;default :return ;
@@ -1205,22 +1194,18 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91cap9_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91CAP9_ID_US0 : pdev = &at91cap9_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91CAP9_ID_US1 : pdev = &at91cap9_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91CAP9_ID_US2 : pdev = &at91cap9_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1232,10 +1217,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91cap9_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91rm9200.c +50 -0
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arch/arm/mach-at91/at91rm9200_devices.c +12 -16
@@ -645,14 +645,7 @@ static struct platform_device at91rm9200_tcb1_device = {static void __init at91_add_device_tc (void ) {/* this chip has a separate clock and irq for each TC channel */ -at91_clock_associate ("tc0_clk" , &at91rm9200_tcb0_device.dev,"t0_clk" ); -at91_clock_associate ("tc1_clk" , &at91rm9200_tcb0_device.dev,"t1_clk" ); -at91_clock_associate ("tc2_clk" , &at91rm9200_tcb0_device.dev,"t2_clk" );platform_device_register (&at91rm9200_tcb0_device); - -at91_clock_associate ("tc3_clk" , &at91rm9200_tcb1_device.dev,"t0_clk" ); -at91_clock_associate ("tc4_clk" , &at91rm9200_tcb1_device.dev,"t1_clk" ); -at91_clock_associate ("tc5_clk" , &at91rm9200_tcb1_device.dev,"t2_clk" );platform_device_register (&at91rm9200_tcb1_device); }#else
@@ -849,17 +842,14 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91RM9200_ID_SSC0 : pdev = &at91rm9200_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"ssc" );break ;case AT91RM9200_ID_SSC1 : pdev = &at91rm9200_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"ssc" );break ;case AT91RM9200_ID_SSC2 : pdev = &at91rm9200_ssc2_device;configure_ssc2_pins (pins); -at91_clock_associate ("ssc2_clk" , &pdev->dev,"ssc" );break ;default :return ;
@@ -1115,27 +1105,22 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91rm9200_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91RM9200_ID_US0 : pdev = &at91rm9200_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91RM9200_ID_US1 : pdev = &at91rm9200_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91RM9200_ID_US2 : pdev = &at91rm9200_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;case AT91RM9200_ID_US3 : pdev = &at91rm9200_uart3_device;configure_usart3_pins (pins); -at91_clock_associate ("usart3_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1147,10 +1132,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91rm9200_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91sam9260.c +51 -0
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arch/arm/mach-at91/at91sam9260_devices.c +12 -19
@@ -609,7 +609,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PA1 ,0 );/* SPI0_MOSI */ at91_set_A_periph (AT91_PIN_PA2 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi0_clk" , &at91sam9260_spi0_device.dev,"spi_clk" );platform_device_register (&at91sam9260_spi0_device); }if (enable_spi1) {
@@ -617,7 +616,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB1 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PB2 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at91sam9260_spi1_device.dev,"spi_clk" );platform_device_register (&at91sam9260_spi1_device); } }
@@ -694,15 +692,7 @@ static struct platform_device at91sam9260_tcb1_device = {static void __init at91_add_device_tc (void ) { -/* this chip has a separate clock and irq for each TC channel */ -at91_clock_associate ("tc0_clk" , &at91sam9260_tcb0_device.dev,"t0_clk" ); -at91_clock_associate ("tc1_clk" , &at91sam9260_tcb0_device.dev,"t1_clk" ); -at91_clock_associate ("tc2_clk" , &at91sam9260_tcb0_device.dev,"t2_clk" );platform_device_register (&at91sam9260_tcb0_device); - -at91_clock_associate ("tc3_clk" , &at91sam9260_tcb1_device.dev,"t0_clk" ); -at91_clock_associate ("tc4_clk" , &at91sam9260_tcb1_device.dev,"t1_clk" ); -at91_clock_associate ("tc5_clk" , &at91sam9260_tcb1_device.dev,"t2_clk" );platform_device_register (&at91sam9260_tcb1_device); }#else
@@ -820,7 +810,6 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91SAM9260_ID_SSC : pdev = &at91sam9260_ssc_device;configure_ssc_pins (pins); -at91_clock_associate ("ssc_clk" , &pdev->dev,"pclk" );break ;default :return ;
@@ -1145,37 +1134,30 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91sam9260_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US0 : pdev = &at91sam9260_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US1 : pdev = &at91sam9260_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US2 : pdev = &at91sam9260_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US3 : pdev = &at91sam9260_uart3_device;configure_usart3_pins (pins); -at91_clock_associate ("usart3_clk" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US4 : pdev = &at91sam9260_uart4_device;configure_usart4_pins (); -at91_clock_associate ("usart4_clk" , &pdev->dev,"usart" );break ;case AT91SAM9260_ID_US5 : pdev = &at91sam9260_uart5_device;configure_usart5_pins (); -at91_clock_associate ("usart5_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1187,10 +1169,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91sam9260_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91sam9261.c +55 -0
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arch/arm/mach-at91/at91sam9261_devices.c +12 -14
@@ -426,7 +426,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PA1 ,0 );/* SPI0_MOSI */ at91_set_A_periph (AT91_PIN_PA2 ,0 );/* SPI0_SPCK */ -at91_clock_associate ("spi0_clk" , &at91sam9261_spi0_device.dev,"spi_clk" );platform_device_register (&at91sam9261_spi0_device); }if (enable_spi1) {
@@ -434,7 +433,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB31 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PB29 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at91sam9261_spi1_device.dev,"spi_clk" );platform_device_register (&at91sam9261_spi1_device); } }
@@ -581,10 +579,6 @@ static struct platform_device at91sam9261_tcb_device = {static void __init at91_add_device_tc (void ) { -/* this chip has a separate clock and irq for each TC channel */ -at91_clock_associate ("tc0_clk" , &at91sam9261_tcb_device.dev,"t0_clk" ); -at91_clock_associate ("tc1_clk" , &at91sam9261_tcb_device.dev,"t1_clk" ); -at91_clock_associate ("tc2_clk" , &at91sam9261_tcb_device.dev,"t2_clk" );platform_device_register (&at91sam9261_tcb_device); }#else
@@ -786,17 +780,14 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91SAM9261_ID_SSC0 : pdev = &at91sam9261_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"pclk" );break ;case AT91SAM9261_ID_SSC1 : pdev = &at91sam9261_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"pclk" );break ;case AT91SAM9261_ID_SSC2 : pdev = &at91sam9261_ssc2_device;configure_ssc2_pins (pins); -at91_clock_associate ("ssc2_clk" , &pdev->dev,"pclk" );break ;default :return ;
@@ -995,22 +986,18 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91sam9261_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91SAM9261_ID_US0 : pdev = &at91sam9261_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91SAM9261_ID_US1 : pdev = &at91sam9261_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91SAM9261_ID_US2 : pdev = &at91sam9261_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1022,10 +1009,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91sam9261_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91sam9263.c +54 -0
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arch/arm/mach-at91/at91sam9263_devices.c +12 -12
@@ -308,7 +308,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc0_data = *data; -at91_clock_associate ("mci0_clk" , &at91sam9263_mmc0_device.dev,"mci_clk" );platform_device_register (&at91sam9263_mmc0_device); }else {/* MCI1 */ /* CLK */
@@ -339,7 +338,6 @@ void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) } mmc1_data = *data; -at91_clock_associate ("mci1_clk" , &at91sam9263_mmc1_device.dev,"mci_clk" );platform_device_register (&at91sam9263_mmc1_device); } }
@@ -686,7 +684,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_B_periph (AT91_PIN_PA1 ,0 );/* SPI0_MOSI */ at91_set_B_periph (AT91_PIN_PA2 ,0 );/* SPI0_SPCK */ -at91_clock_associate ("spi0_clk" , &at91sam9263_spi0_device.dev,"spi_clk" );platform_device_register (&at91sam9263_spi0_device); }if (enable_spi1) {
@@ -694,7 +691,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB13 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PB14 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at91sam9263_spi1_device.dev,"spi_clk" );platform_device_register (&at91sam9263_spi1_device); } }
@@ -942,7 +938,6 @@ static struct platform_device at91sam9263_tcb_device = {static void __init at91_add_device_tc (void ) {/* this chip has one clock and irq for all three TC channels */ -at91_clock_associate ("tcb_clk" , &at91sam9263_tcb_device.dev,"t0_clk" );platform_device_register (&at91sam9263_tcb_device); }#else
@@ -1171,12 +1166,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91SAM9263_ID_SSC0 : pdev = &at91sam9263_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"pclk" );break ;case AT91SAM9263_ID_SSC1 : pdev = &at91sam9263_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"pclk" );break ;default :return ;
@@ -1376,22 +1369,18 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91sam9263_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91SAM9263_ID_US0 : pdev = &at91sam9263_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91SAM9263_ID_US1 : pdev = &at91sam9263_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91SAM9263_ID_US2 : pdev = &at91sam9263_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1403,10 +1392,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91sam9263_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91sam9g45.c +65 -19
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arch/arm/mach-at91/at91sam9g45_devices.c +12 -19
@@ -180,7 +180,6 @@ void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) } usbh_ehci_data = *data; -at91_clock_associate ("uhphs_clk" , &at91_usbh_ehci_device.dev,"ehci_clk" );platform_device_register (&at91_usbh_ehci_device); }#else
@@ -266,10 +265,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)/* Pullup pin is handled internally by USB device peripheral */ -/* Clocks */ -at91_clock_associate ("utmi_clk" , &at91_usba_udc_device.dev,"hclk" ); -at91_clock_associate ("udphs_clk" , &at91_usba_udc_device.dev,"pclk" ); - platform_device_register(&at91_usba_udc_device); }#else
@@ -478,7 +473,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) } mmc0_data = *data; -at91_clock_associate ("mci0_clk" , &at91sam9g45_mmc0_device.dev,"mci_clk" );platform_device_register (&at91sam9g45_mmc0_device); }else {/* MCI1 */
@@ -504,7 +498,6 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data) } mmc1_data = *data; -at91_clock_associate ("mci1_clk" , &at91sam9g45_mmc1_device.dev,"mci_clk" );platform_device_register (&at91sam9g45_mmc1_device); }
@@ -801,7 +794,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB1 ,0 );/* SPI0_MOSI */ at91_set_A_periph (AT91_PIN_PB2 ,0 );/* SPI0_SPCK */ -at91_clock_associate ("spi0_clk" , &at91sam9g45_spi0_device.dev,"spi_clk" );platform_device_register (&at91sam9g45_spi0_device); }if (enable_spi1) {
@@ -809,7 +801,6 @@ void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)at91_set_A_periph (AT91_PIN_PB15 ,0 );/* SPI1_MOSI */ at91_set_A_periph (AT91_PIN_PB16 ,0 );/* SPI1_SPCK */ -at91_clock_associate ("spi1_clk" , &at91sam9g45_spi1_device.dev,"spi_clk" );platform_device_register (&at91sam9g45_spi1_device); } }
@@ -1000,9 +991,7 @@ static struct platform_device at91sam9g45_tcb1_device = {static void __init at91_add_device_tc (void ) {/* this chip has one clock and irq for all six TC channels */ -at91_clock_associate ("tcb0_clk" , &at91sam9g45_tcb0_device.dev,"t0_clk" );platform_device_register (&at91sam9g45_tcb0_device); -at91_clock_associate ("tcb1_clk" , &at91sam9g45_tcb1_device.dev,"t0_clk" );platform_device_register (&at91sam9g45_tcb1_device); }#else
@@ -1286,12 +1275,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91SAM9G45_ID_SSC0 : pdev = &at91sam9g45_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"pclk" );break ;case AT91SAM9G45_ID_SSC1 : pdev = &at91sam9g45_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"pclk" );break ;default :return ;
@@ -1533,27 +1520,22 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91sam9g45_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91SAM9G45_ID_US0 : pdev = &at91sam9g45_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91SAM9G45_ID_US1 : pdev = &at91sam9g45_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91SAM9G45_ID_US2 : pdev = &at91sam9g45_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;case AT91SAM9G45_ID_US3 : pdev = &at91sam9g45_uart3_device;configure_usart3_pins (pins); -at91_clock_associate ("usart3_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1565,10 +1547,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91sam9g45_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91sam9rl.c +51 -0
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arch/arm/mach-at91/at91sam9rl_devices.c +12 -15
@@ -155,10 +155,6 @@ void __init at91_add_device_usba(struct usba_platform_data *data)/* Pullup pin is handled internally by USB device peripheral */ -/* Clocks */ -at91_clock_associate ("utmi_clk" , &at91_usba_udc_device.dev,"hclk" ); -at91_clock_associate ("udphs_clk" , &at91_usba_udc_device.dev,"pclk" ); - platform_device_register(&at91_usba_udc_device); }#else
@@ -606,9 +602,6 @@ static struct platform_device at91sam9rl_tcb_device = {static void __init at91_add_device_tc (void ) {/* this chip has a separate clock and irq for each TC channel */ -at91_clock_associate ("tc0_clk" , &at91sam9rl_tcb_device.dev,"t0_clk" ); -at91_clock_associate ("tc1_clk" , &at91sam9rl_tcb_device.dev,"t1_clk" ); -at91_clock_associate ("tc2_clk" , &at91sam9rl_tcb_device.dev,"t2_clk" );platform_device_register (&at91sam9rl_tcb_device); }#else
@@ -892,12 +885,10 @@ void __init at91_add_device_ssc(unsigned id, unsigned pins)case AT91SAM9RL_ID_SSC0 : pdev = &at91sam9rl_ssc0_device;configure_ssc0_pins (pins); -at91_clock_associate ("ssc0_clk" , &pdev->dev,"pclk" );break ;case AT91SAM9RL_ID_SSC1 : pdev = &at91sam9rl_ssc1_device;configure_ssc1_pins (pins); -at91_clock_associate ("ssc1_clk" , &pdev->dev,"pclk" );break ;default :return ;
@@ -1147,27 +1138,22 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)case 0 :/* DBGU */ pdev = &at91sam9rl_dbgu_device;configure_dbgu_pins (); -at91_clock_associate ("mck" , &pdev->dev,"usart" );break ;case AT91SAM9RL_ID_US0 : pdev = &at91sam9rl_uart0_device;configure_usart0_pins (pins); -at91_clock_associate ("usart0_clk" , &pdev->dev,"usart" );break ;case AT91SAM9RL_ID_US1 : pdev = &at91sam9rl_uart1_device;configure_usart1_pins (pins); -at91_clock_associate ("usart1_clk" , &pdev->dev,"usart" );break ;case AT91SAM9RL_ID_US2 : pdev = &at91sam9rl_uart2_device;configure_usart2_pins (pins); -at91_clock_associate ("usart2_clk" , &pdev->dev,"usart" );break ;case AT91SAM9RL_ID_US3 : pdev = &at91sam9rl_uart3_device;configure_usart3_pins (pins); -at91_clock_associate ("usart3_clk" , &pdev->dev,"usart" );break ;default :return ;
@@ -1179,10 +1165,21 @@ void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) at91_uarts[portnr] = pdev; } +static struct clk_lookup console_lookups = { + .con_id ="usart" , +}; +void __init at91_set_serial_console (unsigned portnr) { -if (portnr <ATMEL_MAX_UART ) +struct atmel_uart_data *pdata; + +if (portnr <ATMEL_MAX_UART ) { atmel_default_console_device = at91_uarts[portnr]; + + pdata = atmel_default_console_device->dev.platform_data; + console_lookups.clk =at91sam9rl_get_uart_clock (pdata->num); +clkdev_add (&console_lookups); + } }void __init at91_add_device_serial (void )
arch/arm/mach-at91/at91x40.c +0 -5
@@ -37,11 +37,6 @@ unsigned long clk_get_rate(struct clk *clk)return AT91X40_MASTER_CLOCK ; } -struct clk *clk_get (struct device *dev,const char *id) -{ -return NULL ; -} -void __init at91x40_initialize (unsigned long main_clock) { at91_extern_irq = (1 <<AT91X40_ID_IRQ0 ) | (1 <<AT91X40_ID_IRQ1 )
arch/arm/mach-at91/clock.c +15 -39
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arch/arm/mach-at91/clock.h +17 -2
@@ -6,6 +6,8 @@* published by the Free Software Foundation. */ +#include <linux/clkdev.h> +#define CLK_TYPE_PRIMARY 0x1#define CLK_TYPE_PLL 0x2#define CLK_TYPE_PROGRAMMABLE 0x4
@@ -16,8 +18,6 @@struct clk {struct list_head node;const char *name;/* unique clock name */ -const char *function;/* function of the clock */ -struct device *dev;/* device associated with function */ unsigned long rate_hz;struct clk *parent;u32 pmc_mask;
@@ -29,3 +29,18 @@ struct clk {extern int __init clk_register (struct clk *clk); +extern struct clk mck; +extern struct clk utmi_clk; + +#define CLKDEV_CON_ID (_id, _clk) \ + { \ + .con_id = _id, \ + .clk = _clk, \ + } + +#define CLKDEV_CON_DEV_ID (_con_id, _dev_id, _clk) \ + { \ + .con_id = _con_id, \ + .dev_id = _dev_id, \ + .clk = _clk, \ + }
arch/arm/mach-at91/generic.h +11 -1
@@ -8,6 +8,8 @@* published by the Free Software Foundation. */ +#include <linux/clkdev.h> +/* Processors */ extern void __init at91rm9200_set_type (int type);extern void __init at91_initialize (unsigned long main_clock);
@@ -26,8 +28,16 @@ extern struct sys_timer at91x40_timer;/* Clocks */ extern int __init at91_clock_init (unsigned long main_clock); +extern struct clk *__init at91rm9200_get_uart_clock (int id); +extern struct clk *__init at91sam9260_get_uart_clock (int id); +extern struct clk *__init at91sam9261_get_uart_clock (int id); +extern struct clk *__init at91sam9263_get_uart_clock (int id); +extern struct clk *__init at91sam9rl_get_uart_clock (int id); +extern struct clk *__init at91sam9g45_get_uart_clock (int id); +extern struct clk *__init at91x40_get_uart_clock (int id); +extern struct clk *__init at91cap9_get_uart_clock (int id); +extern struct clk *__init at572d940hf_get_uart_clock (int id);struct device ; -extern void __init at91_clock_associate (const char *id,struct device *dev,const char *func);/* Power Management */ extern void at91_irq_suspend (void );
arch/arm/mach-at91/include/mach/clkdev.h new file +7 -0
@@ -0,0 +1,7 @@ +#ifndef __ASM_MACH_CLKDEV_H +#define __ASM_MACH_CLKDEV_H + +#define __clk_get (clk) ({ 1; }) +#define __clk_put (clk) do { } while (0) + +#endif
Signature · 1 line
1.7.4.1
PATCH 7/14 at91: switch gpio to early platfrom device
In reply to Jean-Christophe PLAGNIOL-VILLARD---
need patch
clkdev: add support to lookup for early platform device
Best Regards,
J.
arch/arm/mach-at91/at572d940hf.c | 30 ++++++------ arch/arm/mach-at91/at91cap9.c | 34 +++++++------- arch/arm/mach-at91/at91rm9200.c | 43 +++++++++-------- arch/arm/mach-at91/at91sam9260.c | 30 ++++++------ arch/arm/mach-at91/at91sam9261.c | 30 ++++++------ arch/arm/mach-at91/at91sam9263.c | 42 ++++++++--------- arch/arm/mach-at91/at91sam9g45.c | 43 ++++++++--------- arch/arm/mach-at91/at91sam9rl.c | 37 +++++++-------- arch/arm/mach-at91/clock.h | 6 ++ arch/arm/mach-at91/devices.c | 15 ++++++ arch/arm/mach-at91/devices.h | 55 +++++++++++++++++++++ arch/arm/mach-at91/generic.h | 6 -- arch/arm/mach-at91/gpio.c | 78 +++++++++++++++++++----------- arch/arm/mach-at91/soc.c | 97 ++++++++++++++++++++++++++++++++++++++ arch/arm/mach-at91/soc.h | 4 ++ 15 files changed, 365 insertions(+), 185 deletions(-) create mode 100644 arch/arm/mach-at91/devices.c create mode 100644 arch/arm/mach-at91/devices.h
arch/arm/mach-at91/at572d940hf.c +14 -16
@@ -202,9 +202,9 @@ static struct clk *periph_clocks[] __initdata = { };static struct clk_lookup periph_clocks_lookups[] = { -CLKDEV_CON_ID ("pioA_clk" , &pioA_clk), -CLKDEV_CON_ID ("pioB_clk" , &pioB_clk), -CLKDEV_CON_ID ("pioC_clk" , &pioC_clk), +CLKDEV_DEV_ID ("at91_gpio.0" , &pioA_clk), +CLKDEV_DEV_ID ("at91_gpio.1" , &pioB_clk), +CLKDEV_DEV_ID ("at91_gpio.2" , &pioC_clk),CLKDEV_CON_ID ("macb_clk" , &macb_clk),CLKDEV_CON_ID ("mci_clk" , &mmc_clk),CLKDEV_CON_ID ("udc_clk" , &udc_clk),
@@ -336,19 +336,16 @@ struct clk* __init at572d940hf_get_uart_clock(int id)* GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at572d940hf_gpio[] = { +static struct at91_dev_resource at572d940hf_pios[]__initdata = { { - .id =AT572D940HF_ID_PIOA , - .offset =AT91_PIOA , - .clock = &pioA_clk, + .mmio_base =AT91_PIOA , + .irq =AT572D940HF_ID_PIOA , }, { - .id =AT572D940HF_ID_PIOB , - .offset =AT91_PIOB , - .clock = &pioB_clk, + .mmio_base =AT91_PIOB , + .irq =AT572D940HF_ID_PIOB , }, { - .id =AT572D940HF_ID_PIOC , - .offset =AT91_PIOC , - .clock = &pioC_clk, + .mmio_base =AT91_PIOC , + .irq =AT572D940HF_ID_PIOC , } };
@@ -376,9 +373,6 @@ static void __init at572d940hf_initialize(unsigned long main_clock)/* Register the processor-specific clocks */ at572d940hf_register_clocks (); - -/* Register GPIO subsystem */ -at91_gpio_init (at572d940hf_gpio,3 ); }/* --------------------------------------------------------------------
@@ -427,4 +421,8 @@ struct at91_soc __initdata at572d940hf_soc = { .name = "at572d940hf", .default_irq_priority = at572d940hf_default_irq_priority, .init = at572d940hf_initialize, + .gpio = { + .resource = at572d940hf_pios, + .num_resources = ARRAY_SIZE(at572d940hf_pios), + }, };
arch/arm/mach-at91/at91cap9.c +17 -17
@@ -219,7 +219,10 @@ static struct clk *periph_clocks[] __initdata = { };static struct clk_lookup periph_clocks_lookups[] = { -CLKDEV_CON_ID ("pioABCD_clk" , &pioABCD_clk), +CLKDEV_DEV_ID ("at91_gpio.0" , &pioABCD_clk), +CLKDEV_DEV_ID ("at91_gpio.1" , &pioABCD_clk), +CLKDEV_DEV_ID ("at91_gpio.2" , &pioABCD_clk), +CLKDEV_DEV_ID ("at91_gpio.3" , &pioABCD_clk),CLKDEV_CON_ID ("mpb0_clk" , &mpb0_clk),CLKDEV_CON_ID ("mpb1_clk" , &mpb1_clk),CLKDEV_CON_ID ("mpb2_clk" , &mpb2_clk),
@@ -322,23 +325,19 @@ struct clk* __init at91cap9_get_uart_clock(int id)* GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91cap9_gpio[] = { +static struct at91_dev_resource at91cap9_pios[]__initdata = { { - .id =AT91CAP9_ID_PIOABCD , - .offset =AT91_PIOA , - .clock = &pioABCD_clk, + .mmio_base =AT91_PIOA , + .irq =AT91CAP9_ID_PIOABCD , }, { - .id =AT91CAP9_ID_PIOABCD , - .offset =AT91_PIOB , - .clock = &pioABCD_clk, + .mmio_base =AT91_PIOB , + .irq =AT91CAP9_ID_PIOABCD , }, { - .id =AT91CAP9_ID_PIOABCD , - .offset =AT91_PIOC , - .clock = &pioABCD_clk, + .mmio_base =AT91_PIOC , + .irq =AT91CAP9_ID_PIOABCD , }, { - .id =AT91CAP9_ID_PIOABCD , - .offset =AT91_PIOD , - .clock = &pioABCD_clk, + .mmio_base =AT91_PIOD , + .irq =AT91CAP9_ID_PIOABCD , } };
@@ -372,9 +371,6 @@ static void __init at91cap9_initialize(unsigned long main_clock)/* Register the processor-specific clocks */ at91cap9_register_clocks (); -/* Register GPIO subsystem */ -at91_gpio_init (at91cap9_gpio,4 ); -/* Remember the silicon revision */ if (cpu_is_at91cap9_revB ()) system_rev =0xB ;
@@ -428,4 +424,8 @@ struct at91_soc __initdata at91cap9_soc = { .name = "at91cap9", .default_irq_priority = at91cap9_default_irq_priority, .init = at91cap9_initialize, + .gpio = { + .resource = at91cap9_pios, + .num_resources = ARRAY_SIZE(at91cap9_pios), + }, };
arch/arm/mach-at91/at91rm9200.c +22 -21
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arch/arm/mach-at91/at91sam9260.c +14 -16
@@ -215,9 +215,9 @@ static struct clk *periph_clocks[] __initdata = { };static struct clk_lookup periph_clocks_lookups[] = { -CLKDEV_CON_ID ("pioA_clk" , &pioA_clk), -CLKDEV_CON_ID ("pioB_clk" , &pioB_clk), -CLKDEV_CON_ID ("pioC_clk" , &pioC_clk), +CLKDEV_DEV_ID ("at91_gpio.0" , &pioA_clk), +CLKDEV_DEV_ID ("at91_gpio.1" , &pioB_clk), +CLKDEV_DEV_ID ("at91_gpio.2" , &pioC_clk),CLKDEV_CON_ID ("adc_clk" , &adc_clk),CLKDEV_CON_ID ("mci_clk" , &mmc_clk),CLKDEV_CON_ID ("udc_clk" , &udc_clk),
@@ -300,19 +300,16 @@ struct clk* __init at91sam9260_get_uart_clock(int id)* GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9260_gpio[] = { +static struct at91_dev_resource at91sam9260_pios[]__initdata = { { - .id =AT91SAM9260_ID_PIOA , - .offset =AT91_PIOA , - .clock = &pioA_clk, + .mmio_base =AT91_PIOA , + .irq =AT91SAM9260_ID_PIOA , }, { - .id =AT91SAM9260_ID_PIOB , - .offset =AT91_PIOB , - .clock = &pioB_clk, + .mmio_base =AT91_PIOB , + .irq =AT91SAM9260_ID_PIOB , }, { - .id =AT91SAM9260_ID_PIOC , - .offset =AT91_PIOC , - .clock = &pioC_clk, + .mmio_base =AT91_PIOC , + .irq =AT91SAM9260_ID_PIOC , } };
@@ -368,9 +365,6 @@ static void __init at91sam9260_initialize(unsigned long main_clock)/* Register the processor-specific clocks */ at91sam9260_register_clocks (); - -/* Register GPIO subsystem */ -at91_gpio_init (at91sam9260_gpio,3 ); }/* --------------------------------------------------------------------
@@ -419,4 +413,8 @@ struct at91_soc __initdata at91sam9260_soc = { .name = "at91sam9260", .default_irq_priority = at91sam9260_default_irq_priority, .init = at91sam9260_initialize, + .gpio = { + .resource = at91sam9260_pios, + .num_resources = ARRAY_SIZE(at91sam9260_pios), + }, };
arch/arm/mach-at91/at91sam9261.c +14 -16
@@ -171,9 +171,9 @@ static struct clk *periph_clocks[] __initdata = { };static struct clk_lookup periph_clocks_lookups[] = { -CLKDEV_CON_ID ("pioA_clk" , &pioA_clk), -CLKDEV_CON_ID ("pioB_clk" , &pioB_clk), -CLKDEV_CON_ID ("pioC_clk" , &pioC_clk), +CLKDEV_DEV_ID ("at91_gpio.0" , &pioA_clk), +CLKDEV_DEV_ID ("at91_gpio.1" , &pioB_clk), +CLKDEV_DEV_ID ("at91_gpio.2" , &pioC_clk),CLKDEV_CON_ID ("mci_clk" , &mmc_clk),CLKDEV_CON_ID ("udc_clk" , &udc_clk),CLKDEV_CON_ID ("twi_clk" , &twi_clk),
@@ -288,19 +288,16 @@ struct clk* __init at91sam9261_get_uart_clock(int id)* GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9261_gpio[] = { +static struct at91_dev_resource at91sam9261_pios[]__initdata = { { - .id =AT91SAM9261_ID_PIOA , - .offset =AT91_PIOA , - .clock = &pioA_clk, + .mmio_base =AT91_PIOA , + .irq =AT91SAM9261_ID_PIOA , }, { - .id =AT91SAM9261_ID_PIOB , - .offset =AT91_PIOB , - .clock = &pioB_clk, + .mmio_base =AT91_PIOB , + .irq =AT91SAM9261_ID_PIOB , }, { - .id =AT91SAM9261_ID_PIOC , - .offset =AT91_PIOC , - .clock = &pioC_clk, + .mmio_base =AT91_PIOC , + .irq =AT91SAM9261_ID_PIOC , } };
@@ -334,9 +331,6 @@ static void __init at91sam9261_initialize(unsigned long main_clock)/* Register the processor-specific clocks */ at91sam9261_register_clocks (); - -/* Register GPIO subsystem */ -at91_gpio_init (at91sam9261_gpio,3 ); }/* --------------------------------------------------------------------
@@ -385,4 +379,8 @@ struct at91_soc __initdata at91sam9261_soc = { .name = "at91sam9261", .default_irq_priority = at91sam9261_default_irq_priority, .init = at91sam9261_initialize, + .gpio = { + .resource = at91sam9261_pios, + .num_resources = ARRAY_SIZE(at91sam9261_pios), + }, };
arch/arm/mach-at91/at91sam9263.c +20 -22
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arch/arm/mach-at91/at91sam9g45.c +20 -23
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arch/arm/mach-at91/at91sam9rl.c +17 -20
@@ -184,10 +184,10 @@ static struct clk *periph_clocks[] __initdata = { };static struct clk_lookup periph_clocks_lookups[] = { -CLKDEV_CON_ID ("pioA_clk" , &pioA_clk), -CLKDEV_CON_ID ("pioB_clk" , &pioB_clk), -CLKDEV_CON_ID ("pioC_clk" , &pioC_clk), -CLKDEV_CON_ID ("pioD_clk" , &pioD_clk), +CLKDEV_DEV_ID ("at91_gpio.0" , &pioA_clk), +CLKDEV_DEV_ID ("at91_gpio.1" , &pioB_clk), +CLKDEV_DEV_ID ("at91_gpio.2" , &pioC_clk), +CLKDEV_DEV_ID ("at91_gpio.3" , &pioD_clk),CLKDEV_CON_ID ("mci_clk" , &mmc_clk),CLKDEV_CON_ID ("twi0_clk" , &twi0_clk),CLKDEV_CON_ID ("twi1_clk" , &twi1_clk),
@@ -266,23 +266,19 @@ struct clk* __init at91sam9rl_get_uart_clock(int id)* GPIO * -------------------------------------------------------------------- */ -static struct at91_gpio_bank at91sam9rl_gpio[] = { +static struct at91_dev_resource at91sam9rl_pios[]__initdata = { { - .id =AT91SAM9RL_ID_PIOA , - .offset =AT91_PIOA , - .clock = &pioA_clk, + .mmio_base =AT91_PIOA , + .irq =AT91SAM9RL_ID_PIOA , }, { - .id =AT91SAM9RL_ID_PIOB , - .offset =AT91_PIOB , - .clock = &pioB_clk, + .mmio_base =AT91_PIOB , + .irq =AT91SAM9RL_ID_PIOB , }, { - .id =AT91SAM9RL_ID_PIOC , - .offset =AT91_PIOC , - .clock = &pioC_clk, + .mmio_base =AT91_PIOC , + .irq =AT91SAM9RL_ID_PIOC , }, { - .id =AT91SAM9RL_ID_PIOD , - .offset =AT91_PIOD , - .clock = &pioD_clk, + .mmio_base =AT91_PIOD , + .irq =AT91SAM9RL_ID_PIOD , } };
@@ -328,9 +324,6 @@ static void __init at91sam9rl_initialize(unsigned long main_clock)/* Register the processor-specific clocks */ at91sam9rl_register_clocks (); - -/* Register GPIO subsystem */ -at91_gpio_init (at91sam9rl_gpio,4 ); }/* --------------------------------------------------------------------
@@ -379,4 +372,8 @@ struct at91_soc __initdata at91sam9rl_soc = { .name = "at91sam9rl", .default_irq_priority = at91sam9rl_default_irq_priority, .init = at91sam9rl_initialize, + .gpio = { + .resource = at91sam9rl_pios, + .num_resources = ARRAY_SIZE(at91sam9rl_pios), + }, };
arch/arm/mach-at91/clock.h +6 -0
@@ -32,6 +32,12 @@ extern int __init clk_register(struct clk *clk);extern struct clk mck;extern struct clk utmi_clk; +#define CLKDEV_DEV_ID (_id, _clk) \ + { \ + .dev_id = _id, \ + .clk = _clk, \ + } +#define CLKDEV_CON_ID (_id, _clk) \ { \ .con_id = _id, \
arch/arm/mach-at91/devices.c new file +15 -0
@@ -0,0 +1,15 @@ +/* +* Copyright (C) 2007 Stelian Pop <[email protected]> +* Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com> +* Copyright (C) 2007-2011 Atmel Corporation. +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +* +*/ + +#include <linux/platform_device.h> + +#include "devices.h" + +
arch/arm/mach-at91/devices.h new file +55 -0
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arch/arm/mach-at91/generic.h +0 -6
@@ -50,12 +50,6 @@ extern void at91sam9_alt_reset(void);#define AT91RM9200_PQFP 3/* AT91RM9200 PQFP package has 3 banks */ #define AT91RM9200_BGA 4/* AT91RM9200 BGA package has 4 banks */ -struct at91_gpio_bank { -unsigned short id;/* peripheral ID */ -unsigned long offset;/* offset from system peripheral base */ -struct clk *clock;/* associated clock */ -}; -extern void __init at91_gpio_init (struct at91_gpio_bank *,int nr_banks);extern void __init at91_gpio_irq_setup (void );extern void (*at91_arch_reset)(void );
arch/arm/mach-at91/gpio.c +50 -28
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arch/arm/mach-at91/soc.c +97 -0
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arch/arm/mach-at91/soc.h +4 -0
@@ -6,10 +6,14 @@* */ +#include "devices.h" +struct at91_soc {char *name;unsigned int *default_irq_priority; +struct at91_dev_resource_array gpio; +void (*init)(unsigned long main_clock); };
Signature · 1 line
1.7.4.1
PATCH 7/14 at91: switch gpio to early platfrom device
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>---
need patch
clkdev: add support to lookup for early platform device
<snip>
Quoted 49 lines
arch/arm/mach-at91/devices.h new file +43
-0@@ -0,0 +1,55 @@ +/* +* arch/arm/mach-at91/devices.h +* +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +* +*/ + +#ifndef _AT91_DEVICES_H +#define _AT91_DEVICES_H + +#include <linux/types.h> +#include <linux/platform_device.h> + +#define RES_MEM (size) \ + { \ + .end = size - 1, \ + .flags = IORESOURCE_MEM, \ + } + +#define RES_IRQ () \ + { \ + .flags = IORESOURCE_IRQ, \ + } + + +static inline void set_resource_mem (struct resource *res,resource_size_t mmio_base) +{ +BUG_ON (res->flags !=IORESOURCE_MEM ); + res->start = mmio_base; + res->end += mmio_base; +} + +static inline void set_resource_irq (struct resource *res,int irq) +{ +if (!irq) +return ; + +BUG_ON (res->flags !=IORESOURCE_IRQ ); + res->start = irq; + res->end = irq; +}
arch/arm/mach-at91/devices.h line 53
Quoted 10 lines
arch/arm/mach-at91/devices.h new file +10
-0+ +struct at91_dev_resource { +resource_size_t mmio_base; +int irq; +}; + +struct at91_dev_resource_array { +struct at91_dev_resource *resource; +int num_resources; +};
We will have to consolidate here since this conflicts with my patch set. Our approaches are pretty similar though, so hopefully it's not too big a deal. How do you want to manage the merging of our patches? Do you want to take my stuff via your tree and handle the merge there or do you want be to try rebasing my patches on top of a branch of your git tree?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 7/14 at91: switch gpio to early platfrom device
Quoted 67 lines · Ryan Mallon
Quoted 6 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>---
need patch
clkdev: add support to lookup for early platform device<snip>
Quoted 57 lines
arch/arm/mach-at91/devices.h new file +51
-0@@ -0,0 +1,55 @@ +/* +* arch/arm/mach-at91/devices.h +* +* Copyright (C) 2011 Jean-Christophe PLAGNIOL-VILLARD <[email protected]> +* +* Under GPLv2 +* +*/ + +#ifndef _AT91_DEVICES_H +#define _AT91_DEVICES_H + +#include <linux/types.h> +#include <linux/platform_device.h> + +#define RES_MEM(size) \ + { \ + .end = size - 1, \ + .flags = IORESOURCE_MEM, \ + } + +#define RES_IRQ() \ + { \ + .flags = IORESOURCE_IRQ, \ + } + + +static inline void set_resource_mem(struct resource *res, resource_size_t mmio_base) +{ + BUG_ON(res->flags != IORESOURCE_MEM); + res->start = mmio_base; + res->end += mmio_base; +} + +static inline void set_resource_irq(struct resource *res, int irq) +{ + if (!irq) + return; + + BUG_ON(res->flags != IORESOURCE_IRQ); + res->start = irq; + res->end = irq; +} + +struct at91_dev_resource { + resource_size_t mmio_base; + int irq; +}; + +struct at91_dev_resource_array { + struct at91_dev_resource *resource;
Quoted 8 lines
arch/arm/mach-at91/devices.h line 53
Quoted 2 lines
arch/arm/mach-at91/devices.h new file +2
-0+int num_resources; +};We will have to consolidate here since this conflicts with my patch set. Our approaches are pretty similar though, so hopefully it's not too big a deal. How do you want to manage the merging of our patches? Do you want to take my stuff via your tree and handle the merge there or do you want be to try rebasing my patches on top of a branch of your git tree?
I've start to rebase your patchset as this one will allw to simpliify it as we known on which we are on
until the udc
Let me 1 or 2 days to push it
It did test it on some atmel ref board and fix it
Best Regards,
J.
Quoted 11 lines
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 8/14 at91: move gpio to drivers/gpio
In reply to Jean-Christophe PLAGNIOL-VILLARD--- MAINTAINERS | 1 + arch/arm/mach-at91/Makefile | 2 +- drivers/gpio/Makefile | 1 + .../mach-at91/gpio.c => drivers/gpio/at91_gpio.c | 0 4 files changed, 3 insertions(+), 1 deletions(-) rename arch/arm/mach-at91/gpio.c => drivers/gpio/at91_gpio.c (100%)
MAINTAINERS +1 -0
@@ -654,6 +654,7 @@ W: http://maxim.org.za/at91_26.html W: http://www.linux4sam.org S: Supported F: arch/arm/mach-at91/ +F: drivers/gpio/at91_gpio.c ARM/BCMRING ARM ARCHITECTURE M: Jiandong Zheng <[email protected]>
arch/arm/mach-at91/Makefile +1 -1
@@ -2,7 +2,7 @@ # Makefile for the linux kernel. # -obj-y := irq.o gpio.o soc.o +obj-y := irq.o soc.o obj-m := obj-n := obj- :=
drivers/gpio/Makefile +1 -0
@@ -10,6 +10,7 @@ obj-$(CONFIG_GPIOLIB) += gpiolib.o obj-$(CONFIG_GPIO_ADP5520) += adp5520-gpio.o obj-$(CONFIG_GPIO_ADP5588) += adp5588-gpio.o +obj-$(CONFIG_ARCH_AT91) += at91_gpio.o obj-$(CONFIG_GPIO_BASIC_MMIO) += basic_mmio_gpio.o obj-$(CONFIG_GPIO_LANGWELL) += langwell_gpio.o obj-$(CONFIG_GPIO_MAX730X) += max730x.o
drivers/gpio/at91_gpio.c renamed from arch/arm/mach-at91/gpio.c +0 -0
Signature · 1 line
1.7.4.1
PATCH 9/14 at91: switch pit timer to early platform devices
In reply to Jean-Christophe PLAGNIOL-VILLARDthis will allow to specify the resources per soc
as the 5series use a different start address for the pit
--- arch/arm/mach-at91/at572d940hf.c | 6 + arch/arm/mach-at91/at91cap9.c | 6 + arch/arm/mach-at91/at91sam9260.c | 6 + arch/arm/mach-at91/at91sam9261.c | 6 + arch/arm/mach-at91/at91sam9263.c | 6 + arch/arm/mach-at91/at91sam926x_time.c | 277 +++++++++++++++++++++------- arch/arm/mach-at91/at91sam9g45.c | 6 + arch/arm/mach-at91/at91sam9rl.c | 6 + arch/arm/mach-at91/board-afeb-9260v1.c | 2 +- arch/arm/mach-at91/board-at572d940hf_ek.c | 2 +- arch/arm/mach-at91/board-cam60.c | 2 +- arch/arm/mach-at91/board-cap9adk.c | 2 +- arch/arm/mach-at91/board-cpu9krea.c | 2 +- arch/arm/mach-at91/board-flexibity.c | 2 +- arch/arm/mach-at91/board-foxg20.c | 2 +- arch/arm/mach-at91/board-gsia18s.c | 2 +- arch/arm/mach-at91/board-neocore926.c | 2 +- arch/arm/mach-at91/board-pcontrol-g20.c | 2 +- arch/arm/mach-at91/board-qil-a9260.c | 2 +- arch/arm/mach-at91/board-sam9-l9260.c | 2 +- arch/arm/mach-at91/board-sam9260ek.c | 2 +- arch/arm/mach-at91/board-sam9261ek.c | 2 +- arch/arm/mach-at91/board-sam9263ek.c | 2 +- arch/arm/mach-at91/board-sam9g20ek.c | 4 +- arch/arm/mach-at91/board-sam9m10g45ek.c | 2 +- arch/arm/mach-at91/board-sam9rlek.c | 2 +- arch/arm/mach-at91/board-snapper9260.c | 2 +- arch/arm/mach-at91/board-stamp9g20.c | 4 +- arch/arm/mach-at91/board-usb-a926x.c | 4 +- arch/arm/mach-at91/devices.c | 4 +- arch/arm/mach-at91/generic.h | 2 +- arch/arm/mach-at91/include/mach/at91_pit.h | 8 +- arch/arm/mach-at91/soc.c | 42 +++++ arch/arm/mach-at91/soc.h | 1 + 34 files changed, 327 insertions(+), 97 deletions(-)
arch/arm/mach-at91/at572d940hf.c +6 -0
@@ -417,6 +417,11 @@ static unsigned int at572d940hf_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; +struct at91_dev_resource at572d940hf_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at572d940hf_soc = { .name ="at572d940hf" , .default_irq_priority = at572d940hf_default_irq_priority,
@@ -425,4 +430,5 @@ struct at91_soc __initdata at572d940hf_soc = { .resource = at572d940hf_pios, .num_resources = ARRAY_SIZE(at572d940hf_pios), }, + .pit = &at572d940hf_pit, };
arch/arm/mach-at91/at91cap9.c +6 -0
@@ -420,6 +420,11 @@ static unsigned int at91cap9_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; +struct at91_dev_resource at91cap9_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91cap9_soc = { .name ="at91cap9" , .default_irq_priority = at91cap9_default_irq_priority,
@@ -428,4 +433,5 @@ struct at91_soc __initdata at91cap9_soc = { .resource = at91cap9_pios, .num_resources = ARRAY_SIZE(at91cap9_pios), }, + .pit = &at91cap9_pit, };
arch/arm/mach-at91/at91sam9260.c +6 -0
@@ -409,6 +409,11 @@ static unsigned int at91sam9260_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; +struct at91_dev_resource at91sam9260_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91sam9260_soc = { .name ="at91sam9260" , .default_irq_priority = at91sam9260_default_irq_priority,
@@ -417,4 +422,5 @@ struct at91_soc __initdata at91sam9260_soc = { .resource = at91sam9260_pios, .num_resources = ARRAY_SIZE(at91sam9260_pios), }, + .pit = &at91sam9260_pit, };
arch/arm/mach-at91/at91sam9261.c +6 -0
@@ -375,6 +375,11 @@ static unsigned int at91sam9261_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; +struct at91_dev_resource at91sam9261_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91sam9261_soc = { .name ="at91sam9261" , .default_irq_priority = at91sam9261_default_irq_priority,
@@ -383,4 +388,5 @@ struct at91_soc __initdata at91sam9261_soc = { .resource = at91sam9261_pios, .num_resources = ARRAY_SIZE(at91sam9261_pios), }, + .pit = &at91sam9261_pit, };
arch/arm/mach-at91/at91sam9263.c +6 -0
@@ -384,6 +384,11 @@ static unsigned int at91sam9263_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ1) */ }; +struct at91_dev_resource at91sam9263_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91sam9263_soc = { .name ="at91sam9263" , .default_irq_priority = at91sam9263_default_irq_priority,
@@ -392,4 +397,5 @@ struct at91_soc __initdata at91sam9263_soc = { .resource = at91sam9263_pios, .num_resources = ARRAY_SIZE(at91sam9263_pios), }, + .pit = &at91sam9263_pit, };
arch/arm/mach-at91/at91sam926x_time.c +211 -66
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arch/arm/mach-at91/at91sam9g45.c +6 -0
@@ -402,6 +402,11 @@ static unsigned int at91sam9g45_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller (IRQ0) */ }; +struct at91_dev_resource at91sam9g45_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91sam9g45_soc = { .name ="at91sam9g45" , .default_irq_priority = at91sam9g45_default_irq_priority,
@@ -410,4 +415,5 @@ struct at91_soc __initdata at91sam9g45_soc = { .resource = at91sam9g45_pios, .num_resources = ARRAY_SIZE(at91sam9g45_pios), }, + .pit = &at91sam9g45_pit, };
arch/arm/mach-at91/at91sam9rl.c +6 -0
@@ -368,6 +368,11 @@ static unsigned int at91sam9rl_default_irq_priority[NR_AIC_IRQS] __initdata = { 0, /* Advanced Interrupt Controller */ }; +struct at91_dev_resource at91sam9rl_pit__initdata = { + .mmio_base =AT91_PIT , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91sam9rl_soc = { .name ="at91sam9rl" , .default_irq_priority = at91sam9rl_default_irq_priority,
@@ -376,4 +381,5 @@ struct at91_soc __initdata at91sam9rl_soc = { .resource = at91sam9rl_pios, .num_resources = ARRAY_SIZE(at91sam9rl_pios), }, + .pit = &at91sam9rl_pit, };
arch/arm/mach-at91/board-afeb-9260v1.c +1 -1
@@ -219,7 +219,7 @@ static void __init afeb9260_board_init(void)MACHINE_START (AFEB9260 ,"Custom afeb9260 board" )/* Maintainer: Sergey Lapin <[email protected]> */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = afeb9260_map_io, .init_irq = afeb9260_init_irq, .init_machine = afeb9260_board_init,
arch/arm/mach-at91/board-at572d940hf_ek.c +1 -1
@@ -316,7 +316,7 @@ static void __init eb_board_init(void)MACHINE_START (AT572D940HFEB ,"Atmel AT91D940HF-EB" )/* Maintainer: Atmel <[email protected]> */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = eb_map_io, .init_irq = eb_init_irq, .init_machine = eb_board_init,
arch/arm/mach-at91/board-cam60.c +1 -1
@@ -199,7 +199,7 @@ static void __init cam60_board_init(void)MACHINE_START (CAM60 ,"KwikByte CAM60" )/* Maintainer: KwikByte */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = cam60_map_io, .init_irq = cam60_init_irq, .init_machine = cam60_board_init,
arch/arm/mach-at91/board-cap9adk.c +1 -1
@@ -397,7 +397,7 @@ static void __init cap9adk_board_init(void)MACHINE_START (AT91CAP9ADK ,"Atmel AT91CAP9A-DK" )/* Maintainer: Stelian Pop <[email protected]> */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = cap9adk_map_io, .init_irq = cap9adk_init_irq, .init_machine = cap9adk_board_init,
arch/arm/mach-at91/board-cpu9krea.c +1 -1
@@ -376,7 +376,7 @@ MACHINE_START(CPUAT9G20, "Eukrea CPU9G20")#endif /* Maintainer: Eric Benard - EUKREA Electromatique */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = cpu9krea_map_io, .init_irq = cpu9krea_init_irq, .init_machine = cpu9krea_board_init,
arch/arm/mach-at91/board-flexibity.c +1 -1
@@ -155,7 +155,7 @@ static void __init flexibity_board_init(void)MACHINE_START (FLEXIBITY ,"Flexibity Connect" )/* Maintainer: Maxim Osipov */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = flexibity_map_io, .init_irq = flexibity_init_irq, .init_machine = flexibity_board_init,
arch/arm/mach-at91/board-foxg20.c +1 -1
@@ -267,7 +267,7 @@ static void __init foxg20_board_init(void)MACHINE_START (ACMENETUSFOXG20 ,"Acme Systems srl FOX Board G20" )/* Maintainer: Sergio Tanzilli */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = foxg20_map_io, .init_irq = foxg20_init_irq, .init_machine = foxg20_board_init,
arch/arm/mach-at91/board-gsia18s.c +1 -1
@@ -577,7 +577,7 @@ static void __init gsia18s_board_init(void)MACHINE_START (GSIA18S ,"GS_IA18_S" ) .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = gsia18s_map_io, .init_irq = init_irq, .init_machine = gsia18s_board_init,
arch/arm/mach-at91/board-neocore926.c +1 -1
@@ -388,7 +388,7 @@ static void __init neocore926_board_init(void)MACHINE_START (NEOCORE926 ,"ADENEO NEOCORE 926" )/* Maintainer: ADENEO */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = neocore926_map_io, .init_irq = neocore926_init_irq, .init_machine = neocore926_board_init,
arch/arm/mach-at91/board-pcontrol-g20.c +1 -1
@@ -223,7 +223,7 @@ static void __init pcontrol_g20_board_init(void)MACHINE_START (PCONTROL_G20 ,"PControl G20" )/* Maintainer: pgsellmann at portner-elektronik.at */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = pcontrol_g20_map_io, .init_irq = init_irq, .init_machine = pcontrol_g20_board_init,
arch/arm/mach-at91/board-qil-a9260.c +1 -1
@@ -269,7 +269,7 @@ static void __init ek_board_init(void)MACHINE_START (QIL_A9260 ,"CALAO QIL_A9260" )/* Maintainer: calao-systems */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9-l9260.c +1 -1
@@ -213,7 +213,7 @@ static void __init ek_board_init(void)MACHINE_START (SAM9_L9260 ,"Olimex SAM9-L9260" )/* Maintainer: Olimex */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9260ek.c +1 -1
@@ -354,7 +354,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91SAM9260EK ,"Atmel AT91SAM9260-EK" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9261ek.c +1 -1
@@ -621,7 +621,7 @@ MACHINE_START(AT91SAM9G10EK, "Atmel AT91SAM9G10-EK")#endif /* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9263ek.c +1 -1
@@ -452,7 +452,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91SAM9263EK ,"Atmel AT91SAM9263-EK" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9g20ek.c +2 -2
@@ -404,7 +404,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91SAM9G20EK ,"Atmel AT91SAM9G20-EK" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
@@ -413,7 +413,7 @@ MACHINE_ENDMACHINE_START (AT91SAM9G20EK_2MMC ,"Atmel AT91SAM9G20-EK 2 MMC Slot Mod" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9m10g45ek.c +1 -1
@@ -422,7 +422,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91SAM9M10G45EK ,"Atmel AT91SAM9M10G45-EK" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-sam9rlek.c +1 -1
@@ -330,7 +330,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91SAM9RLEK ,"Atmel AT91SAM9RL-EK" )/* Maintainer: Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-snapper9260.c +1 -1
@@ -179,7 +179,7 @@ static void __init snapper9260_board_init(void)MACHINE_START (SNAPPER_9260 ,"Bluewater Systems Snapper 9260/9G20 module" ) .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = snapper9260_map_io, .init_irq = snapper9260_init_irq, .init_machine = snapper9260_board_init,
arch/arm/mach-at91/board-stamp9g20.c +2 -2
@@ -299,7 +299,7 @@ static void __init stamp9g20evb_board_init(void)MACHINE_START (PORTUXG20 ,"taskit PortuxG20" )/* Maintainer: taskit GmbH */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = portuxg20_map_io, .init_irq = init_irq, .init_machine = portuxg20_board_init,
@@ -308,7 +308,7 @@ MACHINE_ENDMACHINE_START (STAMP9G20 ,"taskit Stamp9G20" )/* Maintainer: taskit GmbH */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = stamp9g20evb_map_io, .init_irq = init_irq, .init_machine = stamp9g20evb_board_init,
arch/arm/mach-at91/board-usb-a926x.c +2 -2
@@ -280,7 +280,7 @@ static void __init ek_board_init(void)MACHINE_START (USB_A9263 ,"CALAO USB_A9263" )/* Maintainer: calao-systems */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
@@ -289,7 +289,7 @@ MACHINE_ENDMACHINE_START (USB_A9260 ,"CALAO USB_A9260" )/* Maintainer: calao-systems */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91sam926x_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/devices.c +2 -2
@@ -8,8 +8,8 @@* */ -#include <linux/platform_device.h> -#include "devices.h" + +#include "soc.h"
arch/arm/mach-at91/generic.h +1 -1
@@ -23,7 +23,7 @@ extern void __init at91_aic_init(unsigned int priority[]);/* Timer */ struct sys_timer ;extern struct sys_timer at91rm9200_timer; -extern struct sys_timer at91sam926x_timer; +extern struct sys_timer at91_timer;extern struct sys_timer at91x40_timer;/* Clocks */
arch/arm/mach-at91/include/mach/at91_pit.h +4 -4
@@ -16,16 +16,16 @@#ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00)/* Mode Register */ +#define AT91_PIT_MR (0x00)/* Mode Register */ #define AT91_PIT_PITIEN (1 << 25)/* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24)/* Timer Enabled */ #define AT91_PIT_PIV (0xfffff)/* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04)/* Status Register */ +#define AT91_PIT_SR (0x04)/* Status Register */ #define AT91_PIT_PITS (1 << 0)/* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08)/* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c)/* Periodic Interval Image Register */ +#define AT91_PIT_PIVR (0x08)/* Periodic Interval Value Register */ +#define AT91_PIT_PIIR (0x0c)/* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20)/* Interval Counter */ #define AT91_PIT_CPIV (0xfffff)/* Inverval Value */
arch/arm/mach-at91/soc.c +42 -0
51 lines not on this page · raw message
arch/arm/mach-at91/soc.h +1 -0
@@ -13,6 +13,7 @@ struct at91_soc {unsigned int *default_irq_priority;struct at91_dev_resource_array gpio; +struct at91_dev_resource *pit;void (*init)(unsigned long main_clock); };
Signature · 1 line
1.7.4.1
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 7 lines · Jean-Christophe PLAGNIOL-VILLARD
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>
This patch breaks my Snapper 9G20 board (bisected). With this patch in place the kernel hangs with the following boot log:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Linux version 2.6.39-rc4+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #868 Thu Apr 28 16:37:56 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
AT91: detected soc: at91sam9260
Clocks: CPU 396 MHz, master 132 MHz, main 18.432 MHz
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 16256
Kernel command line: console=ttyS0,115200 nfsroot=/home/ryan/work/internal/package_builder/rootfs ip=any root=/dev/nfs atmel_nand.use_dma=0 PID hash table entries: 256 (order: -2, 1024 bytes)
Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
Memory: 64MB = 64MB total
Memory: 61456k/61456k available, 4080k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000 - 0xffff1000 ( 4 kB)
fixmap : 0xfff00000 - 0xfffe0000 ( 896 kB)
DMA : 0xffc00000 - 0xffe00000 ( 2 MB)
vmalloc : 0xc4800000 - 0xfee00000 ( 934 MB)
lowmem : 0xc0000000 - 0xc4000000 ( 64 MB)
modules : 0xbf000000 - 0xc0000000 ( 16 MB)
.init : 0xc0008000 - 0xc0024000 ( 112 kB)
.text : 0xc0024000 - 0xc03274ac (3086 kB)
.data : 0xc0328000 - 0xc034a280 ( 137 kB)NR_IRQS:192
AT91: 96 gpio irqs in 3 banks
at91_pit.0: used as clock source
at91_pit.0: used for clock events
Console: colour dummy device 80x30
console [ttyS0] enabled
Calibrating delay loop... 197.01 BogoMIPS (lpj=985088)pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 512
CPU: Testing write buffer coherency: ok
NET: Registered protocol family 16
AT91: Power Management
AT91: Starting after general reset
bio: create slab <bio-0> at 0
SCSI subsystem initialized
usbcore: registered new interface driver usbfs
usbcore: registered new interface driver hub
usbcore: registered new device driver usb
Advanced Linux Sound Architecture Driver Version 1.0.24. Switching to clocksource pit
NET: Registered protocol family 2
IP route cache hash table entries: 1024 (order: 0, 4096 bytes) IPv4 FIB: Using LC-trie version 0.409
TCP established hash table entries: 2048 (order: 2, 16384 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes)
TCP: Hash tables configured (established 2048 bind 2048)
TCP reno registered
UDP hash table entries: 256 (order: 0, 4096 bytes)
UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
NET: Registered protocol family 1
RPC: Registered udp transport module.
RPC: Registered tcp transport module.
RPC: Registered tcp NFSv4.1 backchannel transport module. NetWinder Floating Point Emulator V0.97 (double precision)
JFFS2 version 2.2. (NAND) (SUMMARY) ? 2001-2006 Red Hat, Inc. msgmni has been set to 120
io scheduler noop registered (default)
atmel_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a ATMEL_SERIAL atmel_usart.1: ttyS1 at MMIO 0xfffb0000 (irq = 6) is a ATMEL_SERIAL atmel_usart.2: ttyS2 at MMIO 0xfffb4000 (irq = 7) is a ATMEL_SERIAL atmel_usart.3: ttyS3 at MMIO 0xfffb8000 (irq = 8) is a ATMEL_SERIAL
brd: module loaded
loop: module loadedatmel_nand atmel_nand: No DMA support for NAND access.nand_get_flash_type: second ID read did not match 52,2c against 09,2c No NAND device found.MACB_mii_bus: probed
eth0: Atmel MACB at 0xfffc4000 irq 21 (00:00:00:00:00:01)
eth0: attached PHY driver [Generic PHY] (mii_bus:phy_addr=ffffffff:1f, irq=-1)
usbmon: debugfs is not availableohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driverat91_ohci at91_ohci: AT91 OHCIat91_ohci at91_ohci: new USB bus registered, assigned bus number 1 at91_ohci at91_ohci: irq 20, io mem 0x00500000
It just stops dead here. Unfortunately I can't get my ICE unit to connect to it for some reason so I can't give you any more information at the moment.
I've had a quick look through the patch and I can't see anything obviously wrong, but I don't have much experience with the clockevents subsystem either. Any ideas? I can send through my .config if that helps.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 9/14 at91: switch pit timer to early platform devices
In reply to Jean-Christophe PLAGNIOL-VILLARDhi,
Quoted 3 lines
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
I really don't see the fascination with early platform_devices for timer. A sys_timer is initialized way earlier, and there are surely cleaner ways to just pass a "base address" through to the driver.
The interrupt is always AT91_ID_SYS on all chips, so there is no point making it configurable.
Regards,
Andrew Victor
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 11 lines · Andrew Victor
hi,
Quoted 3 lines
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
I really don't see the fascination with early
platform_devicesfor timer. Asys_timeris initialized way earlier, and there are surely cleaner ways to just pass a "base address" through to the driver.
The interrupt is alwaysAT91_ID_SYSon all chips, so there is no point making it configurable.
Me too - it looks like this early device stuff is heading in the wrong direction.
There is a point when the kernel expects to have knowledge of the passing of time initialized, and that's when the system_timer->init callback is made. At this point, everything is in place for the ticks to start, and some of the subsequent parts of the kernel may expect jiffies to be updating after this call has returned.
Shoving stuff in other random places in the initialization order is asking for things to break - maybe not immediately, but down the line as things change in the generic parts of the code.
Stick to using the callbacks provided for their defined purpose and life will be easier. It'll also be a lot easier to consolidate some of the crap we've accumulated across each platform if everyone's doing stuff in the same way.
And that's another reason to say no to this. Please stop inventing new ways to do things unless you're prepared to provide it as a replacement for all the (ARM) platforms we have in the kernel.
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 26 lines · Russell King - ARM Linux
Quoted 11 lines · Andrew Victor
hi,
Quoted 3 lines
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
I really don't see the fascination with early
platform_devicesfor timer. Asys_timeris initialized way earlier, and there are surely cleaner ways to just pass a "base address" through to the driver.
The interrupt is alwaysAT91_ID_SYSon all chips, so there is no point making it configurable.Me too - it looks like this early device stuff is heading in the wrong direction.
There is a point when the kernel expects to have knowledge of the passing of time initialized, and that's when the
system_timer->initcallback is made. At this point, everything is in place for the ticks to start, and some of the subsequent parts of the kernel may expect jiffies to be updating after this call has returned.Shoving stuff in other random places in the initialization order is asking for things to break - maybe not immediately, but down the line as things change in the generic parts of the code.
Quoted 8 lines
Stick to using the callbacks provided for their defined purpose and life will be easier. It'll also be a lot easier to consolidate some of the crap we've accumulated across each platform if everyone's doing stuff in the same way.
And that's another reason to say no to this. Please stop inventing new ways to do things unless you're prepared to provide it as a replacement for all the (ARM) platforms we have in the kernel.
Personally I do not change the current arm way
I init the timer during system_timer->init
I just the the early device their to pass the resources
but if switch all arm timer this way is fine to you I'm ready to do the whole update
Best Regards,
J.
PATCH 9/14 at91: switch pit timer to early platform devices
hi,
Quoted 10 lines
Quoted 3 lines
And that's another reason to say no to this. Please stop inventing new ways to do things unless you're prepared to provide it as a replacement for all the (ARM) platforms we have in the kernel.
Personally I do not change the current arm way
I init the timer during
system_timer->initI just the the early device their to pass the resources
but if switch all arm timer this way is fine to you I'm ready to do the whole update
Well, attached is a simpler way of passing the base-address to the timer drivers. It will solve the timer issues with a single kernel supporting multiple AT91 processors.
I think it would be cleaner still if the "struct sys_timer" could include a register-base-address field. Russell?
Regards,
Andrew Victor
arch/arm/mach-at91/at572d940hf.c +2 -0
@@ -307,6 +307,8 @@/* Map peripherals */ iotable_init (at572d940hf_io_desc,ARRAY_SIZE (at572d940hf_io_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at572d940hf_reset; at91_extern_irq = (1 <<AT572D940HF_ID_IRQ0 ) | (1 <<AT572D940HF_ID_IRQ1 ) | (1 <<AT572D940HF_ID_IRQ2 );
arch/arm/mach-at91/at91cap9.c +2 -0
@@ -308,6 +308,8 @@/* Map peripherals */ iotable_init (at91cap9_io_desc,ARRAY_SIZE (at91cap9_io_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at91cap9_reset; pm_power_off = at91cap9_poweroff; at91_extern_irq = (1 <<AT91CAP9_ID_IRQ0 ) | (1 <<AT91CAP9_ID_IRQ1 );
arch/arm/mach-at91/at91rm9200.c +4 -2
@@ -262,8 +262,8 @@/* * Perform a hardware reset with the use of the Watchdog timer. */ -at91_sys_write (AT91_ST_WDMR ,AT91_ST_RSTEN |AT91_ST_EXTEN |1 ); -at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); +at91_sys_write (AT91_ST +AT91_ST_WDMR ,AT91_ST_RSTEN |AT91_ST_EXTEN |1 ); +at91_sys_write (AT91_ST +AT91_ST_CR ,AT91_ST_WDRST ); }
@@ -275,6 +275,8 @@/* Map peripherals */ iotable_init (at91rm9200_io_desc,ARRAY_SIZE (at91rm9200_io_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_ST ; + at91_arch_reset = at91rm9200_reset; at91_extern_irq = (1 <<AT91RM9200_ID_IRQ0 ) | (1 <<AT91RM9200_ID_IRQ1 ) | (1 <<AT91RM9200_ID_IRQ2 ) | (1 <<AT91RM9200_ID_IRQ3 )
arch/arm/mach-at91/at91rm9200_time.c +18 -15
@@ -28,9 +28,12 @@#include <mach/at91_st.h> +#include "generic.h" +static unsigned long last_crtr;static u32 irqmask;static struct clock_event_device clkevt; +void __iomem *at91_timer_base;/* base address */ /* * The ST_CRTR is updated asynchronously to the master clock ... but
@@ -41,9 +44,9 @@ {unsigned long x1, x2; - x1 =at91_sys_read (AT91_ST_CRTR ); + x1 =__raw_readl (at91_timer_base +AT91_ST_CRTR ); do { - x2 = at91_sys_read(AT91_ST_CRTR); + x2 = __raw_readl(at91_timer_base + AT91_ST_CRTR); if (x1 == x2) break; x1 = x2;
@@ -56,7 +59,7 @@*/ static irqreturn_t at91rm9200_timer_interrupt (int irq,void *dev_id) { -u32 sr =at91_sys_read (AT91_ST_SR ) & irqmask; +u32 sr =__raw_readl (at91_timer_base +AT91_ST_SR ) & irqmask;/* * irqs should be disabled here, but as the irq is shared they are only
@@ -108,22 +111,22 @@ clkevt32k_mode(enum clock_event_mode mode, struct clock_event_device *dev) {/* Disable and flush pending timer interrupts */ - at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_ALMS); - (void )at91_sys_read (AT91_ST_SR ); + __raw_writel(AT91_ST_PITS | AT91_ST_ALMS, at91_timer_base + AT91_ST_IDR); + (void )__raw_readl (at91_timer_base +AT91_ST_SR ); last_crtr =read_CRTR ();switch (mode) {case CLOCK_EVT_MODE_PERIODIC :/* PIT for periodic irqs; fixed rate of 1/HZ */ irqmask =AT91_ST_PITS ; -at91_sys_write (AT91_ST_PIMR ,LATCH ); +__raw_writel (LATCH , at91_timer_base +AT91_ST_PIMR );break ;case CLOCK_EVT_MODE_ONESHOT :/* ALM for oneshot irqs, set by next_event() * before 32 seconds have passed */ irqmask =AT91_ST_ALMS ; -at91_sys_write (AT91_ST_RTAR , last_crtr); +__raw_writel (last_crtr, at91_timer_base +AT91_ST_RTAR );break ;case CLOCK_EVT_MODE_SHUTDOWN :case CLOCK_EVT_MODE_UNUSED :
@@ -131,7 +134,7 @@ irqmask =0 ;break ; } -at91_sys_write (AT91_ST_IER , irqmask); +__raw_writel (irqmask, at91_timer_base +AT91_ST_IER ); } static int
@@ -154,12 +157,12 @@ alm =read_CRTR ();/* Cancel any pending alarm; flush any pending IRQ */ -at91_sys_write (AT91_ST_RTAR , alm); - (void )at91_sys_read (AT91_ST_SR ); +__raw_writel (alm, at91_timer_base +AT91_ST_RTAR ); + (void )__raw_readl (at91_timer_base +AT91_ST_SR );/* Schedule alarm by writing RTAR. */ alm += delta; -at91_sys_write (AT91_ST_RTAR , alm); +__raw_writel (alm, at91_timer_base +AT91_ST_RTAR );return status; }
@@ -179,9 +182,9 @@void __init at91rm9200_timer_init (void ) {/* Disable all timer interrupts, and clear any pending ones */ -at91_sys_write (AT91_ST_IDR , -AT91_ST_PITS |AT91_ST_WDOVF |AT91_ST_RTTINC |AT91_ST_ALMS ); - (void )at91_sys_read (AT91_ST_SR ); +__raw_writel (AT91_ST_PITS |AT91_ST_WDOVF |AT91_ST_RTTINC |AT91_ST_ALMS , + at91_timer_base +AT91_ST_IDR ); + (void )__raw_readl (at91_timer_base +AT91_ST_SR );/* Make IRQs happen for the system timer */ setup_irq (AT91_ID_SYS , &at91rm9200_timer_irq);
@@ -190,7 +193,7 @@* directly for the clocksource and all clockevents, after adjusting * its prescaler from the 1 Hz default. */ -at91_sys_write (AT91_ST_RTMR ,1 ); +__raw_writel (1 , at91_timer_base +AT91_ST_RTMR );/* Setup timer clockevent, with minimum of two ticks (important!!) */ clkevt.mult =div_sc (AT91_SLOW_CLOCK ,NSEC_PER_SEC , clkevt.shift);
arch/arm/mach-at91/at91sam9260.c +3 -0
@@ -307,6 +307,7 @@ at91sam9xe_sram_desc->virtual =AT91_IO_VIRT_BASE - sram_size; at91sam9xe_sram_desc->length = sram_size; +/* Map peripherals */ iotable_init (at91sam9xe_sram_desc,ARRAY_SIZE (at91sam9xe_sram_desc)); }
@@ -322,6 +323,8 @@else iotable_init (at91sam9260_sram_desc,ARRAY_SIZE (at91sam9260_sram_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 <<AT91SAM9260_ID_IRQ0 ) | (1 <<AT91SAM9260_ID_IRQ1 )
arch/arm/mach-at91/at91sam9261.c +1 -0
@@ -277,6 +277,7 @@else iotable_init (at91sam9261_sram_desc,ARRAY_SIZE (at91sam9261_sram_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9261_poweroff;
arch/arm/mach-at91/at91sam9263.c +2 -0
@@ -284,6 +284,8 @@/* Map peripherals */ iotable_init (at91sam9263_io_desc,ARRAY_SIZE (at91sam9263_io_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 <<AT91SAM9263_ID_IRQ0 ) | (1 <<AT91SAM9263_ID_IRQ1 );
arch/arm/mach-at91/at91sam926x_time.c +12 -11
@@ -23,6 +23,7 @@#define PIT_CPIV (x) ((x) & AT91_PIT_CPIV)#define PIT_PICNT (x) (((x) & AT91_PIT_PICNT) >> 20) +void __iomem *at91_timer_base;/* base address */ static u32 pit_cycle;/* write-once */ static u32 pit_cnt;/* access only w/system irq blocked */
@@ -39,7 +40,7 @@raw_local_irq_save (flags); elapsed = pit_cnt; - t =at91_sys_read (AT91_PIT_PIIR ); + t =__raw_readl (at91_timer_base +AT91_PIT_PIIR );raw_local_irq_restore (flags); elapsed +=PIT_PICNT (t) * pit_cycle;
@@ -64,9 +65,9 @@switch (mode) {case CLOCK_EVT_MODE_PERIODIC :/* update clocksource counter */ - pit_cnt += pit_cycle *PIT_PICNT (at91_sys_read (AT91_PIT_PIVR )); -at91_sys_write (AT91_PIT_MR , (pit_cycle -1 ) |AT91_PIT_PITEN - |AT91_PIT_PITIEN ); + pit_cnt += pit_cycle *PIT_PICNT (__raw_readl (at91_timer_base +AT91_PIT_PIVR )); +__raw_writel ((pit_cycle -1 ) |AT91_PIT_PITEN |AT91_PIT_PITIEN , + at91_timer_base +AT91_PIT_MR );break ;case CLOCK_EVT_MODE_ONESHOT :BUG ();
@@ -74,7 +75,7 @@case CLOCK_EVT_MODE_SHUTDOWN :case CLOCK_EVT_MODE_UNUSED :/* disable irq, leaving the clocksource active */ -at91_sys_write (AT91_PIT_MR , (pit_cycle -1 ) |AT91_PIT_PITEN ); +__raw_writel ((pit_cycle -1 ) |AT91_PIT_PITEN , at91_timer_base +AT91_PIT_MR );break ;case CLOCK_EVT_MODE_RESUME :break ;
@@ -103,11 +104,11 @@/* The PIT interrupt may be disabled, and is shared */ if ((pit_clkevt.mode ==CLOCK_EVT_MODE_PERIODIC ) - && (at91_sys_read (AT91_PIT_SR ) &AT91_PIT_PITS )) { + && (__raw_readl (at91_timer_base +AT91_PIT_SR ) &AT91_PIT_PITS )) {unsigned nr_ticks;/* Get number of ticks performed before irq, and ack it */ - nr_ticks =PIT_PICNT (at91_sys_read (AT91_PIT_PIVR )); + nr_ticks =PIT_PICNT (__raw_readl (at91_timer_base +AT91_PIT_PIVR )); do { pit_cnt += pit_cycle; pit_clkevt.event_handler(&pit_clkevt);
@@ -129,14 +130,14 @@static void at91sam926x_pit_reset (void ) {/* Disable timer and irqs */ -at91_sys_write (AT91_PIT_MR ,0 ); +__raw_writel (0 , at91_timer_base +AT91_PIT_MR );/* Clear any pending interrupts, wait for PIT to stop counting */ -while (PIT_CPIV (at91_sys_read (AT91_PIT_PIVR )) !=0 ) +while (PIT_CPIV (__raw_readl (at91_timer_base +AT91_PIT_PIVR )) !=0 )cpu_relax ();/* Start PIT but don't enable IRQ */ -at91_sys_write (AT91_PIT_MR , (pit_cycle -1 ) |AT91_PIT_PITEN ); +__raw_writel ((pit_cycle -1 ) |AT91_PIT_PITEN , at91_timer_base +AT91_PIT_MR ); }/*
@@ -178,7 +179,7 @@static void at91sam926x_pit_suspend (void ) {/* Disable timer */ -at91_sys_write (AT91_PIT_MR ,0 ); +__raw_writel (0 , at91_timer_base +AT91_PIT_MR ); }struct sys_timer at91sam926x_timer = {
arch/arm/mach-at91/at91sam9g45.c +2 -0
@@ -311,6 +311,8 @@/* Map peripherals */ iotable_init (at91sam9g45_io_desc,ARRAY_SIZE (at91sam9g45_io_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at91sam9g45_reset; pm_power_off = at91sam9g45_poweroff; at91_extern_irq = (1 <<AT91SAM9G45_ID_IRQ0 );
arch/arm/mach-at91/at91sam9rl.c +2 -0
@@ -276,6 +276,8 @@/* Map SRAM */ iotable_init (at91sam9rl_sram_desc,ARRAY_SIZE (at91sam9rl_sram_desc)); + at91_timer_base = (void __iomem *)AT91_VA_BASE_SYS +AT91_PIT ; + at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 <<AT91SAM9RL_ID_IRQ0 );
arch/arm/mach-at91/generic.h +2 -0
@@ -64,3 +64,5 @@extern void (*at91_arch_reset)(void );extern int at91_extern_irq; + +extern void __iomem *at91_timer_base;/* base address of system timer */
arch/arm/mach-at91/include/mach/at91_pit.h +4 -4
@@ -16,16 +16,16 @@#ifndef AT91_PIT_H #define AT91_PIT_H -#define AT91_PIT_MR (AT91_PIT + 0x00)/* Mode Register */ +#define AT91_PIT_MR 0x00/* Mode Register */ #define AT91_PIT_PITIEN (1 << 25)/* Timer Interrupt Enable */ #define AT91_PIT_PITEN (1 << 24)/* Timer Enabled */ #define AT91_PIT_PIV (0xfffff)/* Periodic Interval Value */ -#define AT91_PIT_SR (AT91_PIT + 0x04)/* Status Register */ +#define AT91_PIT_SR 0x04/* Status Register */ #define AT91_PIT_PITS (1 << 0)/* Timer Status */ -#define AT91_PIT_PIVR (AT91_PIT + 0x08)/* Periodic Interval Value Register */ -#define AT91_PIT_PIIR (AT91_PIT + 0x0c)/* Periodic Interval Image Register */ +#define AT91_PIT_PIVR 0x08/* Periodic Interval Value Register */ +#define AT91_PIT_PIIR 0x0c/* Periodic Interval Image Register */ #define AT91_PIT_PICNT (0xfff << 20)/* Interval Counter */ #define AT91_PIT_CPIV (0xfffff)/* Inverval Value */
arch/arm/mach-at91/include/mach/at91_st.h +10 -10
@@ -16,34 +16,34 @@#ifndef AT91_ST_H #define AT91_ST_H -#define AT91_ST_CR (AT91_ST + 0x00)/* Control Register */ +#define AT91_ST_CR 0x00/* Control Register */ #define AT91_ST_WDRST (1 << 0)/* Watchdog Timer Restart */ -#define AT91_ST_PIMR (AT91_ST + 0x04)/* Period Interval Mode Register */ +#define AT91_ST_PIMR 0x04/* Period Interval Mode Register */ #define AT91_ST_PIV (0xffff << 0)/* Period Interval Value */ -#define AT91_ST_WDMR (AT91_ST + 0x08)/* Watchdog Mode Register */ +#define AT91_ST_WDMR 0x08/* Watchdog Mode Register */ #define AT91_ST_WDV (0xffff << 0)/* Watchdog Counter Value */ #define AT91_ST_RSTEN (1 << 16)/* Reset Enable */ #define AT91_ST_EXTEN (1 << 17)/* External Signal Assertion Enable */ -#define AT91_ST_RTMR (AT91_ST + 0x0c)/* Real-time Mode Register */ +#define AT91_ST_RTMR 0x0c/* Real-time Mode Register */ #define AT91_ST_RTPRES (0xffff << 0)/* Real-time Prescalar Value */ -#define AT91_ST_SR (AT91_ST + 0x10)/* Status Register */ +#define AT91_ST_SR 0x10/* Status Register */ #define AT91_ST_PITS (1 << 0)/* Period Interval Timer Status */ #define AT91_ST_WDOVF (1 << 1)/* Watchdog Overflow */ #define AT91_ST_RTTINC (1 << 2)/* Real-time Timer Increment */ #define AT91_ST_ALMS (1 << 3)/* Alarm Status */ -#define AT91_ST_IER (AT91_ST + 0x14)/* Interrupt Enable Register */ -#define AT91_ST_IDR (AT91_ST + 0x18)/* Interrupt Disable Register */ -#define AT91_ST_IMR (AT91_ST + 0x1c)/* Interrupt Mask Register */ +#define AT91_ST_IER 0x14/* Interrupt Enable Register */ +#define AT91_ST_IDR 0x18/* Interrupt Disable Register */ +#define AT91_ST_IMR 0x1c/* Interrupt Mask Register */ -#define AT91_ST_RTAR (AT91_ST + 0x20)/* Real-time Alarm Register */ +#define AT91_ST_RTAR 0x20/* Real-time Alarm Register */ #define AT91_ST_ALMV (0xfffff << 0)/* Alarm Value */ -#define AT91_ST_CRTR (AT91_ST + 0x24)/* Current Real-time Register */ +#define AT91_ST_CRTR 0x24/* Current Real-time Register */ #define AT91_ST_CRTV (0xfffff << 0)/* Current Real-Time Value */ #endif
drivers/watchdog/at91rm9200_wdt.c +4 -4
@@ -51,7 +51,7 @@*/ static inline void at91_wdt_stop (void ) { -at91_sys_write (AT91_ST_WDMR ,AT91_ST_EXTEN ); +at91_sys_write (AT91_ST +AT91_ST_WDMR ,AT91_ST_EXTEN ); }/*
@@ -59,9 +59,9 @@*/ static inline void at91_wdt_start (void ) { -at91_sys_write (AT91_ST_WDMR ,AT91_ST_EXTEN |AT91_ST_RSTEN | +at91_sys_write (AT91_ST +AT91_ST_WDMR ,AT91_ST_EXTEN |AT91_ST_RSTEN | (((65536 * wdt_time) >>8 ) &AT91_ST_WDV )); -at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); +at91_sys_write (AT91_ST +AT91_ST_CR ,AT91_ST_WDRST ); }/*
@@ -69,7 +69,7 @@*/ static inline void at91_wdt_reload (void ) { -at91_sys_write (AT91_ST_CR ,AT91_ST_WDRST ); +at91_sys_write (AT91_ST +AT91_ST_CR ,AT91_ST_WDRST ); }/* ......................................................................... */
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 9 lines · Andrew Victor
hi,
Quoted 7 lines
Quoted 3 lines
And that's another reason to say no to this. Please stop inventing new ways to do things unless you're prepared to provide it as a replacement for all the (ARM) platforms we have in the kernel.
Personally I do not change the current arm way
I init the timer during
system_timer->init
Quoted 7 lines
Quoted 3 lines
I just the the early device their to pass the resources
but if switch all arm timer this way is fine to you I'm ready to do the whole updateWell, attached is a simpler way of passing the base-address to the timer drivers. It will solve the timer issues with a single kernel supporting multiple AT91 processors.
I really don't like the idea of having global var for driver
Best Regards,
J.
PATCH 9/14 at91: switch pit timer to early platform devices
In reply to Andrew VictorQuoted 13 lines · Andrew Victor
hi,
Quoted 10 lines
Quoted 3 lines
And that's another reason to say no to this. Please stop inventing new ways to do things unless you're prepared to provide it as a replacement for all the (ARM) platforms we have in the kernel.
Personally I do not change the current arm way
I init the timer during
system_timer->initI just the the early device their to pass the resources
but if switch all arm timer this way is fine to you I'm ready to do the whole update
Quoted 6 lines
Well, attached is a simpler way of passing the base-address to the timer drivers. It will solve the timer issues with a single kernel supporting multiple AT91 processors.
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. Russell?
That's not really what all platforms want, and with the advent of clocksources and clock events, I think the sys_timer thing is mostly dead.
I've been thinking about killing it off for a while for those platforms using the GENERIC_CLOCKEVENTS stuff. From what I can see, the only real users of it are: acorn (riscpc), at91x40, clps711x, ebsa110, ep93xx, h720x, ixp2000, ixp23xx, ks8695, nuc93x, pnx4008, and samsung.
It would be nice to get the modern stuff out of that converted to the clockevents/clocksource stuff - any chance of that happening for AT91x40?
PATCH 9/14 at91: switch pit timer to early platform devices
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ?Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.
How would those systems initialize the system-timer? An "init_timer" method in the machine-description?
Quoted 8 lines
I've been thinking about killing it off for a while for those platforms using the
GENERIC_CLOCKEVENTSstuff. ?From what I can see, the only real users of it are: acorn (riscpc), at91x40, clps711x, ebsa110, ep93xx, h720x, ixp2000, ixp23xx, ks8695, nuc93x, pnx4008, and samsung.It would be nice to get the modern stuff out of that converted to the clockevents/clocksource stuff - any chance of that happening for AT91x40?
The AT91x40 (ARM7) is maintained by Greg Ungerer.
Greg?
Regards,
Andrew Victor
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 11 lines · Andrew Victor
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ?Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.How would those systems initialize the system-timer? An "
init_timer" method in the machine-description?
I was thinking of an init_timekeeping() callback in the machine record rather than having platforms provide a useless sys_timer structure, and maybe having an ARM generic init_legacy_timekeeping() function for those platforms which still use sys_timer() to put into the init_timekeeping() hook.
I've not really firmed up the idea yet though.
Alternatively, if someone wants to come up with a better way to initialize the clocksource and clock event stuff across all platforms...
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 19 lines · Russell King - ARM Linux
Quoted 11 lines · Andrew Victor
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ?Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.How would those systems initialize the system-timer? An "
init_timer" method in the machine-description?I was thinking of an
init_timekeeping()callback in the machine record rather than having platforms provide a uselesssys_timerstructure, and maybe having an ARM genericinit_legacy_timekeeping()function for those platforms which still usesys_timer()to put into theinit_timekeeping()hook.
Quoted 4 lines
I've not really firmed up the idea yet though.
Alternatively, if someone wants to come up with a better way to initialize the clocksource and clock event stuff across all platforms...
I propose we use early device as I did and Magnus did on SH-Mobile
we will have a common early param "earlytimer"
then we register the drivers like this
early_platform_init("earlytimer", &time_device_driver);
and in the arm init we just have to do early_platform_driver_register_all("earlytimer");
and callearly_platform_driver_probe("earlytimer", 1 , 0);
or let the platform do so as some of them may have more than 1 timer to register example on shmobile
We could also have two init one for soc one for machine if (machine_time_init)
machine_time_init()
else
soc_time_init()
as the timer is not really is ofen not machine specific but platform specific. I see that on shmobile, at91 (3 timers sam9, rm9200, x40), nomadok, and other
This will simplify timer sharing across architecture such shmobile arm and sh for renesas but other vendor get the same issue when they soc on different architecture
Best Regards,
J.
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 44 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 19 lines · Russell King - ARM Linux
Quoted 11 lines · Andrew Victor
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ?Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.How would those systems initialize the system-timer? An "
init_timer" method in the machine-description?I was thinking of an
init_timekeeping()callback in the machine record rather than having platforms provide a uselesssys_timerstructure, and maybe having an ARM genericinit_legacy_timekeeping()function for those platforms which still usesys_timer()to put into theinit_timekeeping()hook.Quoted 4 lines
I've not really firmed up the idea yet though.
Alternatively, if someone wants to come up with a better way to initialize the clocksource and clock event stuff across all platforms...
I propose we use early device as I did and Magnus did on SH-Mobile
we will have a common early param "earlytimer"
then we register the drivers like this
early_platform_init("earlytimer", &time_device_driver);and in the arm init we just have to do
early_platform_driver_register_all("earlytimer");
and callearly_platform_driver_probe("earlytimer", 1 , 0);
or let the platform do so as some of them may have more than 1 timer to register example on shmobileWe could also have two init one for soc one for machine if (
machine_time_init)
machine_time_init()
else
Quoted 8 lines
soc_time_init()as the timer is not really is ofen not machine specific but platform specific. I see that on shmobile, at91 (3 timers sam9, rm9200, x40), nomadok, and other
This will simplify timer sharing across architecture such shmobile arm and sh for renesas but other vendor get the same issue when they soc on different architecture
It doesn't sound like this eliminates anything - it just makes things more complex. It seems we _still_ need a callback into the platform code to execute some kind of initialization, eg calling early_platform_driver_* with appropriate arguments. So I'm not sure what we're saving by effectively breaking the initialization function out into two separate functions and an early platform driver thing.
It all sounds much more complex to me with very little benefit for the majority of platforms, and it doesn't seem to change what's required from core code at all - we still need to provide an initialization call into platform code at the appropriate time.
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 61 lines · Russell King - ARM Linux
Quoted 44 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 19 lines · Russell King - ARM Linux
Quoted 11 lines · Andrew Victor
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ?Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.How would those systems initialize the system-timer? An "
init_timer" method in the machine-description?I was thinking of an
init_timekeeping()callback in the machine record rather than having platforms provide a uselesssys_timerstructure, and maybe having an ARM genericinit_legacy_timekeeping()function for those platforms which still usesys_timer()to put into theinit_timekeeping()hook.Quoted 4 lines
I've not really firmed up the idea yet though.
Alternatively, if someone wants to come up with a better way to initialize the clocksource and clock event stuff across all platforms...
I propose we use early device as I did and Magnus did on SH-Mobile
we will have a common early param "earlytimer"
then we register the drivers like this
early_platform_init("earlytimer", &time_device_driver);and in the arm init we just have to do
early_platform_driver_register_all("earlytimer");
and callearly_platform_driver_probe("earlytimer", 1 , 0);
or let the platform do so as some of them may have more than 1 timer to register example on shmobileWe could also have two init one for soc one for machine if (
machine_time_init)
machine_time_init()
elseQuoted 8 lines
soc_time_init()as the timer is not really is ofen not machine specific but platform specific. I see that on shmobile, at91 (3 timers sam9, rm9200, x40), nomadok, and other
This will simplify timer sharing across architecture such shmobile arm and sh for renesas but other vendor get the same issue when they soc on different architecture
It doesn't sound like this eliminates anything - it just makes things more complex. It seems we _still_ need a callback into the platform code to execute some kind of initialization, eg calling early_platform_driver_* with appropriate arguments. So I'm not sure what we're saving by effectively breaking the initialization function out into two separate functions and an early platform driver thing.
Quoted 4 lines
It all sounds much more complex to me with very little benefit for the majority of platforms, and it doesn't seem to change what's required from core code at all - we still need to provide an initialization call into platform code at the appropriate time.
yes we still need a calback to call the early probe but just a callback for the init no resume, suspend
if we want multiple timer early which I do not think is necessarly for really early one timer is enough if you need more you can initialise them later
so if we keep this constrain
in the arm timer initearly_platform_driver_register_all("earlytimer");early_platform_driver_probe("earlytimer", 1 , 0);
and in the init_early you just need to doearly_platform_add_devices(devices, nb);
so it's more generic
Best Regards,
J.
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD
yes we still need a calback to call the early probe but just a callback for the init no resume, suspend
if we want multiple timer early which I do not think is necessarly for really early one timer is enough if you need more you can initialise them later
so if we keep this constrain
Quoted 8 lines
in the arm timer init
early_platform_driver_register_all("earlytimer");early_platform_driver_probe("earlytimer", 1 , 0);and in the
init_earlyyou just need to doearly_platform_add_devices(devices, nb);so it's more generic
I'm still not convinced. What it seems to be doing is moving from this:
time_init() ->
system_timer->init() -> platform code
to this:
setup_arch() ->
init_early() -> platform code -> early_platform_add_devices() time_init() -> early_platform_driver_register_all(), early_platform_driver_probe() -> early timer probe function (platform code)
which to me just looks a whole lot more complex without benefit.
Platform code still has to make the decision at some point about which timers are added - in the former case via the system_timer->init() callback or in the latter case by the init_early() callback.
I can't see how this results in something better, either by simplifing the code or resulting in any kind of consolidation. That's backed up by this patch adding around 230 lines of code.
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 38 lines · Russell King - ARM Linux
Quoted 9 lines · Jean-Christophe PLAGNIOL-VILLARD
yes we still need a calback to call the early probe but just a callback for the init no resume, suspend
if we want multiple timer early which I do not think is necessarly for really early one timer is enough if you need more you can initialise them later
so if we keep this constrain
Quoted 8 lines
in the arm timer init
early_platform_driver_register_all("earlytimer");early_platform_driver_probe("earlytimer", 1 , 0);and in the
init_earlyyou just need to doearly_platform_add_devices(devices, nb);so it's more generic
I'm still not convinced. What it seems to be doing is moving from this:
time_init()->system_timer->init() -> platform codeto this:
setup_arch()->init_early() -> platform code -> early_platform_add_devices() time_init() -> early_platform_driver_register_all(), early_platform_driver_probe() -> early timer probe function (platform code)which to me just looks a whole lot more complex without benefit.
Quoted 7 lines
Platform code still has to make the decision at some point about which timers are added - in the former case via the
system_timer->init()callback or in the latter case by theinit_early()callback.I can't see how this results in something better, either by simplifing the code or resulting in any kind of consolidation. That's backed up by this patch adding around 230 lines of code.
Simplify cross arch timer drivers
Example on SH-Mobile
And Renesas is not the only vendor to have multiple ARCH ip shared more are arriving
allow to probe more than one timer genericly allow to pass resource and platform data in a standard way
this patch switch from static to allocated device that's why we add 230 lines if you just add the early device only
you need aboud 20 lines maybe less
We could have a common cross ARCH way to init timer via earlytimer
so the drivers are arch independant
and no need anymore to store the timer in arch/arm/....
but all timer move to drivers/clocksource/
so less code in arch specially on arm where nearly all vendor have it's own timer drivers
Best Regards,
J.
PATCH 9/14 at91: switch pit timer to early platform devices
In reply to Andrew VictorHi Andrew,
Quoted 18 lines · Andrew Victor
hi Russell,
Quoted 6 lines
Quoted 2 lines
I think it would be cleaner still if the "struct
sys_timer" could include a register-base-address field. ??Russell?That's not really what all platforms want, and with the advent of clocksources and clock events, I think the
sys_timerthing is mostly dead.How would those systems initialize the system-timer? An "
init_timer" method in the machine-description?Quoted 5 lines
I've been thinking about killing it off for a while for those platforms using the
GENERIC_CLOCKEVENTSstuff. ??From what I can see, the only real users of it are: acorn (riscpc), at91x40, clps711x, ebsa110, ep93xx, h720x, ixp2000, ixp23xx, ks8695, nuc93x, pnx4008, and samsung.
Quoted 6 lines
Quoted 3 lines
It would be nice to get the modern stuff out of that converted to the clockevents/clocksource stuff - any chance of that happening for AT91x40?
The AT91x40 (ARM7) is maintained by Greg Ungerer.
Greg?
I'll have a look when I get a minute.
Regards
Greg
------------------------------------------------------------------------
Greg Ungerer -- Principal Engineer EMAIL: gerg at snapgear.com SnapGear Group, McAfee PHONE: +61 7 3435 2888 8 Gardner Close FAX: +61 7 3217 5323 Milton, QLD, 4064, Australia WEB: http://www.SnapGear.com
PATCH 9/14 at91: switch pit timer to early platform devices
In reply to Russell King - ARM LinuxQuoted 7 lines · Russell King - ARM Linux
Quoted 6 lines · Andrew Victor
hi,
Quoted 3 lines
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
Quoted 8 lines
Quoted 5 lines
I really don't see the fascination with early
platform_devicesfor timer. Asys_timeris initialized way earlier, and there are surely cleaner ways to just pass a "base address" through to the driver.
The interrupt is alwaysAT91_ID_SYSon all chips, so there is no point making it configurable.Me too - it looks like this early device stuff is heading in the wrong direction.
Me too. Most of the stuff can be initialized much later and really only timer and interrupts are needed early. Sure there are easily dependencies to clock framework etc, but only those clocks need to be initialized.
Regards,
Tony
PATCH 9/14 at91: switch pit timer to early platform devices
Quoted 14 lines · Tony Lindgren
Quoted 13 lines · Russell King - ARM Linux
Quoted 11 lines · Andrew Victor
hi,
Quoted 3 lines
this will allow to specify the resources per soc
as the 5series use a different start address for the pit
I really don't see the fascination with early
platform_devicesfor timer. Asys_timeris initialized way earlier, and there are surely cleaner ways to just pass a "base address" through to the driver.
The interrupt is alwaysAT91_ID_SYSon all chips, so there is no point making it configurable.
Quoted 7 lines
Quoted 2 lines
Me too - it looks like this early device stuff is heading in the wrong direction.
Me too. Most of the stuff can be initialized much later and really only timer and interrupts are needed early. Sure there are easily dependencies to clock framework etc, but only those clocks need to be initialized.
I agree too
that's why I just do timer, interrupt, earlyprintk and clocks
the rest no need to be so early
Best Regards,
J.
PATCH 10/14 at91: switch st timer to early platform devices
In reply to Jean-Christophe PLAGNIOL-VILLARDthis will allow to specify the resources per soc and have only one time init for all boards except x40
--- arch/arm/mach-at91/at91rm9200.c | 6 + arch/arm/mach-at91/at91rm9200_time.c | 271 +++++++++++++++++++++++--------- arch/arm/mach-at91/board-1arm.c | 2 +- arch/arm/mach-at91/board-carmeva.c | 2 +- arch/arm/mach-at91/board-cpuat91.c | 2 +- arch/arm/mach-at91/board-csb337.c | 2 +- arch/arm/mach-at91/board-csb637.c | 2 +- arch/arm/mach-at91/board-eb9200.c | 2 +- arch/arm/mach-at91/board-ecbat91.c | 2 +- arch/arm/mach-at91/board-eco920.c | 2 +- arch/arm/mach-at91/board-kafa.c | 2 +- arch/arm/mach-at91/board-kb9202.c | 2 +- arch/arm/mach-at91/board-picotux200.c | 2 +- arch/arm/mach-at91/board-rm9200dk.c | 2 +- arch/arm/mach-at91/board-rm9200ek.c | 2 +- arch/arm/mach-at91/board-yl-9200.c | 2 +- arch/arm/mach-at91/generic.h | 2 +- arch/arm/mach-at91/soc.c | 21 +++- arch/arm/mach-at91/soc.h | 1 + 19 files changed, 237 insertions(+), 92 deletions(-)
arch/arm/mach-at91/at91rm9200.c +6 -0
@@ -378,6 +378,11 @@ static unsigned int at91rm9200_default_irq_priority[NR_AIC_IRQS] __initdata = {0 /* Advanced Interrupt Controller (IRQ6) */ }; +struct at91_dev_resource at91rm9200_st__initdata = { + .mmio_base =AT91_ST , + .irq =AT91_ID_SYS , +}; +struct at91_soc __initdata at91rm9200_soc = { .name ="at91rm9200" , .default_irq_priority = at91rm9200_default_irq_priority,
@@ -386,4 +391,5 @@ struct at91_soc __initdata at91rm9200_soc = { .resource = at91rm9200_pios, .num_resources = ARRAY_SIZE(at91rm9200_pios), }, + .st = &at91rm9200_st, };
arch/arm/mach-at91/at91rm9200_time.c +195 -76
378 lines not on this page · raw message
arch/arm/mach-at91/board-1arm.c +1 -1
@@ -97,7 +97,7 @@ static void __init onearm_board_init(void)MACHINE_START (ONEARM ,"Ajeco 1ARM single board computer" )/* Maintainer: Lennert Buytenhek <[email protected]> */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = onearm_map_io, .init_irq = onearm_init_irq, .init_machine = onearm_board_init,
arch/arm/mach-at91/board-carmeva.c +1 -1
@@ -163,7 +163,7 @@ static void __init carmeva_board_init(void)MACHINE_START (CARMEVA ,"Carmeva" )/* Maintainer: Conitec Datasystems */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = carmeva_map_io, .init_irq = carmeva_init_irq, .init_machine = carmeva_board_init,
arch/arm/mach-at91/board-cpuat91.c +1 -1
@@ -180,7 +180,7 @@ static void __init cpuat91_board_init(void)MACHINE_START (CPUAT91 ,"Eukrea" )/* Maintainer: Eric Benard - EUKREA Electromatique */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = cpuat91_map_io, .init_irq = cpuat91_init_irq, .init_machine = cpuat91_board_init,
arch/arm/mach-at91/board-csb337.c +1 -1
@@ -258,7 +258,7 @@ static void __init csb337_board_init(void)MACHINE_START (CSB337 ,"Cogent CSB337" )/* Maintainer: Bill Gatliff */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = csb337_map_io, .init_irq = csb337_init_irq, .init_machine = csb337_board_init,
arch/arm/mach-at91/board-csb637.c +1 -1
@@ -139,7 +139,7 @@ static void __init csb637_board_init(void)MACHINE_START (CSB637 ,"Cogent CSB637" )/* Maintainer: Bill Gatliff */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = csb637_map_io, .init_irq = csb637_init_irq, .init_machine = csb637_board_init,
arch/arm/mach-at91/board-eb9200.c +1 -1
@@ -121,7 +121,7 @@ static void __init eb9200_board_init(void)MACHINE_START (ATEB9200 ,"Embest ATEB9200" ) .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = eb9200_map_io, .init_irq = eb9200_init_irq, .init_machine = eb9200_board_init,
arch/arm/mach-at91/board-ecbat91.c +1 -1
@@ -173,7 +173,7 @@ static void __init ecb_at91board_init(void)MACHINE_START (ECBAT91 ,"emQbit's ECB_AT91" )/* Maintainer: emQbit.com */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = ecb_at91map_io, .init_irq = ecb_at91init_irq, .init_machine = ecb_at91board_init,
arch/arm/mach-at91/board-eco920.c +1 -1
@@ -135,7 +135,7 @@ static void __init eco920_board_init(void)MACHINE_START (ECO920 ,"eco920" )/* Maintainer: Sascha Hauer */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = eco920_map_io, .init_irq = eco920_init_irq, .init_machine = eco920_board_init,
arch/arm/mach-at91/board-kafa.c +1 -1
@@ -99,7 +99,7 @@ static void __init kafa_board_init(void)MACHINE_START (KAFA ,"Sperry-Sun KAFA" )/* Maintainer: Sergei Sharonov */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = kafa_map_io, .init_irq = kafa_init_irq, .init_machine = kafa_board_init,
arch/arm/mach-at91/board-kb9202.c +1 -1
@@ -140,7 +140,7 @@ static void __init kb9202_board_init(void)MACHINE_START (KB9200 ,"KB920x" )/* Maintainer: KwikByte, Inc. */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = kb9202_map_io, .init_irq = kb9202_init_irq, .init_machine = kb9202_board_init,
arch/arm/mach-at91/board-picotux200.c +1 -1
@@ -124,7 +124,7 @@ static void __init picotux200_board_init(void)MACHINE_START (PICOTUX2XX ,"picotux 200" )/* Maintainer: Kleinhenz Elektronik GmbH */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = picotux200_map_io, .init_irq = picotux200_init_irq, .init_machine = picotux200_board_init,
arch/arm/mach-at91/board-rm9200dk.c +1 -1
@@ -228,7 +228,7 @@ static void __init dk_board_init(void)MACHINE_START (AT91RM9200DK ,"Atmel AT91RM9200-DK" )/* Maintainer: SAN People/Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = dk_map_io, .init_irq = dk_init_irq, .init_machine = dk_board_init,
arch/arm/mach-at91/board-rm9200ek.c +1 -1
@@ -194,7 +194,7 @@ static void __init ek_board_init(void)MACHINE_START (AT91RM9200EK ,"Atmel AT91RM9200-EK" )/* Maintainer: SAN People/Atmel */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = ek_map_io, .init_irq = ek_init_irq, .init_machine = ek_board_init,
arch/arm/mach-at91/board-yl-9200.c +1 -1
@@ -599,7 +599,7 @@ static void __init yl9200_board_init(void)MACHINE_START (YL9200 ,"uCdragon YL-9200" )/* Maintainer: S.Birtles */ .boot_params = AT91_SDRAM_BASE + 0x100, - .timer = &at91rm9200_timer, + .timer = &at91_timer, .map_io = yl9200_map_io, .init_irq = yl9200_init_irq, .init_machine = yl9200_board_init,
arch/arm/mach-at91/generic.h +1 -1
@@ -22,7 +22,7 @@ extern void __init at91_aic_init(unsigned int priority[]);/* Timer */ struct sys_timer ; -extern struct sys_timer at91rm9200_timer; +extern struct sys_timer at91_timer;extern struct sys_timer at91_timer;extern struct sys_timer at91x40_timer;
arch/arm/mach-at91/soc.c +20 -1
@@ -229,18 +229,37 @@ static struct platform_device at91_pit_device = { .num_resources = ARRAY_SIZE(pit_resources), }; +/* +* ST (system timer) module supports both clockevents and clocksource. +*/ +static struct resource st_resources[] = { + [0 ] =RES_MEM (SZ_256 ), + [1 ] =RES_IRQ (), +}; + +static struct platform_device at91_st_device = { + .name ="at91_st" , + .id =0 , + .resource = st_resources, + .num_resources =ARRAY_SIZE (st_resources), +}; +static void __init at91_timer_init (void ) {struct at91_dev_resource *res;struct platform_device *pdev;struct resource *r; -BUG_ON (!current_soc.pit); +BUG_ON (!current_soc.pit && !current_soc.st);if (current_soc.pit) { r = pit_resources; res = current_soc.pit; pdev = &at91_pit_device; + }else { + r = st_resources; + res = current_soc.st; + pdev = &at91_st_device; }set_resource_mem (&r[0 ], res->mmio_base);
arch/arm/mach-at91/soc.h +1 -0
@@ -14,6 +14,7 @@ struct at91_soc {struct at91_dev_resource_array gpio;struct at91_dev_resource *pit; +struct at91_dev_resource *st;void (*init)(unsigned long main_clock); };
Signature · 1 line
1.7.4.1
PATCH 11/14 at91: move pit timer to drivers/clocksource
In reply to Jean-Christophe PLAGNIOL-VILLARD--- MAINTAINERS | 1 + arch/arm/mach-at91/Kconfig | 4 ++++ arch/arm/mach-at91/Makefile | 18 +++++++++--------- arch/arm/mach-at91/include/mach/at91_st.h | 20 ++++++++++---------- drivers/clocksource/Makefile | 1 + .../clocksource/at91_pit.c | 0 6 files changed, 25 insertions(+), 19 deletions(-) rename arch/arm/mach-at91/at91sam926x_time.c => drivers/clocksource/at91_pit.c (100%)
MAINTAINERS +1 -0
@@ -655,6 +655,7 @@ W: http://www.linux4sam.org S: Supported F: arch/arm/mach-at91/ F: drivers/gpio/at91_gpio.c +F: drivers/clocksource/at91_* ARM/BCMRING ARM ARCHITECTURE M: Jiandong Zheng <[email protected]>
arch/arm/mach-at91/Kconfig +4 -0
@@ -97,6 +97,10 @@ config AT91_PMC_UNIT bool default !ARCH_AT91X40 +config AT91_PIT + bool + default !ARCH_AT91X40 && !ARCH_AT91RM9200 + # ---------------------------------------------------------- if ARCH_AT91RM9200
arch/arm/mach-at91/Makefile +9 -9
@@ -11,15 +11,15 @@ obj-$(CONFIG_AT91_PMC_UNIT) += clock.o # CPU-specific support obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o -obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam926x_time.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam926x_time.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam926x_time.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam926x_time.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o -obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam926x_time.o at91sam9g45_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91sam926x_time.o at91cap9_devices.o sam9_smc.o -obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at91sam926x_time.o at572d940hf_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9RL) += at91sam9rl.o at91sam9rl_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o +obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT91CAP9) += at91cap9.o at91cap9_devices.o sam9_smc.o +obj-$(CONFIG_ARCH_AT572D940HF) += at572d940hf.o at572d940hf_devices.o sam9_smc.o obj-$(CONFIG_ARCH_AT91X40) += at91x40.o at91x40_time.o # AT91RM9200 board-specific support
arch/arm/mach-at91/include/mach/at91_st.h +10 -10
@@ -16,34 +16,34 @@#ifndef AT91_ST_H #define AT91_ST_H -#define AT91_ST_CR (AT91_ST + 0x00)/* Control Register */ +#define AT91_ST_CR (0x00)/* Control Register */ #define AT91_ST_WDRST (1 << 0)/* Watchdog Timer Restart */ -#define AT91_ST_PIMR (AT91_ST + 0x04)/* Period Interval Mode Register */ +#define AT91_ST_PIMR (0x04)/* Period Interval Mode Register */ #define AT91_ST_PIV (0xffff << 0)/* Period Interval Value */ -#define AT91_ST_WDMR (AT91_ST + 0x08)/* Watchdog Mode Register */ +#define AT91_ST_WDMR (0x08)/* Watchdog Mode Register */ #define AT91_ST_WDV (0xffff << 0)/* Watchdog Counter Value */ #define AT91_ST_RSTEN (1 << 16)/* Reset Enable */ #define AT91_ST_EXTEN (1 << 17)/* External Signal Assertion Enable */ -#define AT91_ST_RTMR (AT91_ST + 0x0c)/* Real-time Mode Register */ +#define AT91_ST_RTMR (0x0c)/* Real-time Mode Register */ #define AT91_ST_RTPRES (0xffff << 0)/* Real-time Prescalar Value */ -#define AT91_ST_SR (AT91_ST + 0x10)/* Status Register */ +#define AT91_ST_SR (0x10)/* Status Register */ #define AT91_ST_PITS (1 << 0)/* Period Interval Timer Status */ #define AT91_ST_WDOVF (1 << 1)/* Watchdog Overflow */ #define AT91_ST_RTTINC (1 << 2)/* Real-time Timer Increment */ #define AT91_ST_ALMS (1 << 3)/* Alarm Status */ -#define AT91_ST_IER (AT91_ST + 0x14)/* Interrupt Enable Register */ -#define AT91_ST_IDR (AT91_ST + 0x18)/* Interrupt Disable Register */ -#define AT91_ST_IMR (AT91_ST + 0x1c)/* Interrupt Mask Register */ +#define AT91_ST_IER (0x14)/* Interrupt Enable Register */ +#define AT91_ST_IDR (0x18)/* Interrupt Disable Register */ +#define AT91_ST_IMR (0x1c)/* Interrupt Mask Register */ -#define AT91_ST_RTAR (AT91_ST + 0x20)/* Real-time Alarm Register */ +#define AT91_ST_RTAR (0x20)/* Real-time Alarm Register */ #define AT91_ST_ALMV (0xfffff << 0)/* Alarm Value */ -#define AT91_ST_CRTR (AT91_ST + 0x24)/* Current Real-time Register */ +#define AT91_ST_CRTR (0x24)/* Current Real-time Register */ #define AT91_ST_CRTV (0xfffff << 0)/* Current Real-Time Value */ #endif
drivers/clocksource/Makefile +1 -0
@@ -1,3 +1,4 @@ +obj-$(CONFIG_AT91_PIT) += at91_pit.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
drivers/clocksource/at91_pit.c renamed from arch/arm/mach-at91/at91sam926x_time.c +0 -0
Signature · 1 line
1.7.4.1
PATCH 12/14 at91: move st timer to drivers/clocksource
In reply to Jean-Christophe PLAGNIOL-VILLARD--- arch/arm/mach-at91/Kconfig | 4 + arch/arm/mach-at91/Makefile | 2 +- arch/arm/mach-at91/at91rm9200_time.c | 328 ---------------------------------- drivers/clocksource/Makefile | 1 + 4 files changed, 6 insertions(+), 329 deletions(-) delete mode 100644 arch/arm/mach-at91/at91rm9200_time.c
arch/arm/mach-at91/Kconfig +4 -0
@@ -101,6 +101,10 @@ config AT91_PIT bool default !ARCH_AT91X40 && !ARCH_AT91RM9200 +config AT91_ST + bool + default ARCH_AT91RM9200 + # ---------------------------------------------------------- if ARCH_AT91RM9200
arch/arm/mach-at91/Makefile +1 -1
@@ -10,7 +10,7 @@ obj- := obj-$(CONFIG_AT91_PMC_UNIT) += clock.o # CPU-specific support -obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devices.o +obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_devices.o obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o sam9_smc.o at91sam9_alt_reset.o
arch/arm/mach-at91/at91rm9200_time.c deleted +0 -328
328 lines not on this page · raw message
drivers/clocksource/Makefile +1 -0
@@ -1,4 +1,5 @@ obj-$(CONFIG_AT91_PIT) += at91_pit.o +obj-$(CONFIG_AT91_ST) += at91_st.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
Signature · 1 line
1.7.4.1
PATCH 13/14 at91: move register clocks to soc generic init
In reply to Jean-Christophe PLAGNIOL-VILLARD--- arch/arm/mach-at91/at572d940hf.c | 4 +--- arch/arm/mach-at91/at91cap9.c | 4 +--- arch/arm/mach-at91/at91rm9200.c | 4 +--- arch/arm/mach-at91/at91sam9260.c | 4 +--- arch/arm/mach-at91/at91sam9261.c | 4 +--- arch/arm/mach-at91/at91sam9263.c | 4 +--- arch/arm/mach-at91/at91sam9g45.c | 4 +--- arch/arm/mach-at91/at91sam9rl.c | 4 +--- arch/arm/mach-at91/soc.c | 3 +++ arch/arm/mach-at91/soc.h | 1 + 10 files changed, 12 insertions(+), 24 deletions(-)
arch/arm/mach-at91/at572d940hf.c +1 -3
@@ -370,9 +370,6 @@ static void __init at572d940hf_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at572d940hf_register_clocks (); }/* --------------------------------------------------------------------
@@ -425,6 +422,7 @@ struct at91_dev_resource at572d940hf_pit __initdata = {struct at91_soc __initdata at572d940hf_soc = { .name ="at572d940hf" , .default_irq_priority = at572d940hf_default_irq_priority, + .register_clocks = at572d940hf_register_clocks, .init = at572d940hf_initialize, .gpio = { .resource = at572d940hf_pios,
arch/arm/mach-at91/at91cap9.c +1 -3
@@ -368,9 +368,6 @@ static void __init at91cap9_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); -/* Register the processor-specific clocks */ -at91cap9_register_clocks (); -/* Remember the silicon revision */ if (cpu_is_at91cap9_revB ()) system_rev =0xB ;
@@ -428,6 +425,7 @@ struct at91_dev_resource at91cap9_pit __initdata = {struct at91_soc __initdata at91cap9_soc = { .name ="at91cap9" , .default_irq_priority = at91cap9_default_irq_priority, + .register_clocks = at91cap9_register_clocks, .init = at91cap9_initialize, .gpio = { .resource = at91cap9_pios,
arch/arm/mach-at91/at91rm9200.c +1 -3
@@ -330,9 +330,6 @@ static void __init at91rm9200_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91rm9200_register_clocks (); }
@@ -386,6 +383,7 @@ struct at91_dev_resource at91rm9200_st __initdata = {struct at91_soc __initdata at91rm9200_soc = { .name ="at91rm9200" , .default_irq_priority = at91rm9200_default_irq_priority, + .register_clocks = at91rm9200_register_clocks, .init = at91rm9200_initialize, .gpio = { .resource = at91rm9200_pios,
arch/arm/mach-at91/at91sam9260.c +1 -3
@@ -362,9 +362,6 @@ static void __init at91sam9260_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9260_register_clocks (); }/* --------------------------------------------------------------------
@@ -417,6 +414,7 @@ struct at91_dev_resource at91sam9260_pit __initdata = {struct at91_soc __initdata at91sam9260_soc = { .name ="at91sam9260" , .default_irq_priority = at91sam9260_default_irq_priority, + .register_clocks = at91sam9260_register_clocks, .init = at91sam9260_initialize, .gpio = { .resource = at91sam9260_pios,
arch/arm/mach-at91/at91sam9261.c +1 -3
@@ -328,9 +328,6 @@ static void __init at91sam9261_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9261_register_clocks (); }/* --------------------------------------------------------------------
@@ -383,6 +380,7 @@ struct at91_dev_resource at91sam9261_pit __initdata = {struct at91_soc __initdata at91sam9261_soc = { .name ="at91sam9261" , .default_irq_priority = at91sam9261_default_irq_priority, + .register_clocks = at91sam9261_register_clocks, .init = at91sam9261_initialize, .gpio = { .resource = at91sam9261_pios,
arch/arm/mach-at91/at91sam9263.c +1 -3
@@ -337,9 +337,6 @@ static void __init at91sam9263_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9263_register_clocks (); }/* --------------------------------------------------------------------
@@ -392,6 +389,7 @@ struct at91_dev_resource at91sam9263_pit __initdata = {struct at91_soc __initdata at91sam9263_soc = { .name ="at91sam9263" , .default_irq_priority = at91sam9263_default_irq_priority, + .register_clocks = at91sam9263_register_clocks, .init = at91sam9263_initialize, .gpio = { .resource = at91sam9263_pios,
arch/arm/mach-at91/at91sam9g45.c +1 -3
@@ -355,9 +355,6 @@ static void __init at91sam9g45_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9g45_register_clocks (); }/* --------------------------------------------------------------------
@@ -410,6 +407,7 @@ struct at91_dev_resource at91sam9g45_pit __initdata = {struct at91_soc __initdata at91sam9g45_soc = { .name ="at91sam9g45" , .default_irq_priority = at91sam9g45_default_irq_priority, + .register_clocks = at91sam9g45_register_clocks, .init = at91sam9g45_initialize, .gpio = { .resource = at91sam9g45_pios,
arch/arm/mach-at91/at91sam9rl.c +1 -3
@@ -321,9 +321,6 @@ static void __init at91sam9rl_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9rl_register_clocks (); }/* --------------------------------------------------------------------
@@ -376,6 +373,7 @@ struct at91_dev_resource at91sam9rl_pit __initdata = {struct at91_soc __initdata at91sam9rl_soc = { .name ="at91sam9rl" , .default_irq_priority = at91sam9rl_default_irq_priority, + .register_clocks = at91sam9rl_register_clocks, .init = at91sam9rl_initialize, .gpio = { .resource = at91sam9rl_pios,
arch/arm/mach-at91/soc.c +3 -0
@@ -117,6 +117,9 @@ void __init at91_initialize(unsigned long main_clock) current_soc.init (main_clock); +/* Register the processor-specific clocks */ + current_soc.register_clocks (); +/* Register GPIO subsystem */ at91_add_gpio (); }
arch/arm/mach-at91/soc.h +1 -0
@@ -16,6 +16,7 @@ struct at91_soc {struct at91_dev_resource *pit;struct at91_dev_resource *st; +void (*register_clocks)(void );void (*init)(unsigned long main_clock); };
Signature · 1 line
1.7.4.1
PATCH 13/14 at91: move register clocks to soc generic init
Quoted 3 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>
Looks good.
Quoted 215 lines
--- arch/arm/mach-at91/at572d940hf.c | 4 +--- arch/arm/mach-at91/at91cap9.c | 4 +--- arch/arm/mach-at91/at91rm9200.c | 4 +--- arch/arm/mach-at91/at91sam9260.c | 4 +--- arch/arm/mach-at91/at91sam9261.c | 4 +--- arch/arm/mach-at91/at91sam9263.c | 4 +--- arch/arm/mach-at91/at91sam9g45.c | 4 +--- arch/arm/mach-at91/at91sam9rl.c | 4 +--- arch/arm/mach-at91/soc.c | 3 +++ arch/arm/mach-at91/soc.h | 1 + 10 files changed, 12 insertions(+), 24 deletions(-)arch/arm/mach-at91/at572d940hf.c +1
-3@@ -370,9 +370,6 @@ static void __init at572d940hf_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at572d940hf_register_clocks (); }/* -------------------------------------------------------------------- @@ -425,6 +422,7 @@ struct at91_dev_resource at572d940hf_pit __initdata = {struct at91_soc __initdata at572d940hf_soc = { .name ="at572d940hf" , .default_irq_priority = at572d940hf_default_irq_priority, + .register_clocks = at572d940hf_register_clocks, .init = at572d940hf_initialize, .gpio = { .resource = at572d940hf_pios,arch/arm/mach-at91/at91cap9.c +1
-3@@ -368,9 +368,6 @@ static void __init at91cap9_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); -/* Register the processor-specific clocks */ -at91cap9_register_clocks (); -/* Remember the silicon revision */ if (cpu_is_at91cap9_revB ()) system_rev =0xB ;@@ -428,6 +425,7 @@ struct at91_dev_resource at91cap9_pit __initdata = {struct at91_soc __initdata at91cap9_soc = { .name ="at91cap9" , .default_irq_priority = at91cap9_default_irq_priority, + .register_clocks = at91cap9_register_clocks, .init = at91cap9_initialize, .gpio = { .resource = at91cap9_pios,arch/arm/mach-at91/at91rm9200.c +1
-3@@ -330,9 +330,6 @@ static void __init at91rm9200_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91rm9200_register_clocks (); }@@ -386,6 +383,7 @@ struct at91_dev_resource at91rm9200_st __initdata = {struct at91_soc __initdata at91rm9200_soc = { .name ="at91rm9200" , .default_irq_priority = at91rm9200_default_irq_priority, + .register_clocks = at91rm9200_register_clocks, .init = at91rm9200_initialize, .gpio = { .resource = at91rm9200_pios,arch/arm/mach-at91/at91sam9260.c +1
-3@@ -362,9 +362,6 @@ static void __init at91sam9260_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9260_register_clocks (); }/* -------------------------------------------------------------------- @@ -417,6 +414,7 @@ struct at91_dev_resource at91sam9260_pit __initdata = {struct at91_soc __initdata at91sam9260_soc = { .name ="at91sam9260" , .default_irq_priority = at91sam9260_default_irq_priority, + .register_clocks = at91sam9260_register_clocks, .init = at91sam9260_initialize, .gpio = { .resource = at91sam9260_pios,arch/arm/mach-at91/at91sam9261.c +1
-3@@ -328,9 +328,6 @@ static void __init at91sam9261_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9261_register_clocks (); }/* -------------------------------------------------------------------- @@ -383,6 +380,7 @@ struct at91_dev_resource at91sam9261_pit __initdata = {struct at91_soc __initdata at91sam9261_soc = { .name ="at91sam9261" , .default_irq_priority = at91sam9261_default_irq_priority, + .register_clocks = at91sam9261_register_clocks, .init = at91sam9261_initialize, .gpio = { .resource = at91sam9261_pios,arch/arm/mach-at91/at91sam9263.c +1
-3@@ -337,9 +337,6 @@ static void __init at91sam9263_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9263_register_clocks (); }/* -------------------------------------------------------------------- @@ -392,6 +389,7 @@ struct at91_dev_resource at91sam9263_pit __initdata = {struct at91_soc __initdata at91sam9263_soc = { .name ="at91sam9263" , .default_irq_priority = at91sam9263_default_irq_priority, + .register_clocks = at91sam9263_register_clocks, .init = at91sam9263_initialize, .gpio = { .resource = at91sam9263_pios,arch/arm/mach-at91/at91sam9g45.c +1
-3@@ -355,9 +355,6 @@ static void __init at91sam9g45_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9g45_register_clocks (); }/* -------------------------------------------------------------------- @@ -410,6 +407,7 @@ struct at91_dev_resource at91sam9g45_pit __initdata = {struct at91_soc __initdata at91sam9g45_soc = { .name ="at91sam9g45" , .default_irq_priority = at91sam9g45_default_irq_priority, + .register_clocks = at91sam9g45_register_clocks, .init = at91sam9g45_initialize, .gpio = { .resource = at91sam9g45_pios,arch/arm/mach-at91/at91sam9rl.c +1
-3@@ -321,9 +321,6 @@ static void __init at91sam9rl_initialize(unsigned long main_clock)/* Init clock subsystem */ at91_clock_init (main_clock); - -/* Register the processor-specific clocks */ -at91sam9rl_register_clocks (); }/* -------------------------------------------------------------------- @@ -376,6 +373,7 @@ struct at91_dev_resource at91sam9rl_pit __initdata = {struct at91_soc __initdata at91sam9rl_soc = { .name ="at91sam9rl" , .default_irq_priority = at91sam9rl_default_irq_priority, + .register_clocks = at91sam9rl_register_clocks, .init = at91sam9rl_initialize, .gpio = { .resource = at91sam9rl_pios,arch/arm/mach-at91/soc.c +3
-0@@ -117,6 +117,9 @@ void __init at91_initialize(unsigned long main_clock) current_soc.init (main_clock); +/* Register the processor-specific clocks */ + current_soc.register_clocks (); +/* Register GPIO subsystem */ at91_add_gpio (); }arch/arm/mach-at91/soc.h +1
-0@@ -16,6 +16,7 @@ struct at91_soc {struct at91_dev_resource *pit;struct at91_dev_resource *st; +void (*register_clocks)(void );void (*init)(unsigned long main_clock); };
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 14/14 at91: move clock subsystem init to soc generic init
In reply to Jean-Christophe PLAGNIOL-VILLARD--- arch/arm/mach-at91/at572d940hf.c | 5 +---- arch/arm/mach-at91/at91cap9.c | 5 +---- arch/arm/mach-at91/at91rm9200.c | 5 +---- arch/arm/mach-at91/at91sam9260.c | 5 +---- arch/arm/mach-at91/at91sam9261.c | 5 +---- arch/arm/mach-at91/at91sam9263.c | 5 +---- arch/arm/mach-at91/at91sam9g45.c | 5 +---- arch/arm/mach-at91/at91sam9rl.c | 5 +---- arch/arm/mach-at91/soc.c | 5 ++++- arch/arm/mach-at91/soc.h | 2 +- 10 files changed, 13 insertions(+), 34 deletions(-)
arch/arm/mach-at91/at572d940hf.c +1 -4
@@ -359,7 +359,7 @@ static void at572d940hf_reset(void)* AT572D940HF processor initialization * -------------------------------------------------------------------- */ -static void __init at572d940hf_initialize (unsigned long main_clock) +static void __init at572d940hf_initialize (void ) {/* Map peripherals */ iotable_init (at572d940hf_io_desc,ARRAY_SIZE (at572d940hf_io_desc));
@@ -367,9 +367,6 @@ static void __init at572d940hf_initialize(unsigned long main_clock) at91_arch_reset = at572d940hf_reset; at91_extern_irq = (1 <<AT572D940HF_ID_IRQ0 ) | (1 <<AT572D940HF_ID_IRQ1 ) | (1 <<AT572D940HF_ID_IRQ2 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/at91cap9.c +1 -4
@@ -356,7 +356,7 @@ static void at91cap9_poweroff(void)* AT91CAP9 processor initialization * -------------------------------------------------------------------- */ -static void __init at91cap9_initialize (unsigned long main_clock) +static void __init at91cap9_initialize (void ) {/* Map peripherals */ iotable_init (at91cap9_io_desc,ARRAY_SIZE (at91cap9_io_desc));
@@ -365,9 +365,6 @@ static void __init at91cap9_initialize(unsigned long main_clock) pm_power_off = at91cap9_poweroff; at91_extern_irq = (1 <<AT91CAP9_ID_IRQ0 ) | (1 <<AT91CAP9_ID_IRQ1 ); -/* Init clock subsystem */ -at91_clock_init (main_clock); -/* Remember the silicon revision */ if (cpu_is_at91cap9_revB ()) system_rev =0xB ;
arch/arm/mach-at91/at91rm9200.c +1 -4
@@ -312,7 +312,7 @@ static void at91rm9200_reset(void)/* -------------------------------------------------------------------- * AT91RM9200 processor initialization * -------------------------------------------------------------------- */ -static void __init at91rm9200_initialize (unsigned long main_clock) +static void __init at91rm9200_initialize (void ) {if (cpu_is_at91rm9200_bga ()) at91rm9200_soc.gpio.num_resources =AT91RM9200_BGA ;
@@ -327,9 +327,6 @@ static void __init at91rm9200_initialize(unsigned long main_clock) | (1 << AT91RM9200_ID_IRQ2) | (1 << AT91RM9200_ID_IRQ3) | (1 <<AT91RM9200_ID_IRQ4 ) | (1 <<AT91RM9200_ID_IRQ5 ) | (1 <<AT91RM9200_ID_IRQ6 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }
arch/arm/mach-at91/at91sam9260.c +1 -4
@@ -344,7 +344,7 @@ static void __init at91sam9xe_initialize(void)iotable_init (at91sam9xe_sram_desc,ARRAY_SIZE (at91sam9xe_sram_desc)); } -static void __init at91sam9260_initialize (unsigned long main_clock) +static void __init at91sam9260_initialize (void ) {/* Map peripherals */
@@ -359,9 +359,6 @@ static void __init at91sam9260_initialize(unsigned long main_clock) pm_power_off = at91sam9260_poweroff; at91_extern_irq = (1 <<AT91SAM9260_ID_IRQ0 ) | (1 <<AT91SAM9260_ID_IRQ1 ) | (1 <<AT91SAM9260_ID_IRQ2 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/at91sam9261.c +1 -4
@@ -311,7 +311,7 @@ static void at91sam9261_poweroff(void)* AT91SAM9261 processor initialization * -------------------------------------------------------------------- */ -static void __init at91sam9261_initialize (unsigned long main_clock) +static void __init at91sam9261_initialize (void ) {/* Map peripherals */
@@ -325,9 +325,6 @@ static void __init at91sam9261_initialize(unsigned long main_clock) pm_power_off = at91sam9261_poweroff; at91_extern_irq = (1 <<AT91SAM9261_ID_IRQ0 ) | (1 <<AT91SAM9261_ID_IRQ1 ) | (1 <<AT91SAM9261_ID_IRQ2 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/at91sam9263.c +1 -4
@@ -326,7 +326,7 @@ static void at91sam9263_poweroff(void)* AT91SAM9263 processor initialization * -------------------------------------------------------------------- */ -static void __init at91sam9263_initialize (unsigned long main_clock) +static void __init at91sam9263_initialize (void ) {/* Map peripherals */ iotable_init (at91sam9263_io_desc,ARRAY_SIZE (at91sam9263_io_desc));
@@ -334,9 +334,6 @@ static void __init at91sam9263_initialize(unsigned long main_clock) at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9263_poweroff; at91_extern_irq = (1 <<AT91SAM9263_ID_IRQ0 ) | (1 <<AT91SAM9263_ID_IRQ1 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/at91sam9g45.c +1 -4
@@ -344,7 +344,7 @@ static void at91sam9g45_poweroff(void)* AT91SAM9G45 processor initialization * -------------------------------------------------------------------- */ -static void __init at91sam9g45_initialize (unsigned long main_clock) +static void __init at91sam9g45_initialize (void ) {/* Map peripherals */ iotable_init (at91sam9g45_io_desc,ARRAY_SIZE (at91sam9g45_io_desc));
@@ -352,9 +352,6 @@ static void __init at91sam9g45_initialize(unsigned long main_clock) at91_arch_reset = at91sam9g45_reset; pm_power_off = at91sam9g45_poweroff; at91_extern_irq = (1 <<AT91SAM9G45_ID_IRQ0 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/at91sam9rl.c +1 -4
@@ -292,7 +292,7 @@ static void at91sam9rl_poweroff(void)* AT91SAM9RL processor initialization * -------------------------------------------------------------------- */ -static void __init at91sam9rl_initialize (unsigned long main_clock) +static void __init at91sam9rl_initialize (void ) {unsigned long cidr, sram_size;
@@ -318,9 +318,6 @@ static void __init at91sam9rl_initialize(unsigned long main_clock) at91_arch_reset = at91sam9_alt_reset; pm_power_off = at91sam9rl_poweroff; at91_extern_irq = (1 <<AT91SAM9RL_ID_IRQ0 ); - -/* Init clock subsystem */ -at91_clock_init (main_clock); }/* --------------------------------------------------------------------
arch/arm/mach-at91/soc.c +4 -1
@@ -115,7 +115,10 @@ void __init at91_initialize(unsigned long main_clock)pr_info ("AT91: detected soc: %s\n" , current_soc.name); - current_soc.init (main_clock); + current_soc.init (); + +/* Init clock subsystem */ +at91_clock_init (main_clock);/* Register the processor-specific clocks */ current_soc.register_clocks ();
arch/arm/mach-at91/soc.h +1 -1
@@ -17,7 +17,7 @@ struct at91_soc {struct at91_dev_resource *st;void (*register_clocks)(void ); -void (*init)(unsigned long main_clock); +void (*init)(void ); };extern struct at91_soc at572d940hf_soc;
Signature · 1 line
1.7.4.1
PATCH 14/14 at91: move clock subsystem init to soc generic init
Quoted 3 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]>
<snip>
arch/arm/mach-at91/soc.c void __init at91_initialize(unsigned long main_clock) · line 118
Quoted 11 lines
/* --------------------------------------------------------------------
arch/arm/mach-at91/soc.c +1
-1@@ -115,7 +115,10 @@ void __init at91_initialize(unsigned long main_clock)pr_info ("AT91: detected soc: %s\n" , current_soc.name); - current_soc.init (main_clock); + current_soc.init ();
I think this patch should go near the beginning of the series so that current_soc.init never needs to take an argument.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 14/14 at91: move clock subsystem init to soc generic init
Quoted 14 lines · Ryan Mallon
Quoted 3 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]><snip>
Quoted 7 lines
/* --------------------------------------------------------------------
arch/arm/mach-at91/soc.c +0
-0@@ -115,7 +115,10 @@ void __init at91_initialize(unsigned long main_clock)
Quoted 7 lines
arch/arm/mach-at91/soc.c void __init at91_initialize(unsigned long main_clock) · line 118
Quoted 4 lines
arch/arm/mach-at91/soc.c +1
-1pr_info ("AT91: detected soc: %s\n" , current_soc.name); - current_soc.init (main_clock); + current_soc.init ();I think this patch should go near the beginning of the series so that current_soc.init never needs to take an argument.
no until you factorize the at91_init_clock you do need it
Best Regards,
J.
PATCH 14/14 at91: move clock subsystem init to soc generic init
Quoted 15 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 14 lines · Ryan Mallon
Quoted 3 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]><snip>
Quoted 7 lines
/* --------------------------------------------------------------------
arch/arm/mach-at91/soc.c +0
-0@@ -115,7 +115,10 @@ void __init at91_initialize(unsigned long main_clock)
Quoted 8 lines
Quoted 7 lines
arch/arm/mach-at91/soc.c void __init at91_initialize(unsigned long main_clock) · line 118
Quoted 4 lines
arch/arm/mach-at91/soc.c +1
-1pr_info ("AT91: detected soc: %s\n" , current_soc.name); - current_soc.init (main_clock); + current_soc.init ();I think this patch should go near the beginning of the series so that current_soc.init never needs to take an argument.
no until you factorize the
at91_init_clockyou do need it
That's my point. If you move this patch earlier so that at91_init_clock is factorised early then current_soc.init won't ever need the argument.
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
PATCH 14/14 at91: move clock subsystem init to soc generic init
Quoted 23 lines · Ryan Mallon
Quoted 22 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 21 lines · Ryan Mallon
Quoted 3 lines · Jean-Christophe PLAGNIOL-VILLARD
Signed-off-by Jean-Christophe PLAGNIOL-VILLARD <[email protected]>Cc Nicolas Ferre <[email protected]>Cc Patrice Vilchez <[email protected]><snip>
arch/arm/mach-at91/soc.c void __init at91_initialize(unsigned long main_clock) · line 118
Quoted 11 lines
/* --------------------------------------------------------------------
arch/arm/mach-at91/soc.c +1
-1@@ -115,7 +115,10 @@ void __init at91_initialize(unsigned long main_clock)pr_info ("AT91: detected soc: %s\n" , current_soc.name); - current_soc.init (main_clock); + current_soc.init ();I think this patch should go near the beginning of the series so that current_soc.init never needs to take an argument.
Quoted 4 lines
Quoted 1 line
no until you factorize the
at91_init_clockyou do need itThat's my point. If you move this patch earlier so that
at91_init_clockis factorised early then current_soc.init won't ever need the argument.
to do this I need to move the gpio and the cloock register and to do so I need to switch to clkdev and early device
if I move the gpio I need do to much more changesets so keep the change less intrusive is better
Best Regards,
J.
cover at91: factorize soc init and switch to early platform
In reply to Jean-Christophe PLAGNIOL-VILLARDQuoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
I finally had a chance to test this. On our Snapper 9G20 board (AT91SAM9G20) the latest linux-next gives me:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
<5>Linux version 2.6.39-rc4-next-20110427+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #850 Thu Apr 28 09:07:43 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
<0>Kernel panic - not syncing: Impossible to detect the CPU type
[<c002fb1c>] (unwind_backtrace+0x0/0xe4) from [<c0230820>] (panic+0x50/0x178)
[<c0230820>] (panic+0x50/0x178) from [<c000d414>] (at91_initialize+0x18/0x20)
[<c000d414>] (at91_initialize+0x18/0x20) from [<c000e298>] (snapper9260_map_io+0xc/0x5c)
[<c000e298>] (snapper9260_map_io+0xc/0x5c) from [<c000d0ec>] (paging_init+0x668/0x728)
[<c000d0ec>] (paging_init+0x668/0x728) from [<c000b5cc>] (setup_arch+0x39c/0x620)
[<c000b5cc>] (setup_arch+0x39c/0x620) from [<c000873c>] (start_kernel+0x6c/0x2c8)
I'll have a better look at this later to see if I can find the problem, though I suspect the remapping of the AT91_DBGU location is to blame. What platforms have you tested this on?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
cover at91: factorize soc init and switch to early platform
Quoted 30 lines · Ryan Mallon
Quoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
I finally had a chance to test this. On our Snapper 9G20 board (AT91SAM9G20) the latest linux-next gives me:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
<5>Linux version 2.6.39-rc4-next-20110427+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #850 Thu Apr 28 09:07:43 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
<0>Kernel panic - not syncing: Impossible to detect the CPU type
[<c002fb1c>] (unwind_backtrace+0x0/0xe4) from [<c0230820>] (panic+0x50/0x178)
[<c0230820>] (panic+0x50/0x178) from [<c000d414>] (at91_initialize+0x18/0x20)
[<c000d414>] (at91_initialize+0x18/0x20) from [<c000e298>] (snapper9260_map_io+0xc/0x5c)
[<c000e298>] (snapper9260_map_io+0xc/0x5c) from [<c000d0ec>] (paging_init+0x668/0x728)
[<c000d0ec>] (paging_init+0x668/0x728) from [<c000b5cc>] (setup_arch+0x39c/0x620)
[<c000b5cc>] (setup_arch+0x39c/0x620) from [<c000873c>] (start_kernel+0x6c/0x2c8)
Quoted 3 lines
I'll have a better look at this later to see if I can find the problem, though I suspect the remapping of the
AT91_DBGUlocation is to blame. What platforms have you tested this on?
9263ek
rm9200ek
try this branchgit://github.com/at91linux/linux-2.6-at91.git
branch test_cleanup
Best Regards,
J.
cover at91: factorize soc init and switch to early platform
In reply to Ryan MallonQuoted 30 lines · Ryan Mallon
Quoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
I finally had a chance to test this. On our Snapper 9G20 board (AT91SAM9G20) the latest linux-next gives me:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
<5>Linux version 2.6.39-rc4-next-20110427+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #850 Thu Apr 28 09:07:43 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
<0>Kernel panic - not syncing: Impossible to detect the CPU type
[<c002fb1c>] (unwind_backtrace+0x0/0xe4) from [<c0230820>] (panic+0x50/0x178)
[<c0230820>] (panic+0x50/0x178) from [<c000d414>] (at91_initialize+0x18/0x20)
[<c000d414>] (at91_initialize+0x18/0x20) from [<c000e298>] (snapper9260_map_io+0xc/0x5c)
[<c000e298>] (snapper9260_map_io+0xc/0x5c) from [<c000d0ec>] (paging_init+0x668/0x728)
[<c000d0ec>] (paging_init+0x668/0x728) from [<c000b5cc>] (setup_arch+0x39c/0x620)
[<c000b5cc>] (setup_arch+0x39c/0x620) from [<c000873c>] (start_kernel+0x6c/0x2c8)
Quoted 3 lines
I'll have a better look at this later to see if I can find the problem, though I suspect the remapping of the
AT91_DBGUlocation is to blame. What platforms have you tested this on?
I already found the issue and fix it
git://github.com/at91linux/linux-2.6-at91.git test_cleanup
Best Regards,
J.
cover at91: factorize soc init and switch to early platform
Quoted 31 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 30 lines · Ryan Mallon
Quoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
I finally had a chance to test this. On our Snapper 9G20 board (AT91SAM9G20) the latest linux-next gives me:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
<5>Linux version 2.6.39-rc4-next-20110427+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #850 Thu Apr 28 09:07:43 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
<0>Kernel panic - not syncing: Impossible to detect the CPU type
[<c002fb1c>] (unwind_backtrace+0x0/0xe4) from [<c0230820>] (panic+0x50/0x178)
[<c0230820>] (panic+0x50/0x178) from [<c000d414>] (at91_initialize+0x18/0x20)
[<c000d414>] (at91_initialize+0x18/0x20) from [<c000e298>] (snapper9260_map_io+0xc/0x5c)
[<c000e298>] (snapper9260_map_io+0xc/0x5c) from [<c000d0ec>] (paging_init+0x668/0x728)
[<c000d0ec>] (paging_init+0x668/0x728) from [<c000b5cc>] (setup_arch+0x39c/0x620)
[<c000b5cc>] (setup_arch+0x39c/0x620) from [<c000873c>] (start_kernel+0x6c/0x2c8)
Quoted 6 lines
Quoted 3 lines
I'll have a better look at this later to see if I can find the problem, though I suspect the remapping of the
AT91_DBGUlocation is to blame. What platforms have you tested this on?I already found the issue and fix it
git://github.com/at91linux/linux-2.6-at91.gittest_cleanup
Okay, that is working a bit better, not quite booting yet, but a little further along :-).
Couple of bugs I've noticed so far: In board-stamp9g20.c and board-sam9g20ek.c you have missed the .init_irq initialisation change for the first MACHINE_START. It causes a build failure if either of these boards are included.
Also at91x40 (e.g. board-eb01.c) does not get converted? I don't known anything about this SoC. Is this intentional?
~Ryan
Signature · 7 lines
Bluewater Systems Ltd - ARM Technology Solution Centre Ryan Mallon 5 Amuri Park, 404 Barbadoes St ryan at bluewatersys.com PO Box 13 889, Christchurch 8013 http://www.bluewatersys.com New Zealand Phone: +64 3 3779127 Freecall: Australia 1800 148 751 Fax: +64 3 3779135 USA 1800 261 2934
cover at91: factorize soc init and switch to early platform
Quoted 42 lines · Ryan Mallon
Quoted 31 lines · Jean-Christophe PLAGNIOL-VILLARD
Quoted 30 lines · Ryan Mallon
Quoted 8 lines · Jean-Christophe PLAGNIOL-VILLARD
Hi,
The following patch series start to factorize the soc init and switch gpio and timers to early platform
diff stat on arm
80 files changed, 1690 insertions(+), 2053 deletions(-)
I finally had a chance to test this. On our Snapper 9G20 board (AT91SAM9G20) the latest linux-next gives me:
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
<5>Linux version 2.6.39-rc4-next-20110427+ (ryan at okiwi) (gcc version 4.4.1 (Sourcery G++ Lite 2010q1-202) ) #850 Thu Apr 28 09:07:43 NZST 2011
CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00053177
CPU: VIVT data cache, VIVT instruction cache
Machine: Bluewater Systems Snapper 9260/9G20 module
Memory policy: ECC disabled, Data cache writeback
<0>Kernel panic - not syncing: Impossible to detect the CPU type
[<c002fb1c>] (unwind_backtrace+0x0/0xe4) from [<c0230820>] (panic+0x50/0x178)
[<c0230820>] (panic+0x50/0x178) from [<c000d414>] (at91_initialize+0x18/0x20)
[<c000d414>] (at91_initialize+0x18/0x20) from [<c000e298>] (snapper9260_map_io+0xc/0x5c)
[<c000e298>] (snapper9260_map_io+0xc/0x5c) from [<c000d0ec>] (paging_init+0x668/0x728)
[<c000d0ec>] (paging_init+0x668/0x728) from [<c000b5cc>] (setup_arch+0x39c/0x620)
[<c000b5cc>] (setup_arch+0x39c/0x620) from [<c000873c>] (start_kernel+0x6c/0x2c8)Quoted 6 lines
Quoted 3 lines
I'll have a better look at this later to see if I can find the problem, though I suspect the remapping of the
AT91_DBGUlocation is to blame. What platforms have you tested this on?I already found the issue and fix it
git://github.com/at91linux/linux-2.6-at91.gittest_cleanupOkay, that is working a bit better, not quite booting yet, but a little further along :-).
Quoted 7 lines
Couple of bugs I've noticed so far: In
board-stamp9g20.candboard-sam9g20ek.cyou have missed the .init_irq initialisation change for the firstMACHINE_START. It causes a build failure if either of these boards are included.Also at91x40 (e.g.
board-eb01.c) does not get converted? I don't known anything about this SoC. Is this intentional?
Yes it's intentionnal
this is a nommu soc and with just timer and clock driver so I do not update it and this soc does not have a DBGU so until we have a real implementation it's stay as now
Best Regards,
J.