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S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)

PATCH New Minkyu Kang 2 participants 2 messages May 19, 2011 – May 20, 2011 Arm (32-bit)

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Minkyu Kang

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PATCH 1/1 S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)

The source of pwm clock is fixed at evt1.
And some registers for pwm clock are removed.

Signed-off-by Minkyu Kang <[email protected]>
Signed-off-by Kyungmin Park <[email protected]>
---
 arch/arm/cpu/armv7/s5pc2xx/clock.c |   46 ++++++++++++++++++++---------------
 1 files changed, 26 insertions(+), 20 deletions(-)
arch/arm/cpu/armv7/s5pc2xx/clock.c +26 -20
index 624de62..5ecd475 100644
@@ -124,29 +124,35 @@ static unsigned long s5pc210_get_pwm_clk(void)
 	unsigned int sel;
 	unsigned int ratio;
 
-	/*
-	 * CLK_SRC_PERIL0
-	 * PWM_SEL [27:24]
-	 */
-	sel = readl(&clk->src_peril0);
-	sel = (sel >> 24) & 0xf;
-
-	if (sel == 0x6)
+	if (s5p_get_cpu_rev() == 0) {
+		/*
+		 * CLK_SRC_PERIL0
+		 * PWM_SEL [27:24]
+		 */
+		sel = readl(&clk->src_peril0);
+		sel = (sel >> 24) & 0xf;
+
+		if (sel == 0x6)
+			sclk = get_pll_clk(MPLL);
+		else if (sel == 0x7)
+			sclk = get_pll_clk(EPLL);
+		else if (sel == 0x8)
+			sclk = get_pll_clk(VPLL);
+		else
+			return 0;
+
+		/*
+		 * CLK_DIV_PERIL3
+		 * PWM_RATIO [3:0]
+		 */
+		ratio = readl(&clk->div_peril3);
+		ratio = ratio & 0xf;
+	} else if (s5p_get_cpu_rev() == 1) {
 		sclk = get_pll_clk(MPLL);
-	else if (sel == 0x7)
-		sclk = get_pll_clk(EPLL);
-	else if (sel == 0x8)
-		sclk = get_pll_clk(VPLL);
-	else
+		ratio = 8;
+	} else
 		return 0;
 
-	/*
-	 * CLK_DIV_PERIL3
-	 * PWM_RATIO [3:0]
-	 */
-	ratio = readl(&clk->div_peril3);
-	ratio = ratio & 0xf;
-
 	pclk = sclk / (ratio + 1);
 
 	return pclk;
Signature · 1 line
1.7.4.1