ARM: exynos4: fix secondary CPU boot

PATCH New Marc Zyngier 4 participants 13 messages May 20, 2011 – Jun 29, 2011

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Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Marc Zyngier

author

2011-05-20 13:46 UTC #0 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Patch 7d30e8b38 (ARM: EXYNOS4: Add EXYNOS4 CPU initialization support) renamed the s5pv310 to exynos4, and also changed the value of EXYNOS4_PA_SYSRAM, which is used to release the secondary CPU from spinning in BL0. As a result, CPU1 can't be brought up anymore.

This patch simply reverts EXYNOS4_PA_SYSRAM to its original value, which results in a working CPU1.

Tested on an SMDK-v310.

Cc Kukjin Kim <[email protected]>

Signed-off-by Marc Zyngier <[email protected]>

---
 arch/arm/mach-exynos4/include/mach/map.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/mach-exynos4/include/mach/map.h +1 -1

index 6330b73..862967f 100644
@@ -23,7 +23,7 @@
 
 #include <plat/map-s5p.h>
 
-#define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM		0x02025000
 
 #define EXYNOS4_PA_FIMC0		0x11800000
 #define EXYNOS4_PA_FIMC1		0x11810000

Signature · 1 line

1.7.0.4

Kukjin Kim

2011-05-25 17:28 UTC #1 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 21 lines · Marc Zyngier

Patch 7d30e8b38 (ARM: EXYNOS4: Add EXYNOS4 CPU initialization support) renamed the s5pv310 to exynos4, and also changed the value of EXYNOS4_PA_SYSRAM, which is used to release the secondary CPU from spinning in BL0. As a result, CPU1 can't be brought up anymore.
This patch simply reverts EXYNOS4_PA_SYSRAM to its original value, which results in a working CPU1.
Tested on an SMDK-v310.
Cc Kukjin Kim<[email protected]>
Signed-off-by Marc Zyngier<[email protected]>
---
  arch/arm/mach-exynos4/include/mach/map.h |    2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-exynos4/include/mach/map.h +0 -0
index 6330b73..862967f 100644

arch/arm/mach-exynos4/include/mach/map.h line 27

Quoted 6 lines

arch/arm/mach-exynos4/include/mach/map.h +1 -1

@@ -23,7 +23,7 @@
 
  #include<plat/map-s5p.h>
 
-#define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM		0x02025000

Hi Marc,

Hmm...the value, 0x02020000 is correct on Exynos4210 now.

So can't apply this but I know, you're right on old version of Exynos4210...let's think again about this.

Maybe I missed its commit for changing when I submitted it...

Quoted 2 lines

arch/arm/mach-exynos4/include/mach/map.h +0 -0

  #define EXYNOS4_PA_FIMC0		0x11800000
  #define EXYNOS4_PA_FIMC1		0x11810000

Signature · 7 lines

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Marc Zyngier

author

2011-05-25 18:03 UTC #2 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 30 lines · Kukjin Kim

Quoted 21 lines · Marc Zyngier
Patch 7d30e8b38 (ARM: EXYNOS4: Add EXYNOS4 CPU initialization support) renamed the s5pv310 to exynos4, and also changed the value of EXYNOS4_PA_SYSRAM, which is used to release the secondary CPU from spinning in BL0. As a result, CPU1 can't be brought up anymore.
This patch simply reverts EXYNOS4_PA_SYSRAM to its original value, which results in a working CPU1.
Tested on an SMDK-v310.
Cc Kukjin Kim<[email protected]>
Signed-off-by Marc Zyngier<[email protected]>
---
  arch/arm/mach-exynos4/include/mach/map.h |    2 +-
  1 files changed, 1 insertions(+), 1 deletions(-)
arch/arm/mach-exynos4/include/mach/map.h +0 -0
index 6330b73..862967f 100644
arch/arm/mach-exynos4/include/mach/map.h line 27
Quoted 6 lines
arch/arm/mach-exynos4/include/mach/map.h +1 -1
@@ -23,7 +23,7 @@
 
  #include<plat/map-s5p.h>
 
-#define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM		0x02025000
 
Hi Marc,

Quoted 4 lines

Hmm...the value, 0x02020000 is correct on Exynos4210 now.
So can't apply this but I know, you're right on old version of Exynos4210...let's think again about this.

So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.

What about the following patch?

M.

Quoted 1 line

From c27e75b86e1ee181987a9364286a888421e76205 Mon Sep 17 00:00:00 2001

From: Marc Zyngier <[email protected]>
Date: Fri, 20 May 2011 14:38:25 +0100
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions

It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.

The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).

Try to solve the problem by poking both locations. This should be safe as this is done early enough in the kernel boot process, and nobody should be using the SRAM yet.

Tested on a vintage SMDK-v310.

Cc Kukjin Kim <[email protected]>

Signed-off-by Marc Zyngier <[email protected]>

---
 arch/arm/mach-exynos4/include/mach/map.h |    1 +
 arch/arm/mach-exynos4/platsmp.c          |   14 ++++++++++++++
 2 files changed, 15 insertions(+), 0 deletions(-)

arch/arm/mach-exynos4/include/mach/map.h +1 -0

index 0009e77..781e149 100644
@@ -24,6 +24,7 @@
 #include <plat/map-s5p.h>
 
 #define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM_EVT0		0x02025000
 
 #define EXYNOS4_PA_FIMC0		0x11800000
 #define EXYNOS4_PA_FIMC1		0x11810000

arch/arm/mach-exynos4/platsmp.c +14 -0

index c5e65a0..f261c34 100644
@@ -155,6 +155,7 @@ void __init smp_init_cpus(void)
 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 {
 	int i;
+	void __iomem *sysram_evt0;
 
 	/*
 	 * Initialise the present map, which describes the set of CPUs

@@ -172,4 +173,17 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 	 * secondary CPU branches to this address.
 	 */
 	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+
+	/*
+	 * EVT0 has the system-wide flags register at a different address.
+	 * Poke it as well, in case we're running on an old SoC revision.
+	 */
+	sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);
+	if (!sysram_evt0) {
+		pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");
+		return;
+	}
+
+	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), sysram_evt0);
+	iounmap(sysram_evt0);
 }

Signature · 6 lines

1.7.0.4



-- 
Reality is an implementation detail.

Kukjin Kim

2011-05-25 19:06 UTC #3 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 2 lines · Marc Zyngier

Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:

(snip)

Quoted 4 lines

So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.

I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...

Quoted 2 lines

What about the following patch?

Uhm...this is really hack but I'd like to use another normal way...?

Quoted 14 lines

	M.
Quoted 1 line
From c27e75b86e1ee181987a9364286a888421e76205 Mon Sep 17 00:00:00 2001
From: Marc Zyngier<[email protected]>
Date: Fri, 20 May 2011 14:38:25 +0100
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.
The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).

Quoted 5 lines

Try to solve the problem by poking both locations. This should be safe as this is done early enough in the kernel boot process, and nobody should be using the SRAM yet.
Tested on a vintage SMDK-v310.

vintage ;)

Quoted 33 lines

Cc Kukjin Kim<[email protected]>

Signed-off-by Marc Zyngier<[email protected]>

---
  arch/arm/mach-exynos4/include/mach/map.h |    1 +
  arch/arm/mach-exynos4/platsmp.c          |   14 ++++++++++++++
  2 files changed, 15 insertions(+), 0 deletions(-)

arch/arm/mach-exynos4/include/mach/map.h +1 -0

index 0009e77..781e149 100644
@@ -24,6 +24,7 @@
  #include<plat/map-s5p.h>
 
  #define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM_EVT0		0x02025000
 
  #define EXYNOS4_PA_FIMC0		0x11800000
  #define EXYNOS4_PA_FIMC1		0x11810000

arch/arm/mach-exynos4/platsmp.c +1 -0

index c5e65a0..f261c34 100644
@@ -155,6 +155,7 @@ void __init smp_init_cpus(void)
  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  {
  	int i;
+	void __iomem *sysram_evt0;
 
  	/*
  	 * Initialise the present map, which describes the set of CPUs

arch/arm/mach-exynos4/platsmp.c void __init platform_smp_prepare_cpus(unsigned int max_cpus) · line 181

Quoted 9 lines

arch/arm/mach-exynos4/platsmp.c +6 -0

@@ -172,4 +173,17 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  	 * secondary CPU branches to this address.
  	 */
  	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+
+	/*
+	 * EVT0 has the system-wide flags register at a different address.
+	 * Poke it as well, in case we're running on an old SoC revision.
+	 */
+	sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);

Hmm...first of all, need to check whether can ioremap the area on newer one but I'm out off office now so will check it after backing.

arch/arm/mach-exynos4/platsmp.c void __init platform_smp_prepare_cpus(unsigned int max_cpus) · line 183

Quoted 2 lines

arch/arm/mach-exynos4/platsmp.c +2 -0

+	if (!sysram_evt0) {
+		pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");

Do we really need 'pr_err' here?...

Quoted 6 lines

arch/arm/mach-exynos4/platsmp.c +5 -0

+		return;
+	}
+
+	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), sysram_evt0);
+	iounmap(sysram_evt0);
  }

Signature · 7 lines

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.

Marc Zyngier

author

2011-05-26 15:11 UTC #4 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 10 lines · Kukjin Kim

Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.

Quoted 6 lines

I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?

Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.

Is there such a way to identify the SoC revision?

Quoted 12 lines

Quoted 12 lines
Quoted 1 line
From c27e75b86e1ee181987a9364286a888421e76205 Mon Sep 17 00:00:00 2001
From: Marc Zyngier<[email protected]>
Date: Fri, 20 May 2011 14:38:25 +0100
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.
The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).

Quoted 7 lines

Quoted 5 lines
Try to solve the problem by poking both locations. This should be safe as this is done early enough in the kernel boot process, and nobody should be using the SRAM yet.
Tested on a vintage SMDK-v310.
vintage ;)

Well, I thought I was the uber-cool guy in the office because of that shiny blue board on my desk, only to discover that it's sooo last year... ;-)

Quoted 30 lines

Cc Kukjin Kim<[email protected]>

Signed-off-by Marc Zyngier<[email protected]>

---
  arch/arm/mach-exynos4/include/mach/map.h |    1 +
  arch/arm/mach-exynos4/platsmp.c          |   14 ++++++++++++++
  2 files changed, 15 insertions(+), 0 deletions(-)

arch/arm/mach-exynos4/include/mach/map.h +1 -0

index 0009e77..781e149 100644
@@ -24,6 +24,7 @@
  #include<plat/map-s5p.h>
 
  #define EXYNOS4_PA_SYSRAM		0x02020000
+#define EXYNOS4_PA_SYSRAM_EVT0		0x02025000
 
  #define EXYNOS4_PA_FIMC0		0x11800000
  #define EXYNOS4_PA_FIMC1		0x11810000

arch/arm/mach-exynos4/platsmp.c +1 -0

index c5e65a0..f261c34 100644
@@ -155,6 +155,7 @@ void __init smp_init_cpus(void)
  void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  {
  	int i;
+	void __iomem *sysram_evt0;

Quoted 15 lines

arch/arm/mach-exynos4/platsmp.c void __init platform_smp_prepare_cpus(unsigned int max_cpus) · line 181
Quoted 12 lines
arch/arm/mach-exynos4/platsmp.c +6 -0
  	/*
  	 * Initialise the present map, which describes the set of CPUs
@@ -172,4 +173,17 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
  	 * secondary CPU branches to this address.
  	 */
  	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+
+	/*
+	 * EVT0 has the system-wide flags register at a different address.
+	 * Poke it as well, in case we're running on an old SoC revision.
+	 */
+	sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);
Hmm...first of all, need to check whether can ioremap the area on newer one but I'm out off office now so will check it after backing.

The only documentation I have access to refers to the iRAM (SRAM) being mapped between 0x02020000 and 0x02040000. Unless the HW guys have gone completely wild and changed this range as well, I think we're pretty safe.

Quoted 4 lines

arch/arm/mach-exynos4/platsmp.c void __init platform_smp_prepare_cpus(unsigned int max_cpus) · line 183
Quoted 2 lines
arch/arm/mach-exynos4/platsmp.c +2 -0
+	if (!sysram_evt0) {
+		pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");
Do we really need 'pr_err' here?...

No. Anything will do. Though not being able to ioremap() that region may indicate further trouble down the road.

Quoted 7 lines

arch/arm/mach-exynos4/platsmp.c void __init platform_smp_prepare_cpus(unsigned int max_cpus) · line 189
Quoted 6 lines
arch/arm/mach-exynos4/platsmp.c +5 -0
+		return;
+	}
+
+	__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), sysram_evt0);
+	iounmap(sysram_evt0);
  }

Cheers,

M.

Signature · 1 line

Reality is an implementation detail.

Kyungmin Park

2011-06-02 07:01 UTC #5 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 16 lines · Marc Zyngier

Quoted 15 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?

Quoted 7 lines

Quoted 1 line
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Is there such a way to identify the SoC revision?

It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.

platform codes should provide the these function. please see the OMAP codes. how to handle it.

Thank you,
Kyungmin Park

Quoted 104 lines

Quoted 13 lines
Quoted 13 lines
Quoted 2 lines
From c27e75b86e1ee181987a9364286a888421e76205 Mon Sep 17 00:00:00 2001
From: Marc Zyngier<[email protected]>
Date: Fri, 20 May 2011 14:38:25 +0100
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.
The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).
Quoted 7 lines
Quoted 5 lines
Try to solve the problem by poking both locations. This should be safe as this is done early enough in the kernel boot process, and nobody should be using the SRAM yet.
Tested on a vintage SMDK-v310.
vintage ;)
Well, I thought I was the uber-cool guy in the office because of that shiny blue board on my desk, only to discover that it's sooo last year... ;-)
Quoted 30 lines
Quoted 30 lines
Cc Kukjin Kim<[email protected]>
Signed-off-by Marc Zyngier<[email protected]>
---
? arch/arm/mach-exynos4/include/mach/map.h | ? ?1 +
? arch/arm/mach-exynos4/platsmp.c ? ? ? ? ?| ? 14 ++++++++++++++ ? 2 files changed, 15 insertions(+), 0 deletions(-)
arch/arm/mach-exynos4/include/mach/map.h +0 -0
index 0009e77..781e149 100644
@@ -24,6 +24,7 @@
? #include<plat/map-s5p.h>
? #define EXYNOS4_PA_SYSRAM ? ? ? ? 0x02020000 +#define EXYNOS4_PA_SYSRAM_EVT0 ? ? ? ? ? ? 0x02025000
? #define EXYNOS4_PA_FIMC0 ? ? ? ? ?0x11800000
? #define EXYNOS4_PA_FIMC1 ? ? ? ? ?0x11810000
arch/arm/mach-exynos4/platsmp.c +1 -0
index c5e65a0..f261c34 100644
@@ -155,6 +155,7 @@ void __init smp_init_cpus(void)
 ? void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 ? {
 ? ? int i;
+ ? void __iomem *sysram_evt0;
 
Quoted 15 lines
Quoted 4 lines
? ? /*
? ? ?* Initialise the present map, which describes the set of CPUs
arch/arm/mach-exynos4/platsmp.c +0 -0
@@ -172,4 +173,17 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
? ? ?* secondary CPU branches to this address.
Quoted 8 lines
? ? ?*/
? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM); +
+ ? /*
+ ? ?* EVT0 has the system-wide flags register at a different address.
+ ? ?* Poke it as well, in case we're running on an old SoC revision.
+ ? ?*/
+ ? sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);
Hmm...first of all, need to check whether can ioremap the area on newer one but I'm out off office now so will check it after backing.
The only documentation I have access to refers to the iRAM (SRAM) being mapped between 0x02020000 and 0x02040000. Unless the HW guys have gone completely wild and changed this range as well, I think we're pretty safe.
Quoted 4 lines
Quoted 2 lines
+ ? if (!sysram_evt0) {
+ ? ? ? ? ? pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");
Do we really need 'pr_err' here?...
No. Anything will do. Though not being able to ioremap() that region may indicate further trouble down the road.
Quoted 7 lines
Quoted 6 lines
+ ? ? ? ? ? return;
+ ? }
+
+ ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), sysram_evt0);
+ ? iounmap(sysram_evt0);
? }
Cheers,
? ? ? ?M.
--
Reality is an implementation detail.
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Marc Zyngier

author

2011-06-02 08:34 UTC #6 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 23 lines · Kyungmin Park

Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.

Quoted 7 lines

Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.

So we know there's a need beyond the wish to see the second core up and running on my board.

Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.

Cheers,

M.

Signature · 1 line

Reality is an implementation detail.

Kyungmin Park

2011-06-02 08:39 UTC #7 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 32 lines · Marc Zyngier

Quoted 23 lines · Kyungmin Park
Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Quoted 7 lines
Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.

Quoted 6 lines

So we know there's a need beyond the wish to see the second core up and running on my board.
Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.

It can be distinguished by chip id. but there's no code to handle this one.

0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2

Thank you,
Kyungmin Park

Quoted 9 lines

Cheers,
? ? ? ?M.
--
Reality is an implementation detail.

Marc Zyngier

author

2011-06-02 08:53 UTC #8 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 40 lines · Kyungmin Park

Quoted 32 lines · Marc Zyngier
Quoted 23 lines · Kyungmin Park
Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Quoted 7 lines
Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.
Quoted 6 lines
So we know there's a need beyond the wish to see the second core up and running on my board.
Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.

Quoted 5 lines

It can be distinguished by chip id. but there's no code to handle this one.
0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2

Apparently, the low 8 bits can be overloaded by the efuse. Which makes telling EVT1 from EVT2 unreliable.

But at least this is a start. I'll see if I can come up with something minimal enough to be merged as a fix.

Thanks,

M.

Signature · 1 line

Reality is an implementation detail.

Angus Ainslie

2011-06-14 22:26 UTC #9 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 60 lines · Marc Zyngier

Quoted 40 lines · Kyungmin Park
Quoted 32 lines · Marc Zyngier
Quoted 23 lines · Kyungmin Park
Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Quoted 7 lines
Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.
Quoted 6 lines
So we know there's a need beyond the wish to see the second core up and running on my board.
Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.
Quoted 5 lines
It can be distinguished by chip id. but there's no code to handle this one.
0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2
Apparently, the low 8 bits can be overloaded by the efuse. Which makes telling EVT1 from EVT2 unreliable.
But at least this is a start. I'll see if I can come up with something minimal enough to be merged as a fix.
Thanks,
? ? ? ?M.
--
Reality is an implementation detail.

Quoted 5 lines

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Would something like this work instead ? It seems to work on EVT0 but I haven't had a chance to test on EVT1.

Kyungmin Park

2011-06-15 00:52 UTC #10 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 79 lines · Angus Ainslie

Quoted 60 lines · Marc Zyngier
Quoted 40 lines · Kyungmin Park
Quoted 32 lines · Marc Zyngier
Quoted 23 lines · Kyungmin Park
Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Quoted 7 lines
Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.
Quoted 6 lines
So we know there's a need beyond the wish to see the second core up and running on my board.
Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.
Quoted 5 lines
It can be distinguished by chip id. but there's no code to handle this one.
0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2
Apparently, the low 8 bits can be overloaded by the efuse. Which makes telling EVT1 from EVT2 unreliable.
But at least this is a start. I'll see if I can come up with something minimal enough to be merged as a fix.
Thanks,
? ? ? ?M.
--
Reality is an implementation detail.
Quoted 5 lines
--
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Would something like this work instead ? It seems to work on EVT0 but I haven't had a chance to test on EVT1.
From a4c1b643596599df9d79776c9b94f2536661a4c9 Mon Sep 17 00:00:00 2001
From: Angus Ainslie <[email protected]>
Date: Tue, 14 Jun 2011 16:13:35 -0600
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.

Quoted 6 lines

The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).
Use the CPU id to decide whether we are running on EVT0 and use the old location in that case.

Hi Angus,

Now this information is also required for other device drivers such as OneNAND. So can you make a generic function at common place such as plat-s5p? I mean we need a generic helper function for handling the EVT version at samsung platform.

Thank you,
Kyungmin Park

Quoted 81 lines

Signed-off-by Marc Zyngier <[email protected]>
Signed-off-by Angus Ainslie <[email protected]>
---
?arch/arm/mach-exynos4/include/mach/map.h | ? ?1 + ?arch/arm/mach-exynos4/platsmp.c ? ? ? ? ?| ? 23 ++++++++++++++++++++++- ?2 files changed, 23 insertions(+), 1 deletions(-)
arch/arm/mach-exynos4/include/mach/map.h +0 -0
index 0009e77..781e149 100644
@@ -24,6 +24,7 @@
?#include <plat/map-s5p.h>
?#define EXYNOS4_PA_SYSRAM ? ? ? ? ? ? ?0x02020000 +#define EXYNOS4_PA_SYSRAM_EVT0 ? ? ? ? 0x02025000
?#define EXYNOS4_PA_FIMC0 ? ? ? ? ? ? ? 0x11800000 ?#define EXYNOS4_PA_FIMC1 ? ? ? ? ? ? ? 0x11810000
arch/arm/mach-exynos4/platsmp.c +2 -0
index c5e65a0..5f70aec 100644
@@ -155,6 +155,8 @@ void __init smp_init_cpus(void)
 ?void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 ?{
 ? ? ? ?int i;
+ ? ? ? unsigned long idcode;
+ ? ? ? void __iomem *sysram_evt0;
 
? ? ? ?/*
? ? ? ? * Initialise the present map, which describes the set of CPUs
arch/arm/mach-exynos4/platsmp.c +2 -0
@@ -165,11 +167,30 @@ void __init platform_smp_prepare_cpus(unsigned
 int max_cpus)
 
 ? ? ? ?scu_enable(scu_base_addr());
 
+ ? ? ? idcode = __raw_readl(S5P_VA_CHIPID);
+
? ? ? ?/*
? ? ? ? * Write the address of secondary startup into the
? ? ? ? * system-wide flags register. The boot monitor waits
? ? ? ? * until it receives a soft interrupt, and then the
? ? ? ? * secondary CPU branches to this address.
? ? ? ? */
- ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+ ? ? ? if ((idcode & 0xF0000) == 0) {
+ ? ? ? ? ? ? ? /*
+ ? ? ? ? ? ? ? ?* EVT0 has the system-wide flags register at a different address.
+ ? ? ? ? ? ? ? ?* Poke it as well, in case we're running on an old SoC revision.
+ ? ? ? ? ? ? ? ?*/
+ ? ? ? ? ? ? ? sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);
+ ? ? ? ? ? ? ? if (!sysram_evt0) {
+ ? ? ? ? ? ? ? ? ? ? ? pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");
+ ? ? ? ? ? ? ? ? ? ? ? return;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?sysram_evt0);
+ ? ? ? ? ? ? ? iounmap(sysram_evt0);
+ ? ? ? } else {
+ ? ? ? ? ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?S5P_VA_SYSRAM);
+ ? ? ? }
+
?}
--
1.7.4.1
--
Angus Ainslie <[email protected]>
Team Lead, Samsung Landing Team
--
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Marc Zyngier

author

2011-06-15 09:53 UTC #11 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

Quoted 87 lines · Kyungmin Park

Quoted 79 lines · Angus Ainslie
Quoted 56 lines · Marc Zyngier
Quoted 40 lines · Kyungmin Park
Quoted 32 lines · Marc Zyngier
Quoted 23 lines · Kyungmin Park
Quoted 22 lines · Marc Zyngier
Quoted 10 lines · Kukjin Kim
Quoted 2 lines · Marc Zyngier
Quoted 1 line · Kukjin Kim
On 05/20/11 06:46, Marc Zyngier wrote:
(snip)
Quoted 4 lines
So that address has changed between two SoC revisions? That's unfortunate, to say the least. I'm most probably using an early revision of the hardware (EVT0?), as it doesn't even support MCT.
Quoted 6 lines
I'm afraid :( and I agree secondary CPU should work on all of Exynos4210. But I'm still think about the method...
Quoted 2 lines
What about the following patch?
Uhm...this is really hack but I'd like to use another normal way...?
Oh, no question about the hack status. The trouble is, unless there is a sure way to tell which SoC revision we're running on, there's little else we can do than poke both locations and pray.
Quoted 7 lines
Quoted 1 line
Is there such a way to identify the SoC revision?
It's also required for OneNAND. as you know C210 EVT0 OneNAND DMA has bug and need to workaround.
platform codes should provide the these function. please see the OMAP codes. how to handle it.
Quoted 6 lines
So we know there's a need beyond the wish to see the second core up and running on my board.
Now what is the proper method to detect the revision of the SOC? Handling it is no problem, once we have the information. Unfortunately the documentation I have is less than helpful on that subject.
Quoted 5 lines
It can be distinguished by chip id. but there's no code to handle this one.
0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2
Apparently, the low 8 bits can be overloaded by the efuse. Which makes telling EVT1 from EVT2 unreliable.
But at least this is a start. I'll see if I can come up with something minimal enough to be merged as a fix.
Thanks,
       M.
Quoted 9 lines
--
Reality is an implementation detail.
--
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Would something like this work instead ? It seems to work on EVT0 but I haven't had a chance to test on EVT1.
From a4c1b643596599df9d79776c9b94f2536661a4c9 Mon Sep 17 00:00:00 2001
From: Angus Ainslie <[email protected]>
Date: Tue, 14 Jun 2011 16:13:35 -0600
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.
Quoted 6 lines
The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).
Use the CPU id to decide whether we are running on EVT0 and use the old location in that case.

Quoted 6 lines

Hi Angus,
Now this information is also required for other device drivers such as OneNAND. So can you make a generic function at common place such as plat-s5p? I mean we need a generic helper function for handling the EVT version at samsung platform.

Here's what I have in my current tree. I just added a s3c_get_chip_id() helper, and used that in the secondary boot path. The same function could be used for OneNAND and MCT.

Cheers,

M.

Signature · 5 lines

Jazz is not dead. It just smells funny...
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Kyungmin Park

2011-06-29 05:52 UTC #12 lore raw

PATCH 1/1 ARM: exynos4: fix secondary CPU boot

It's first step to handle the EVT.

Acked-by Kyungmin Park <[email protected]>

Quoted 138 lines

Jazz is not dead. It just smells funny...
From a24392183d396fab790557b0efb35e840c9e8a81 Mon Sep 17 00:00:00 2001
From: Marc Zyngier <[email protected]>
Date: Fri, 20 May 2011 14:38:25 +0100
Subject: [PATCH] ARM: exynos4: fix secondary CPU boot on early SoC revisions
It appears that the system-wide flags register that used to be at 0x02025000 on the first revision of Exynos4 has moved to 0x02020000.
The kernel has been updated accordingly, but this unfortunately leaves early boards without SMP support (the secondary CPU spins endlessly in BL0 waiting for an address to be written at that memory location).
Solve the problem by providing an s3c_get_chip_id() function, common to all s3c/s5p implementations, and test the result on the secondary boot path.
Revision table, as provided by Kyungmin Park <[email protected]>:
0x4320 0200 EVT0
0x4321 0210 EVT1
0x4321 0211 EVT2
The last 8 bits can be overrided by efuses, so only bits [16:19] are used to identify the revision.
Tested on a vintage SMDK-v310.
Cc Kukjin Kim <[email protected]>
Cc Kyungmin Park <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
?arch/arm/mach-exynos4/include/mach/map.h | ? ?1 +
?arch/arm/mach-exynos4/platsmp.c ? ? ? ? ?| ? 22 +++++++++++++++++++++-
?arch/arm/plat-samsung/include/plat/cpu.h | ? ?2 ++
?arch/arm/plat-samsung/init.c ? ? ? ? ? ? | ? ?8 ++++++++
?4 files changed, 32 insertions(+), 1 deletions(-)
arch/arm/mach-exynos4/include/mach/map.h +0 -0
index 57d8074..da08f5c 100644
@@ -24,6 +24,7 @@
?#include <plat/map-s5p.h>
?#define EXYNOS4_PA_SYSRAM ? ? ? ? ? ? ?0x02020000 +#define EXYNOS4_PA_SYSRAM_EVT0 ? ? ? ? 0x02025000
?#define EXYNOS4_PA_FIMC0 ? ? ? ? ? ? ? 0x11800000 ?#define EXYNOS4_PA_FIMC1 ? ? ? ? ? ? ? 0x11810000
arch/arm/mach-exynos4/platsmp.c +0 -0
index c5e65a0..086d1e3 100644
@@ -26,6 +26,8 @@
?#include <asm/smp_scu.h>
?#include <asm/unified.h>
arch/arm/mach-exynos4/platsmp.c +2 -0
+#include <plat/cpu.h>
+
?#include <mach/hardware.h>
?#include <mach/regs-clock.h>
arch/arm/mach-exynos4/platsmp.c +0 -0
@@ -170,6 +172,24 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
? ? ? ? * system-wide flags register. The boot monitor waits
? ? ? ? * until it receives a soft interrupt, and then the
? ? ? ? * secondary CPU branches to this address.
+ ? ? ? ?*
+ ? ? ? ?* EVT0 has the system-wide flags register at a different
+ ? ? ? ?* address, hence the following hackery...
? ? ? ? */
- ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
+ ? ? ? if (s3c_get_chip_id() & 0xF0000UL)
+ ? ? ? ? ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?S5P_VA_SYSRAM);
+ ? ? ? else {
+ ? ? ? ? ? ? ? void __iomem *sysram_evt0;
arch/arm/mach-exynos4/platsmp.c +11 -0
+
+ ? ? ? ? ? ? ? sysram_evt0 = ioremap(EXYNOS4_PA_SYSRAM_EVT0, SZ_4K);
+ ? ? ? ? ? ? ? if (!sysram_evt0) {
+ ? ? ? ? ? ? ? ? ? ? ? pr_err("Unable to remap EXYNOS4_PA_SYSRAM_EVT0\n");
+ ? ? ? ? ? ? ? ? ? ? ? return;
+ ? ? ? ? ? ? ? }
+ ? ? ? ? ? ? ? __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ ? ? ? ? ? ? ? ? ? ? ? ? ? ?sysram_evt0);
+ ? ? ? ? ? ? ? iounmap(sysram_evt0);
+ ? ? ? }
+
?}
arch/arm/plat-samsung/include/plat/cpu.h +2 -0
index c0a5741..41573cc 100644
@@ -44,6 +44,8 @@ struct cpu_table {
 ?extern void s3c_init_cpu(unsigned long idcode,
 ? ? ? ? ? ? ? ? ? ? ? ? struct cpu_table *cpus, unsigned int cputab_size);
 
+extern unsigned long s3c_get_chip_id(void);
+
?/* core initialisation functions */
?extern void s3c24xx_init_irq(void);
arch/arm/plat-samsung/init.c +0 -0
index 79d10fc..320b88f 100644
@@ -30,6 +30,7 @@
?#include <plat/regs-serial.h>
?static struct cpu_table *cpu;
+static unsigned long s3c_chip_id;
?static struct cpu_table * __init s3c_lookup_cpu(unsigned long idcode, ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?struct cpu_table *tab,
arch/arm/plat-samsung/init.c +7 -1
@@ -60,6 +61,8 @@ void __init s3c_init_cpu(unsigned long idcode,
 ? ? ? ? ? ? ? ?panic("Unsupported Samsung CPU");
 ? ? ? ?}
 
+ ? ? ? s3c_chip_id = idcode;
+
 ? ? ? ?cpu->map_io();
 ?}
 
@@ -140,6 +143,11 @@ void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
 ? ? ? ? ? ? ? ?(cpu->init_uarts)(cfg, no);
 ?}
 
+unsigned long s3c_get_chip_id(void)
+{
+ ? ? ? return s3c_chip_id;
+}
+
 ?static int __init s3c_arch_init(void)
 ?{
 ? ? ? ?int ret;
--
1.7.0.4