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powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value

PATCH New York Sun 4 participants 19 messages May 26, 2011 – Jun 3, 2011

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York Sun

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#0 lore raw

PATCH 1/7 powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value

From: york <[email protected]>

EEPROM requires tWR for write cycle time. Since there is no other way to poll if the internal programming ends, wait for 5ms which is the max timing for AT24C01/02/04/08/16 by default. It can be overridden by defining CONFIG_I2C_TWR in configuration file if the slowest device has different write cycle time.

Signed-off-by York Sun <[email protected]>
---
 README                |    7 +++++++
 drivers/i2c/fsl_i2c.c |    9 +++++++++
 2 files changed, 16 insertions(+), 0 deletions(-)
README +7 -0
index 8bb9c8d..83a316c 100644
@@ -1717,6 +1717,13 @@ The following options need to be configured:
 		devices can use either method, but some require one or
 		the other.
 
+		CONFIG_I2C_TWR
+
+		defining this will override the default write cycle time
+		5ms which is the default for AT24C01/02/4/08/16. If the
+		slowest I2C device has different write cycle time, this
+		option should be defined. The unit is microsecond.
+
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
drivers/i2c/fsl_i2c.c +9 -0
index cb13dee..d192b2a 100644
@@ -42,6 +42,14 @@
 #define CONFIG_I2C_TIMEOUT	10000
 #endif
 
+/*
+ * tWR is the write cycle time for EEPROM device
+ * in microseconds
+ */
+#ifndef CONFIG_I2C_TWR
+#define CONFIG_I2C_TWR 5000
+#endif
+
 #define I2C_READ_BIT  1
 #define I2C_WRITE_BIT 0
 

@@ -416,6 +424,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 	if (i2c_wait4bus()) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
+	udelay(CONFIG_I2C_TWR);
 	if (i == length)
 	    return 0;
Signature · 1 line
1.7.0.4
author
#1 lore raw

PATCH 2/7 powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width

From: york <[email protected]>

If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc8xxx/ddr/options.c |   24 ++++++++++++++++++++----
 1 files changed, 20 insertions(+), 4 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/options.c +20 -4
index 6ccc3b0..80c7046 100644
@@ -418,8 +418,19 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	/* Choose dynamic power management mode. */
 	popts->dynamic_power = 0;
 
-	/* 0 = 64-bit, 1 = 32-bit, 2 = 16-bit */
-	popts->data_bus_width = 0;
+	/*
+	 * check first dimm for primary sdram width
+	 * presuming all dimms are similar
+	 * 0 = 64-bit, 1 = 32-bit, 2 = 16-bit
+	 */
+	if (pdimm[0].primary_sdram_width == 64)
+		popts->data_bus_width = 0;
+	else if (pdimm[0].primary_sdram_width == 32)
+		popts->data_bus_width = 1;
+	else if (pdimm[0].primary_sdram_width == 16)
+		popts->data_bus_width = 2;
+	else
+		panic("Error: invalid primary sdram width!\n");
 
 	/* Choose burst length. */
 #if defined(CONFIG_FSL_DDR3)

@@ -427,8 +438,13 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
 #else
-	popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
-	popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+	if (popts->data_bus_width == 1) {	/* 32-bit bus */
+		popts->OTF_burst_chop_en = 0;
+		popts->burst_length = DDR_BL8;
+	} else {
+		popts->OTF_burst_chop_en = 1;	/* on-the-fly burst chop */
+		popts->burst_length = DDR_OTF;	/* on-the-fly BC4 and BL8 */
+	}
 #endif
 #else
 	popts->burst_length = DDR_BL4;	/* has to be 4 for DDR2 */
Signature · 1 line
1.7.0.4
Applied
#2 lore raw

PATCH 2/7 powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width

Quoted 9 lines · York Sun

From: york <[email protected]>

If the bus width is 32-bit, burst chop should be disabled and burst length should be 8. Read from SPD or other source to determine the width.

Signed-off-by York Sun <[email protected]>

---
arch/powerpc/cpu/mpc8xxx/ddr/options.c | 24 ++++++++++++++++++++----

1 files changed, 20 insertions(+), 4 deletions(-)

applied to 85xx next

- k

author
#3 lore raw

PATCH 3/7 powerpc/mpc8xxx: Enable calculation for fixed DDR chips

In reply to York Sun

From: york <[email protected]>

We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
 arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    5 +++++
 arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
 4 files changed, 31 insertions(+), 3 deletions(-)
arch/powerpc/cpu/mpc85xx/cpu.c +3 -1
index f863f4a..8c2272a 100644
@@ -336,7 +336,9 @@ phys_size_t initdram(int board_type)
 	}
 #endif
 
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if	defined(CONFIG_SPD_EEPROM)	|| \
+	defined(CONFIG_DDR_SPD)		|| \
+	defined(CONFIG_DDR_RAW_TIMING)
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
arch/powerpc/cpu/mpc8xxx/ddr/Makefile +11 -2
index 4a5a785..d1b4c4b 100644
@@ -12,15 +12,24 @@ LIB	= $(obj)libddr.o
 
 COBJS-$(CONFIG_FSL_DDR1)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 
 COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
+endif
+
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +5 -0
index 1e866fe..eb2180e 100644
@@ -14,6 +14,7 @@
 
 #include "common_timing_params.h"
 
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
  * Bind the main DDR setup driver's generic names
  * to this specific DDR technology.

@@ -25,6 +26,7 @@ compute_dimm_parameters(const generic_spd_eeprom_t *spd,
 {
 	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
 }
+#endif
 
 /*
  * Data Structures

@@ -80,4 +82,7 @@ extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int dimm_number);
 #endif
arch/powerpc/cpu/mpc8xxx/ddr/main.c +12 -0
index c8fa123..2b43e73 100644
@@ -313,6 +313,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 
 	switch (start_step) {
 	case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 		/* STEP 1:  Gather all DIMM SPD data */
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);

@@ -344,6 +345,17 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			}
 		}
 
+#else
+	case STEP_COMPUTE_DIMM_PARMS:
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				dimm_params_t *pdimm =
+					&(pinfo->dimm_params[i][j]);
+				fsl_ddr_get_dimm_params(pdimm, i);
+			}
+		}
+		debug("Filling dimm parameters from board specific file\n");
+#endif
 	case STEP_COMPUTE_COMMON_PARMS:
 		/*
 		 * STEP 3: Compute a common set of timing parameters
Signature · 1 line
1.7.0.4
Applied
#4 lore raw

PATCH 3/7 powerpc/mpc8xxx: Enable calculation for fixed DDR chips

Quoted 5 lines · York Sun

From: york <[email protected]>

We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.

Quoted 7 lines
Signed-off-by York Sun <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    5 +++++
arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
4 files changed, 31 insertions(+), 3 deletions(-)

applied to 85xx next

- k

#5 lore raw

PATCH 3/7 powerpc/mpc8xxx: Enable calculation for fixed DDR chips

Quoted 16 lines · Kumar Gala
Quoted 5 lines · York Sun

From: york <[email protected]>

We used to have fixed parameters for soldered DDR chips. This patch enables calculation based on raw timing data, implemneted in board-specific file.

Quoted 7 lines
Signed-off-by York Sun <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cpu.c        |    4 +++-
arch/powerpc/cpu/mpc8xxx/ddr/Makefile |   13 +++++++++++--
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h    |    5 +++++
arch/powerpc/cpu/mpc8xxx/ddr/main.c   |   12 ++++++++++++
4 files changed, 31 insertions(+), 3 deletions(-)
Quoted 1 line

applied to 85xx next

After further review, I'm dropping this one for now. We need to add some docs about 'RAW TIMING'

- k

author
#6 lore raw

PATCH 4/7 powerpc/mpc8xxx: check SPD length before using part number

In reply to York Sun

From: york <[email protected]>

Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c +2 -1
index 756b15f..838cebe 100644
@@ -114,7 +114,8 @@ ddr_compute_dimm_parameters(const ddr3_spd_eeprom_t *spd,
 	 * and copying the part name in ASCII from the SPD onto it
 	 */
 	memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
-	memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
+	if ((spd->info_size_crc & 0xF) > 1)
+		memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
 
 	/* DIMM organization parameters */
 	pdimm->n_ranks = ((spd->organization >> 3) & 0x7) + 1;
Signature · 1 line
1.7.0.4
Applied
#7 lore raw

PATCH 4/7 powerpc/mpc8xxx: check SPD length before using part number

Quoted 9 lines · York Sun

From: york <[email protected]>

Only use DDR DIMM part number if SPD has valid length, to prevent from display garbage in case SPD doesn't cover these fields.

Signed-off-by York Sun <[email protected]>

---
arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c | 3 ++-

1 files changed, 2 insertions(+), 1 deletions(-)

applied to 85xx next

- k

author
#8 lore raw

PATCH 5/7 powerpc/mpc8xxx: Add 16-bit support for DDR3

In reply to York Sun

Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c      |   14 +++++++++++++-
 arch/powerpc/cpu/mpc8xxx/ddr/options.c   |    3 ++-
 arch/powerpc/include/asm/fsl_ddr_sdram.h |    3 +++
 3 files changed, 18 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/main.c +13 -1
index 2b43e73..db7cf11 100644
@@ -174,7 +174,19 @@ int step_assign_addresses(fsl_ddr_info_t *pinfo,
 		switch (pinfo->memctl_opts[i].data_bus_width) {
 		case 2:
 			/* 16-bit */
-			printf("can't handle 16-bit mode yet\n");
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				unsigned int dw;
+				if (!pinfo->dimm_params[i][j].n_ranks)
+					continue;
+				dw = pinfo->dimm_params[i][j].primary_sdram_width;
+				if ((dw == 72 || dw == 64)) {
+					dbw_cap_adj[i] = 2;
+					break;
+				} else if ((dw == 40 || dw == 32)) {
+					dbw_cap_adj[i] = 1;
+					break;
+				}
+			}
 			break;
 
 		case 1:
arch/powerpc/cpu/mpc8xxx/ddr/options.c +2 -1
index 80c7046..02efe58 100644
@@ -438,7 +438,8 @@ unsigned int populate_memctl_options(int all_DIMMs_registered,
 	popts->OTF_burst_chop_en = 0;	/* on-the-fly burst chop disable */
 	popts->burst_length = DDR_BL8;	/* Fixed 8-beat burst len */
 #else
-	if (popts->data_bus_width == 1) {	/* 32-bit bus */
+	if ((popts->data_bus_width == 1) || (popts->data_bus_width == 2)) {
+		/* 32-bit or 16-bit bus */
 		popts->OTF_burst_chop_en = 0;
 		popts->burst_length = DDR_BL8;
 	} else {
arch/powerpc/include/asm/fsl_ddr_sdram.h +3 -0
index 127a840..1778cc5 100644
@@ -181,6 +181,9 @@ typedef struct memctl_options_partial_s {
 	unsigned int all_DIMMs_minimum_tRCD_ps;
 } memctl_options_partial_t;
 
+#define DDR_DATA_BUS_WIDTH_64 0
+#define DDR_DATA_BUS_WIDTH_32 1
+#define DDR_DATA_BUS_WIDTH_16 2
 /*
  * Generalized parameters for memory controller configuration,
  * might be a little specific to the FSL memory controller
Signature · 1 line
1.7.0.4
Applied
#9 lore raw

PATCH 5/7 powerpc/mpc8xxx: Add 16-bit support for DDR3

Quoted 9 lines · York Sun

Add support for 16-bit DDR bus. Also deal with system using 64- and 32-bit DDR devices.

Signed-off-by York Sun <[email protected]>

---

arch/powerpc/cpu/mpc8xxx/ddr/main.c      |   14 +++++++++++++-
arch/powerpc/cpu/mpc8xxx/ddr/options.c   |    3 ++-
arch/powerpc/include/asm/fsl_ddr_sdram.h |    3 +++
3 files changed, 18 insertions(+), 2 deletions(-)

applied to 85xx next

- k

author
#10 lore raw

PATCH 6/7 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

In reply to York Sun

In case of empty SPD or checksum error, fallback to raw timing on supported boards.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/main.c +8 -0
index db7cf11..2e43da6 100644
@@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->dimm_params[i][j]);
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_DDR_RAW_TIMING
+				if (retval != 0) {
+					printf("SPD error! Trying fallback to "
+					"raw timing calculation\n");
+					fsl_ddr_get_dimm_params(pdimm, i, j);
+				}
+#else
 				if (retval == 2) {
 					printf("Error: compute_dimm_parameters"
 					" non-zero returned FATAL value "
 					"for memctl=%u dimm=%u\n", i, j);
 					return 0;
 				}
+#endif
 				if (retval) {
 					debug("Warning: compute_dimm_parameters"
 					" non-zero return value for memctl=%u "
Signature · 1 line
1.7.0.4
#11 lore raw

PATCH 6/7 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

Quoted 13 lines · York Sun

In case of empty SPD or checksum error, fallback to raw timing on supported boards.

Signed-off-by York Sun <[email protected]>

---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++

1 files changed, 8 insertions(+), 0 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/main.c +0 -0
index db7cf11..2e43da6 100644

arch/powerpc/cpu/mpc8xxx/ddr/main.c fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, · line 346

Quoted 4 lines
arch/powerpc/cpu/mpc8xxx/ddr/main.c +1 -0
@@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->dimm_params[i][j]);
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_DDR_RAW_TIMING

Should this be CONFIG_SYS_DDR_RAW_TIMING??

We need this added to README at a minimum for what DDR_RAW_TIMING means.

Quoted 24 lines
arch/powerpc/cpu/mpc8xxx/ddr/main.c +7 -0
+				if (retval != 0) {
+					printf("SPD error! Trying fallback to "
+					"raw timing calculation\n");
+					fsl_ddr_get_dimm_params(pdimm, i, j);
+				}
+#else
 				if (retval == 2) {
 					printf("Error: compute_dimm_parameters"
 					" non-zero returned FATAL value "
 					"for memctl=%u dimm=%u\n", i, j);
 					return 0;
 				}
+#endif
 				if (retval) {
 					debug("Warning: compute_dimm_parameters"
 					" non-zero return value for memctl=%u "
Signature · 7 lines
1.7.0.4


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author
#12 lore raw

PATCH 6/7 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

Quoted 17 lines · Kumar Gala
Quoted 15 lines · York Sun

In case of empty SPD or checksum error, fallback to raw timing on supported boards.

Signed-off-by York Sun <[email protected]>

---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++

1 files changed, 8 insertions(+), 0 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/main.c +0 -0
index db7cf11..2e43da6 100644
@@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->dimm_params[i][j]);
Quoted 7 lines

arch/powerpc/cpu/mpc8xxx/ddr/main.c fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, · line 346

Quoted 2 lines
arch/powerpc/cpu/mpc8xxx/ddr/main.c +1 -0
 				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_DDR_RAW_TIMING

Should this be CONFIG_SYS_DDR_RAW_TIMING??

We need this added to README at a minimum for what DDR_RAW_TIMING means.

Will do.

York

#13 lore raw

PATCH 6/7 powerpc/mpc8xxx: Adding fallback to raw timing on supported boards

Quoted 23 lines · York Sun
Quoted 22 lines · Kumar Gala
Quoted 13 lines · York Sun

In case of empty SPD or checksum error, fallback to raw timing on supported boards.

Signed-off-by York Sun <[email protected]>

---
arch/powerpc/cpu/mpc8xxx/ddr/main.c | 8 ++++++++

1 files changed, 8 insertions(+), 0 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/main.c +0 -0
index db7cf11..2e43da6 100644

arch/powerpc/cpu/mpc8xxx/ddr/main.c fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, · line 346

Quoted 4 lines
arch/powerpc/cpu/mpc8xxx/ddr/main.c +1 -0
@@ -343,12 +343,20 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 					&(pinfo->dimm_params[i][j]);
 
 				retval = compute_dimm_parameters(spd, pdimm, i);
+#ifdef CONFIG_DDR_RAW_TIMING

Should this be CONFIG_SYS_DDR_RAW_TIMING??

Quoted 6 lines
Quoted 2 lines

We need this added to README at a minimum for what DDR_RAW_TIMING means.

Will do.

York

thanks. Might be good to do it in patch 3/7.

Just repost 3/7, 6/7, 7/7 against 'next' branch of git://git.denx.de/u-boot-mpc85xx.git

- k

author
#14 lore raw

PATCH 7/7 powerpc/mpc8xxx: change raw timing function call parameters

In reply to York Sun

Adding controller number so board implementation can distinguish.

Signed-off-by York Sun <[email protected]>
---
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h  |    4 +++-
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |    2 +-
 2 files changed, 4 insertions(+), 2 deletions(-)
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +3 -1
index eb2180e..f59aa33 100644
@@ -84,5 +84,7 @@ extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
 
 /* board specific function */
-int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int dimm_number);
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
 #endif
arch/powerpc/cpu/mpc8xxx/ddr/main.c +1 -1
index 2e43da6..b559787 100644
@@ -371,7 +371,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 				dimm_params_t *pdimm =
 					&(pinfo->dimm_params[i][j]);
-				fsl_ddr_get_dimm_params(pdimm, i);
+				fsl_ddr_get_dimm_params(pdimm, i, j);
 			}
 		}
 		debug("Filling dimm parameters from board specific file\n");
Signature · 1 line
1.7.0.4
author
#16 lore raw

PATCH 1/7 powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value

Quoted 6 lines · On Thu, 2011-05-26 at 17:20 -0700, Tabi Timur-B04825 wrote:
Quoted 1 line · York Sun

From: york <[email protected]>

You should fix this so that it includes your full name.

Sure. I can fix it along with other feedback.

York

#17 lore raw

PATCH 1/7 powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value

In reply to York Sun

Hello York,

Quoted 19 lines · York Sun

From: york <[email protected]>

EEPROM requires tWR for write cycle time. Since there is no other way to poll if the internal programming ends, wait for 5ms which is the max timing for AT24C01/02/04/08/16 by default. It can be overridden by defining CONFIG_I2C_TWR in configuration file if the slowest device has different write cycle time.

Signed-off-by York Sun <[email protected]>
---
 README                |    7 +++++++
 drivers/i2c/fsl_i2c.c |    9 +++++++++
 2 files changed, 16 insertions(+), 0 deletions(-)
README +0 -0
index 8bb9c8d..83a316c 100644

README The following options need to be configured: · line 1720

Quoted 4 lines
README +1 -0
@@ -1717,6 +1717,13 @@ The following options need to be configured:
 		devices can use either method, but some require one or
 		the other.
 
+		CONFIG_I2C_TWR

Maybe CONFIG_SYS_I2C_EEPROM_TWR is better?

README The following options need to be configured: · line 1722

Quoted 2 lines
README +2 -0
+
+		defining this will override the default write cycle time

the default eeprom write cycle time ...

Quoted 27 lines
README +4 -0
+		5ms which is the default for AT24C01/02/4/08/16. If the
+		slowest I2C device has different write cycle time, this
+		option should be defined. The unit is microsecond.
+
 - SPI Support:	CONFIG_SPI
 
 		Enables SPI driver (so far only tested with
drivers/i2c/fsl_i2c.c +8 -0
index cb13dee..d192b2a 100644
@@ -42,6 +42,14 @@
 #define CONFIG_I2C_TIMEOUT	10000
 #endif
 
+/*
+ * tWR is the write cycle time for EEPROM device
+ * in microseconds
+ */
+#ifndef CONFIG_I2C_TWR
+#define CONFIG_I2C_TWR 5000
+#endif
+
 #define I2C_READ_BIT  1
 #define I2C_WRITE_BIT 0

drivers/i2c/fsl_i2c.c i2c_write(u8 dev, uint addr, int alen, u8 *data, int length) · line 430

Quoted 7 lines
drivers/i2c/fsl_i2c.c +1 -0
@@ -416,6 +424,7 @@ i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
 	if (i2c_wait4bus()) /* Wait until STOP */
 		debug("i2c_write: wait4bus timed out\n");
 
+	udelay(CONFIG_I2C_TWR);
 	if (i == length)
 	    return 0;

Hmm.. you add this timeout in the i2c driver, which will result in adding this default 5 ms delay for *all* i2c writes, not only for eeprom devices ... why you didn;t add this timeout in cmd_eeprom, where it seems to me is the better place for it? Looking in this common/cmd_eeprom.c there is a CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS define ... is this not adequate?

bye,
Heiko

Signature · 2 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
author
#18 lore raw

PATCH 1/7 powerpc/i2c: introduce CONFIG_I2C_TWR for setting tWR value

Quoted 7 lines · Heiko Schocher

Hmm.. you add this timeout in the i2c driver, which will result in adding this default 5 ms delay for *all* i2c writes, not only for eeprom devices ... why you didn;t add this timeout in cmd_eeprom, where it seems to me is the better place for it? Looking in this common/cmd_eeprom.c there is a CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS define ... is this not adequate?

You are right. I overlooked CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS and should use this instead.

Drop this patch, please.

York