Consolidating GIC per-cpu interrupts
Subsystems (8)
v5 cover Consolidating GIC per-cpu interrupts
The current GIC per-cpu interrupts (aka PPIs) suffer from a number of problems:
- They use a completely separate scheme to handle the interrupts, mostly because the PPI concept doesn't really match the kernel view of an interrupt.
- Some low-level code gets duplicated, as usual...
- PPIs can only be used by the timer code, unless we add more low-level assembly code.
- At least one platform (msm) has started implementing its own alternative scheme.
The proposed solution is to let the GIC code expose the PPIs as something that the kernel can manage. Instead of having a single interrupt number shared on all cores, make the interrupt number be different on each CPU.
This enables the use of the normal kernel API (request_irq() and friends) and the elimination of some low level code. On the other side, it causes quite a bit of churn in the timer code.
This patch set is based on 3.0-rc1. Tested on PB-11MP, Pandaboard and SMDK-V310.
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From [email protected] Wed May 25 18:46:03 2011
From: [email protected] ()
Date: Wed, 25 May 2011 22:46:03 -0000
Subject: No subject
Message-ID: <[email protected]>
- Fix arch/arm/common/Kconfig indentation
- Fix MSM warning when building UP.
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From [email protected] Wed May 25 18:46:03 2011
From: [email protected] ()
Date: Wed, 25 May 2011 22:46:03 -0000
Subject: No subject
Message-ID: <[email protected]>
- Fix yet another CPU_HOTPLUG problem: instead of calling free_irq() on timer halt, just disable the interrupt. On timer restart, detect that the interrupt has been requested already and just enable the interrupt back. This avoid doing a request_irq() with preemption disabled, which triggers an ugly warning. Reported by Stephen Boyd.
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From [email protected] Wed May 25 18:46:03 2011
From: [email protected] ()
Date: Wed, 25 May 2011 22:46:03 -0000
Subject: No subject
Message-ID: <[email protected]>
- More MSM fixes
- Dropped MSM interrupt handler removal, as this requires more discussion, and will be addressed in a separate series.
- Moved introduction of percpu_timer_handler to a separate patch
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From [email protected] Wed May 25 18:46:03 2011
From: [email protected] ()
Date: Wed, 25 May 2011 22:46:03 -0000
Subject: No subject
Message-ID: <[email protected]>
- Fix crash while hotpluging a CPU
- Use handle_percpu_irq() instead of handle_fasteoi_irq()
- MSM fixes courtesy of Stephen Boyd
- MSM switched to percpu_timer_handler()
- Remove local timer interrupt accounting
- Restructure patches #1 and #2
Marc Zyngier (13):
ARM: gic: add per-cpu interrupt multiplexer
ARM: smp: add interrupt handler for local timers
ARM: smp_twd: add support for remapped PPI interrupts
ARM: omap4: use remapped PPI interrupts for local timer
ARM: versatile: use remapped PPI interrupts for local timer
ARM: shmobile: use remapped PPI interrupts for local timer
ARM: ux500: use remapped PPI interrupts for local timer
ARM: tegra: use remapped PPI interrupts for local timer
ARM: msm: use remapped PPI interrupts for local timer
ARM: exynos4: use remapped PPI interrupts for local timer
ARM: gic: remove previous local timer interrupt handling
ARM: gic: add compute_irqnr macro for exynos4
ARM: SMP: automatically select ARM_GIC_VPPI
arch/arm/Kconfig | 1 + arch/arm/common/Kconfig | 5 + arch/arm/common/gic.c | 143 +++++++++++++++++++-- arch/arm/include/asm/entry-macro-multi.S | 7 - arch/arm/include/asm/hardirq.h | 3 - arch/arm/include/asm/hardware/entry-macro-gic.S | 31 ++--- arch/arm/include/asm/hardware/gic.h | 12 ++- arch/arm/include/asm/localtimer.h | 7 +- arch/arm/include/asm/smp.h | 5 - arch/arm/kernel/irq.c | 11 +- arch/arm/kernel/smp.c | 27 +--- arch/arm/kernel/smp_twd.c | 25 +++- arch/arm/mach-exynos4/include/mach/entry-macro.S | 70 +---------- arch/arm/mach-exynos4/localtimer.c | 3 +- arch/arm/mach-msm/board-msm8x60.c | 11 -- arch/arm/mach-msm/include/mach/entry-macro-qgic.S | 73 +----------- arch/arm/mach-msm/timer.c | 59 +++++---- arch/arm/mach-omap2/include/mach/entry-macro.S | 14 +-- arch/arm/mach-omap2/timer-mpu.c | 3 +- arch/arm/mach-shmobile/entry-intc.S | 3 - arch/arm/mach-shmobile/include/mach/entry-macro.S | 3 - arch/arm/mach-shmobile/localtimer.c | 3 +- arch/arm/mach-tegra/localtimer.c | 3 +- arch/arm/mach-ux500/localtimer.c | 3 +- arch/arm/plat-versatile/localtimer.c | 3 +- 25 files changed, 246 insertions(+), 282 deletions(-)
Signature · 1 line
1.7.5.2
RFC PATCH v5 1/13 ARM: gic: add per-cpu interrupt multiplexer
The kernel doesn't handle very well the concept of per-cpu interrupt as implemented by the ARM architecture (the same interrupt level is exposed on each core).
To work around the problem, add another irq_chip to handle PPIs and remap them so that a single interrupt number is only used on a given CPU (for example, IRQ 29 and 30 get exposed as IRQ 128 and 129 on core 0, 130 and 131 on core 1...).
A helper function gic_ppi_to_vppi() is used to convert the PPI number to the per-processor IRQ.
--- arch/arm/common/Kconfig | 5 + arch/arm/common/gic.c | 133 ++++++++++++++++++++++- arch/arm/include/asm/entry-macro-multi.S | 2 +- arch/arm/include/asm/hardware/entry-macro-gic.S | 19 ++-- arch/arm/include/asm/hardware/gic.h | 11 ++ arch/arm/kernel/irq.c | 8 ++- 6 files changed, 165 insertions(+), 13 deletions(-)
arch/arm/common/Kconfig +5 -0
@@ -1,6 +1,11 @@ config ARM_GIC bool +config ARM_GIC_VPPI + depends on ARM_GIC + select SPARSE_IRQ + bool + config ARM_VIC bool
arch/arm/common/gic.c +129 -4
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arch/arm/include/asm/entry-macro-multi.S +1 -1
@@ -24,7 +24,7 @@ adrne lr, BSYM(1b) bne do_IPI -#ifdef CONFIG_LOCAL_TIMERS +#if defined(CONFIG_LOCAL_TIMERS) && !defined(CONFIG_ARM_GIC_VPPI) test_for_ltirq r0, r6, r5, lr movne r0, sp adrne lr, BSYM(1b)
arch/arm/include/asm/hardware/entry-macro-gic.S +12 -7
@@ -17,23 +17,26 @@ .endm #endif +#ifdef CONFIG_ARM_GIC_VPPI +#define DO_IRQ_BASE 16 +#else +#define DO_IRQ_BASE 30 +#endif + /* * The interrupt numbering scheme is defined in the * interrupt controller spec. To wit: * * Interrupts 0-15 are IPI - * 16-28 are reserved - * 29-31 are local. We allow 30 to be used for the watchdog. + * 16-31 are local. We allow 30 to be used for the watchdog. * 32-1020 are global * 1021-1022 are reserved * 1023 is "spurious" (no interrupt) * - * For now, we ignore all local interrupts so only return an interrupt if it's - * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs. - * * A simple read from the controller will tell us the number of the highest * priority enabled interrupt. We then just need to check whether it is in the - * valid range for an IRQ (30-1020 inclusive). + * valid range for an IRQ (30-1020 inclusive). If CONFIG_ARM_GIC_VPPI is + * enabled, local interrupts are handled the same way as global ones. */ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
@@ -43,7 +46,7 @@ ldr \tmp, =1021 bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #29 + cmp \irqnr, #(DO_IRQ_BASE - 1) cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr
@@ -63,6 +66,7 @@ cmpcs \irqnr, \irqnr .endm +#ifndef CONFIG_ARM_GIC_VPPI /* As above, this assumes that irqstat and base are preserved.. */ .macro test_for_ltirq, irqnr, irqstat, base, tmp
@@ -73,3 +77,4 @@ streq \irqstat, [\base, #GIC_CPU_EOI] cmp \tmp, #0 .endm +#endif
arch/arm/include/asm/hardware/gic.h +11 -0
@@ -33,6 +33,8 @@#define GIC_DIST_SOFTINT 0xf00#ifndef __ASSEMBLY__ +#include <linux/cpumask.h> +extern void __iomem *gic_cpu_base_addr;extern struct irq_chip gic_arch_extn;
@@ -41,6 +43,15 @@ void gic_secondary_init(unsigned int);void gic_cascade_irq (unsigned int gic_nr,unsigned int irq);void gic_raise_softirq (const struct cpumask *mask,unsigned int irq);void gic_enable_ppi (unsigned int ); +#ifdef CONFIG_ARM_GIC_VPPI +unsigned int gic_ppi_to_vppi (unsigned int irq); +#else +static inline unsigned int gic_ppi_to_vppi (unsigned int irq) +{ +return irq; +} +#endif +#endif #endif
arch/arm/kernel/irq.c +7 -1
@@ -124,8 +124,14 @@ void __init init_IRQ(void)#ifdef CONFIG_SPARSE_IRQ int __init arch_probe_nr_irqs (void ) { +int initcnt; + nr_irqs = machine_desc->nr_irqs ? machine_desc->nr_irqs :NR_IRQS ; -return nr_irqs; + initcnt = nr_irqs; +#ifdef CONFIG_ARM_GIC_VPPI + nr_irqs +=16 *8 ;/* 16 PPIs, 8 CPUs */ +#endif +return initcnt; }#endif
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1.7.5.2
RFC PATCH v5 2/13 ARM: smp: add interrupt handler for local timers
In reply to Marc ZyngierProvide a "normal" interrupt handler for local timers. It is expected that most timer implementations will use this handler unless they have more specific requirements.
--- arch/arm/include/asm/localtimer.h | 6 ++++++ arch/arm/kernel/smp.c | 12 ++++++++++++ 2 files changed, 18 insertions(+), 0 deletions(-)
arch/arm/include/asm/localtimer.h +6 -0
@@ -10,6 +10,8 @@#ifndef __ASM_ARM_LOCALTIMER_H#define __ASM_ARM_LOCALTIMER_H +#include <linux/interrupt.h> +struct clock_event_device ;/*
@@ -22,6 +24,10 @@ void percpu_timer_setup(void);*/ asmlinkage void do_local_timer(struct pt_regs *); +/* +* Per-cpu timer IRQ handler +*/ +irqreturn_t percpu_timer_handler (int irq,void *dev_id);#ifdef CONFIG_LOCAL_TIMERS
arch/arm/kernel/smp.c +12 -0
@@ -460,6 +460,18 @@ asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)set_irq_regs (old_regs); } +irqreturn_t percpu_timer_handler (int irq,void *dev_id) +{ +struct clock_event_device *evt = dev_id; + +if (local_timer_ack ()) { + evt->event_handler (evt); +return IRQ_HANDLED ; + } + +return IRQ_NONE ; +} +void show_local_irqs (struct seq_file *p,int prec) {unsigned int cpu;
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1.7.5.2
RFC PATCH v5 3/13 ARM: smp_twd: add support for remapped PPI interrupts
In reply to Marc ZyngierWhen CONFIG_ARM_GIC_VPPI is enabled, let smp_twd request interrupts the normal way (ie using request_irq()).
This involves letting PPIs go via the same code path as SPIs and having normal interrupt handler for the local timer code.
The previous ad-hoc code is still supported when CONFIG_ARM_GIC_VPPI is not defined.
--- arch/arm/kernel/smp_twd.c | 28 +++++++++++++++++++++++++++- 1 files changed, 27 insertions(+), 1 deletions(-)
arch/arm/kernel/smp_twd.c +27 -1
@@ -15,16 +15,18 @@#include <linux/smp.h> #include <linux/jiffies.h> #include <linux/clockchips.h> -#include <linux/irq.h> +#include <linux/interrupt.h> #include <linux/io.h> #include <asm/smp_twd.h> +#include <asm/localtimer.h> #include <asm/hardware/gic.h> /* set up by the platform code */ void __iomem *twd_base;static unsigned long twd_timer_rate; +static DEFINE_PER_CPU(bool, irq_reqd);static void twd_set_mode (enum clock_event_mode mode,struct clock_event_device *clk)
@@ -43,6 +45,10 @@ static void twd_set_mode(enum clock_event_mode mode, ctrl =TWD_TIMER_CONTROL_IT_ENABLE |TWD_TIMER_CONTROL_ONESHOT ;break ;case CLOCK_EVT_MODE_UNUSED : +#ifdef CONFIG_ARM_GIC_VPPI +disable_irq (clk->irq); +/* fall through */ +#endif case CLOCK_EVT_MODE_SHUTDOWN :default : ctrl =0 ;
@@ -124,6 +130,9 @@ static void __cpuinit twd_calibrate_rate(void)*/ void __cpuinit twd_timer_setup (struct clock_event_device *clk) { +int err; +bool *reqd; +twd_calibrate_rate (); clk->name ="local_timer" ;
@@ -137,8 +146,25 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) clk->max_delta_ns =clockevent_delta2ns (0xffffffff , clk); clk->min_delta_ns =clockevent_delta2ns (0xf , clk); +#ifdef CONFIG_ARM_GIC_VPPI + reqd = &__get_cpu_var (irq_reqd); +if (!*reqd) { + err =request_irq (clk->irq, percpu_timer_handler, +IRQF_PERCPU |IRQF_NOBALANCING |IRQF_TIMER , + clk->name, clk); +if (err) { +pr_err ("%s: can't register interrupt %d on cpu %d (%d)\n" , + clk->name, clk->irq,smp_processor_id (), err); +return ; + } + + *reqd = true; + }else +enable_irq (clk->irq); +#else /* Make sure our local interrupt controller has this enabled */ gic_enable_ppi (clk->irq); +#endif clockevents_register_device (clk); }
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1.7.5.2
RFC PATCH v5 4/13 ARM: omap4: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
Tested on a Pandaboard.
--- arch/arm/mach-omap2/Kconfig | 1 + arch/arm/mach-omap2/include/mach/entry-macro.S | 14 +------------- arch/arm/mach-omap2/timer-mpu.c | 3 ++- 3 files changed, 4 insertions(+), 14 deletions(-)
arch/arm/mach-omap2/Kconfig +1 -0
@@ -44,6 +44,7 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC + select ARM_GIC_VPPI select LOCAL_TIMERS if SMP select PL310_ERRATA_588369 select PL310_ERRATA_727915
arch/arm/mach-omap2/include/mach/entry-macro.S +1 -13
@@ -78,7 +78,7 @@ 4401: ldr \irqstat, [\base, #GIC_CPU_INTACK] ldr \tmp, =1021 bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #29 + cmp \irqnr, #15 cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr
@@ -101,18 +101,6 @@ it cs cmpcs \irqnr, \irqnr .endm - - /* As above, this assumes that irqstat and base are preserved */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #29 - itt eq - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm #endif /* CONFIG_SMP */ #else /* MULTI_OMAP2 */
arch/arm/mach-omap2/timer-mpu.c +2 -1
@@ -22,6 +22,7 @@#include <asm/irq.h> #include <asm/smp_twd.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> /* * Setup the local clock events for a CPU.
@@ -32,7 +33,7 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)if (omap_rev () ==OMAP4430_REV_ES1_0 )return -ENXIO ; - evt->irq =OMAP44XX_IRQ_LOCALTIMER ; + evt->irq =gic_ppi_to_vppi (OMAP44XX_IRQ_LOCALTIMER );twd_timer_setup (evt);return 0 ; }
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1.7.5.2
RFC PATCH v5 5/13 ARM: versatile: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
Tested on VExpress and PB-11MP.
--- arch/arm/mach-realview/Kconfig | 2 ++ arch/arm/mach-vexpress/Kconfig | 1 + arch/arm/plat-versatile/localtimer.c | 3 ++- 3 files changed, 5 insertions(+), 1 deletions(-)
arch/arm/mach-realview/Kconfig +2 -0
@@ -38,6 +38,7 @@ config MACH_REALVIEW_PB11MP bool "Support RealView(R) Platform Baseboard for ARM11MPCore" select CPU_V6K select ARM_GIC + select ARM_GIC_VPPI select HAVE_PATA_PLATFORM select ARCH_HAS_BARRIERS if SMP help
@@ -76,6 +77,7 @@ config MACH_REALVIEW_PBA8 config MACH_REALVIEW_PBX bool "Support RealView(R) Platform Baseboard Explore" select ARM_GIC + select ARM_GIC_VPPI select HAVE_PATA_PLATFORM select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM
arch/arm/mach-vexpress/Kconfig +1 -0
@@ -5,6 +5,7 @@ config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" select CPU_V7 select ARM_GIC + select ARM_GIC_VPPI select ARM_ERRATA_720789 select ARM_ERRATA_751472 select ARM_ERRATA_753970
arch/arm/plat-versatile/localtimer.c +2 -1
@@ -14,6 +14,7 @@#include <asm/smp_twd.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> #include <mach/irqs.h> /*
@@ -21,7 +22,7 @@*/ int __cpuinit local_timer_setup (struct clock_event_device *evt) { - evt->irq =IRQ_LOCALTIMER ; + evt->irq =gic_ppi_to_vppi (IRQ_LOCALTIMER );twd_timer_setup (evt);return 0 ; }
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1.7.5.2
RFC PATCH v5 6/13 ARM: shmobile: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
--- arch/arm/mach-shmobile/Kconfig | 1 + arch/arm/mach-shmobile/entry-intc.S | 3 --- arch/arm/mach-shmobile/include/mach/entry-macro.S | 3 --- arch/arm/mach-shmobile/localtimer.c | 3 ++- 4 files changed, 3 insertions(+), 7 deletions(-)
arch/arm/mach-shmobile/Kconfig +1 -0
@@ -26,6 +26,7 @@ config ARCH_SH73A0 select SH_CLK_CPG select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC + select ARM_GIC_VPPI comment "SH-Mobile Board Type"
arch/arm/mach-shmobile/entry-intc.S +0 -3
@@ -51,7 +51,4 @@ .macro test_for_ipi, irqnr, irqstat, base, tmp .endm - .macro test_for_ltirq, irqnr, irqstat, base, tmp - .endm - arch_irq_handler shmobile_handle_irq_intc
arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -3
@@ -27,8 +27,5 @@ .macro test_for_ipi, irqnr, irqstat, base, tmp .endm - .macro test_for_ltirq, irqnr, irqstat, base, tmp - .endm - .macro arch_ret_to_user, tmp1, tmp2 .endm
arch/arm/mach-shmobile/localtimer.c +2 -1
@@ -14,13 +14,14 @@#include <linux/clockchips.h> #include <asm/smp_twd.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> /* * Setup the local clock events for a CPU. */ int __cpuinit local_timer_setup (struct clock_event_device *evt) { - evt->irq =29 ; + evt->irq =gic_ppi_to_vppi (29 );twd_timer_setup (evt);return 0 ; }
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1.7.5.2
RFC PATCH v5 7/13 ARM: ux500: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
--- arch/arm/mach-ux500/Kconfig | 1 + arch/arm/mach-ux500/localtimer.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/mach-ux500/Kconfig +1 -0
@@ -4,6 +4,7 @@ config UX500_SOC_COMMON bool default y select ARM_GIC + select ARM_GIC_VPPI select HAS_MTU select ARM_ERRATA_753970
arch/arm/mach-ux500/localtimer.c +2 -1
@@ -17,13 +17,14 @@#include <asm/irq.h> #include <asm/smp_twd.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> /* * Setup the local clock events for a CPU. */ int __cpuinit local_timer_setup (struct clock_event_device *evt) { - evt->irq =IRQ_LOCALTIMER ; + evt->irq =gic_ppi_to_vppi (IRQ_LOCALTIMER );twd_timer_setup (evt);return 0 ; }
Signature · 1 line
1.7.5.2
RFC PATCH v5 8/13 ARM: tegra: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
--- arch/arm/mach-tegra/Kconfig | 1 + arch/arm/mach-tegra/localtimer.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletions(-)
arch/arm/mach-tegra/Kconfig +1 -0
@@ -9,6 +9,7 @@ config ARCH_TEGRA_2x_SOC bool "Tegra 2 family" select CPU_V7 select ARM_GIC + select ARM_GIC_VPPI select ARCH_REQUIRE_GPIOLIB select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_SUPPORT
arch/arm/mach-tegra/localtimer.c +2 -1
@@ -14,13 +14,14 @@#include <asm/irq.h> #include <asm/smp_twd.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> /* * Setup the local clock events for a CPU. */ int __cpuinit local_timer_setup (struct clock_event_device *evt) { - evt->irq =IRQ_LOCALTIMER ; + evt->irq =gic_ppi_to_vppi (IRQ_LOCALTIMER );twd_timer_setup (evt);return 0 ; }
Signature · 1 line
1.7.5.2
RFC PATCH v5 9/13 ARM: msm: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
MSM already had a very similar scheme, though still mixing both GIC-specific and generic APIs.
Fixes and ideas courtesy of Stephen Boyd.
--- arch/arm/mach-msm/Kconfig | 2 + arch/arm/mach-msm/board-msm8x60.c | 11 --- arch/arm/mach-msm/include/mach/entry-macro-qgic.S | 73 +-------------------- arch/arm/mach-msm/timer.c | 59 +++++++++-------- 4 files changed, 33 insertions(+), 112 deletions(-)
arch/arm/mach-msm/Kconfig +2 -0
@@ -42,6 +42,7 @@ config ARCH_MSM8X60 && !MACH_MSM8X60_FFA) select ARCH_MSM_SCORPIONMP select ARM_GIC + select ARM_GIC_VPPI select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX
@@ -52,6 +53,7 @@ config ARCH_MSM8960 select ARCH_MSM_SCORPIONMP select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) select ARM_GIC + select ARM_GIC_VPPI select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX
arch/arm/mach-msm/board-msm8x60.c +0 -11
@@ -36,8 +36,6 @@ static void __init msm8x60_map_io(void)static void __init msm8x60_init_irq (void ) { -unsigned int i; -gic_init (0 ,GIC_PPI_START ,MSM_QGIC_DIST_BASE , (void *)MSM_QGIC_CPU_BASE );
@@ -49,15 +47,6 @@ static void __init msm8x60_init_irq(void)*/ if (!machine_is_msm8x60_sim ())writel (0x0000FFFF ,MSM_QGIC_DIST_BASE +GIC_DIST_ENABLE_SET ); - -/* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet -* as they are configured as level, which does not play nice with -* handle_percpu_irq. -*/ -for (i =GIC_PPI_START ; i <GIC_SPI_START ; i++) { -if (i !=AVS_SVICINT && i !=AVS_SVICINTSWDONE ) -irq_set_handler (i, handle_percpu_irq); - } }static void __init msm8x60_init (void )
arch/arm/mach-msm/include/mach/entry-macro-qgic.S +1 -72
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arch/arm/mach-msm/timer.c +30 -29
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Signature · 1 line
1.7.5.2
RFC PATCH v5 10/13 ARM: exynos4: use remapped PPI interrupts for local timer
In reply to Marc ZyngierUse the normal interrupt scheme for the local timers by using a remapped PPI interrupt.
Tested on a SMDK-S5PV310 board.
--- arch/arm/mach-exynos4/include/mach/entry-macro.S | 12 +----------- arch/arm/mach-exynos4/localtimer.c | 3 ++- arch/arm/plat-s5p/Kconfig | 1 + 3 files changed, 4 insertions(+), 12 deletions(-)
arch/arm/mach-exynos4/include/mach/entry-macro.S +1 -11
@@ -50,7 +50,7 @@ bic \irqnr, \irqstat, #0x1c00 - cmp \irqnr, #29 + cmp \irqnr, #15 cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr
@@ -72,13 +72,3 @@ cmpcs \irqnr, \irqnr .endm - /* As above, this assumes that irqstat and base are preserved.. */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #29 - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm
arch/arm/mach-exynos4/localtimer.c +2 -1
@@ -14,13 +14,14 @@#include <asm/irq.h> #include <asm/localtimer.h> +#include <asm/hardware/gic.h> /* * Setup the local clock events for a CPU. */ int __cpuinit local_timer_setup (struct clock_event_device *evt) { - evt->irq =IRQ_LOCALTIMER ; + evt->irq =gic_ppi_to_vppi (IRQ_LOCALTIMER );twd_timer_setup (evt);return 0 ; }
arch/arm/plat-s5p/Kconfig +1 -0
@@ -11,6 +11,7 @@ config PLAT_S5P default y select ARM_VIC if !ARCH_EXYNOS4 select ARM_GIC if ARCH_EXYNOS4 + select ARM_GIC_VPPI if ARCH_EXYNOS4 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK
Signature · 1 line
1.7.5.2
RFC PATCH v5 11/13 ARM: gic: remove previous local timer interrupt handling
In reply to Marc ZyngierNow that all users of local timers are using CONFIG_ARM_GIC_VPPI, the now unused local timer infrastructure can be safely removed.
--- arch/arm/common/gic.c | 10 -------- arch/arm/include/asm/entry-macro-multi.S | 7 ----- arch/arm/include/asm/hardirq.h | 3 -- arch/arm/include/asm/hardware/entry-macro-gic.S | 13 ---------- arch/arm/include/asm/hardware/gic.h | 1 - arch/arm/include/asm/localtimer.h | 5 ---- arch/arm/include/asm/smp.h | 5 ---- arch/arm/kernel/irq.c | 3 -- arch/arm/kernel/smp.c | 29 ----------------------- arch/arm/kernel/smp_twd.c | 7 ----- 10 files changed, 0 insertions(+), 83 deletions(-)
arch/arm/common/gic.c +0 -10
@@ -501,16 +501,6 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)gic_cpu_init (&gic_data[gic_nr]); } -void __cpuinit gic_enable_ppi (unsigned int irq) -{ -unsigned long flags; - -local_irq_save (flags); -irq_set_status_flags (irq,IRQ_NOPROBE ); -gic_unmask_irq (irq_get_irq_data (irq)); -local_irq_restore (flags); -} -#ifdef CONFIG_SMP void gic_raise_softirq (const struct cpumask *mask,unsigned int irq) {
arch/arm/include/asm/entry-macro-multi.S +0 -7
@@ -23,13 +23,6 @@ movne r1, sp adrne lr, BSYM(1b) bne do_IPI - -#if defined(CONFIG_LOCAL_TIMERS) && !defined(CONFIG_ARM_GIC_VPPI) - test_for_ltirq r0, r6, r5, lr - movne r0, sp - adrne lr, BSYM(1b) - bne do_local_timer -#endif #endif 9997: .endm
arch/arm/include/asm/hardirq.h +0 -3
@@ -9,9 +9,6 @@ typedef struct { unsigned int __softirq_pending; -#ifdef CONFIG_LOCAL_TIMERS - unsigned int local_timer_irqs; -#endif #ifdef CONFIG_SMP unsigned int ipi_irqs[NR_IPI]; #endif
arch/arm/include/asm/hardware/entry-macro-gic.S +0 -13
@@ -65,16 +65,3 @@ strcc \irqstat, [\base, #GIC_CPU_EOI] cmpcs \irqnr, \irqnr .endm - -#ifndef CONFIG_ARM_GIC_VPPI -/* As above, this assumes that irqstat and base are preserved.. */ - - .macro test_for_ltirq, irqnr, irqstat, base, tmp - bic \irqnr, \irqstat, #0x1c00 - mov \tmp, #0 - cmp \irqnr, #29 - moveq \tmp, #1 - streq \irqstat, [\base, #GIC_CPU_EOI] - cmp \tmp, #0 - .endm -#endif
arch/arm/include/asm/hardware/gic.h +0 -1
@@ -42,7 +42,6 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);void gic_secondary_init (unsigned int );void gic_cascade_irq (unsigned int gic_nr,unsigned int irq);void gic_raise_softirq (const struct cpumask *mask,unsigned int irq); -void gic_enable_ppi (unsigned int );#ifdef CONFIG_ARM_GIC_VPPI unsigned int gic_ppi_to_vppi (unsigned int irq);#else
arch/arm/include/asm/localtimer.h +0 -5
@@ -20,11 +20,6 @@ struct clock_event_device;void percpu_timer_setup (void );/* -* Called from assembly, this is the local timer IRQ handler -*/ -asmlinkage void do_local_timer(struct pt_regs *); - -/* * Per-cpu timer IRQ handler */ irqreturn_t percpu_timer_handler (int irq,void *dev_id);
arch/arm/include/asm/smp.h +0 -5
@@ -88,9 +88,4 @@ extern void platform_cpu_enable(unsigned int cpu);extern void arch_send_call_function_single_ipi (int cpu);extern void arch_send_call_function_ipi_mask (const struct cpumask *mask); -/* -* show local interrupt info -*/ -extern void show_local_irqs (struct seq_file *,int ); -#endif /* ifndef __ASM_ARM_SMP_H */
arch/arm/kernel/irq.c +0 -3
@@ -59,9 +59,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)#ifdef CONFIG_SMP show_ipi_list (p, prec);#endif -#ifdef CONFIG_LOCAL_TIMERS -show_local_irqs (p, prec); -#endif seq_printf (p,"%*s: %10lu\n" , prec,"Err" , irq_err_count);return 0 ; }
arch/arm/kernel/smp.c +0 -29
@@ -426,10 +426,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)for (i =0 ; i <NR_IPI ; i++) sum +=__get_irq_stat (cpu, ipi_irqs[i]); -#ifdef CONFIG_LOCAL_TIMERS - sum +=__get_irq_stat (cpu, local_timer_irqs); -#endif -return sum; }
@@ -447,19 +443,6 @@ static void ipi_timer(void) }#ifdef CONFIG_LOCAL_TIMERS -asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs) -{ -struct pt_regs *old_regs =set_irq_regs (regs); -int cpu =smp_processor_id (); - -if (local_timer_ack ()) { -__inc_irq_stat (cpu, local_timer_irqs); -ipi_timer (); - } - -set_irq_regs (old_regs); -} -irqreturn_t percpu_timer_handler (int irq,void *dev_id) {struct clock_event_device *evt = dev_id;
@@ -471,18 +454,6 @@ irqreturn_t percpu_timer_handler(int irq, void *dev_id) return IRQ_NONE; } - -void show_local_irqs (struct seq_file *p,int prec) -{ -unsigned int cpu; - -seq_printf (p,"%*s: " , prec,"LOC" ); - -for_each_present_cpu (cpu) -seq_printf (p,"%10u " ,__get_irq_stat (cpu, local_timer_irqs)); - -seq_printf (p," Local timer interrupts\n" ); -}#endif #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
arch/arm/kernel/smp_twd.c +0 -7
@@ -45,10 +45,8 @@ static void twd_set_mode(enum clock_event_mode mode, ctrl =TWD_TIMER_CONTROL_IT_ENABLE |TWD_TIMER_CONTROL_ONESHOT ;break ;case CLOCK_EVT_MODE_UNUSED : -#ifdef CONFIG_ARM_GIC_VPPI disable_irq (clk->irq);/* fall through */ -#endif case CLOCK_EVT_MODE_SHUTDOWN :default : ctrl =0 ;
@@ -146,7 +144,6 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) clk->max_delta_ns =clockevent_delta2ns (0xffffffff , clk); clk->min_delta_ns =clockevent_delta2ns (0xf , clk); -#ifdef CONFIG_ARM_GIC_VPPI reqd = &__get_cpu_var (irq_reqd);if (!*reqd) { err = request_irq(clk->irq, percpu_timer_handler,
@@ -161,10 +158,6 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk) *reqd = true; }else enable_irq (clk->irq); -#else -/* Make sure our local interrupt controller has this enabled */ -gic_enable_ppi (clk->irq); -#endif clockevents_register_device (clk); }
Signature · 1 line
1.7.5.2
RFC PATCH v5 12/13 ARM: gic: add compute_irqnr macro for exynos4
In reply to Marc Zyngierexynos4 has a full copy of entry-macro-gic.S, just for the sake of an offset added to the IRQ number read from the GIC.
Add a compute_irqnr macro to entry-macro-gic.S so that any platform can add it's own hook without having to copy the whole file again.
--- arch/arm/include/asm/hardware/entry-macro-gic.S | 3 + arch/arm/mach-exynos4/include/mach/entry-macro.S | 60 ++-------------------- 2 files changed, 8 insertions(+), 55 deletions(-)
arch/arm/include/asm/hardware/entry-macro-gic.S +3 -0
@@ -50,6 +50,9 @@ cmpcc \irqnr, \irqnr cmpne \irqnr, \tmp cmpcs \irqnr, \irqnr +#ifdef HAVE_GIC_BASE_OFFSET + compute_irqnr \irqnr, \tmp +#endif .endm /* We assume that irqstat (the raw value of the IRQ acknowledge
arch/arm/mach-exynos4/include/mach/entry-macro.S +5 -55
71 lines not on this page · raw message
Signature · 1 line
1.7.5.2
RFC PATCH v5 13/13 ARM: SMP: automatically select ARM_GIC_VPPI
In reply to Marc ZyngierAll SMP platforms are selecting ARM_GIC_VPPI.
Instead, make SMP select ARM_GIC_VPPI and remove select statements from the platform code.
--- arch/arm/Kconfig | 1 + arch/arm/mach-msm/Kconfig | 2 -- arch/arm/mach-omap2/Kconfig | 1 - arch/arm/mach-realview/Kconfig | 2 -- arch/arm/mach-shmobile/Kconfig | 1 - arch/arm/mach-tegra/Kconfig | 1 - arch/arm/mach-ux500/Kconfig | 1 - arch/arm/mach-vexpress/Kconfig | 1 - arch/arm/plat-s5p/Kconfig | 1 - 9 files changed, 1 insertions(+), 10 deletions(-)
arch/arm/Kconfig +1 -0
@@ -1313,6 +1313,7 @@ config SMP ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE select USE_GENERIC_SMP_HELPERS + select ARM_GIC_VPPI select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP help This enables support for systems with more than one CPU. If you have
arch/arm/mach-msm/Kconfig +0 -2
@@ -42,7 +42,6 @@ config ARCH_MSM8X60 && !MACH_MSM8X60_FFA) select ARCH_MSM_SCORPIONMP select ARM_GIC - select ARM_GIC_VPPI select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX
@@ -53,7 +52,6 @@ config ARCH_MSM8960 select ARCH_MSM_SCORPIONMP select MACH_MSM8960_SIM if (!MACH_MSM8960_RUMI3) select ARM_GIC - select ARM_GIC_VPPI select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX
arch/arm/mach-omap2/Kconfig +0 -1
@@ -44,7 +44,6 @@ config ARCH_OMAP4 depends on ARCH_OMAP2PLUS select CPU_V7 select ARM_GIC - select ARM_GIC_VPPI select LOCAL_TIMERS if SMP select PL310_ERRATA_588369 select PL310_ERRATA_727915
arch/arm/mach-realview/Kconfig +0 -2
@@ -38,7 +38,6 @@ config MACH_REALVIEW_PB11MP bool "Support RealView(R) Platform Baseboard for ARM11MPCore" select CPU_V6K select ARM_GIC - select ARM_GIC_VPPI select HAVE_PATA_PLATFORM select ARCH_HAS_BARRIERS if SMP help
@@ -77,7 +76,6 @@ config MACH_REALVIEW_PBA8 config MACH_REALVIEW_PBX bool "Support RealView(R) Platform Baseboard Explore" select ARM_GIC - select ARM_GIC_VPPI select HAVE_PATA_PLATFORM select ARCH_SPARSEMEM_ENABLE if CPU_V7 && !REALVIEW_HIGH_PHYS_OFFSET select ZONE_DMA if SPARSEMEM
arch/arm/mach-shmobile/Kconfig +0 -1
@@ -26,7 +26,6 @@ config ARCH_SH73A0 select SH_CLK_CPG select ARCH_WANT_OPTIONAL_GPIOLIB select ARM_GIC - select ARM_GIC_VPPI comment "SH-Mobile Board Type"
arch/arm/mach-tegra/Kconfig +0 -1
@@ -9,7 +9,6 @@ config ARCH_TEGRA_2x_SOC bool "Tegra 2 family" select CPU_V7 select ARM_GIC - select ARM_GIC_VPPI select ARCH_REQUIRE_GPIOLIB select USB_ARCH_HAS_EHCI if USB_SUPPORT select USB_ULPI if USB_SUPPORT
arch/arm/mach-ux500/Kconfig +0 -1
@@ -4,7 +4,6 @@ config UX500_SOC_COMMON bool default y select ARM_GIC - select ARM_GIC_VPPI select HAS_MTU select ARM_ERRATA_753970
arch/arm/mach-vexpress/Kconfig +0 -1
@@ -5,7 +5,6 @@ config ARCH_VEXPRESS_CA9X4 bool "Versatile Express Cortex-A9x4 tile" select CPU_V7 select ARM_GIC - select ARM_GIC_VPPI select ARM_ERRATA_720789 select ARM_ERRATA_751472 select ARM_ERRATA_753970
arch/arm/plat-s5p/Kconfig +0 -1
@@ -11,7 +11,6 @@ config PLAT_S5P default y select ARM_VIC if !ARCH_EXYNOS4 select ARM_GIC if ARCH_EXYNOS4 - select ARM_GIC_VPPI if ARCH_EXYNOS4 select NO_IOPORT select ARCH_REQUIRE_GPIOLIB select S3C_GPIO_TRACK
Signature · 1 line
1.7.5.2
RFC PATCH v5 13/13 ARM: SMP: automatically select ARM_GIC_VPPI
arch/arm/Kconfig config SMP · line 1317
Quoted 10 lines · Marc Zyngier
arch/arm/Kconfig +1
-0@@ -1313,6 +1313,7 @@ config SMP ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE select USE_GENERIC_SMP_HELPERS + select ARM_GIC_VPPI select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
Would it be better to select GIC_VPPI only if GIC is selected as well? So
select ARM_GIC_VPPI if ARM_GIC
Or put this select under ARM_GIC and have it be
select ARM_GIC_VPPI if SMP
?
Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
RFC PATCH v5 13/13 ARM: SMP: automatically select ARM_GIC_VPPI
Quoted 14 lines · Stephen Boyd
arch/arm/Kconfig config SMP · line 1317
Quoted 10 lines · Marc Zyngier
arch/arm/Kconfig +1
-0@@ -1313,6 +1313,7 @@ config SMP ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \ ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE select USE_GENERIC_SMP_HELPERS + select ARM_GIC_VPPI select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMPWould it be better to select
GIC_VPPIonly if GIC is selected as well? So
Quoted 1 line
select
ARM_GIC_VPPIifARM_GIC
Possibly.
Quoted 5 lines
Or put this select under
ARM_GICand have it beselect
ARM_GIC_VPPIif SMP?
No, I want to be able to select GIC_VPPI even on UP (A15x1 requires it, for exemple).
But in the end, if everybody agrees this whole series is sensible, I'd rather get rid of the option and make it a permanent feature (patch #11 removes gic_enable_ppi() anyway, making the use of naked PPIs tricky at best...).
M.
Signature · 1 line
Reality is an implementation detail.
RFC PATCH v5 13/13 ARM: SMP: automatically select ARM_GIC_VPPI
Quoted 9 lines · Marc Zyngier
Quoted 3 lines · Stephen Boyd
Would it be better to select
GIC_VPPIonly if GIC is selected as well? Soselect
ARM_GIC_VPPIifARM_GICPossibly.
Quoted 4 lines
Or put this select under
ARM_GICand have it beselect
ARM_GIC_VPPIif SMP
Quoted 8 lines
Quoted 1 line
?
No, I want to be able to select
GIC_VPPIeven on UP (A15x1 requires it, for exemple).But in the end, if everybody agrees this whole series is sensible, I'd rather get rid of the option and make it a permanent feature (patch #11 removes
gic_enable_ppi()anyway, making the use of naked PPIs tricky at best...).
That sounds even better.
Signature · 2 lines
Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.