Add clkdev support for Samsung platforms
cover Add clkdev support for Samsung platforms
This patch series adds clkdev support for all Samsung platforms. clkdev support is a prerequisite for adding device tree on Samsung platforms and possibly revive framebuffer driver patches for Exynos4 platforms.
The first of the two patches are for eliminating the explict console_initcall from the serial drivers. This is required to prevent the clk_get being invoked at time when device registrations have not completed.
This patch series is based on the latest git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git for-next
and the patch "[PATCH] Consolidate the clkdev header files".
It has been tested on the following boards.
SMDK2416, SMDK2440, SMDK2450, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210 and SMDKV310.
Thomas Abraham (9):
serial: samsung: Fix unintended usage of uart port 0 as console
serial: Remove redundant console_initcall from s3c and s5p console drivers
ARM: SAMSUNG: Add clkdev infrastructure
ARM: S3C24XX: Add clkdev support
ARM: S3C64XX: Add clkdev support
ARM: S5P64X0: Add clkdev support
ARM: S5PC100: Add clkdev support
ARM: S5PV210: Add clkdev support
ARM: Exynos4: Add clkdev support
arch/arm/Kconfig | 6 + arch/arm/mach-exynos4/clock.c | 200 +++++++++------------------- arch/arm/mach-exynos4/time.c | 2 + arch/arm/mach-s3c2412/clock.c | 36 +----- arch/arm/mach-s3c2416/clock.c | 10 +- arch/arm/mach-s3c2440/clock.c | 3 - arch/arm/mach-s3c2443/clock.c | 16 +-- arch/arm/mach-s3c64xx/clock.c | 86 ++++--------- arch/arm/mach-s5p64x0/clock-s5p6440.c | 74 +++-------- arch/arm/mach-s5p64x0/clock-s5p6450.c | 68 +++------- arch/arm/mach-s5pc100/clock.c | 163 ++++++----------------- arch/arm/mach-s5pv210/clock.c | 130 ++++++------------- arch/arm/plat-s3c24xx/clock-dclk.c | 4 - arch/arm/plat-s3c24xx/s3c2410-clock.c | 21 +--- arch/arm/plat-s3c24xx/s3c2443-clock.c | 39 +----- arch/arm/plat-s5p/s5p-time.c | 9 ++ arch/arm/plat-samsung/clock.c | 98 +------------- arch/arm/plat-samsung/include/plat/clock.h | 3 + arch/arm/plat-samsung/pwm-clock.c | 10 ++ arch/arm/plat-samsung/time.c | 2 + drivers/tty/serial/s3c2400.c | 2 - drivers/tty/serial/s3c2410.c | 2 - drivers/tty/serial/s3c2412.c | 2 - drivers/tty/serial/s3c2440.c | 2 - drivers/tty/serial/s3c24a0.c | 2 - drivers/tty/serial/s3c6400.c | 2 - drivers/tty/serial/s5pv210.c | 7 - drivers/tty/serial/samsung.c | 9 +- drivers/tty/serial/samsung.h | 19 --- 29 files changed, 271 insertions(+), 756 deletions(-)
PATCH 1/9 serial: samsung: Fix unintended usage of uart port 0 as console
In s3c24xx_serial_console_setup function, if the uart port that is being setup as a console has not been initialized, an error can be returned instead of using uart port 0 as the default console port. The uart port that was intended to be used as a console could be initialized at a later point during boot and then registered as a console. This will avoid using uart port 0 as a unintended console port.
--- drivers/tty/serial/samsung.c | 6 ++---- 1 files changed, 2 insertions(+), 4 deletions(-)
drivers/tty/serial/samsung.c +2 -4
@@ -1416,10 +1416,8 @@ s3c24xx_serial_console_setup(struct console *co, char *options)/* is the port configured? */ -if (port->mapbase ==0x0 ) { - co->index =0 ; - port = &s3c24xx_serial_ports[co->index].port; - } +if (port->mapbase ==0x0 ) +return -ENODEV ; cons_uart = port;
Signature · 1 line
1.6.6.rc2
PATCH 2/9 serial: Remove redundant console_initcall from s3c and s5p console drivers
In reply to Thomas AbrahamUart port is registered as a console during the driver's probe. So explict registration of console with console_initcall is removed.
--- drivers/tty/serial/s3c2400.c | 2 -- drivers/tty/serial/s3c2410.c | 2 -- drivers/tty/serial/s3c2412.c | 2 -- drivers/tty/serial/s3c2440.c | 2 -- drivers/tty/serial/s3c24a0.c | 2 -- drivers/tty/serial/s3c6400.c | 2 -- drivers/tty/serial/s5pv210.c | 7 ------- drivers/tty/serial/samsung.c | 3 ++- drivers/tty/serial/samsung.h | 19 ------------------- 9 files changed, 2 insertions(+), 39 deletions(-)
drivers/tty/serial/s3c2400.c +0 -2
@@ -84,8 +84,6 @@ static struct platform_driver s3c2400_serial_driver = { }, }; -s3c24xx_console_init (&s3c2400_serial_driver, &s3c2400_uart_inf); -static inline int s3c2400_serial_init (void ) {return s3c24xx_serial_init (&s3c2400_serial_driver, &s3c2400_uart_inf);
drivers/tty/serial/s3c2410.c +0 -2
@@ -96,8 +96,6 @@ static struct platform_driver s3c2410_serial_driver = { }, }; -s3c24xx_console_init (&s3c2410_serial_driver, &s3c2410_uart_inf); -static int __init s3c2410_serial_init (void ) {return s3c24xx_serial_init (&s3c2410_serial_driver, &s3c2410_uart_inf);
drivers/tty/serial/s3c2412.c +0 -2
@@ -130,8 +130,6 @@ static struct platform_driver s3c2412_serial_driver = { }, }; -s3c24xx_console_init (&s3c2412_serial_driver, &s3c2412_uart_inf); -static inline int s3c2412_serial_init (void ) {return s3c24xx_serial_init (&s3c2412_serial_driver, &s3c2412_uart_inf);
drivers/tty/serial/s3c2440.c +0 -2
@@ -159,8 +159,6 @@ static struct platform_driver s3c2440_serial_driver = { }, }; -s3c24xx_console_init (&s3c2440_serial_driver, &s3c2440_uart_inf); -static int __init s3c2440_serial_init (void ) {return s3c24xx_serial_init (&s3c2440_serial_driver, &s3c2440_uart_inf);
drivers/tty/serial/s3c24a0.c +0 -2
@@ -100,8 +100,6 @@ static struct platform_driver s3c24a0_serial_driver = { }, }; -s3c24xx_console_init (&s3c24a0_serial_driver, &s3c24a0_uart_inf); -static int __init s3c24a0_serial_init (void ) {return s3c24xx_serial_init (&s3c24a0_serial_driver, &s3c24a0_uart_inf);
drivers/tty/serial/s3c6400.c +0 -2
@@ -130,8 +130,6 @@ static struct platform_driver s3c6400_serial_driver = { }, }; -s3c24xx_console_init (&s3c6400_serial_driver, &s3c6400_uart_inf); -static int __init s3c6400_serial_init (void ) {return s3c24xx_serial_init (&s3c6400_serial_driver, &s3c6400_uart_inf);
drivers/tty/serial/s5pv210.c +0 -7
@@ -135,13 +135,6 @@ static struct platform_driver s5p_serial_driver = { }, }; -static int __init s5pv210_serial_console_init (void ) -{ -return s3c24xx_serial_initconsole (&s5p_serial_driver, s5p_uart_inf); -} - -console_initcall (s5pv210_serial_console_init); -static int __init s5p_serial_init (void ) {return s3c24xx_serial_init (&s5p_serial_driver, *s5p_uart_inf);
drivers/tty/serial/samsung.c +2 -1
@@ -1449,7 +1449,8 @@ static struct console s3c24xx_serial_console = { .flags = CON_PRINTBUFFER, .index = -1, .write = s3c24xx_serial_console_write, - .setup = s3c24xx_serial_console_setup + .setup = s3c24xx_serial_console_setup, + .data = &s3c24xx_uart_drv, }; int s3c24xx_serial_initconsole(struct platform_driver *drv,
drivers/tty/serial/samsung.h +0 -19
@@ -79,25 +79,6 @@ extern int s3c24xx_serial_initconsole(struct platform_driver *drv,extern int s3c24xx_serial_init (struct platform_driver *drv,struct s3c24xx_uart_info *info); -#ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE - -#define s3c24xx_console_init (__drv, __inf) \ -static int __init s3c_serial_console_init(void) \ -{ \ - struct s3c24xx_uart_info *uinfo[CONFIG_SERIAL_SAMSUNG_UARTS]; \ - int i; \ - \ - for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) \ - uinfo[i] = __inf; \ - return s3c24xx_serial_initconsole(__drv, uinfo); \ -} \ - \ -console_initcall(s3c_serial_console_init) - -#else -#define s3c24xx_console_init (drv, inf) extern void no_console(void) -#endif -#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG extern void printascii (const char *);
Signature · 1 line
1.6.6.rc2
PATCH 3/9 ARM: SAMSUNG: Add clkdev infrastructure
In reply to Thomas AbrahamThe struct clk definition for Samsung platforms is extended to include a instance of struct clk_lookup and a device name. When clocks are registered using s3c24xx_register_clock function, the dev_id, con_id and clk members are initialized with information from the struct clk instance and struct clk_lookup member is registered.
--- arch/arm/plat-samsung/clock.c | 88 ++-------------------------- arch/arm/plat-samsung/include/plat/clock.h | 3 + 2 files changed, 9 insertions(+), 82 deletions(-)
arch/arm/plat-samsung/clock.c +6 -82
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)return 0 ; } -static int dev_is_s3c_uart (struct device *dev) -{ -struct platform_device **pdev = s3c24xx_uart_devs; -int i; -for (i =0 ; i <ARRAY_SIZE (s3c24xx_uart_devs); i++, pdev++) -if (*pdev && dev == &(*pdev)->dev) -return 1 ; -return 0 ; -} - -/* -* Serial drivers call get_clock() very early, before platform bus -* has been set up, this requires a special check to let them get -* a proper clock -*/ - -static int dev_is_platform_device (struct device *dev) -{ -return dev->bus == &platform_bus_type || - (dev->bus ==NULL &&dev_is_s3c_uart (dev)); -} - -/* Clock API calls */ - -struct clk *clk_get (struct device *dev,const char *id) -{ -struct clk *p; -struct clk *clk =ERR_PTR (-ENOENT ); -int idno; - -if (dev ==NULL || !dev_is_platform_device (dev)) - idno =-1 ; -else - idno =to_platform_device (dev)->id; - -spin_lock (&clocks_lock); - -list_for_each_entry (p, &clocks, list) { -if (p->id == idno && -strcmp (id, p->name) ==0 && -try_module_get (p->owner)) { - clk = p; -break ; - } - } - -/* check for the case where a device was supplied, but the -* clock that was being searched for is not device specific */ - -if (IS_ERR (clk)) { -list_for_each_entry (p, &clocks, list) { -if (p->id ==-1 &&strcmp (id, p->name) ==0 && -try_module_get (p->owner)) { - clk = p; -break ; - } - } - } - -spin_unlock (&clocks_lock); -return clk; -} - -void clk_put (struct clk *clk) -{ -module_put (clk->owner); -} -int clk_enable (struct clk *clk) {if (IS_ERR (clk) || clk ==NULL )
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)return ret; } -EXPORT_SYMBOL (clk_get); -EXPORT_SYMBOL (clk_put);EXPORT_SYMBOL (clk_enable);EXPORT_SYMBOL (clk_disable);EXPORT_SYMBOL (clk_get_rate);
@@ -346,14 +276,11 @@ int s3c24xx_register_clock(struct clk *clk)if (clk->enable ==NULL ) clk->enable = clk_null_enable; -/* add to the list of available clocks */ - -/* Quick check to see if this clock has already been registered. */ -BUG_ON (clk->list.prev != clk->list.next); - -spin_lock (&clocks_lock); -list_add (&clk->list, &clocks); -spin_unlock (&clocks_lock); +/* fill up the clk_lookup structure and register it*/ + clk->lookup.dev_id = clk->devname; + clk->lookup.con_id = clk->name; + clk->lookup.clk = clk; +clkdev_add (&clk->lookup);return 0 ; }
@@ -463,10 +390,7 @@ static int clk_debugfs_register_one(struct clk *c)char s[255 ];char *p = s; - p +=sprintf (p,"%s" , c->name); - -if (c->id >=0 ) -sprintf (p,":%d" , c->id); + p +=sprintf (p,"%s" , c->devname); d =debugfs_create_dir (s, pa ? pa->dent : clk_debugfs_root);if (!d)
arch/arm/plat-samsung/include/plat/clock.h +3 -0
@@ -10,6 +10,7 @@*/ #include <linux/spinlock.h> +#include <linux/clkdev.h> struct clk ;
@@ -40,6 +41,7 @@ struct clk {struct module *owner;struct clk *parent;const char *name; +const char *devname;int id;int usage;unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {struct clk_ops *ops;int (*enable)(struct clk *,int enable); +struct clk_lookup lookup;#if defined(CONFIG_PM_DEBUG ) && defined(CONFIG_DEBUG_FS )struct dentry *dent;/* For visible tree hierarchy */ #endif
Signature · 1 line
1.6.6.rc2
PATCH 4/9 ARM: S3C24XX: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's s3c24xx platforms.
--- arch/arm/Kconfig | 1 + arch/arm/mach-s3c2412/clock.c | 36 ++--------------------------- arch/arm/mach-s3c2416/clock.c | 10 ++++---- arch/arm/mach-s3c2440/clock.c | 3 -- arch/arm/mach-s3c2443/clock.c | 16 +++---------- arch/arm/plat-s3c24xx/clock-dclk.c | 4 --- arch/arm/plat-s3c24xx/s3c2410-clock.c | 21 ++--------------- arch/arm/plat-s3c24xx/s3c2443-clock.c | 39 +++----------------------------- arch/arm/plat-samsung/clock.c | 10 -------- arch/arm/plat-samsung/pwm-clock.c | 10 ++++++++ arch/arm/plat-samsung/time.c | 2 + 11 files changed, 32 insertions(+), 120 deletions(-)
arch/arm/Kconfig +1 -0
@@ -687,6 +687,7 @@ config ARCH_S3C2410 select GENERIC_GPIO select ARCH_HAS_CPUFREQ select HAVE_CLK + select CLKDEV_LOOKUP select ARCH_USES_GETTIMEOFFSET select HAVE_S3C2410_I2C if I2C help
arch/arm/mach-s3c2412/clock.c +3 -33
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)static struct clk clk_erefclk = { .name ="erefclk" , - .id =-1 , };static struct clk clk_urefclk = { .name ="urefclk" , - .id =-1 , };static int s3c2412_setparent_usysclk (struct clk *clk,struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)static struct clk clk_usysclk = { .name ="usysclk" , - .id =-1 , .parent = &clk_xtal, .ops = &(struct clk_ops ) { .set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {static struct clk clk_mrefclk = { .name ="mrefclk" , .parent = &clk_xtal, - .id =-1 , };static struct clk clk_mdivclk = { .name ="mdivclk" , .parent = &clk_xtal, - .id =-1 , };static int s3c2412_setparent_usbsrc (struct clk *clk,struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)static struct clk clk_usbsrc = { .name ="usbsrc" , - .id =-1 , .ops = &(struct clk_ops ) { .get_rate = s3c2412_getrate_usbsrc, .set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)static struct clk clk_msysclk = { .name ="msysclk" , - .id =-1 , .ops = &(struct clk_ops ) { .set_parent = s3c2412_setparent_msysclk, },
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)static struct clk clk_armclk = { .name ="armclk" , - .id =-1 , .parent = &clk_msysclk, .ops = &(struct clk_ops ) { .set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)static struct clk clk_uart = { .name ="uartclk" , - .id =-1 , .ops = &(struct clk_ops ) { .get_rate = s3c2412_getrate_uart, .set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)static struct clk clk_i2s = { .name ="i2sclk" , - .id =-1 , .ops = &(struct clk_ops ) { .get_rate = s3c2412_getrate_i2s, .set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)static struct clk clk_cam = { .name ="camif-upll" ,/* same as 2440 name */ - .id =-1 , .ops = &(struct clk_ops ) { .get_rate = s3c2412_getrate_cam, .set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {static struct clk init_clocks_disable[] = { { .name ="nand" , - .id =-1 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_NAND , }, { .name ="sdi" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_SDI , }, { .name ="adc" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_ADC , }, { .name ="i2c" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_IIC , }, { .name ="iis" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_IIS , }, { .name ="spi" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_SPI ,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {static struct clk init_clocks[] = { { .name ="dma" , - .id =0 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_DMA0 , }, { .name ="dma" , - .id =1 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_DMA1 , }, { .name ="dma" , - .id =2 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_DMA2 , }, { .name ="dma" , - .id =3 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_DMA3 , }, { .name ="lcd" , - .id =-1 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_LCDC , }, { .name ="gpio" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_GPIO , }, { .name ="usb-host" , - .id =-1 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_USBH , }, { .name ="usb-device" , - .id =-1 , .parent = &clk_h, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_USBD , }, { .name ="timers" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_PWMT , }, { .name ="uart" , - .id =0 , + .devname ="s3c2412-uart.0" , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_UART0 , }, { .name ="uart" , - .id =1 , + .devname ="s3c2412-uart.1" , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_UART1 , }, { .name ="uart" , - .id =2 , + .devname ="s3c2412-uart.2" , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_UART2 , }, { .name ="rtc" , - .id =-1 , .parent = &clk_p, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_RTC , }, { .name ="watchdog" , - .id =-1 , .parent = &clk_p, .ctrlbit =0 , }, { .name ="usb-bus-gadget" , - .id =-1 , .parent = &clk_usb_bus, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_USB_DEV48 , }, { .name ="usb-bus-host" , - .id =-1 , .parent = &clk_usb_bus, .enable = s3c2412_clkcon_enable, .ctrlbit =S3C2412_CLKCON_USB_HOST48 ,
arch/arm/mach-s3c2416/clock.c +5 -5
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = { [0] = { .clk = { .name = "hsmmc-div", - .id = 0, + .devname = "s3c-sdhci.0", .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = { [1] = { .clk = { .name = "hsmmc-div", - .id = 1, + .devname = "s3c-sdhci.1", .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {static struct clksrc_clk hsmmc_mux[] = { [0 ] = { .clk = { - .id =0 , .name ="hsmmc-if" , + .devname ="s3c-sdhci.0" , .ctrlbit = (1 <<6 ), .enable = s3c2443_clkcon_enable_s, },
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = { }, [1] = { .clk = { - .id = 1, .name = "hsmmc-if", + .devname = "s3c-sdhci.1", .ctrlbit = (1 << 12), .enable = s3c2443_clkcon_enable_s, },
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {static struct clk hsmmc0_clk = { .name ="hsmmc" , - .id =0 , + .devname ="s3c-sdhci.0" , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2416_HCLKCON_HSMMC0 ,
arch/arm/mach-s3c2440/clock.c +0 -3
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)static struct clk s3c2440_clk_cam = { .name ="camif" , - .id =-1 , .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2440_CLKCON_CAMERA , };static struct clk s3c2440_clk_cam_upll = { .name ="camif-upll" , - .id =-1 , .ops = &(struct clk_ops ) { .set_rate = s3c2440_camif_upll_setrate, .round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {static struct clk s3c2440_clk_ac97 = { .name ="ac97" , - .id =-1 , .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2440_CLKCON_CAMERA , };
arch/arm/mach-s3c2443/clock.c +4 -12
@@ -59,7 +59,6 @@static struct clk clk_i2s_ext = { .name ="i2s-ext" , - .id =-1 , };/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)static struct clk clk_armdiv = { .name ="armdiv" , - .id =-1 , .parent = &clk_msysclk.clk, .ops = &(struct clk_ops ) { .round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {static struct clksrc_clk clk_arm = { .clk = { .name ="armclk" , - .id =-1 , }, .sources = &(struct clksrc_sources ) { .sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {static struct clksrc_clk clk_hsspi = { .clk = { .name ="hsspi" , - .id =-1 , .parent = &clk_esysclk.clk, .ctrlbit =S3C2443_SCLKCON_HSSPICLK , .enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {static struct clksrc_clk clk_hsmmc_div = { .clk = { .name ="hsmmc-div" , - .id =1 , + .devname ="s3c-sdhci.1" , .parent = &clk_esysclk.clk, }, .reg_div = { .reg =S3C2443_CLKDIV1 , .size =2 , .shift =6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)static struct clk clk_hsmmc = { .name ="hsmmc-if" , - .id =1 , + .devname ="s3c-sdhci.1" , .parent = &clk_hsmmc_div.clk, .enable = s3c2443_enable_hsmmc, .ops = &(struct clk_ops ) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {static struct clksrc_clk clk_i2s_eplldiv = { .clk = { .name ="i2s-eplldiv" , - .id =-1 , .parent = &clk_esysclk.clk, }, .reg_div = { .reg =S3C2443_CLKDIV1 , .size =4 , .shift =12 , },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {static struct clksrc_clk clk_i2s = { .clk = { .name ="i2s-if" , - .id =-1 , .ctrlbit =S3C2443_SCLKCON_I2SCLK , .enable = s3c2443_clkcon_enable_s,
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {static struct clk init_clocks_off[] = { { .name ="sdi" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_SDI , }, { .name ="iis" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_IIS , }, { .name ="spi" , - .id =0 , + .devname ="s3c2410-spi.0" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_SPI0 , }, { .name ="spi" , - .id =1 , + .devname ="s3c2410-spi.1" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_SPI1 ,
arch/arm/plat-s3c24xx/clock-dclk.c +0 -4
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {struct clk s3c24xx_dclk0 = { .name ="dclk0" , - .id =-1 , .ctrlbit =S3C2410_DCLKCON_DCLK0EN , .enable = s3c24xx_dclk_enable, .ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {struct clk s3c24xx_dclk1 = { .name ="dclk1" , - .id =-1 , .ctrlbit =S3C2410_DCLKCON_DCLK1EN , .enable = s3c24xx_dclk_enable, .ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {struct clk s3c24xx_clkout0 = { .name ="clkout0" , - .id =-1 , .ops = &clkout_ops, };struct clk s3c24xx_clkout1 = { .name ="clkout1" , - .id =-1 , .ops = &clkout_ops, };
arch/arm/plat-s3c24xx/s3c2410-clock.c +3 -18
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)static struct clk init_clocks_off[] = { { .name ="nand" , - .id =-1 , .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_NAND , }, { .name ="sdi" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_SDI , }, { .name ="adc" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_ADC , }, { .name ="i2c" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_IIC , }, { .name ="iis" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_IIS , }, { .name ="spi" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_SPI ,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {static struct clk init_clocks[] = { { .name ="lcd" , - .id =-1 , .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_LCDC , }, { .name ="gpio" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_GPIO , }, { .name ="usb-host" , - .id =-1 , .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_USBH , }, { .name ="usb-device" , - .id =-1 , .parent = &clk_h, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_USBD , }, { .name ="timers" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_PWMT , }, { .name ="uart" , - .id =0 , + .devname ="s3c2410-uart.0" , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_UART0 , }, { .name ="uart" , - .id =1 , + .devname ="s3c2410-uart.1" , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_UART1 , }, { .name ="uart" , - .id =2 , + .devname ="s3c2410-uart.2" , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_UART2 , }, { .name ="rtc" , - .id =-1 , .parent = &clk_p, .enable = s3c2410_clkcon_enable, .ctrlbit =S3C2410_CLKCON_RTC , }, { .name ="watchdog" , - .id =-1 , .parent = &clk_p, .ctrlbit =0 , }, { .name ="usb-bus-host" , - .id =-1 , .parent = &clk_usb_bus, }, { .name ="usb-bus-gadget" , - .id =-1 , .parent = &clk_usb_bus, }, };
arch/arm/plat-s3c24xx/s3c2443-clock.c +4 -35
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)struct clk clk_mpllref = { .name ="mpllref" , .parent = &clk_xtal, - .id =-1 , };static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {struct clksrc_clk clk_epllref = { .clk = { .name ="epllref" , - .id =-1 , }, .sources = &(struct clksrc_sources ) { .sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = { .clk = { .name = "esysclk", .parent = &clk_epll, - .id = -1, }, .sources = &(struct clksrc_sources ) { .sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)static struct clk clk_mdivclk = { .name ="mdivclk" , .parent = &clk_mpllref, - .id =-1 , .ops = &(struct clk_ops ) { .get_rate = s3c2443_getrate_mdivclk, },
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = { .clk = { .name = "msysclk", .parent = &clk_xtal, - .id = -1, }, .sources = &(struct clksrc_sources ) { .sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)static struct clk clk_prediv = { .name ="prediv" , - .id =-1 , .parent = &clk_msysclk.clk, .ops = &(struct clk_ops ) { .get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {static struct clksrc_clk clk_usb_bus_host = { .clk = { .name ="usb-bus-host-parent" , - .id =-1 , .parent = &clk_esysclk.clk, .ctrlbit =S3C2443_SCLKCON_USBHOST , .enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {/* ART baud-rate clock sourced from esysclk via a divisor */ .clk = { .name = "uartclk", - .id = -1, .parent = &clk_esysclk.clk, }, .reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {/* camera interface bus-clock, divided down from esysclk */ .clk = { .name = "camif-upll", /* same as 2440 name */ - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_CAMCLK, .enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = { }, { .clk = { .name = "display-if", - .id = -1, .parent = &clk_esysclk.clk, .ctrlbit = S3C2443_SCLKCON_DISPCLK, .enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {static struct clk init_clocks_off[] = { { .name ="adc" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_ADC , }, { .name ="i2c" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_IIC ,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {static struct clk init_clocks[] = { { .name ="dma" , - .id =0 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA0 , }, { .name ="dma" , - .id =1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA1 , }, { .name ="dma" , - .id =2 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA2 , }, { .name ="dma" , - .id =3 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA3 , }, { .name ="dma" , - .id =4 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA4 , }, { .name ="dma" , - .id =5 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_DMA5 , }, { .name ="hsmmc" , - .id =1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_HSMMC , }, { .name ="gpio" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_GPIO , }, { .name ="usb-host" , - .id =-1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_USBH , }, { .name ="usb-device" , - .id =-1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_USBD , }, { .name ="lcd" , - .id =-1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_LCDC , }, { .name ="timers" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_PWMT , }, { .name ="cfc" , - .id =-1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_CFC , }, { .name ="ssmc" , - .id =-1 , .parent = &clk_h, .enable = s3c2443_clkcon_enable_h, .ctrlbit =S3C2443_HCLKCON_SSMC , }, { .name ="uart" , - .id =0 , + .devname ="s3c2440-uart.0" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_UART0 , }, { .name ="uart" , - .id =1 , + .devname ="s3c2440-uart.1" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_UART1 , }, { .name ="uart" , - .id =2 , + .devname ="s3c2440-uart.2" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_UART2 , }, { .name ="uart" , - .id =3 , + .devname ="s3c2440-uart.3" , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_UART3 , }, { .name ="rtc" , - .id =-1 , .parent = &clk_p, .enable = s3c2443_clkcon_enable_p, .ctrlbit =S3C2443_PCLKCON_RTC , }, { .name ="watchdog" , - .id =-1 , .parent = &clk_p, .ctrlbit =S3C2443_PCLKCON_WDT , }, { .name ="ac97" , - .id =-1 , .parent = &clk_p, .ctrlbit =S3C2443_PCLKCON_AC97 , }, { .name ="nand" , - .id =-1 , .parent = &clk_h, }, { .name ="usb-bus-host" , - .id =-1 , .parent = &clk_usb_bus_host.clk, } };
arch/arm/plat-samsung/clock.c +0 -10
@@ -195,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {struct clk clk_xtal = { .name ="xtal" , - .id =-1 , .rate =0 , .parent =NULL , .ctrlbit =0 ,
@@ -203,30 +202,25 @@ struct clk clk_xtal = {struct clk clk_ext = { .name ="ext" , - .id =-1 , };struct clk clk_epll = { .name ="epll" , - .id =-1 , };struct clk clk_mpll = { .name ="mpll" , - .id =-1 , .ops = &clk_ops_def_setrate, };struct clk clk_upll = { .name ="upll" , - .id =-1 , .parent =NULL , .ctrlbit =0 , };struct clk clk_f = { .name ="fclk" , - .id =-1 , .rate =0 , .parent = &clk_mpll, .ctrlbit =0 ,
@@ -234,7 +228,6 @@ struct clk clk_f = {struct clk clk_h = { .name ="hclk" , - .id =-1 , .rate =0 , .parent =NULL , .ctrlbit =0 ,
@@ -243,7 +236,6 @@ struct clk clk_h = {struct clk clk_p = { .name ="pclk" , - .id =-1 , .rate =0 , .parent =NULL , .ctrlbit =0 ,
@@ -252,7 +244,6 @@ struct clk clk_p = {struct clk clk_usb_bus = { .name ="usb-bus" , - .id =-1 , .rate =0 , .parent = &clk_upll, };
@@ -260,7 +251,6 @@ struct clk clk_usb_bus = {struct clk s3c24xx_uclk = { .name ="uclk" , - .id =-1 , };/* initialise the clock system */
arch/arm/plat-samsung/pwm-clock.c +10 -0
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [0] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.0", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[0], },
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [1] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.1", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[0], }
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [2] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.2", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], },
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [3] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.3", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], },
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = { [4] = { .clk = { .name = "pwm-tdiv", + .devname = "s3c24xx-pwm.4", .ops = &clk_tdiv_ops, .parent = &clk_timer_scaler[1], },
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {static struct clk clk_tin[] = { [0 ] = { .name ="pwm-tin" , + .devname ="s3c24xx-pwm.0" , .id =0 , .ops = &clk_tin_ops, }, [1 ] = { .name ="pwm-tin" , + .devname ="s3c24xx-pwm.1" , .id =1 , .ops = &clk_tin_ops, }, [2 ] = { .name ="pwm-tin" , + .devname ="s3c24xx-pwm.2" , .id =2 , .ops = &clk_tin_ops, }, [3 ] = { .name ="pwm-tin" , + .devname ="s3c24xx-pwm.3" , .id =3 , .ops = &clk_tin_ops, }, [4 ] = { .name ="pwm-tin" , + .devname ="s3c24xx-pwm.4" , .id =4 , .ops = &clk_tin_ops, },
arch/arm/plat-samsung/time.c +2 -0
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)clk_enable (timerclk);if (!use_tclk1_12 ()) { + tmpdev.id =4 ; + tmpdev.dev.init_name ="s3c24xx-pwm.4" ; tin =clk_get (&tmpdev.dev,"pwm-tin" );if (IS_ERR (tin))panic ("failed to get pwm-tin clock for system timer" );
Signature · 1 line
1.6.6.rc2
PATCH 5/9 ARM: S3C64XX: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's s3c64xx platforms.
--- arch/arm/Kconfig | 1 + arch/arm/mach-s3c64xx/clock.c | 86 ++++++++++++----------------------------- 2 files changed, 26 insertions(+), 61 deletions(-)
arch/arm/Kconfig +1 -0
@@ -705,6 +705,7 @@ config ARCH_S3C64XX select CPU_V6 select ARM_VIC select HAVE_CLK + select CLKDEV_LOOKUP select NO_IOPORT select ARCH_USES_GETTIMEOFFSET select ARCH_HAS_CPUFREQ
arch/arm/mach-s3c64xx/clock.c +25 -61
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Signature · 1 line
1.6.6.rc2
PATCH 6/9 ARM: S5P64X0: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's s5p64x0 platforms.
--- arch/arm/Kconfig | 1 + arch/arm/mach-s5p64x0/clock-s5p6440.c | 74 +++++++++------------------------ arch/arm/mach-s5p64x0/clock-s5p6450.c | 68 ++++++++---------------------- arch/arm/plat-s5p/s5p-time.c | 9 ++++ 4 files changed, 49 insertions(+), 103 deletions(-)
arch/arm/Kconfig +1 -0
@@ -730,6 +730,7 @@ config ARCH_S5P64X0 select CPU_V6 select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select HAVE_S3C2410_WATCHDOG if WATCHDOG select GENERIC_CLOCKEVENTS select HAVE_SCHED_CLOCK
arch/arm/mach-s5p64x0/clock-s5p6440.c +20 -54
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arch/arm/mach-s5p64x0/clock-s5p6450.c +19 -49
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arch/arm/plat-s5p/s5p-time.c +9 -0
@@ -384,6 +384,7 @@ static void __init s5p_timer_resources(void)unsigned long event_id = timer_source.event_id;unsigned long source_id = timer_source.source_id; +char devname[15 ]; timerclk =clk_get (NULL ,"timers" );if (IS_ERR (timerclk))
@@ -391,6 +392,10 @@ static void __init s5p_timer_resources(void)clk_enable (timerclk); +sprintf (devname,"s3c24xx-pwm.%lu" , event_id); + s3c_device_timer[event_id].id = event_id; + s3c_device_timer[event_id].dev.init_name = devname; + tin_event =clk_get (&s3c_device_timer[event_id].dev,"pwm-tin" );if (IS_ERR (tin_event))panic ("failed to get pwm-tin clock for event timer" );
@@ -401,6 +406,10 @@ static void __init s5p_timer_resources(void)clk_enable (tin_event); +sprintf (devname,"s3c24xx-pwm.%lu" , source_id); + s3c_device_timer[source_id].id = source_id; + s3c_device_timer[source_id].dev.init_name = devname; + tin_source =clk_get (&s3c_device_timer[source_id].dev,"pwm-tin" );if (IS_ERR (tin_source))panic ("failed to get pwm-tin clock for source timer" );
Signature · 1 line
1.6.6.rc2
PATCH 7/9 ARM: S5PC100: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's s5pc100 platforms.
--- arch/arm/Kconfig | 1 + arch/arm/mach-s5pc100/clock.c | 163 ++++++++++------------------------------- 2 files changed, 41 insertions(+), 123 deletions(-)
arch/arm/Kconfig +1 -0
@@ -744,6 +744,7 @@ config ARCH_S5PC100 bool "Samsung S5PC100" select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select CPU_V7 select ARM_L1_CACHE_SHIFT_6 select ARCH_USES_GETTIMEOFFSET
arch/arm/mach-s5pc100/clock.c +40 -123
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Signature · 1 line
1.6.6.rc2
PATCH 8/9 ARM: S5PV210: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's s5pv210 platform.
--- arch/arm/Kconfig | 1 + arch/arm/mach-s5pv210/clock.c | 130 +++++++++++++---------------------------- 2 files changed, 41 insertions(+), 90 deletions(-)
arch/arm/Kconfig +1 -0
@@ -760,6 +760,7 @@ config ARCH_S5PV210 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select ARM_L1_CACHE_SHIFT_6 select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS
arch/arm/mach-s5pv210/clock.c +40 -90
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Signature · 1 line
1.6.6.rc2
PATCH 9/9 ARM: Exynos4: Add clkdev support
In reply to Thomas AbrahamAdd clkdev support for Samsung's Exynos4 platform and fixes the incorrect clock name for the dw_mmc controller.
--- arch/arm/Kconfig | 1 + arch/arm/mach-exynos4/clock.c | 200 ++++++++++++++--------------------------- arch/arm/mach-exynos4/time.c | 2 + 3 files changed, 69 insertions(+), 134 deletions(-)
arch/arm/Kconfig +1 -0
@@ -777,6 +777,7 @@ config ARCH_EXYNOS4 select ARCH_SPARSEMEM_ENABLE select GENERIC_GPIO select HAVE_CLK + select CLKDEV_LOOKUP select ARCH_HAS_CPUFREQ select GENERIC_CLOCKEVENTS select HAVE_S3C_RTC if RTC_CLASS
arch/arm/mach-exynos4/clock.c +66 -134
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arch/arm/mach-exynos4/time.c +2 -0
@@ -264,6 +264,7 @@ static void __init exynos4_timer_resources(void)clk_enable (timerclk); tmpdev.id =2 ; + tmpdev.dev.init_name ="s3c24xx-pwm.2" ; tin2 =clk_get (&tmpdev.dev,"pwm-tin" );if (IS_ERR (tin2))panic ("failed to get pwm-tin2 clock for system timer" );
@@ -274,6 +275,7 @@ static void __init exynos4_timer_resources(void)clk_enable (tin2); tmpdev.id =4 ; + tmpdev.dev.init_name ="s3c24xx-pwm.4" ; tin4 =clk_get (&tmpdev.dev,"pwm-tin" );if (IS_ERR (tin4))panic ("failed to get pwm-tin4 clock for system timer" );
Signature · 1 line
1.6.6.rc2
cover Add clkdev support for Samsung platforms
In reply to Thomas AbrahamQuoted 12 lines · Thomas Abraham
This patch series adds clkdev support for all Samsung platforms. clkdev support is a prerequisite for adding device tree on Samsung platforms and possibly revive framebuffer driver patches for Exynos4 platforms.
The first of the two patches are for eliminating the explict
console_initcallfrom the serial drivers. This is required to prevent theclk_getbeing invoked at time when device registrations have not completed.This patch series is based on the latest git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git for-next
Quoted 7 lines
and the patch "[PATCH] Consolidate the clkdev header files".
It has been tested on the following boards.
SMDK2416, SMDK2440, SMDK2450, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210 and SMDKV310.
Thomas,
Basically, this is good to me. I will check again after backing to my office and will apply whole series :)
If any problems, let you know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
cover Add clkdev support for Samsung platforms
In reply to Thomas AbrahamQuoted 12 lines · Thomas Abraham
This patch series adds clkdev support for all Samsung platforms. clkdev support is a prerequisite for adding device tree on Samsung platforms and possibly revive framebuffer driver patches for Exynos4 platforms.
The first of the two patches are for eliminating the explict
console_initcallfrom the serial drivers. This is required to prevent theclk_getbeing invoked at time when device registrations have not completed.This patch series is based on the latest git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung.git for-next
Quoted 6 lines
and the patch "[PATCH] Consolidate the clkdev header files".
It has been tested on the following boards.
SMDK2416, SMDK2440, SMDK2450, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210 and SMDKV310.
looks good
Best Regards,
J.