U-Boot MMC SPL for OMAP4

index f63a2ff..4198d76 100644
@@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 

index 005e0d2..f74e2b9 100644
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types

index f5859d7..ec6d75e 100644
@@ -155,6 +155,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 

index 9033a7d..3b49645 100644
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */

229 lines not on this page · raw message

50 lines not on this page · raw message

new file mode 100644
index 0000000..03db2f5
@@ -0,0 +1,51 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef	_OMAP_COMMON_H_
+#define	_OMAP_COMMON_H_
+
+/* extract a bit field from a bit vector */
+#define get_bit_field(nr, start, mask)\
+	(((nr) & (mask)) >> (start))
+
+/* Set a field in a bit vector */
+#define set_bit_field(nr, start, mask, val)\
+	do { \
+		(nr) = ((nr) & ~(mask)) | (((val) << (start)) & (mask));\
+	} while (0);
+
+/*
+ * Utility macro for read-modify-write of a hardware register
+ *	addr - address of the register
+ *	shift - starting bit position of the field to be modified
+ *	msk - mask for the field
+ *	val - value to be shifted masked and written to the field
+ */
+#define modify_reg_32(addr, shift, msk, val) \
+	do {\
+		writel(((readl(addr) & ~(msk))|(((val) << (shift)) & (msk))),\
+		       (addr));\
+	} while (0);
+
+#endif /* _OMAP_COMMON_H_ */

index fcd29a7..7583a0d 100644
@@ -28,6 +28,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <asm/armv7.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>

@@ -127,3 +128,37 @@ int arch_cpu_init(void)
 	set_muxconf_regs();
 	return 0;
 }
+
+static u32 cortex_a9_rev(void)
+{
+
+	unsigned int rev;
+
+	/* Read Main ID Register (MIDR) */
+	asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev));
+
+	return rev;
+}
+
+u32 omap4_revision(void)
+{
+	if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_1)
+		return OMAP4430_ES2_1;
+	else if (readl(CONTROL_ID_CODE) == OMAP4_CONTROL_ID_CODE_ES2_2)
+		return OMAP4430_ES2_2;
+	/*
+	 * For some of the ES2/ES1 boards ID_CODE is not reliable:
+	 * Also, ES1 and ES2 have different ARM revisions
+	 * So use ARM revision for identification
+	 */
+	unsigned int rev = cortex_a9_rev();
+
+	switch (rev) {
+	case MIDR_CORTEX_A9_R0P1:
+		return OMAP4430_ES1_0;
+	case MIDR_CORTEX_A9_R1P2:
+		return OMAP4430_ES2_0;
+	default:
+		return OMAP4430_SILICON_ID_INVALID;
+	}
+}

index a30bb33..1f88732 100644
@@ -51,6 +51,11 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* CONTROL_ID_CODE */
+#define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
+
+#define OMAP4_CONTROL_ID_CODE_ES2_1	0x3B95C02F
+#define OMAP4_CONTROL_ID_CODE_ES2_2	0x4B95C02F
 /* UART */
 #define UART1_BASE		(OMAP44XX_L4_PER_BASE + 0x6a000)
 #define UART2_BASE		(OMAP44XX_L4_PER_BASE + 0x6c000)

@@ -121,11 +126,11 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
-/*
- * OMAP4 real hardware:
- * TODO: Change this to the IDCODE in the hw regsiter
- */
-#define CPU_OMAP4430_ES10	1
-#define CPU_OMAP4430_ES20	2
+/* Silicon revisions */
+#define OMAP4430_SILICON_ID_INVALID	0
+#define OMAP4430_ES1_0	1
+#define OMAP4430_ES2_0	2
+#define OMAP4430_ES2_1	3
+#define OMAP4430_ES2_2	4
 
 #endif

new file mode 100644
index 0000000..6c24a80
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Aneesh V <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef ARMV7_H
+#define ARMV7_H
+
+#define MIDR_CORTEX_A9_R0P1	0x410FC091
+#define MIDR_CORTEX_A9_R1P2	0x411FC092
+
+#endif /* ARMV7_H */

index a01e0d6..54533fc 100644
@@ -41,6 +41,13 @@
 
 static void cache_flush(void);
 
+void save_boot_params_default(u32 r0, u32 r1, u32 r2, u32 r3)
+{
+}
+
+void save_boot_params(u32 r0, u32 r1, u32 r2, u32 r3)
+	__attribute__((weak, alias("save_boot_params_default")));
+
 int cleanup_before_linux(void)
 {
 	unsigned int i;

index 7583a0d..a5d585b 100644
@@ -35,6 +35,20 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_PRELOADER
+u32 omap4_boot_device = BOOT_DEVICE_MMC1;
+u32 omap4_boot_mode = MMCSD_MODE_FAT;
+u32 omap_boot_device(void)
+{
+	return omap4_boot_device;
+}
+
+u32 omap_boot_mode(void)
+{
+	return omap4_boot_mode;
+}
+#endif
+
 /*
  * Routine: s_init
  * Description: Does early system init of muxing and clocks.

index 1f88732..740ca9d 100644
@@ -133,4 +133,12 @@ struct s32ktimer {
 #define OMAP4430_ES2_1	3
 #define OMAP4430_ES2_2	4
 
+/* ROM code defines */
+/* Boot device */
+#define BOOT_DEVICE_MASK	0xFF
+#define BOOT_DEVICE_OFFSET	0x8
+#define DEV_DESC_PTR_OFFSET	0x4
+#define DEV_DATA_PTR_OFFSET	0x18
+#define BOOT_MODE_OFFSET	0x8
+
 #endif

index 4813e9e..ce86b36 100644
@@ -23,6 +23,7 @@
 
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
+#include <asm/omap_common.h>
 
 struct omap_sysinfo {
 	char *board_string;

index 03db2f5..06c511c 100644
@@ -48,4 +48,24 @@
 		       (addr));\
 	} while (0);
 
+/* Boot device */
+#define BOOT_DEVICE_NONE	0
+#define BOOT_DEVICE_XIP		1
+#define BOOT_DEVICE_XIPWAIT	2
+#define BOOT_DEVICE_NAND	3
+#define BOOT_DEVICE_ONE_NAND	4
+#define BOOT_DEVICE_MMC1	5
+#define BOOT_DEVICE_MMC2	6
+
+/* Boot type */
+#define	MMCSD_MODE_UNDEFINED	0
+#define MMCSD_MODE_RAW		1
+#define MMCSD_MODE_FAT		2
+
+/* Magic number passed from SPL to U-Boot */
+#define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
+
+u32 omap_boot_device(void);
+u32 omap_boot_mode(void);
+
 #endif /* _OMAP_COMMON_H_ */

index 2a84d27..2ce020e 100644
@@ -89,6 +89,11 @@ typedef	struct	global_data {
 #define GD_FLG_DISABLE_CONSOLE	0x00040	/* Disable console (in & out)		*/
 #define GD_FLG_ENV_READY	0x00080	/* Environment imported into hash table	*/
 
+#ifdef CONFIG_PRELOADER
+/* SPL works from internal RAM. gd pointer can be in .data section */
+#define DECLARE_GLOBAL_DATA_PTR     extern gd_t *gd
+#else
 #define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("r8")
+#endif
 
 #endif /* __ASM_GBL_DATA_H */

new file mode 100644
index 0000000..0e08f4f
@@ -0,0 +1,47 @@
+/*
+ *
+ * Clock initialization for OMAP4
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Aneesh V <[email protected]>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/u-boot.h>
+#include <asm/arch/sys_proto.h>
+#include <timestamp_autogenerated.h>
+
+/* Define global data structure pointer to it*/
+gd_t gdata __attribute__ ((section(".data")));
+bd_t bdata __attribute__ ((section(".data")));
+gd_t *gd = &gdata;
+
+void board_init_f(ulong dummy)
+{
+	relocate_code(CONFIG_SYS_SPL_STACK, &gdata, CONFIG_SYS_SPL_TEXT_BASE);
+}
+
+void board_init_r(gd_t *id, ulong dummy)
+{
+	for (;;)
+		;
+}

index 9a8bb73..5b20841 100644
@@ -122,7 +122,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */

@@ -240,4 +242,21 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */

index a5d585b..da79669 100644
@@ -57,6 +57,9 @@ u32 omap_boot_mode(void)
 void s_init(void)
 {
 	watchdog_init();
+#ifdef CONFIG_PRELOADER
+	preloader_console_init();
+#endif
 }
 
 /*

index 06c511c..95116f4 100644
@@ -67,5 +67,6 @@
 
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
+void preloader_console_init(void);
 
 #endif /* _OMAP_COMMON_H_ */

index 0e08f4f..57ddb7d 100644
@@ -45,3 +45,13 @@ void board_init_r(gd_t *id, ulong dummy)
 	for (;;)
 		;
 }
+
+void preloader_console_init(void)
+{
+	gd->bd = &bdata;
+	gd->flags |= GD_FLG_RELOC;
+	gd->baudrate = CONFIG_BAUDRATE;
+	serial_init();		/* serial communications setup */
+	printf("\nU-Boot SPL for Texas Instruments OMAP4 (%s - %s)\n",
+		U_BOOT_DATE, U_BOOT_TIME);
+}

index ce86b36..19da2e1 100644
@@ -38,6 +38,53 @@ void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
 
+static inline u32 running_from_sdram(void)
+{
+	u32 pc;
+	asm volatile ("mov %0, pc" : "=r" (pc));
+	return ((pc >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
+	    (pc < OMAP44XX_DRAM_ADDR_SPACE_END));
+}
+
+static inline u8 uboot_loaded_by_spl(void)
+{
+	/*
+	 * Configuration Header is not supported yet, so u-boot init running
+	 * from SDRAM implies that it was loaded by SPL. When this situation
+	 * changes one of these approaches could be taken:
+	 * i.  Pass a magic from SPL to U-Boot and U-Boot save it at a known
+	 *     location.
+	 * ii. Check the OPP. CH can support only 50% OPP while SPL initializes
+	 *     the DPLLs@100% OPP.
+	 */
+	return running_from_sdram();
+}
+/*
+ * The basic hardware init of OMAP(s_init()) can happen in 4
+ * different contexts:
+ *  1. SPL running from SRAM
+ *  2. U-Boot running from FLASH
+ *  3. Non-XIP U-Boot loaded to SDRAM by SPL
+ *  4. Non-XIP U-Boot loaded to SDRAM by ROM code using the
+ *     Configuration Header feature
+ *
+ * This function finds this context.
+ * Defining as inline may help in compiling out unused functions in SPL
+ */
+static inline u32 omap4_hw_init_context(void)
+{
+#ifdef CONFIG_PRELOADER
+	return OMAP_INIT_CONTEXT_SPL;
+#else
+	if (uboot_loaded_by_spl())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL;
+	else if (running_from_sdram())
+		return OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH;
+	else
+		return OMAP_INIT_CONTEXT_XIP_UBOOT;
+#endif
+}
+
 extern const struct omap_sysinfo sysinfo;
 
 #endif

index 95116f4..50247af 100644
@@ -65,6 +65,12 @@
 /* Magic number passed from SPL to U-Boot */
 #define OMAP_SPL_TO_UBOOT_MAGIC_NUMBER	0xDEADBEEF
 
+/* HW Init Context */
+#define OMAP_INIT_CONTEXT_SPL			0
+#define OMAP_INIT_CONTEXT_XIP_UBOOT		1
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL	2
+#define OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH	3
+
 u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 void preloader_console_init(void);

index da79669..95b6a96 100644
@@ -32,9 +32,30 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+{
+	int i;
+	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
+
+	for (i = 0; i < size; i++, pad++)
+		writew(pad->val, base + pad->offset);
+}
+
+static void set_muxconf_regs_essential(void)
+{
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential,
+		   sizeof(core_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
+		   sizeof(wkup_padconf_array_essential) /
+		   sizeof(struct pad_conf_entry));
+}
+
 #ifdef CONFIG_PRELOADER
 u32 omap4_boot_device = BOOT_DEVICE_MMC1;
 u32 omap4_boot_mode = MMCSD_MODE_FAT;

@@ -49,14 +70,41 @@ u32 omap_boot_mode(void)
 }
 #endif
 
+static void set_mux_conf_regs(void)
+{
+	switch (omap4_hw_init_context()) {
+	case OMAP_INIT_CONTEXT_SPL:
+		set_muxconf_regs_essential();
+		break;
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_SPL:
+		set_muxconf_regs_non_essential();
+		break;
+	case OMAP_INIT_CONTEXT_XIP_UBOOT:
+	case OMAP_INIT_CONTEXT_UBOOT_LOADED_BY_CH:
+		set_muxconf_regs_essential();
+		set_muxconf_regs_non_essential();
+		break;
+	}
+}
+
 /*
  * Routine: s_init
- * Description: Does early system init of muxing and clocks.
- *              - Called path is with SRAM stack.
+ * Description: Does early system init of watchdog, muxing, clocks, and
+ * sdram. Watchdog disable is done always. For the rest what gets done
+ * depends on the boot mode in which this function is executed
+ *   1. s_init of SPL running from SRAM
+ *   2. s_init of U-Boot running from FLASH
+ *   3. s_init of U-Boot loaded to SDRAM by SPL
+ *   4. s_init of U-Boot loaded to SDRAM by ROM code using the Configuration
+ *	Header feature
+ * Please have a look at the respective functions to see what gets done in
+ * each of these cases
+ * This function is called with SRAM stack.
  */
 void s_init(void)
 {
 	watchdog_init();
+	set_mux_conf_regs();
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif

@@ -142,7 +190,6 @@ int checkboard(void)
 */
 int arch_cpu_init(void)
 {
-	set_muxconf_regs();
 	return 0;
 }
 

76 lines not on this page · raw message

index 19da2e1..33a1666 100644
@@ -24,6 +24,7 @@
 #include <asm/arch/omap4.h>
 #include <asm/io.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mux_omap4.h>
 
 struct omap_sysinfo {
 	char *board_string;

@@ -33,7 +34,8 @@ void gpmc_init(void);
 void watchdog_init(void);
 u32 get_device_type(void);
 void invalidate_dcache(u32);
-void set_muxconf_regs(void);
+void do_set_mux(u32 base, struct pad_conf_entry const *array, int size);
+void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);

index 78e1910..9afed80 100644
@@ -25,7 +25,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "panda.h"
+#include "panda_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -65,27 +65,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 

99 lines not on this page · raw message

index b13c4c5..a5ea682 100644
@@ -27,7 +27,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mmc_host_def.h>
 
-#include "sdp.h"
+#include "sdp4430_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 

@@ -70,27 +70,14 @@ int misc_init_r(void)
 	return 0;
 }
 
-void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
+void set_muxconf_regs_non_essential(void)
 {
-	int i;
-	struct pad_conf_entry *pad = (struct pad_conf_entry *) array;
-
-	for (i = 0; i < size; i++, pad++)
-		writew(pad->val, base + pad->offset);
-}
-
-/**
- * @brief set_muxconf_regs Setting up the configuration Mux registers
- * specific to the board.
- */
-void set_muxconf_regs(void)
-{
-	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array,
-		   sizeof(core_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_non_essential,
+		   sizeof(core_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 
-	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array,
-		   sizeof(wkup_padconf_array) /
+	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_non_essential,
+		   sizeof(wkup_padconf_array_non_essential) /
 		   sizeof(struct pad_conf_entry));
 }
 

100 lines not on this page · raw message

index 8bb7fe5..16cc0ad 100644
@@ -23,11 +23,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#ifndef _SDP4430_MUX_DATA_H
+#define _SDP4430_MUX_DATA_H
 
-#ifndef _PANDA_MUX_DATA_H_
-#define _PANDA_MUX_DATA_H_
-
-#include <asm/io.h>
 #include <asm/arch/mux_omap4.h>
 
 const struct pad_conf_entry core_padconf_array_non_essential[] = {

@@ -45,7 +43,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_A19, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row7 */
 	{GPMC_A20, (IEN | M3)},						/* gpio_44 */
 	{GPMC_A21, (M3)},						/* gpio_45 */
-	{GPMC_A22, (M3)},						/* gpio_46 */
+	{GPMC_A22, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col6 */
 	{GPMC_A23, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col7 */
 	{GPMC_A24, (PTD | M3)},						/* gpio_48 */
 	{GPMC_A25, (PTD | M3)},						/* gpio_49 */

@@ -59,9 +57,9 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{GPMC_NBE0_CLE, (M3)},						/* gpio_59 */
 	{GPMC_NBE1, (PTD | M3)},					/* gpio_60 */
 	{GPMC_WAIT0, (PTU | IEN | M3)},					/* gpio_61 */
-	{GPMC_WAIT1,  (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_62 */
+	{GPMC_WAIT1, (IEN | M3)},					/* gpio_62 */
 	{C2C_DATA11, (PTD | M3)},					/* gpio_100 */
-	{C2C_DATA12, (PTU | IEN | M3)},					/* gpio_101 */
+	{C2C_DATA12, (M1)},						/* dsi1_te0 */
 	{C2C_DATA13, (PTD | M3)},					/* gpio_102 */
 	{C2C_DATA14, (M1)},						/* dsi2_te0 */
 	{C2C_DATA15, (PTD | M3)},					/* gpio_104 */

@@ -86,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */

@@ -106,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */

@@ -143,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */

@@ -157,12 +155,12 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBB2_ULPITLL_DAT7, (IEN | M5)},				/* dispc2_data11 */
 	{USBB2_HSIC_DATA, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_169 */
 	{USBB2_HSIC_STROBE, (PTD | OFF_EN | OFF_OUT_PTU | M3)},		/* gpio_170 */
-	{UNIPRO_TX0, (PTD | IEN | M3)},					/* gpio_171 */
+	{UNIPRO_TX0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col0 */
 	{UNIPRO_TY0, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col1 */
 	{UNIPRO_TX1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col2 */
 	{UNIPRO_TY1, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col3 */
-	{UNIPRO_TX2, (PTU | IEN | M3)},					/* gpio_0 */
-	{UNIPRO_TY2, (PTU | IEN | M3)},					/* gpio_1 */
+	{UNIPRO_TX2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col4 */
+	{UNIPRO_TY2, (OFF_EN | OFF_PD | OFF_IN | M1)},			/* kpd_col5 */
 	{UNIPRO_RX0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row0 */
 	{UNIPRO_RY0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row1 */
 	{UNIPRO_RX1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)},	/* kpd_row2 */

@@ -173,13 +171,13 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{USBA0_OTG_DP, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dp */
 	{USBA0_OTG_DM, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},		/* usba0_otg_dm */
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
-	{FREF_CLK2_OUT, (PTU | IEN | M3)},				/* gpio_182 */
+	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */

@@ -205,25 +203,28 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 };
 
 const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
-	{PAD0_SIM_IO, (IEN | M0)},					/* sim_io */
-	{PAD1_SIM_CLK, (M0)},						/* sim_clk */
-	{PAD0_SIM_RESET, (M0)},						/* sim_reset */
-	{PAD1_SIM_CD, (PTU | IEN | M0)},				/* sim_cd */
-	{PAD0_SIM_PWRCTRL, (M0)},					/* sim_pwrctrl */
-	{PAD1_FREF_XTAL_IN, (M0)},					/* # */
-	{PAD0_FREF_SLICER_IN, (M0)},					/* fref_slicer_in */
-	{PAD1_FREF_CLK_IOREQ, (M0)},					/* fref_clk_ioreq */
-	{PAD0_FREF_CLK0_OUT, (M2)},					/* sys_drm_msecure */
-	{PAD1_FREF_CLK3_REQ, (M3)},					/* gpio_wk30 */
-	{PAD0_FREF_CLK3_OUT, (M0)},					/* fref_clk3_out */
-	{PAD1_FREF_CLK4_REQ, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_1 */
-	{PAD0_FREF_CLK4_OUT, (PTU | OFF_EN | OFF_OUT_PTU | M3)},	/* led status_2 */
-	{PAD0_SYS_NRESPWRON, (M0)},					/* sys_nrespwron */
-	{PAD1_SYS_NRESWARM, (M0)},					/* sys_nreswarm */
-	{PAD0_SYS_PWR_REQ, (PTU | M0)},					/* sys_pwr_req */
-	{PAD1_SYS_PWRON_RESET, (M3)},					/* gpio_wk29 */
-	{PAD0_SYS_BOOT6, (IEN | M3)},					/* gpio_wk9 */
-	{PAD1_SYS_BOOT7, (IEN | M3)},					/* gpio_wk10 */
+	{PAD0_SIM_IO, (IEN | M0)},		/* sim_io */
+	{PAD1_SIM_CLK, (M0)},			/* sim_clk */
+	{PAD0_SIM_RESET, (M0)},			/* sim_reset */
+	{PAD1_SIM_CD, (PTU | IEN | M0)},	/* sim_cd */
+	{PAD0_SIM_PWRCTRL, (M0)},		/* sim_pwrctrl */
+	{PAD1_FREF_XTAL_IN, (M0)},		/* # */
+	{PAD0_FREF_SLICER_IN, (M0)},		/* fref_slicer_in */
+	{PAD1_FREF_CLK_IOREQ, (M0)},		/* fref_clk_ioreq */
+	{PAD0_FREF_CLK0_OUT, (M2)},		/* sys_drm_msecure */
+	{PAD1_FREF_CLK3_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK3_OUT, (M0)},		/* fref_clk3_out */
+	{PAD1_FREF_CLK4_REQ, (PTU | IEN | M0)},	/* # */
+	{PAD0_FREF_CLK4_OUT, (M0)},		/* # */
+	{PAD0_SYS_NRESPWRON, (M0)},		/* sys_nrespwron */
+	{PAD1_SYS_NRESWARM, (M0)},		/* sys_nreswarm */
+	{PAD0_SYS_PWR_REQ, (PTU | M0)},		/* sys_pwr_req */
+	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
+	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
+	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
-#endif /* _PANDA_MUX_DATA_H_ */
+#endif /* _SDP4430_MUX_DATA_H */

index e6081dc..16cc0ad 100644
@@ -84,14 +84,14 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{CAM_SHUTTER, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_shutter */
 	{CAM_STROBE, (OFF_EN | OFF_PD | OFF_OUT_PTD | M0)},		/* cam_strobe */
 	{CAM_GLOBALRESET, (PTD | OFF_EN | OFF_PD | OFF_OUT_PTD | M3)},	/* gpio_83 */
-	{USBB1_ULPITLL_CLK, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M4)},/* usbb1_ulpiphy_clk */
-	{USBB1_ULPITLL_STP, (OFF_EN | OFF_OUT_PTD | M4)},		/* usbb1_ulpiphy_stp */
-	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dir */
-	{USBB1_ULPITLL_NXT, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_nxt */
-	{USBB1_ULPITLL_DAT0, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat0 */
-	{USBB1_ULPITLL_DAT1, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat1 */
-	{USBB1_ULPITLL_DAT2, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat2 */
-	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat3 */
+	{USBB1_ULPITLL_CLK, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cawake */
+	{USBB1_ULPITLL_STP, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_cadata */
+	{USBB1_ULPITLL_DIR, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caflag */
+	{USBB1_ULPITLL_NXT, (OFF_EN | M1)},				/* hsi1_acready */
+	{USBB1_ULPITLL_DAT0, (OFF_EN | M1)},				/* hsi1_acwake */
+	{USBB1_ULPITLL_DAT1, (OFF_EN | M1)},				/* hsi1_acdata */
+	{USBB1_ULPITLL_DAT2, (OFF_EN | M1)},				/* hsi1_acflag */
+	{USBB1_ULPITLL_DAT3, (IEN | OFF_EN | OFF_IN | M1)},		/* hsi1_caready */
 	{USBB1_ULPITLL_DAT4, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat4 */
 	{USBB1_ULPITLL_DAT5, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat5 */
 	{USBB1_ULPITLL_DAT6, (IEN | OFF_EN | OFF_PD | OFF_IN | M4)},	/* usbb1_ulpiphy_dat6 */

@@ -104,8 +104,8 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{ABE_MCBSP2_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp2_dr */
 	{ABE_MCBSP2_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp2_dx */
 	{ABE_MCBSP2_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp2_fsx */
-	{ABE_MCBSP1_CLKX, (IEN | M1)},					/* abe_slimbus1_clock */
-	{ABE_MCBSP1_DR, (IEN | M1)},					/* abe_slimbus1_data */
+	{ABE_MCBSP1_CLKX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_clkx */
+	{ABE_MCBSP1_DR, (IEN | OFF_EN | OFF_OUT_PTD | M0)},		/* abe_mcbsp1_dr */
 	{ABE_MCBSP1_DX, (OFF_EN | OFF_OUT_PTD | M0)},			/* abe_mcbsp1_dx */
 	{ABE_MCBSP1_FSX, (IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_mcbsp1_fsx */
 	{ABE_PDM_UL_DATA, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* abe_pdm_ul_data */

@@ -141,7 +141,7 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{MCSPI4_CS0, (PTD | IEN | OFF_EN | OFF_PD | OFF_IN | M0)},	/* mcspi4_cs0 */
 	{UART4_RX, (IEN | M0)},						/* uart4_rx */
 	{UART4_TX, (M0)},						/* uart4_tx */
-	{USBB2_ULPITLL_CLK, (IEN | M3)},				/* gpio_157 */
+	{USBB2_ULPITLL_CLK, (PTD | IEN | M3)},				/* gpio_157 */
 	{USBB2_ULPITLL_STP, (IEN | M5)},				/* dispc2_data23 */
 	{USBB2_ULPITLL_DIR, (IEN | M5)},				/* dispc2_data22 */
 	{USBB2_ULPITLL_NXT, (IEN | M5)},				/* dispc2_data21 */

@@ -173,11 +173,11 @@ const struct pad_conf_entry core_padconf_array_non_essential[] = {
 	{FREF_CLK1_OUT, (M0)},						/* fref_clk1_out */
 	{FREF_CLK2_OUT, (M0)},						/* fref_clk2_out */
 	{SYS_NIRQ1, (PTU | IEN | M0)},					/* sys_nirq1 */
-	{SYS_NIRQ2, (PTU | IEN | M0)},					/* sys_nirq2 */
+	{SYS_NIRQ2, (M7)},						/* sys_nirq2 */
 	{SYS_BOOT0, (PTU | IEN | M3)},					/* gpio_184 */
 	{SYS_BOOT1, (M3)},						/* gpio_185 */
 	{SYS_BOOT2, (PTD | IEN | M3)},					/* gpio_186 */
-	{SYS_BOOT3, (M3)},						/* gpio_187 */
+	{SYS_BOOT3, (PTD | IEN | M3)},					/* gpio_187 */
 	{SYS_BOOT4, (M3)},						/* gpio_188 */
 	{SYS_BOOT5, (PTD | IEN | M3)},					/* gpio_189 */
 	{DPM_EMU0, (IEN | M0)},						/* dpm_emu0 */

@@ -222,6 +222,9 @@ const struct pad_conf_entry wkup_padconf_array_non_essential[] = {
 	{PAD1_SYS_PWRON_RESET, (M3)},		/* gpio_wk29 */
 	{PAD0_SYS_BOOT6, (IEN | M3)},		/* gpio_wk9 */
 	{PAD1_SYS_BOOT7, (IEN | M3)},		/* gpio_wk10 */
+	{PAD1_FREF_CLK3_REQ, (M3)},		/* gpio_wk30 */
+	{PAD1_FREF_CLK4_REQ, (M3)},		/* gpio_wk7 */
+	{PAD0_FREF_CLK4_OUT, (M3)},		/* gpio_wk8 */
 };
 
 #endif /* _SDP4430_MUX_DATA_H */

index 95b6a96..62a59ad 100644
@@ -105,6 +105,7 @@ void s_init(void)
 {
 	watchdog_init();
 	set_mux_conf_regs();
+	prcm_init();
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif

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index 33a1666..fd21afd 100644
@@ -39,6 +39,12 @@ void set_muxconf_regs_non_essential(void);
 void sr32(void *, u32, u32, u32);
 u32 wait_on_value(u32, u32, void *, u32);
 void sdelay(unsigned long);
+void prcm_init(void);
+void bypass_dpll(u32 base);
+void freq_update_core(void);
+u32 get_syc_clk_freq(void);
+u32 omap4_ddr_clk(void);
+u32 omap4_revision(void);
 
 static inline u32 running_from_sdram(void)
 {

index 50247af..49daa85 100644
@@ -25,6 +25,9 @@
 #ifndef	_OMAP_COMMON_H_
 #define	_OMAP_COMMON_H_
 
+/* Max value for DPLL multiplier M */
+#define OMAP_DPLL_MAX_N	127
+
 /* extract a bit field from a bit vector */
 #define get_bit_field(nr, start, mask)\
 	(((nr) & (mask)) >> (start))

index 62a59ad..89b1213 100644
@@ -109,6 +109,7 @@ void s_init(void)
 #ifdef CONFIG_PRELOADER
 	preloader_console_init();
 #endif
+	sdram_init();
 }
 
 /*

@@ -169,7 +170,6 @@ u32 sdram_size(void)
  */
 int dram_init(void)
 {
-
 	gd->ram_size = sdram_size();
 
 	return 0;

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index 740ca9d..a1c4883 100644
@@ -51,6 +51,17 @@
 #define CONTROL_PADCONF_CORE	(OMAP44XX_L4_CORE_BASE + 0x100000)
 #define CONTROL_PADCONF_WKUP	(OMAP44XX_L4_CORE_BASE + 0x31E000)
 
+/* LPDDR2 IO regs */
+#define CONTROL_LPDDR2IO1_0	(CONTROL_PADCONF_CORE + 0x0638)
+#define CONTROL_LPDDR2IO1_1	(CONTROL_PADCONF_CORE + 0x063C)
+#define CONTROL_LPDDR2IO1_2	(CONTROL_PADCONF_CORE + 0x0640)
+#define CONTROL_LPDDR2IO1_3	(CONTROL_PADCONF_CORE + 0x0644)
+#define CONTROL_LPDDR2IO2_0	(CONTROL_PADCONF_CORE + 0x0648)
+#define CONTROL_LPDDR2IO2_1	(CONTROL_PADCONF_CORE + 0x064C)
+#define CONTROL_LPDDR2IO2_2	(CONTROL_PADCONF_CORE + 0x0650)
+#define CONTROL_LPDDR2IO2_3	(CONTROL_PADCONF_CORE + 0x0654)
+#define CONTROL_EFUSE_2		(CONTROL_PADCONF_CORE + 0x0704)
+
 /* CONTROL_ID_CODE */
 #define CONTROL_ID_CODE		(CTRL_BASE + 0x204)
 

index fd21afd..4beff42 100644
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_syc_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void sdram_init(void);
 u32 omap4_revision(void);
 
 static inline u32 running_from_sdram(void)

index 5b20841..07d45a0 100644
@@ -245,11 +245,6 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
-/* Defines for SDRAM init */
-#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
-#define CONFIG_SYS_EMIF_UPDATE_TIMINGS		1
-#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
-
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304360

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index 89b1213..925601d 100644
@@ -32,6 +32,7 @@
 #include <asm/arch/cpu.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
+#include <asm/arch/emif.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;

@@ -148,13 +149,13 @@ u32 sdram_size(void)
 {
 	u32 section, i, total_size = 0, size, addr;
 	for (i = 0; i < 4; i++) {
-		section	= __raw_readl(DMM_LISA_MAP_BASE + i*4);
-		addr = section & DMM_LISA_MAP_SYS_ADDR_MASK;
+		section	= __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4);
+		addr = section & OMAP44XX_SYS_ADDR_MASK;
 		/* See if the address is valid */
 		if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) &&
 		    (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) {
-			size	= ((section & DMM_LISA_MAP_SYS_SIZE_MASK) >>
-				    DMM_LISA_MAP_SYS_SIZE_SHIFT);
+			size	= ((section & OMAP44XX_SYS_SIZE_MASK) >>
+				   OMAP44XX_SYS_SIZE_SHIFT);
 			size	= 1 << size;
 			size	*= SZ_16M;
 			total_size += size;

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index a1c4883..fd8fb10 100644
@@ -86,12 +86,7 @@
 /* GPMC */
 #define OMAP44XX_GPMC_BASE	0x50000000
 
-/* DMM */
-#define OMAP44XX_DMM_BASE		0x4E000000
-#define DMM_LISA_MAP_BASE		(OMAP44XX_DMM_BASE + 0x40)
-#define DMM_LISA_MAP_SYS_SIZE_MASK	(7 << 20)
-#define DMM_LISA_MAP_SYS_SIZE_SHIFT	20
-#define DMM_LISA_MAP_SYS_ADDR_MASK	(0xFF << 24)
+
 /*
  * Hardware Register Details
  */

@@ -137,6 +132,17 @@ struct s32ktimer {
 /* Temporary SRAM stack used while low level init is done */
 #define LOW_LEVEL_SRAM_STACK	NON_SECURE_SRAM_END
 
+#define SRAM_SCRATCH_SPACE_ADDR		NON_SECURE_SRAM_START
+
+/*
+ * SRAM scratch space entries
+ */
+
+/* Boot parameter passed from SPL to U-Boot */
+#define OMAP4_SRAM_SCRATCH_EMIF_SIZE	SRAM_SCRATCH_SPACE_ADDR
+#define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0x8)
+#define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
+
 /* Silicon revisions */
 #define OMAP4430_SILICON_ID_INVALID	0
 #define OMAP4430_ES1_0	1

index 4beff42..211d3b8 100644
@@ -44,6 +44,7 @@ void bypass_dpll(u32 base);
 void freq_update_core(void);
 u32 get_syc_clk_freq(void);
 u32 omap4_ddr_clk(void);
+void cancel_out(u32 *num, u32 *den, u32 den_limit);
 void sdram_init(void);
 u32 omap4_revision(void);
 

index 49daa85..9f2616c 100644
@@ -51,6 +51,27 @@
 		       (addr));\
 	} while (0);
 
+/* find log2 of number n - rounded up */
+static inline u32 log_2_n_round_up(u32 n)
+{
+	u32 clz;
+	/* count leading zeros */
+	asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n));
+	if (n & (n - 1))
+		return 31 - clz; /* power of 2 */
+	else
+		return 32 - clz; /* not power of 2 - round up */
+}
+
+/* find log2 of number n - rounded down */
+static inline u32 log_2_n_round_down(u32 n)
+{
+	u32 clz;
+	/* count leading zeros */
+	asm volatile ("CLZ %0, %1" : "=r" (clz) : "r" (n));
+	return 31 - clz;
+}
+
 /* Boot device */
 #define BOOT_DEVICE_NONE	0
 #define BOOT_DEVICE_XIP		1

index 07d45a0..c29b184 100644
@@ -245,6 +245,11 @@
 /* Defines for Clock init */
 #define CONFIG_SYS_OMAP4_ABE_SYSCK
 
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
 /* Defines for SPL */
 #define CONFIG_SPL
 #define CONFIG_SYS_SPL_TEXT_BASE	0x40304360

index 1bdb1d2..006d065 100644
@@ -165,7 +165,8 @@ static const struct lpddr2_min_tck min_tck_jedec = {
 	.tFAW = 8
 };
 
-static const struct lpddr2_ac_timings *jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
+static const struct lpddr2_ac_timings const*
+			jedec_ac_timings[MAX_NUM_SPEEDBINS] = {
 	&timings_jedec_200_mhz,
 	&timings_jedec_333_mhz,
 	&timings_jedec_400_mhz

@@ -779,6 +780,146 @@ void emif_reset_phy(u32 base)
 	writel(iodft, &emif->emif_iodft_tlgc);
 }
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+static void display_sdram_details(u32 emif_nr, u32 cs,
+				  struct lpddr2_device_details *device)
+{
+	const char *mfg_str;
+	const char *type_str;
+	char density_str[10];
+	u32 density;
+
+	debug("EMIF%d CS%d\t", emif_nr, cs);
+
+	if (!device) {
+		debug("None\n");
+		return;
+	}
+
+	mfg_str = get_lpddr2_manufacturer(device->manufacturer);
+	type_str = get_lpddr2_type(device->type);
+
+	density = lpddr2_density_2_size_in_mbytes[device->density];
+	if ((density / 1024 * 1024) == density) {
+		density /= 1024;
+		sprintf(density_str, "%d GB", density);
+	} else
+		sprintf(density_str, "%d MB", density);
+	if (mfg_str && type_str)
+		debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
+}
+
+static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
+				  struct lpddr2_device_details *lpddr2_device)
+{
+	u32 mr = 0, temp;
+
+	mr = get_mr(base, cs, LPDDR2_MR0);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, LPDDR2_MR0_DI_SHIFT, LPDDR2_MR0_DI_MASK);
+	if (temp) {
+		/* Not SDRAM */
+		return 0;
+	}
+	temp = get_bit_field(mr, LPDDR2_MR0_DNVI_SHIFT, LPDDR2_MR0_DNVI_MASK);
+
+	if (temp) {
+		/* DNV supported - But DNV is only supported for NVM */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR4);
+	if (mr > 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR5);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	if (!get_lpddr2_manufacturer(mr)) {
+		/* Manufacturer not identified */
+		return 0;
+	}
+	lpddr2_device->manufacturer = mr;
+
+	mr = get_mr(base, cs, LPDDR2_MR6);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR7);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	mr = get_mr(base, cs, LPDDR2_MR8);
+	if (mr >= 0xFF) {
+		/* Mode register value bigger than 8 bit */
+		return 0;
+	}
+
+	temp = get_bit_field(mr, MR8_TYPE_SHIFT, MR8_TYPE_MASK);
+	if (!get_lpddr2_type(temp)) {
+		/* Not SDRAM */
+		return 0;
+	}
+	lpddr2_device->type = temp;
+
+	temp = get_bit_field(mr, MR8_DENSITY_SHIFT, MR8_DENSITY_MASK);
+	if (temp > LPDDR2_DENSITY_32Gb) {
+		/* Density not supported */
+		return 0;
+	}
+	lpddr2_device->density = temp;
+
+	temp = get_bit_field(mr, MR8_IO_WIDTH_SHIFT, MR8_IO_WIDTH_MASK);
+	if (!get_lpddr2_io_width(temp)) {
+		/* IO width unsupported value */
+		return 0;
+	}
+	lpddr2_device->io_width = temp;
+
+	/*
+	 * If all the above tests pass we should
+	 * have a device on this chip-select
+	 */
+	return 1;
+}
+
+static struct lpddr2_device_details *get_lpddr2_details(u32 base, u8 cs,
+			struct lpddr2_device_details *lpddr2_dev_details)
+{
+	u32 phy;
+	struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+	if (!lpddr2_dev_details)
+		return NULL;
+
+	/* Do the minimum init for mode register accesses */
+	if (!running_from_sdram()) {
+		phy = get_ddr_phy_ctrl_1(get_syc_clk_freq() / 2, RL_BOOT);
+		writel(phy, &emif->emif_ddr_phy_ctrl_1);
+	}
+
+	if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
+		return NULL;
+
+	display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
+
+	return lpddr2_dev_details;
+}
+#endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
+
 static void do_lpddr2_init(u32 base, u32 cs)
 {
 	u32 mr_addr;

@@ -862,9 +1003,7 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 
 static void do_sdram_init(u32 base)
 {
-	struct emif_device_details dev_details;
 	const struct emif_regs *regs;
-
 	u32 in_sdram, emif_nr;
 
 	in_sdram = running_from_sdram();

@@ -872,6 +1011,7 @@ static void do_sdram_init(u32 base)
 
 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 	const struct emif_regs *tmp_regs;
+
 	emif_get_reg_dump(&regs, &tmp_regs);
 	regs = (emif_nr == 1) ? regs : tmp_regs;
 #else

@@ -879,23 +1019,48 @@ static void do_sdram_init(u32 base)
 	 * The user has not provided the register values. We need to
 	 * calculate it based on the timings and the DDR frequency
 	 */
+	struct emif_device_details dev_details = { NULL, NULL };
+	struct emif_regs calculated_regs;
 
+#if !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
+
+	/* We need some input about the devices from the user */
 	const struct emif_device_details *dev_details_user_provided;
 	const struct emif_device_details *tmp_details;
-	struct emif_regs calculated_regs;
 
-	/* We need some input about the devices from the user */
 	emif_get_device_details(&dev_details_user_provided, &tmp_details);
 	dev_details_user_provided = (emif_nr == 1) ? dev_details_user_provided
 						   : tmp_details;
 	if (!dev_details_user_provided)
 		return;
+#endif
 
+#ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
+	struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+
+	/* Automatically find the device details */
+	if (!in_sdram) {
+		dev_details.cs0_device_details =
+		    get_lpddr2_details(base, CS0, &cs0_dev_details);
+		dev_details.cs1_device_details =
+		    get_lpddr2_details(base, CS1, &cs1_dev_details);
+		/*
+		 * Reset the PHY - if there is nothing connected on any
+		 * of the chip selects(typically CS1) mode register reads
+		 * will mess up with the PHY state and subsequent
+		 * initialization won't work. PHY reset brings back PHY to
+		 * a good state.
+		 */
+		emif_reset_phy(base);
+	}
+#else
 	dev_details.cs0_device_details =
 			dev_details_user_provided->cs0_device_details;
 	dev_details.cs1_device_details =
 			dev_details_user_provided->cs1_device_details;
 
+#endif
 	/* Return if no devices on this EMIF */
 	if (!dev_details.cs0_device_details &&
 	    !dev_details.cs1_device_details) {

index e7d2bd5..8dfe6f9 100644
@@ -86,10 +86,8 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 	.dmm_lisa_map_3 = 0x80640300
 };
 
-void emif_get_reg_dump_sdp(const struct emif_regs **emif1_regs,
-			const struct emif_regs **emif2_regs)
-
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 	.max_freq	= 400000000,

@@ -245,7 +243,8 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 	__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 
-#else
+#elif !defined(CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION) || \
+	!defined(CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS)
 
 static void emif_get_device_details_sdp(
 			const struct emif_device_details **emif1_details,

index c29b184..a4332b7 100644
@@ -247,6 +247,7 @@
 
 /* Defines for SDRAM init */
 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
 #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
 #endif
 

index 9f2616c..c2efa7c 100644
@@ -99,4 +99,8 @@ u32 omap_boot_device(void);
 u32 omap_boot_mode(void);
 void preloader_console_init(void);
 
+/* symbols from start.S */
+extern u32 _u_boot_size;
+extern u32 _start;
+
 #endif /* _OMAP_COMMON_H_ */

index a4332b7..0ed474d 100644
@@ -257,7 +257,10 @@
 #define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
 #define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
 
-#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
-#define CONFIG_SYS_SPL_BSS_MAX_SIZE	0x80000		/* 512 KB */
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
 
 #endif /* __CONFIG_H */

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index 0ed474d..dcc9e39 100644
@@ -259,6 +259,7 @@
 
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
 
 #define CONFIG_SYS_SPL_BSS_START_ADDR		0x80000000
 #define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

index b64eac9..3612434 100644
@@ -29,6 +29,7 @@
 #include <asm/u-boot.h>
 #include <asm/arch/sys_proto.h>
 #include <mmc.h>
+#include <fat.h>
 #include <timestamp_autogenerated.h>
 #include <asm/omap_common.h>
 #include <asm/arch/mmc_host_def.h>

@@ -101,6 +102,25 @@ end:
 	}
 }
 
+static void mmc_load_uboot_fat(struct mmc *mmc)
+{
+	s32 err;
+
+	err = fat_register_device(&mmc->block_dev,
+				CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION);
+	if (err) {
+		printf("spl: fat register err - %d\n", err);
+		hang();
+	}
+
+	err = file_fat_read("u-boot.bin", (u8 *)CONFIG_SYS_TEXT_BASE, 0);
+
+	if (err <= 0) {
+		printf("spl: error reading u-boot.bin - %d\n", err);
+		hang();
+	}
+}
+
 static void mmc_load_uboot(u32 mmc_dev)
 {
 	struct mmc *mmc;

@@ -124,6 +144,8 @@ static void mmc_load_uboot(u32 mmc_dev)
 	boot_mode = omap_boot_mode();
 	if (boot_mode == MMCSD_MODE_RAW)
 		mmc_load_uboot_raw(mmc, mmc_dev);
+	else if (boot_mode == MMCSD_MODE_FAT)
+		mmc_load_uboot_fat(mmc);
 	else {
 		puts("spl: wrong MMC boot mode\n");
 		hang();

index 8cc3230..b95e545 100644
@@ -520,11 +520,11 @@
 
 /* Trap for invalid TILER PAT entries */
 #define DMM_LISA_MAP_0_INVAL_ADDR_TRAP		(\
-		(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
-		(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
-		(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
-		(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
-		(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
+	(0  << OMAP44XX_SDRC_ADDR_SHIFT) |\
+	(DMM_SDRC_MAP_EMIF1_ONLY << OMAP44XX_SDRC_MAP_SHIFT)|\
+	(DMM_SDRC_ADDR_SPC_INVALID << OMAP44XX_SDRC_ADDRSPC_SHIFT)|\
+	(DMM_SDRC_INTL_NONE << OMAP44XX_SDRC_INTL_SHIFT)|\
+	(0xFF << OMAP44XX_SYS_ADDR_SHIFT))
 
 
 /* Reg mapping structure */

index 2b03b0f..b389035 100644
@@ -117,7 +117,9 @@
 
 /* USB device configuration */
 #define CONFIG_USB_DEVICE		1
+#ifndef CONFIG_PRELOADER
 #define CONFIG_USB_TTY			1
+#endif
 #define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
 
 /* Flash */

@@ -234,4 +236,26 @@
 					 CONFIG_SYS_INIT_RAM_SIZE - \
 					 GENERATED_GBL_DATA_SIZE)
 
+/* Defines for Clock init */
+#define CONFIG_SYS_OMAP4_ABE_SYSCK
+
+/* Defines for SDRAM init */
+#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
+#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION	1
+#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS	1
+#endif
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SYS_SPL_TEXT_BASE	0x40304360
+#define CONFIG_SYS_SPL_MAX_SIZE		0x7800	/* 30 K */
+#define CONFIG_SYS_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+
+#define CONFIG_SYS_SPL_BSS_START_ADDR	0x80000000
+#define CONFIG_SYS_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */
+
 #endif /* __CONFIG_H */

index e542a57..7f6fe1c 100644
@@ -141,6 +141,7 @@ static const table_entry_t uimage_type[] = {
 	{	IH_TYPE_FLATDT,     "flat_dt",    "Flat Device Tree",	},
 	{	IH_TYPE_KWBIMAGE,   "kwbimage",   "Kirkwood Boot Image",},
 	{	IH_TYPE_IMXIMAGE,   "imximage",   "Freescale i.MX Boot Image",},
+	{	IH_TYPE_OMAPIMAGE,  "omapimage",  "TI OMAP CH/GP Boot Image",},
 	{	-1,		    "",		  "",			},
 };
 

index c31e862..c606644 100644
@@ -157,6 +157,7 @@
 #define IH_TYPE_FLATDT		8	/* Binary Flat Device Tree Blob	*/
 #define IH_TYPE_KWBIMAGE	9	/* Kirkwood Boot Image		*/
 #define IH_TYPE_IMXIMAGE	10	/* Freescale IMXBoot Image	*/
+#define IH_TYPE_OMAPIMAGE	11	/* TI OMAP Config Header Image	*/
 
 /*
  * Compression Types

index 60f7263..b6a7cb7 100644
@@ -156,6 +156,8 @@ main (int argc, char **argv)
 	init_imx_image_type ();
 	/* Init FIT image generation/list support */
 	init_fit_image_type ();
+	/* Init TI OMAP Boot image generation/list support */
+	init_omap_image_type();
 	/* Init Default image generation/list support */
 	init_default_image_type ();
 

index 9033a7d..3b49645 100644
@@ -143,5 +143,6 @@ void init_kwb_image_type (void);
 void init_imx_image_type (void);
 void init_default_image_type (void);
 void init_fit_image_type (void);
+void init_omap_image_type(void);
 
 #endif /* _MKIIMAGE_H_ */

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