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nestedsvm: Support TSC Rate MSR

PATCH New Christoph Egger 1 participant 1 message Jul 15, 2011

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Christoph Egger

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PATCH 1/1 nestedsvm: Support TSC Rate MSR

Support TSC Rate MSR and enable TSC scaling for
nested virtualization.

With it, guest VMs don't need take #VMEXIT to calculate a translated TSC value when it is running under TSC emulation mode.

I measured native performance of the rdtsc instruction in the l2 guest with xen-on-xen and both host and and l1 guest run under TSC emulation mode.

TSC scaling just needs MSR emulation and correct tsc offset calculation to be done and thus can be emulated also on older hardware. In this case rdtsc instruction is intercepted and handled by the host directly and safes the cost of a full VMRUN/VMEXIT emulation cycle.

Signed-off-by Christoph Egger <[email protected]>
Signature · 6 lines
---to satisfy European Law for business letters:
Advanced Micro Devices GmbH
Einsteinring 24, 85689 Dornach b. Muenchen
Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd
Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen
Registergericht Muenchen, HRB Nr. 43632
tools/libxc/xc_cpuid_x86.c +1 -1
diff -r 2c59b4c17c7b -r 857475b2e37c tools/libxc/xc_cpuid_x86.c
@@ -157,7 +157,7 @@ static void amd_xc_cpuid_policy(
             SVM_FEATURE_DECODEASSISTS);
 
         /* Pass 2: Always enable SVM features which are emulated */
-        regs[3] |= SVM_FEATURE_VMCBCLEAN;
+        regs[3] |= SVM_FEATURE_VMCBCLEAN | SVM_FEATURE_TSCRATEMSR;
         break;
     }
xen/arch/x86/hvm/svm/nestedsvm.c +15 -0
diff -r 2c59b4c17c7b -r 857475b2e37c xen/arch/x86/hvm/svm/nestedsvm.c
@@ -147,6 +147,8 @@ int nsvm_vcpu_reset(struct vcpu *v)
     svm->ns_msr_hsavepa = VMCX_EADDR;
     svm->ns_ovvmcb_pa = VMCX_EADDR;
 
+    svm->ns_tscratio = DEFAULT_TSC_RATIO;
+
     svm->ns_cr_intercepts = 0;
     svm->ns_dr_intercepts = 0;
     svm->ns_exception_intercepts = 0;

@@ -1185,6 +1187,9 @@ int nsvm_rdmsr(struct vcpu *v, unsigned 
     case MSR_K8_VM_HSAVE_PA:
         *msr_content = svm->ns_msr_hsavepa;
         break;
+    case MSR_AMD64_TSC_RATIO:
+        *msr_content = svm->ns_tscratio;
+        break;
     default:
         ret = 0;
         break;

@@ -1211,6 +1216,16 @@ int nsvm_wrmsr(struct vcpu *v, unsigned 
         }
         svm->ns_msr_hsavepa = msr_content;
         break;
+    case MSR_AMD64_TSC_RATIO:
+        if ((msr_content & ~TSC_RATIO_RSVD_BITS) != msr_content) {
+            gdprintk(XENLOG_ERR,
+                "reserved bits set in MSR_AMD64_TSC_RATIO 0x%"PRIx64"\n",
+                msr_content);
+            ret = -1; /* inject #GP */
+            break;
+        }
+        svm->ns_tscratio = msr_content;
+        break;
     default:
         ret = 0;
         break;
xen/arch/x86/hvm/svm/svm.c +30 -14

72 lines not on this page · raw message

xen/include/asm-x86/hvm/svm/nestedsvm.h +5 -0
diff -r 2c59b4c17c7b -r 857475b2e37c xen/include/asm-x86/hvm/svm/nestedsvm.h
@@ -36,6 +36,11 @@ struct nestedsvm {
      */
     uint64_t ns_ovvmcb_pa;
 
+    /* virtual tscratio holding the value l1 guest writes to the
+     * MSR_AMD64_TSC_RATIO MSR.
+     */
+    uint64_t ns_tscratio;
+
     /* Cached real intercepts of the l2 guest */
     uint32_t ns_cr_intercepts;
     uint32_t ns_dr_intercepts;

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