ARM: MX5: Fix broken leftover TO-2 errata workaround
Subsystems (2)
PATCH v3 1/1 ARM: MX5: Fix broken leftover TO-2 errata workaround
This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51.
Signed-off-by David Jander <[email protected]>
---
Changed in this version:
- Move patch changelog below '---' line.
arch/arm/cpu/armv7/mx5/lowlevel_init.S | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
arch/arm/cpu/armv7/mx5/lowlevel_init.S +5 -1
@@ -39,10 +39,14 @@ orr r0, r0, #(1 << 23) /* disable write allocate combine */ orr r0, r0, #(1 << 22) /* disable write allocate */ - cmp r3, #0x10 /* r3 contains the silicon rev */ +#if defined(CONFIG_MX51) + ldr r1, =0x0 + ldr r3, [r1, #ROM_SI_REV] + cmp r3, #0x10 /* disable write combine for TO 2 and lower revs */ orrls r0, r0, #(1 << 25) +#endif mcr 15, 1, r0, c9, c0, 2 .endm /* init_l2cc */
Signature · 1 line
1.7.4.1
PATCH v3 1/1 ARM: MX5: Fix broken leftover TO-2 errata workaround
Quoted 5 lines · David Jander
This check was broken. r3 does not contain the silicon revision anymore, so we need to reload it. Also, this errata only applies to i.MX51.
Signed-off-by David Jander <[email protected]>---
Applied to u-boot-imx, thanks.
Best regards,
Stefano Babic
Signature · 5 lines
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