Memory API, batch 2: PCI devices
v4 cover Memory API, batch 2: PCI devices
This is a mostly mindless conversion of all QEMU PCI devices to the memory API. After this patchset is applied, it is no longer possible to create a PCI device using the old API.
An immediate benefit is that PCI BARs that overlap each other are now handled
correctly: currently, the sequence
map BAR 0
map BAR 1 at an overlapping address
unmap either BAR 0 or BAR 1
will leave a hole where the overlap exists. With the patchset, the memory map is restored correctly.
Note that overlaps of PCI BARs with memory or non-PCI resources are still not resolved correctly; this will be fixed later on.
The vga patches have ugly intermediate states; however the result is fairly clean.
Changes from v3:
- dropped virtio-pci config patch; will be fixed outside this patchset if necessary
- minor style fixes
Changes from v2:
- added patch from Michael simplifying virtio-pci config setup
Changes from v1:
- cmd646 type fix
- folded a fixlet into its parent
Avi Kivity (39):
memory: rename PORTIO_END to PORTIO_END_OF_LIST
pci: add API to get a BAR's mapped address
vmsvga: don't remember pci BAR address in callback any more
vga: convert vga and its derivatives to the memory API
cirrus: simplify mmio BAR access functions
cirrus: simplify bitblt BAR access functions
cirrus: simplify vga window mmio access functions
vga: simplify vga window mmio access functions
cirrus: simplify linear framebuffer access functions Integrate I/O memory regions into qemu
pci: pass I/O address space to new PCI bus
pci: allow I/O BARs to be registered with pci_register_bar_region()
rtl8139: convert to memory API
ac97: convert to memory API
e1000: convert to memory API
eepro100: convert to memory API
es1370: convert to memory API
ide: convert to memory API
ivshmem: convert to memory API
virtio-pci: convert to memory API
ahci: convert to memory API
intel-hda: convert to memory API
lsi53c895a: convert to memory API
ppc: convert to memory API
ne2000: convert to memory API
pcnet: convert to memory API
i6300esb: convert to memory API
isa-mmio: convert to memory API
sun4u: convert to memory API
ehci: convert to memory API
uhci: convert to memory API
xen-platform: convert to memory API
msix: convert to memory API
pci: remove pci_register_bar_simple()
pci: convert pci rom to memory API
pci: remove pci_register_bar()
pci: fold BAR mapping function into its caller
pci: rename pci_register_bar_region() to pci_register_bar()
pci: remove support for pre memory API BARs
exec-memory.h | 5 + exec.c | 10 ++ hw/ac97.c | 88 ++++++----- hw/apb_pci.c | 1 + hw/bonito.c | 1 + hw/cirrus_vga.c | 459 ++++++++++++++++----------------------------------- hw/cuda.c | 6 +- hw/e1000.c | 113 ++++++-------- hw/eepro100.c | 181 ++++----------------- hw/es1370.c | 43 +++-- hw/escc.c | 42 +++--- hw/escc.h | 2 +- hw/grackle_pci.c | 8 +- hw/gt64xxx.c | 4 +- hw/heathrow_pic.c | 29 ++-- hw/ide.h | 2 +- hw/ide/ahci.c | 31 ++-- hw/ide/ahci.h | 2 +- hw/ide/cmd646.c | 204 +++++++++++++++--------- hw/ide/ich.c | 3 +- hw/ide/macio.c | 36 +++-- hw/ide/pci.c | 25 ++-- hw/ide/pci.h | 19 ++- hw/ide/piix.c | 63 ++++++-- hw/ide/via.c | 64 ++++++-- hw/intel-hda.c | 35 +++-- hw/isa.h | 2 + hw/isa_mmio.c | 29 ++-- hw/ivshmem.c | 158 +++++++------------ hw/lance.c | 31 ++-- hw/lsi53c895a.c | 257 +++++++----------------------- hw/mac_dbdma.c | 32 ++-- hw/mac_dbdma.h | 4 +- hw/mac_nvram.c | 39 ++--- hw/macio.c | 73 ++++----- hw/msix.c | 64 +++----- hw/msix.h | 6 +- hw/ne2000-isa.c | 13 +-- hw/ne2000.c | 77 ++++++--- hw/ne2000.h | 8 +- hw/openpic.c | 81 +++++----- hw/openpic.h | 2 +- hw/pc.h | 4 +- hw/pc_piix.c | 6 +- hw/pci.c | 133 +++++----------- hw/pci.h | 26 ++-- hw/pci_internals.h | 3 +- hw/pcnet-pci.c | 74 +++++---- hw/pcnet.h | 4 +- hw/piix_pci.c | 14 +- hw/ppc4xx_pci.c | 1 + hw/ppc_mac.h | 27 ++-- hw/ppc_newworld.c | 34 ++-- hw/ppc_oldworld.c | 27 ++-- hw/ppc_prep.c | 2 +- hw/ppce500_pci.c | 7 +- hw/prep_pci.c | 8 +- hw/prep_pci.h | 4 +- hw/qxl-render.c | 2 +- hw/qxl.c | 129 ++++++---------- hw/qxl.h | 6 +- hw/rtl8139.c | 70 ++++---- hw/sh_pci.c | 4 +- hw/sun4u.c | 53 +++---- hw/unin_pci.c | 16 ++- hw/usb-ehci.c | 36 +--- hw/usb-ohci.c | 2 +- hw/usb-uhci.c | 41 +++-- hw/versatile_pci.c | 2 +- hw/vga-isa-mm.c | 46 ++++-- hw/vga-isa.c | 10 +- hw/vga-pci.c | 27 +--- hw/vga.c | 178 +++++++------------- hw/vga_int.h | 18 +-- hw/virtio-pci.c | 86 ++++------ hw/virtio-pci.h | 3 +- hw/vmware_vga.c | 153 +++++++++--------- hw/wdt_i6300esb.c | 43 ++++-- hw/xen_platform.c | 82 ++++++---- memory.h | 2 +- 80 files changed, 1650 insertions(+), 2085 deletions(-)
Signature · 1 line
1.7.5.3
PATCH v4 1/39 memory: rename PORTIO_END to PORTIO_END_OF_LIST
For consistency with other _END_OF_LIST macros.
Signed-off-by Avi Kivity <[email protected]>
--- memory.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
memory.h +1 -1
@@ -133,7 +133,7 @@ struct MemoryRegionPortio {IOPortWriteFunc *write; }; -#define PORTIO_END { } +#define PORTIO_END_OF_LIST () { }/** * memory_region_init: Initialize a memory region
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 01/39] memory: rename PORTIO_END to PORTIO_END_OF_LIST
Quoted 3 lines · Avi Kivity
For consistency with other
_END_OF_LISTmacros.Signed-off-by Avi Kivity<[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Regards,
Anthony Liguori
Quoted 17 lines
--- memory.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)memory.h +1
-1@@ -133,7 +133,7 @@ struct MemoryRegionPortio {IOPortWriteFunc *write; }; -#define PORTIO_END { } +#define PORTIO_END_OF_LIST () { }/** * memory_region_init: Initialize a memory region
PATCH v4 2/39 pci: add API to get a BAR's mapped address
In reply to Avi KivitySome (hacky) devices that have a back-channel to read this address back outside the normal configuration mechanisms, such as VMware svga.
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 5 +++++ hw/pci.h | 1 + 2 files changed, 6 insertions(+), 0 deletions(-)
hw/pci.c +5 -0
@@ -952,6 +952,11 @@ void pci_register_bar_region(PCIDevice *pci_dev, int region_num, pci_dev->io_regions[region_num].memory = memory; } +pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num) +{ +return pci_dev->io_regions[region_num].addr; +} +static void pci_bridge_filter (PCIDevice *d,pcibus_t *addr,pcibus_t *size,uint8_t type) {
hw/pci.h +1 -0
@@ -207,6 +207,7 @@ void pci_register_bar_simple(PCIDevice *pci_dev, int region_num, pcibus_t size, uint8_t attr, ram_addr_t ram_addr);void pci_register_bar_region (PCIDevice *pci_dev,int region_num,uint8_t attr,MemoryRegion *memory); +pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num);int pci_add_capability (PCIDevice *pdev,uint8_t cap_id,uint8_t offset,uint8_t size);
Signature · 1 line
1.7.5.3
PATCH v4 3/39 vmsvga: don't remember pci BAR address in callback any more
In reply to Avi KivityWe're going to remove the callback, so we can't use it to save the address. Use the pci API instead.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/vmware_vga.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-)
hw/vmware_vga.c +6 -6
@@ -52,8 +52,6 @@ struct vmsvga_state_s {int on; } cursor; -target_phys_addr_t vram_base; -int index;int scratch_size;uint32_t *scratch;
@@ -761,8 +759,11 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)case SVGA_REG_BYTES_PER_LINE :return ((s->depth +7 ) >>3 ) * s->new_width; -case SVGA_REG_FB_START : -return s->vram_base; +case SVGA_REG_FB_START : { +struct pci_vmsvga_state_s *pci_vmsvga + = container_of(s, struct pci_vmsvga_state_s, chip); +return pci_get_bar_addr (&pci_vmsvga->card,1 ); + }case SVGA_REG_FB_OFFSET :return 0x0 ;
@@ -1247,14 +1248,13 @@ static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,struct vmsvga_state_s *s = &d->chip;ram_addr_t iomemtype; - s->vram_base = addr;#ifdef DIRECT_VRAM iomemtype =cpu_register_io_memory (vmsvga_vram_read, vmsvga_vram_write, s,DEVICE_NATIVE_ENDIAN );#else iomemtype = s->vga.vram_offset |IO_MEM_RAM ;#endif -cpu_register_physical_memory (s->vram_base, s->vga.vram_size, +cpu_register_physical_memory (addr, s->vga.vram_size, iomemtype); s->vga.map_addr = addr;
Signature · 1 line
1.7.5.3
PATCH v4 4/39 vga: convert vga and its derivatives to the memory API
In reply to Avi KivityConvert all vga memory to the memory API. Note we need to fall back to get_system_memory(), since the various buses don't pass the vga window as a memory region.
We no longer need to sync the dirty bitmap of the cirrus mapped memory banks, since the memory API takes care of that for us.
[jan: fix vga-pci logging]
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 342 ++++++++++++++++++++++++++++++++----------------------- hw/qxl-render.c | 2 +- hw/qxl.c | 135 ++++++++-------------- hw/qxl.h | 6 +- hw/vga-isa-mm.c | 46 +++++--- hw/vga-isa.c | 10 +- hw/vga-pci.c | 28 +---- hw/vga.c | 146 +++++++++++------------- hw/vga_int.h | 14 +-- hw/vmware_vga.c | 143 ++++++++++++----------- 10 files changed, 437 insertions(+), 435 deletions(-)
hw/cirrus_vga.c +202 -140
@@ -32,6 +32,7 @@#include "console.h" #include "vga_int.h" #include "loader.h" +#include "exec-memory.h" /* * TODO:
@@ -200,9 +201,14 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, typedef struct CirrusVGAState { VGACommonState vga; - int cirrus_linear_io_addr; - int cirrus_linear_bitblt_io_addr; - int cirrus_mmio_io_addr; + MemoryRegion cirrus_linear_io; + MemoryRegion cirrus_linear_bitblt_io; + MemoryRegion cirrus_mmio_io; + MemoryRegion pci_bar; + bool linear_vram; /* vga.vram mapped over cirrus_linear_io */ + MemoryRegion low_mem_container; /* container for 0xa0000-0xc0000 */ + MemoryRegion low_mem; /* always mapped, overridden by: */ + MemoryRegion *cirrus_bank[2]; /* aliases at 0xa0000-0xb0000 */ uint32_t cirrus_addr_mask; uint32_t linear_mmio_mask; uint8_t cirrus_shadow_gr0;
@@ -612,7 +618,7 @@ static void cirrus_invalidate_region(CirrusVGAState * s, int off_begin, off_cur_end = (off_cur + bytesperline) & s->cirrus_addr_mask; off_cur &=TARGET_PAGE_MASK ;while (off_cur < off_cur_end) { -cpu_physical_memory_set_dirty (s->vga.vram_offset + off_cur); +memory_region_set_dirty (&s->vga.vram, off_cur); off_cur +=TARGET_PAGE_SIZE ; } off_begin += off_pitch;
@@ -1177,12 +1183,6 @@ static void cirrus_update_bank_ptr(CirrusVGAState * s, unsigned bank_index) }if (limit >0 ) { -/* Thinking about changing bank base? First, drop the dirty bitmap information -* on the current location, otherwise we lose this pointer forever */ -if (s->vga.lfb_vram_mapped) { -target_phys_addr_t base_addr = isa_mem_base +0xa0000 + bank_index *0x8000 ; -cpu_physical_sync_dirty_bitmap (base_addr, base_addr +0x8000 ); - } s->cirrus_bank_base[bank_index] = offset; s->cirrus_bank_limit[bank_index] = limit; }else {
@@ -1921,8 +1921,8 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s, val <<=1 ; dst++; } -cpu_physical_memory_set_dirty (s->vga.vram_offset + offset); -cpu_physical_memory_set_dirty (s->vga.vram_offset + offset +7 ); +memory_region_set_dirty (&s->vga.vram, offset); +memory_region_set_dirty (&s->vga.vram, offset +7 ); } static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
@@ -1946,8 +1946,8 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s, val <<=1 ; dst +=2 ; } -cpu_physical_memory_set_dirty (s->vga.vram_offset + offset); -cpu_physical_memory_set_dirty (s->vga.vram_offset + offset +15 ); +memory_region_set_dirty (&s->vga.vram, offset); +memory_region_set_dirty (&s->vga.vram, offset +15 ); }/***************************************
@@ -2057,8 +2057,7 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, mode = s->vga.gr[0x05 ] &0x7 ;if (mode <4 || mode >5 || ((s->vga.gr[0x0B ] &0x4 ) ==0 )) { *(s->vga.vram_ptr + bank_offset) = mem_value; -cpu_physical_memory_set_dirty (s->vga.vram_offset + - bank_offset); +memory_region_set_dirty (&s->vga.vram, bank_offset); }else {if ((s->vga.gr[0x0B ] &0x14 ) !=0x14 ) { cirrus_mem_writeb_mode4and5_8bpp(s, mode,
@@ -2099,16 +2098,37 @@ static void cirrus_vga_mem_writel(void *opaque, target_phys_addr_t addr, uint32_cirrus_vga_mem_writeb (opaque, addr +3 , (val >>24 ) &0xff ); } -static CPUReadMemoryFunc *const cirrus_vga_mem_read[3 ] = { - cirrus_vga_mem_readb, - cirrus_vga_mem_readw, - cirrus_vga_mem_readl, +static uint64_t cirrus_vga_mem_read (void *opaque, +target_phys_addr_t addr, +uint32_t size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_vga_mem_readb (s, addr); +case 2 :return cirrus_vga_mem_readw (s, addr); +case 4 :return cirrus_vga_mem_readl (s, addr); +default :abort (); + } +} + +static void cirrus_vga_mem_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_vga_mem_writeb (s, addr, data); +case 2 :return cirrus_vga_mem_writew (s, addr, data); +case 4 :return cirrus_vga_mem_writel (s, addr, data); +default :abort (); + } }; -static CPUWriteMemoryFunc *const cirrus_vga_mem_write[3 ] = { - cirrus_vga_mem_writeb, - cirrus_vga_mem_writew, - cirrus_vga_mem_writel, +static const MemoryRegionOps cirrus_vga_mem_ops = { + .read = cirrus_vga_mem_read, + .write = cirrus_vga_mem_write, + .endianness =DEVICE_LITTLE_ENDIAN , };/***************************************
@@ -2365,7 +2385,7 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, mode = s->vga.gr[0x05 ] &0x7 ;if (mode <4 || mode >5 || ((s->vga.gr[0x0B ] &0x4 ) ==0 )) { *(s->vga.vram_ptr + addr) = (uint8_t ) val; -cpu_physical_memory_set_dirty (s->vga.vram_offset + addr); +memory_region_set_dirty (&s->vga.vram, addr); }else {if ((s->vga.gr[0x0B ] &0x14 ) !=0x14 ) {cirrus_mem_writeb_mode4and5_8bpp (s, mode, addr, val);
@@ -2393,17 +2413,31 @@ static void cirrus_linear_writel(void *opaque, target_phys_addr_t addr, } -static CPUReadMemoryFunc *const cirrus_linear_read[3 ] = { - cirrus_linear_readb, - cirrus_linear_readw, - cirrus_linear_readl, -}; +static uint64_t cirrus_linear_read (void *opaque,target_phys_addr_t addr, +unsigned size) +{ +CirrusVGAState *s = opaque; -static CPUWriteMemoryFunc *const cirrus_linear_write[3 ] = { - cirrus_linear_writeb, - cirrus_linear_writew, - cirrus_linear_writel, -}; +switch (size) { +case 1 :return cirrus_linear_readb (s, addr); +case 2 :return cirrus_linear_readw (s, addr); +case 4 :return cirrus_linear_readl (s, addr); +default :abort (); + } +} + +static void cirrus_linear_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_linear_writeb (s, addr, data); +case 2 :return cirrus_linear_writew (s, addr, data); +case 4 :return cirrus_linear_writel (s, addr, data); +default :abort (); + } +}/*************************************** *
@@ -2471,67 +2505,95 @@ static void cirrus_linear_bitblt_writel(void *opaque, target_phys_addr_t addr,cirrus_linear_bitblt_writeb (opaque, addr +3 , (val >>24 ) &0xff ); } +static uint64_t cirrus_linear_bitblt_read (void *opaque, +target_phys_addr_t addr, +unsigned size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_linear_bitblt_readb (s, addr); +case 2 :return cirrus_linear_bitblt_readw (s, addr); +case 4 :return cirrus_linear_bitblt_readl (s, addr); +default :abort (); + } +}; + +static void cirrus_linear_bitblt_write (void *opaque, +target_phys_addr_t addr, +uint64_t data, +unsigned size) +{ +CirrusVGAState *s = opaque; -static CPUReadMemoryFunc *const cirrus_linear_bitblt_read[3 ] = { - cirrus_linear_bitblt_readb, - cirrus_linear_bitblt_readw, - cirrus_linear_bitblt_readl, +switch (size) { +case 1 :return cirrus_linear_bitblt_writeb (s, addr, data); +case 2 :return cirrus_linear_bitblt_writew (s, addr, data); +case 4 :return cirrus_linear_bitblt_writel (s, addr, data); +default :abort (); + } }; -static CPUWriteMemoryFunc *const cirrus_linear_bitblt_write[3 ] = { - cirrus_linear_bitblt_writeb, - cirrus_linear_bitblt_writew, - cirrus_linear_bitblt_writel, +static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { + .read = cirrus_linear_bitblt_read, + .write = cirrus_linear_bitblt_write, + .endianness =DEVICE_LITTLE_ENDIAN , }; -static void map_linear_vram (CirrusVGAState *s) +static void unmap_bank (CirrusVGAState *s,unsigned bank) { -if (!s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) { - s->vga.map_addr = s->vga.lfb_addr; - s->vga.map_end = s->vga.lfb_end; -cpu_register_physical_memory_log (s->vga.map_addr, - s->vga.map_end - s->vga.map_addr, - s->vga.vram_offset,0 , true); +if (s->cirrus_bank[bank]) { +memory_region_del_subregion (&s->low_mem_container, + s->cirrus_bank[bank]); +memory_region_destroy (s->cirrus_bank[bank]); +qemu_free (s->cirrus_bank[bank]); + s->cirrus_bank[bank] =NULL ; } +} -if (!s->vga.map_addr) -return ; - - s->vga.lfb_vram_mapped =0 ; +static void map_linear_vram_bank (CirrusVGAState *s,unsigned bank) +{ +MemoryRegion *mr; +static const char *names[] = {"vga.bank0" ,"vga.bank1" };if (!(s->cirrus_srcptr != s->cirrus_srcptr_end) && !((s->vga.sr[0x07 ] &0x01 ) ==0 ) && !((s->vga.gr[0x0B ] &0x14 ) ==0x14 ) && !(s->vga.gr[0x0B ] &0x02 )) { -cpu_register_physical_memory_log (isa_mem_base +0xa0000 ,0x8000 , - (s->vga.vram_offset + - s->cirrus_bank_base[0 ]) | -IO_MEM_RAM ,0 , true); -cpu_register_physical_memory_log (isa_mem_base +0xa8000 ,0x8000 , - (s->vga.vram_offset + - s->cirrus_bank_base[1 ]) | -IO_MEM_RAM ,0 , true); - - s->vga.lfb_vram_mapped =1 ; - } -else { -cpu_register_physical_memory (isa_mem_base +0xa0000 ,0x20000 , - s->vga.vga_io_memory); + mr =qemu_malloc (sizeof (*mr)); +memory_region_init_alias (mr, names[bank], &s->vga.vram, + s->cirrus_bank_base[bank],0x8000 ); +memory_region_add_subregion_overlap ( + &s->low_mem_container, +0x8000 * bank, + mr, +1 ); +unmap_bank (s, bank); + s->cirrus_bank[bank] = mr; + }else { +unmap_bank (s, bank); } +} -vga_dirty_log_start (&s->vga); +static void map_linear_vram (CirrusVGAState *s) +{ +if (!s->linear_vram) { + s->linear_vram = true; +memory_region_add_subregion_overlap (&s->pci_bar,0 , &s->vga.vram,1 ); + } +map_linear_vram_bank (s,0 ); +map_linear_vram_bank (s,1 ); }static void unmap_linear_vram (CirrusVGAState *s) { -if (s->vga.map_addr && s->vga.lfb_addr && s->vga.lfb_end) { - s->vga.map_addr = s->vga.map_end =0 ; -cpu_register_physical_memory (s->vga.lfb_addr, s->vga.vram_size, - s->cirrus_linear_io_addr); +if (s->linear_vram) { + s->linear_vram = false; +memory_region_del_subregion (&s->pci_bar, &s->vga.vram); } -cpu_register_physical_memory (isa_mem_base +0xa0000 ,0x20000 , - s->vga.vga_io_memory); +unmap_bank (s,0 ); +unmap_bank (s,1 ); }/* Compute the memory access functions */
@@ -2829,16 +2891,36 @@ static void cirrus_mmio_writel(void *opaque, target_phys_addr_t addr, } -static CPUReadMemoryFunc *const cirrus_mmio_read[3 ] = { - cirrus_mmio_readb, - cirrus_mmio_readw, - cirrus_mmio_readl, +static uint64_t cirrus_mmio_read (void *opaque,target_phys_addr_t addr, +unsigned size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_mmio_readb (s, addr); +case 2 :return cirrus_mmio_readw (s, addr); +case 4 :return cirrus_mmio_readl (s, addr); +default :abort (); + } +}; + +static void cirrus_mmio_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) +{ +CirrusVGAState *s = opaque; + +switch (size) { +case 1 :return cirrus_mmio_writeb (s, addr, data); +case 2 :return cirrus_mmio_writew (s, addr, data); +case 4 :return cirrus_mmio_writel (s, addr, data); +default :abort (); + } }; -static CPUWriteMemoryFunc *const cirrus_mmio_write[3 ] = { - cirrus_mmio_writeb, - cirrus_mmio_writew, - cirrus_mmio_writel, +static const MemoryRegionOps cirrus_mmio_io_ops = { + .read = cirrus_mmio_read, + .write = cirrus_mmio_write, + .endianness =DEVICE_LITTLE_ENDIAN , };/* load/save state */
@@ -2947,6 +3029,12 @@ static void cirrus_reset(void *opaque) s->cirrus_hidden_dac_data =0 ; } +static const MemoryRegionOps cirrus_linear_io_ops = { + .read = cirrus_linear_read, + .write = cirrus_linear_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; +static void cirrus_init_common (CirrusVGAState * s,int device_id,int is_pci) {int i;
@@ -2993,28 +3081,33 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci)register_ioport_read (0x3ba ,1 ,1 , cirrus_vga_ioport_read, s);register_ioport_read (0x3da ,1 ,1 , cirrus_vga_ioport_read, s); - s->vga.vga_io_memory =cpu_register_io_memory (cirrus_vga_mem_read, - cirrus_vga_mem_write, s, -DEVICE_LITTLE_ENDIAN ); -cpu_register_physical_memory (isa_mem_base +0x000a0000 ,0x20000 , - s->vga.vga_io_memory); -qemu_register_coalesced_mmio (isa_mem_base +0x000a0000 ,0x20000 ); +memory_region_init (&s->low_mem_container, +"cirrus-lowmem-container" , +0x20000 ); + +memory_region_init_io (&s->low_mem, &cirrus_vga_mem_ops, s, +"cirrus-low-memory" ,0x20000 ); +memory_region_add_subregion (&s->low_mem_container,0 , &s->low_mem); +memory_region_add_subregion_overlap (get_system_memory (), + isa_mem_base +0x000a0000 , + &s->low_mem_container, +1 ); +memory_region_set_coalescing (&s->low_mem);/* I/O handler for LFB */ - s->cirrus_linear_io_addr = -cpu_register_io_memory (cirrus_linear_read, cirrus_linear_write, s, -DEVICE_LITTLE_ENDIAN ); +memory_region_init_io (&s->cirrus_linear_io, &cirrus_linear_io_ops, s, +"cirrus-linear-io" ,VGA_RAM_SIZE );/* I/O handler for LFB */ - s->cirrus_linear_bitblt_io_addr = -cpu_register_io_memory (cirrus_linear_bitblt_read, - cirrus_linear_bitblt_write, s, -DEVICE_LITTLE_ENDIAN ); +memory_region_init_io (&s->cirrus_linear_bitblt_io, + &cirrus_linear_bitblt_io_ops, + s, +"cirrus-bitblt-mmio" , +0x400000 );/* I/O handler for memory-mapped I/O */ - s->cirrus_mmio_io_addr = -cpu_register_io_memory (cirrus_mmio_read, cirrus_mmio_write, s, -DEVICE_LITTLE_ENDIAN ); +memory_region_init_io (&s->cirrus_mmio_io, &cirrus_mmio_io_ops, s, +"cirrus-mmio" ,CIRRUS_PNPMMIO_SIZE ); s->real_vram_size = (s->device_id ==CIRRUS_ID_CLGD5446 ) ?4096 *1024 :2048 *1024 ;
@@ -3060,42 +3153,6 @@ void isa_cirrus_vga_init(void)* ***************************************/ -static void cirrus_pci_lfb_map (PCIDevice *d,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -CirrusVGAState *s = &DO_UPCAST (PCICirrusVGAState, dev, d)->cirrus_vga; - -/* XXX: add byte swapping apertures */ -cpu_register_physical_memory (addr, s->vga.vram_size, - s->cirrus_linear_io_addr); -cpu_register_physical_memory (addr +0x1000000 ,0x400000 , - s->cirrus_linear_bitblt_io_addr); - - s->vga.map_addr = s->vga.map_end =0 ; - s->vga.lfb_addr = addr &TARGET_PAGE_MASK ; - s->vga.lfb_end = ((addr +VGA_RAM_SIZE ) +TARGET_PAGE_SIZE -1 ) &TARGET_PAGE_MASK ; -/* account for overflow */ -if (s->vga.lfb_end < addr +VGA_RAM_SIZE ) - s->vga.lfb_end = addr +VGA_RAM_SIZE ; - -vga_dirty_log_start (&s->vga); -} - -static void pci_cirrus_write_config (PCIDevice *d, -uint32_t address,uint32_t val,int len) -{ -PCICirrusVGAState *pvs =DO_UPCAST (PCICirrusVGAState, dev, d); -CirrusVGAState *s = &pvs->cirrus_vga; - -pci_default_write_config (d, address, val, len); -if (s->vga.map_addr && d->io_regions[0 ].addr ==PCI_BAR_UNMAPPED ) { - s->vga.map_addr =0 ; - s->vga.lfb_addr =0 ; - s->vga.lfb_end =0 ; - } -cirrus_update_memory_access (s); -} -static int pci_cirrus_vga_initfn (PCIDevice *dev) {PCICirrusVGAState *d =DO_UPCAST (PCICirrusVGAState, dev, dev);
@@ -3112,15 +3169,21 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)/* setup PCI */ +memory_region_init (&s->pci_bar,"cirrus-pci-bar0" ,0x2000000 ); + +/* XXX: add byte swapping apertures */ +memory_region_add_subregion (&s->pci_bar,0 , &s->cirrus_linear_io); +memory_region_add_subregion (&s->pci_bar,0x1000000 , + &s->cirrus_linear_bitblt_io); +/* setup memory space */ /* memory #0 LFB */ /* memory #1 memory-mapped I/O */ /* XXX: s->vga.vram_size must be a power of two */ -pci_register_bar (&d->dev,0 ,0x2000000 , -PCI_BASE_ADDRESS_MEM_PREFETCH , cirrus_pci_lfb_map); +pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , + &s->pci_bar);if (device_id ==CIRRUS_ID_CLGD5446 ) { -pci_register_bar_simple (&d->dev,1 ,CIRRUS_PNPMMIO_SIZE ,0 , - s->cirrus_mmio_io_addr); +pci_register_bar_region (&d->dev,1 ,0 , &s->cirrus_mmio_io); }return 0 ; }
@@ -3138,7 +3201,6 @@ static PCIDeviceInfo cirrus_vga_info = { .no_hotplug = 1, .init = pci_cirrus_vga_initfn, .romfile = VGABIOS_CIRRUS_FILENAME, - .config_write = pci_cirrus_write_config, .vendor_id = PCI_VENDOR_ID_CIRRUS, .device_id = CIRRUS_ID_CLGD5446, .class_id = PCI_CLASS_DISPLAY_VGA,
hw/qxl-render.c +1 -1
@@ -86,7 +86,7 @@ void qxl_render_update(PCIQXLDevice *qxl) }qemu_free_displaysurface (vga->ds); - qxl->guest_primary.data =qemu_get_ram_ptr (qxl->vga.vram_offset); + qxl->guest_primary.data =memory_region_get_ram_ptr (&qxl->vga.vram);if (qxl->guest_primary.stride <0 ) {/* spice surface is upside down -> need extra buffer to flip */ qxl->guest_primary.stride = -qxl->guest_primary.stride;
hw/qxl.c +49 -86
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hw/qxl.h +3 -3
@@ -79,14 +79,14 @@ typedef struct PCIQXLDevice {QXLRom *rom;QXLModes *modes;uint32_t rom_size; -uint64_t rom_offset; +MemoryRegion rom_bar;/* vram pci bar */ uint32_t vram_size; -uint64_t vram_offset; +MemoryRegion vram_bar;/* io bar */ -uint32_t io_base; +MemoryRegion io_bar; } PCIQXLDevice;#define PANIC_ON (x) if ((x)) { \
hw/vga-isa-mm.c +28 -18
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hw/vga-isa.c +6 -4
@@ -28,6 +28,7 @@#include "pixel_ops.h" #include "qemu-timer.h" #include "loader.h" +#include "exec-memory.h" typedef struct ISAVGAState { ISADevice dev;
@@ -46,13 +47,14 @@ static int vga_initfn(ISADevice *dev) {ISAVGAState *d =DO_UPCAST (ISAVGAState, dev, dev);VGACommonState *s = &d->state; -int vga_io_memory; +MemoryRegion *vga_io_memory;vga_common_init (s,VGA_RAM_SIZE ); vga_io_memory =vga_init_io (s); -cpu_register_physical_memory (isa_mem_base +0x000a0000 ,0x20000 , - vga_io_memory); -qemu_register_coalesced_mmio (isa_mem_base +0x000a0000 ,0x20000 ); +memory_region_add_subregion_overlap (get_system_memory (), + isa_mem_base +0x000a0000 , + vga_io_memory,1 ); +memory_region_set_coalescing (vga_io_memory);isa_init_ioport (dev,0x3c0 );isa_init_ioport (dev,0x3b4 );isa_init_ioport (dev,0x3ba );
hw/vga-pci.c +2 -26
@@ -47,29 +47,6 @@ static const VMStateDescription vmstate_vga_pci = { } }; -static void vga_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -PCIVGAState *d = (PCIVGAState *)pci_dev; -VGACommonState *s = &d->vga; - -cpu_register_physical_memory (addr, s->vram_size, s->vram_offset); - s->map_addr = addr; - s->map_end = addr + s->vram_size; -vga_dirty_log_start (s); -} - -static void pci_vga_write_config (PCIDevice *d, -uint32_t address,uint32_t val,int len) -{ -PCIVGAState *pvs =container_of (d, PCIVGAState, dev); -VGACommonState *s = &pvs->vga; - -pci_default_write_config (d, address, val, len); -if (s->map_addr && pvs->dev.io_regions[0 ].addr ==-1 ) - s->map_addr =0 ; -} -static int pci_vga_initfn (PCIDevice *dev) {PCIVGAState *d =DO_UPCAST (PCIVGAState, dev, dev);
@@ -83,8 +60,8 @@ static int pci_vga_initfn(PCIDevice *dev) s->screen_dump, s->text_update, s);/* XXX: VGA_RAM_SIZE must be a power of two */ -pci_register_bar (&d->dev,0 ,VGA_RAM_SIZE , -PCI_BASE_ADDRESS_MEM_PREFETCH , vga_map); +pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , + &s->vram);if (!dev->rom_bar) {/* compatibility with pc-0.13 and older */
@@ -106,7 +83,6 @@ static PCIDeviceInfo vga_info = { .qdev.vmsd = &vmstate_vga_pci, .no_hotplug = 1, .init = pci_vga_initfn, - .config_write = pci_vga_write_config, .romfile = "vgabios-stdvga.bin",/* dummy VGA (same as Bochs ID) */
hw/vga.c +67 -79
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hw/vga_int.h +5 -9
@@ -23,6 +23,7 @@*/ #include <hw/hw.h> +#include "memory.h" #define MSR_COLOR_EMULATION 0x01#define MSR_PAGE_SELECT 0x20
@@ -105,11 +106,7 @@ typedef void (* vga_update_retrace_info_fn)(struct VGACommonState *s); typedef struct VGACommonState { uint8_t *vram_ptr; - ram_addr_t vram_offset; - target_phys_addr_t lfb_addr; - target_phys_addr_t lfb_end; - target_phys_addr_t map_addr; - target_phys_addr_t map_end; + MemoryRegion vram; uint32_t vram_size; uint32_t latch; uint32_t lfb_vram_mapped; /* whether 0xa0000 is mapped as ram */
@@ -134,7 +131,7 @@ typedef struct VGACommonState {int dac_8bit;uint8_t palette[768 ];int32_t bank_offset; -int vga_io_memory; +MemoryRegion *vga_io_memory;int (*get_bpp)(struct VGACommonState *s); void (*get_offsets)(struct VGACommonState *s, uint32_t *pline_offset,
@@ -191,7 +188,7 @@ static inline int c6_to_8(int v)void vga_common_init (VGACommonState *s,int vga_ram_size);void vga_init (VGACommonState *s); -int vga_init_io (VGACommonState *s); +MemoryRegion *vga_init_io (VGACommonState *s);void vga_common_reset (VGACommonState *s);void vga_dirty_log_start (VGACommonState *s);
@@ -229,5 +226,4 @@ extern const uint8_t gr_mask[16];#define VGABIOS_FILENAME "vgabios.bin"#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin" -extern CPUReadMemoryFunc *const vga_mem_read[3 ]; -extern CPUWriteMemoryFunc *const vga_mem_write[3 ]; +extern const MemoryRegionOps vga_mem_ops;
hw/vmware_vga.c +74 -69
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Signature · 1 line
1.7.5.3
PATCH v4 5/39 cirrus: simplify mmio BAR access functions
In reply to Avi KivityMake use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses.
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 78 +++++------------------------------------------------- 1 files changed, 8 insertions(+), 70 deletions(-)
hw/cirrus_vga.c +8 -70
@@ -2827,12 +2827,11 @@ static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)* ***************************************/ -static uint32_t cirrus_mmio_readb (void *opaque,target_phys_addr_t addr) +static uint64_t cirrus_mmio_read (void *opaque,target_phys_addr_t addr, +unsigned size) {CirrusVGAState *s = opaque; - addr &=CIRRUS_PNPMMIO_SIZE -1 ; -if (addr >=0x100 ) {return cirrus_mmio_blt_read (s, addr -0x100 ); }else {
@@ -2840,33 +2839,11 @@ static uint32_t cirrus_mmio_readb(void *opaque, target_phys_addr_t addr) } } -static uint32_t cirrus_mmio_readw (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_mmio_readb (opaque, addr); - v |=cirrus_mmio_readb (opaque, addr +1 ) <<8 ; -return v; -} - -static uint32_t cirrus_mmio_readl (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_mmio_readb (opaque, addr); - v |=cirrus_mmio_readb (opaque, addr +1 ) <<8 ; - v |=cirrus_mmio_readb (opaque, addr +2 ) <<16 ; - v |=cirrus_mmio_readb (opaque, addr +3 ) <<24 ; -return v; -} - -static void cirrus_mmio_writeb (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void cirrus_mmio_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {CirrusVGAState *s = opaque; - addr &=CIRRUS_PNPMMIO_SIZE -1 ; -if (addr >=0x100 ) {cirrus_mmio_blt_write (s, addr -0x100 , val); }else {
@@ -2874,53 +2851,14 @@ static void cirrus_mmio_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_mmio_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_mmio_writeb (opaque, addr, val &0xff ); -cirrus_mmio_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -} - -static void cirrus_mmio_writel (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_mmio_writeb (opaque, addr, val &0xff ); -cirrus_mmio_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -cirrus_mmio_writeb (opaque, addr +2 , (val >>16 ) &0xff ); -cirrus_mmio_writeb (opaque, addr +3 , (val >>24 ) &0xff ); -} - - -static uint64_t cirrus_mmio_read (void *opaque,target_phys_addr_t addr, -unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_mmio_readb (s, addr); -case 2 :return cirrus_mmio_readw (s, addr); -case 4 :return cirrus_mmio_readl (s, addr); -default :abort (); - } -}; - -static void cirrus_mmio_write (void *opaque,target_phys_addr_t addr, -uint64_t data,unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_mmio_writeb (s, addr, data); -case 2 :return cirrus_mmio_writew (s, addr, data); -case 4 :return cirrus_mmio_writel (s, addr, data); -default :abort (); - } -}; -static const MemoryRegionOps cirrus_mmio_io_ops = { .read = cirrus_mmio_read, .write = cirrus_mmio_write, .endianness =DEVICE_LITTLE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, };/* load/save state */
Signature · 1 line
1.7.5.3
PATCH v4 6/39 cirrus: simplify bitblt BAR access functions
In reply to Avi KivityMake use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 81 +++++++++---------------------------------------------- 1 files changed, 13 insertions(+), 68 deletions(-)
hw/cirrus_vga.c +13 -68
@@ -2446,37 +2446,23 @@ static void cirrus_linear_write(void *opaque, target_phys_addr_t addr,***************************************/ -static uint32_t cirrus_linear_bitblt_readb (void *opaque,target_phys_addr_t addr) +static uint64_t cirrus_linear_bitblt_read (void *opaque, +target_phys_addr_t addr, +unsigned size) { +CirrusVGAState *s = opaque;uint32_t ret;/* XXX handle bitblt */ + (void )s; ret =0xff ;return ret; } -static uint32_t cirrus_linear_bitblt_readw (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_linear_bitblt_readb (opaque, addr); - v |=cirrus_linear_bitblt_readb (opaque, addr +1 ) <<8 ; -return v; -} - -static uint32_t cirrus_linear_bitblt_readl (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_linear_bitblt_readb (opaque, addr); - v |=cirrus_linear_bitblt_readb (opaque, addr +1 ) <<8 ; - v |=cirrus_linear_bitblt_readb (opaque, addr +2 ) <<16 ; - v |=cirrus_linear_bitblt_readb (opaque, addr +3 ) <<24 ; -return v; -} - -static void cirrus_linear_bitblt_writeb (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void cirrus_linear_bitblt_write (void *opaque, +target_phys_addr_t addr, +uint64_t val, +unsigned size) {CirrusVGAState *s = opaque;
@@ -2489,55 +2475,14 @@ static void cirrus_linear_bitblt_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_linear_bitblt_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_linear_bitblt_writeb (opaque, addr, val &0xff ); -cirrus_linear_bitblt_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -} - -static void cirrus_linear_bitblt_writel (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_linear_bitblt_writeb (opaque, addr, val &0xff ); -cirrus_linear_bitblt_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -cirrus_linear_bitblt_writeb (opaque, addr +2 , (val >>16 ) &0xff ); -cirrus_linear_bitblt_writeb (opaque, addr +3 , (val >>24 ) &0xff ); -} - -static uint64_t cirrus_linear_bitblt_read (void *opaque, -target_phys_addr_t addr, -unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_linear_bitblt_readb (s, addr); -case 2 :return cirrus_linear_bitblt_readw (s, addr); -case 4 :return cirrus_linear_bitblt_readl (s, addr); -default :abort (); - } -}; - -static void cirrus_linear_bitblt_write (void *opaque, -target_phys_addr_t addr, -uint64_t data, -unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_linear_bitblt_writeb (s, addr, data); -case 2 :return cirrus_linear_bitblt_writew (s, addr, data); -case 4 :return cirrus_linear_bitblt_writel (s, addr, data); -default :abort (); - } -}; -static const MemoryRegionOps cirrus_linear_bitblt_io_ops = { .read = cirrus_linear_bitblt_read, .write = cirrus_linear_bitblt_write, .endianness =DEVICE_LITTLE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, };static void unmap_bank (CirrusVGAState *s,unsigned bank)
Signature · 1 line
1.7.5.3
PATCH v4 7/39 cirrus: simplify vga window mmio access functions
In reply to Avi KivityMake use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 79 +++++++----------------------------------------------- 1 files changed, 11 insertions(+), 68 deletions(-)
hw/cirrus_vga.c +11 -68
@@ -1956,7 +1956,9 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,* ***************************************/ -static uint32_t cirrus_vga_mem_readb (void *opaque,target_phys_addr_t addr) +static uint64_t cirrus_vga_mem_read (void *opaque, +target_phys_addr_t addr, +uint32_t size) {CirrusVGAState *s = opaque;unsigned bank_index;
@@ -1967,8 +1969,6 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)return vga_mem_readb (s, addr); } - addr &=0x1ffff ; -if (addr <0x10000 ) {/* XXX handle bitblt */ /* video memory */
@@ -2000,28 +2000,10 @@ static uint32_t cirrus_vga_mem_readb(void *opaque, target_phys_addr_t addr)return val; } -static uint32_t cirrus_vga_mem_readw (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_vga_mem_readb (opaque, addr); - v |=cirrus_vga_mem_readb (opaque, addr +1 ) <<8 ; -return v; -} - -static uint32_t cirrus_vga_mem_readl (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_vga_mem_readb (opaque, addr); - v |=cirrus_vga_mem_readb (opaque, addr +1 ) <<8 ; - v |=cirrus_vga_mem_readb (opaque, addr +2 ) <<16 ; - v |=cirrus_vga_mem_readb (opaque, addr +3 ) <<24 ; -return v; -} - -static void cirrus_vga_mem_writeb (void *opaque,target_phys_addr_t addr, -uint32_t mem_value) +static void cirrus_vga_mem_write (void *opaque, +target_phys_addr_t addr, +uint64_t mem_value, +uint32_t size) {CirrusVGAState *s = opaque;unsigned bank_index;
@@ -2033,8 +2015,6 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr,return ; } - addr &=0x1ffff ; -if (addr <0x10000 ) {if (s->cirrus_srcptr != s->cirrus_srcptr_end) {/* bitblt */
@@ -2084,51 +2064,14 @@ static void cirrus_vga_mem_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_vga_mem_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -cirrus_vga_mem_writeb (opaque, addr, val &0xff ); -cirrus_vga_mem_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -} - -static void cirrus_vga_mem_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -cirrus_vga_mem_writeb (opaque, addr, val &0xff ); -cirrus_vga_mem_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -cirrus_vga_mem_writeb (opaque, addr +2 , (val >>16 ) &0xff ); -cirrus_vga_mem_writeb (opaque, addr +3 , (val >>24 ) &0xff ); -} - -static uint64_t cirrus_vga_mem_read (void *opaque, -target_phys_addr_t addr, -uint32_t size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_vga_mem_readb (s, addr); -case 2 :return cirrus_vga_mem_readw (s, addr); -case 4 :return cirrus_vga_mem_readl (s, addr); -default :abort (); - } -} - -static void cirrus_vga_mem_write (void *opaque,target_phys_addr_t addr, -uint64_t data,unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_vga_mem_writeb (s, addr, data); -case 2 :return cirrus_vga_mem_writew (s, addr, data); -case 4 :return cirrus_vga_mem_writel (s, addr, data); -default :abort (); - } -}; -static const MemoryRegionOps cirrus_vga_mem_ops = { .read = cirrus_vga_mem_read, .write = cirrus_vga_mem_write, .endianness =DEVICE_LITTLE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, };/***************************************
Signature · 1 line
1.7.5.3
PATCH v4 8/39 vga: simplify vga window mmio access functions
In reply to Avi KivityMake use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses.
We have to keep vga_mem_{read,write}b() since they're used by cirrus.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 4 +- hw/vga.c | 56 +++++++----------------------------------------------- hw/vga_int.h | 4 +- 3 files changed, 12 insertions(+), 52 deletions(-)
hw/cirrus_vga.c +2 -2
@@ -1966,7 +1966,7 @@ static uint64_t cirrus_vga_mem_read(void *opaque,uint32_t val;if ((s->vga.sr[0x07 ] &0x01 ) ==0 ) { -return vga_mem_readb (s, addr); +return vga_mem_readb (&s->vga, addr); }if (addr <0x10000 ) {
@@ -2011,7 +2011,7 @@ static void cirrus_vga_mem_write(void *opaque,unsigned mode;if ((s->vga.sr[0x07 ] &0x01 ) ==0 ) { -vga_mem_writeb (s, addr, mem_value); +vga_mem_writeb (&s->vga, addr, mem_value);return ; }
hw/vga.c +8 -48
95 lines not on this page · raw message
hw/vga_int.h +2 -2
@@ -198,8 +198,8 @@ void vga_dirty_log_restart(VGACommonState *s);extern const VMStateDescription vmstate_vga_common;uint32_t vga_ioport_read (void *opaque,uint32_t addr);void vga_ioport_write (void *opaque,uint32_t addr,uint32_t val); -uint32_t vga_mem_readb (void *opaque,target_phys_addr_t addr); -void vga_mem_writeb (void *opaque,target_phys_addr_t addr,uint32_t val); +uint32_t vga_mem_readb (VGACommonState *s,target_phys_addr_t addr); +void vga_mem_writeb (VGACommonState *s,target_phys_addr_t addr,uint32_t val);void vga_invalidate_scanlines (VGACommonState *s,int y1,int y2);int ppm_save (const char *filename,struct DisplaySurface *ds);
Signature · 1 line
1.7.5.3
PATCH v4 9/39 cirrus: simplify linear framebuffer access functions
In reply to Avi KivityMake use of the memory API's ability to satisfy multi-byte accesses via multiple single-byte accesses.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cirrus_vga.c | 74 ++++++------------------------------------------------- 1 files changed, 8 insertions(+), 66 deletions(-)
hw/cirrus_vga.c +8 -66
@@ -2250,7 +2250,8 @@ static void cirrus_cursor_draw_line(VGACommonState *s1, uint8_t *d1, int scr_y)* ***************************************/ -static uint32_t cirrus_linear_readb (void *opaque,target_phys_addr_t addr) +static uint64_t cirrus_linear_read (void *opaque,target_phys_addr_t addr, +unsigned size) {CirrusVGAState *s = opaque;uint32_t ret;
@@ -2278,28 +2279,8 @@ static uint32_t cirrus_linear_readb(void *opaque, target_phys_addr_t addr)return ret; } -static uint32_t cirrus_linear_readw (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_linear_readb (opaque, addr); - v |=cirrus_linear_readb (opaque, addr +1 ) <<8 ; -return v; -} - -static uint32_t cirrus_linear_readl (void *opaque,target_phys_addr_t addr) -{ -uint32_t v; - - v =cirrus_linear_readb (opaque, addr); - v |=cirrus_linear_readb (opaque, addr +1 ) <<8 ; - v |=cirrus_linear_readb (opaque, addr +2 ) <<16 ; - v |=cirrus_linear_readb (opaque, addr +3 ) <<24 ; -return v; -} - -static void cirrus_linear_writeb (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void cirrus_linear_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {CirrusVGAState *s = opaque;unsigned mode;
@@ -2339,49 +2320,6 @@ static void cirrus_linear_writeb(void *opaque, target_phys_addr_t addr, } } -static void cirrus_linear_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_linear_writeb (opaque, addr, val &0xff ); -cirrus_linear_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -} - -static void cirrus_linear_writel (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -cirrus_linear_writeb (opaque, addr, val &0xff ); -cirrus_linear_writeb (opaque, addr +1 , (val >>8 ) &0xff ); -cirrus_linear_writeb (opaque, addr +2 , (val >>16 ) &0xff ); -cirrus_linear_writeb (opaque, addr +3 , (val >>24 ) &0xff ); -} - - -static uint64_t cirrus_linear_read (void *opaque,target_phys_addr_t addr, -unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_linear_readb (s, addr); -case 2 :return cirrus_linear_readw (s, addr); -case 4 :return cirrus_linear_readl (s, addr); -default :abort (); - } -} - -static void cirrus_linear_write (void *opaque,target_phys_addr_t addr, -uint64_t data,unsigned size) -{ -CirrusVGAState *s = opaque; - -switch (size) { -case 1 :return cirrus_linear_writeb (s, addr, data); -case 2 :return cirrus_linear_writew (s, addr, data); -case 4 :return cirrus_linear_writel (s, addr, data); -default :abort (); - } -} -/*************************************** * * system to screen memory access
@@ -2859,6 +2797,10 @@ static const MemoryRegionOps cirrus_linear_io_ops = { .read = cirrus_linear_read, .write = cirrus_linear_write, .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, };static void cirrus_init_common (CirrusVGAState * s,int device_id,int is_pci)
Signature · 1 line
1.7.5.3
PATCH v4 10/39 Integrate I/O memory regions into qemu
In reply to Avi Kivityget_system_io() returns the root I/O memory region.
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- exec-memory.h | 5 +++++ exec.c | 10 ++++++++++ 2 files changed, 15 insertions(+), 0 deletions(-)
exec-memory.h +5 -0
@@ -28,6 +28,11 @@*/ MemoryRegion *get_system_memory (void ); +/* Get the root I/O port region. This interface should only be used +* temporarily until a proper bus interface is available. +*/ +MemoryRegion *get_system_io (void ); +/* Set the root memory region. This region is the system memory map. */ void set_system_memory_map (MemoryRegion *mr);
exec.c +10 -0
@@ -113,6 +113,7 @@ static int in_migration;RAMList ram_list = { .blocks =QLIST_HEAD_INITIALIZER (ram_list) };static MemoryRegion *system_memory; +static MemoryRegion *system_io;#endif
@@ -3830,6 +3831,10 @@ static void memory_map_init(void) system_memory =qemu_malloc (sizeof (*system_memory));memory_region_init (system_memory,"system" ,INT64_MAX );set_system_memory_map (system_memory); + + system_io =qemu_malloc (sizeof (*system_io)); +memory_region_init (system_io,"io" ,65536 ); +set_system_io_map (system_io); }MemoryRegion *get_system_memory (void )
@@ -3837,6 +3842,11 @@ MemoryRegion *get_system_memory(void) return system_memory; } +MemoryRegion *get_system_io (void ) +{ +return system_io; +} +#endif /* !defined(CONFIG_USER_ONLY) */ /* physical memory access (slow version, mainly for debug) */
Signature · 1 line
1.7.5.3
PATCH v4 11/39 pci: pass I/O address space to new PCI bus
In reply to Avi KivityThis lets us register BARs in the I/O address space.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/apb_pci.c | 1 + hw/bonito.c | 1 + hw/grackle_pci.c | 8 ++++++-- hw/gt64xxx.c | 4 +++- hw/pc.h | 4 +++- hw/pc_piix.c | 6 +++++- hw/pci.c | 18 ++++++++++++------ hw/pci.h | 10 +++++++--- hw/piix_pci.c | 14 +++++++++----- hw/ppc4xx_pci.c | 1 + hw/ppc_mac.h | 11 ++++++++--- hw/ppc_newworld.c | 4 ++-- hw/ppc_oldworld.c | 4 +++- hw/ppc_prep.c | 2 +- hw/ppce500_pci.c | 7 ++++--- hw/prep_pci.c | 8 ++++++-- hw/prep_pci.h | 4 +++- hw/sh_pci.c | 4 +++- hw/unin_pci.c | 16 ++++++++++++---- hw/versatile_pci.c | 2 +- 20 files changed, 91 insertions(+), 38 deletions(-)
hw/apb_pci.c +1 -0
@@ -348,6 +348,7 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, d->bus =pci_register_bus (&d->busdev.qdev,"pci" , pci_apb_set_irq, pci_pbm_map_irq, d,get_system_memory (), +get_system_io (),0 ,32 );pci_bus_set_mem_base (d->bus, mem_base);
hw/bonito.c +1 -0
@@ -775,6 +775,7 @@ PCIBus *bonito_init(qemu_irq *pic) pcihost =FROM_SYSBUS (BonitoState,sysbus_from_qdev (dev)); b =pci_register_bus (&pcihost->busdev.qdev,"pci" , pci_bonito_set_irq, pci_bonito_map_irq, pic,get_system_memory (), +get_system_io (),0x28 ,32 ); pcihost->bus = b;qdev_init_nofail (dev);
hw/grackle_pci.c +6 -2
@@ -62,7 +62,8 @@ static void pci_grackle_reset(void *opaque) }PCIBus *pci_grackle_init (uint32_t base,qemu_irq *pic, -MemoryRegion *address_space) +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io) {DeviceState *dev;SysBusDevice *s;
@@ -75,7 +76,10 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, d->host_state.bus =pci_register_bus (&d->busdev.qdev,"pci" , pci_grackle_set_irq, pci_grackle_map_irq, - pic, address_space,0 ,4 ); + pic, + address_space_mem, + address_space_io, +0 ,4 );pci_create_simple (d->host_state.bus,0 ,"grackle" );
hw/gt64xxx.c +3 -1
@@ -1093,7 +1093,9 @@ PCIBus *gt64120_register(qemu_irq *pic) d =FROM_SYSBUS (GT64120State, s); d->pci.bus =pci_register_bus (&d->busdev.qdev,"pci" , gt64120_pci_set_irq, gt64120_pci_map_irq, - pic,get_system_memory (), + pic, +get_system_memory (), +get_system_io (),PCI_DEVFN (18 ,0 ),4 ); d->ISD_handle =cpu_register_io_memory (gt64120_read, gt64120_write, d,DEVICE_NATIVE_ENDIAN );
hw/pc.h +3 -1
@@ -179,7 +179,9 @@ struct PCII440FXState;typedef struct PCII440FXState PCII440FXState ;PCIBus *i440fx_init (PCII440FXState **pi440fx_state,int *piix_devfn, -qemu_irq *pic,MemoryRegion *address_space, +qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,ram_addr_t ram_size);void i440fx_init_memory_mappings (PCII440FXState *d);
hw/pc_piix.c +5 -1
@@ -69,6 +69,7 @@ static void ioapic_init(IsaIrqState *isa_irq_state)/* PC hardware initialisation */ static void pc_init1(MemoryRegion *system_memory, + MemoryRegion *system_io, ram_addr_t ram_size, const char *boot_device, const char *kernel_filename,
@@ -129,7 +130,7 @@ static void pc_init1(MemoryRegion *system_memory,if (pci_enabled) { pci_bus =i440fx_init (&i440fx_state, &piix3_devfn, isa_irq, - system_memory, ram_size); + system_memory, system_io, ram_size); }else { pci_bus =NULL ; i440fx_state =NULL ;
@@ -218,6 +219,7 @@ static void pc_init_pci(ram_addr_t ram_size, const char *cpu_model) {pc_init1 (get_system_memory (), +get_system_io (), ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model,1 ,1 );
@@ -231,6 +233,7 @@ static void pc_init_pci_no_kvmclock(ram_addr_t ram_size, const char *cpu_model) {pc_init1 (get_system_memory (), +get_system_io (), ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model,1 ,0 );
@@ -246,6 +249,7 @@ static void pc_init_isa(ram_addr_t ram_size,if (cpu_model ==NULL ) cpu_model ="486" ;pc_init1 (get_system_memory (), +get_system_io (), ram_size, boot_device, kernel_filename, kernel_cmdline, initrd_filename, cpu_model,0 ,1 );
hw/pci.c +12 -6
@@ -264,13 +264,14 @@ int pci_find_domain(const PCIBus *bus)void pci_bus_new_inplace (PCIBus *bus,DeviceState *parent,const char *name, -MemoryRegion *address_space, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,uint8_t devfn_min) {qbus_create_inplace (&bus->qbus, &pci_bus_info, parent, name);assert (PCI_FUNC (devfn_min) ==0 ); bus->devfn_min = devfn_min; - bus->address_space = address_space; + bus->address_space = address_space_mem;/* host bridge */ QLIST_INIT (&bus->child);
@@ -280,13 +281,16 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent, }PCIBus *pci_bus_new (DeviceState *parent,const char *name, -MemoryRegion *address_space,uint8_t devfn_min) +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io, +uint8_t devfn_min) {PCIBus *bus; bus =qemu_mallocz (sizeof (*bus)); bus->qbus.qdev_allocated =1 ; -pci_bus_new_inplace (bus, parent, name, address_space, devfn_min); +pci_bus_new_inplace (bus, parent, name, address_space_mem, + address_space_io, devfn_min);return bus; }
@@ -315,12 +319,14 @@ void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)PCIBus *pci_register_bus (DeviceState *parent,const char *name,pci_set_irq_fn set_irq,pci_map_irq_fn map_irq,void *irq_opaque, -MemoryRegion *address_space, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,uint8_t devfn_min,int nirq) {PCIBus *bus; - bus =pci_bus_new (parent, name, address_space, devfn_min); + bus =pci_bus_new (parent, name, address_space_mem, + address_space_io, devfn_min);pci_bus_irqs (bus, set_irq, map_irq, irq_opaque, nirq);return bus; }
hw/pci.h +7 -3
@@ -239,10 +239,13 @@ typedef int (*pci_hotplug_fn)(DeviceState *qdev, PCIDevice *pci_dev, PCIHotplugState state);void pci_bus_new_inplace (PCIBus *bus,DeviceState *parent,const char *name, -MemoryRegion *address_space, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,uint8_t devfn_min);PCIBus *pci_bus_new (DeviceState *parent,const char *name, -MemoryRegion *address_space,uint8_t devfn_min); +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io, +uint8_t devfn_min);void pci_bus_irqs (PCIBus *bus,pci_set_irq_fn set_irq,pci_map_irq_fn map_irq,void *irq_opaque,int nirq);int pci_bus_get_irq_level (PCIBus *bus,int irq_num);
@@ -250,7 +253,8 @@ void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *dev);PCIBus *pci_register_bus (DeviceState *parent,const char *name,pci_set_irq_fn set_irq,pci_map_irq_fn map_irq,void *irq_opaque, -MemoryRegion *address_space, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,uint8_t devfn_min,int nirq);void pci_device_reset (PCIDevice *dev);void pci_bus_reset (PCIBus *bus);
hw/piix_pci.c +9 -5
@@ -242,7 +242,8 @@ static PCIBus *i440fx_common_init(const char *device_name, PCII440FXState **pi440fx_state, int *piix3_devfn, qemu_irq *pic, - MemoryRegion *address_space, + MemoryRegion *address_space_mem, + MemoryRegion *address_space_io, ram_addr_t ram_size) { DeviceState *dev;
@@ -253,8 +254,9 @@ static PCIBus *i440fx_common_init(const char *device_name, dev =qdev_create (NULL ,"i440FX-pcihost" ); s =FROM_SYSBUS (I440FXState,sysbus_from_qdev (dev)); - s->address_space = address_space; - b =pci_bus_new (&s->busdev.qdev,NULL , s->address_space,0 ); + s->address_space = address_space_mem; + b =pci_bus_new (&s->busdev.qdev,NULL , s->address_space, + address_space_io,0 ); s->bus = b;qdev_init_nofail (dev);
@@ -291,13 +293,15 @@ static PCIBus *i440fx_common_init(const char *device_name, }PCIBus *i440fx_init (PCII440FXState **pi440fx_state,int *piix3_devfn, -qemu_irq *pic,MemoryRegion *address_space, +qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io,ram_addr_t ram_size) {PCIBus *b; b =i440fx_common_init ("i440FX" , pi440fx_state, piix3_devfn, pic, - address_space, ram_size); + address_space_mem, address_space_io, ram_size);return b; }
hw/ppc4xx_pci.c +1 -0
@@ -348,6 +348,7 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4], ppc4xx_pci_map_irq, pci_irqs,get_system_memory (), +get_system_io (), 0, 4); controller->pci_dev = pci_register_device(controller->pci_state.bus,
hw/ppc_mac.h +8 -3
@@ -55,11 +55,16 @@ qemu_irq *heathrow_pic_init(int *pmem_index,/* Grackle PCI */ PCIBus *pci_grackle_init (uint32_t base,qemu_irq *pic, -MemoryRegion *address_space); +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io);/* UniNorth PCI */ -PCIBus *pci_pmac_init (qemu_irq *pic,MemoryRegion *address_space); -PCIBus *pci_pmac_u3_init (qemu_irq *pic,MemoryRegion *address_space); +PCIBus *pci_pmac_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io); +PCIBus *pci_pmac_u3_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io);/* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState ;
hw/ppc_newworld.c +2 -2
@@ -318,10 +318,10 @@ static void ppc_core99_init (ram_addr_t ram_size, pic =openpic_init (NULL , &pic_mem_index, smp_cpus, openpic_irqs,NULL );if (PPC_INPUT (env) ==PPC_FLAGS_INPUT_970 ) {/* 970 gets a U3 bus */ - pci_bus =pci_pmac_u3_init (pic,get_system_memory ()); + pci_bus =pci_pmac_u3_init (pic,get_system_memory (),get_system_io ()); machine_arch =ARCH_MAC99_U3 ; }else { - pci_bus =pci_pmac_init (pic,get_system_memory ()); + pci_bus =pci_pmac_init (pic,get_system_memory (),get_system_io ()); machine_arch =ARCH_MAC99 ; }/* init basic PC hardware */
hw/ppc_oldworld.c +3 -1
@@ -234,7 +234,9 @@ static void ppc_heathrow_init (ram_addr_t ram_size,hw_error ("Only 6xx bus is supported on heathrow machine\n" ); } pic =heathrow_pic_init (&pic_mem_index,1 , heathrow_irqs); - pci_bus =pci_grackle_init (0xfec00000 , pic,get_system_memory ()); + pci_bus =pci_grackle_init (0xfec00000 , pic, +get_system_memory (), +get_system_io ());pci_vga_init (pci_bus); escc_mem_index = escc_init(0x80013000, pic[0x0f], pic[0x10], serial_hds[0],
hw/ppc_prep.c +1 -1
@@ -649,7 +649,7 @@ static void ppc_prep_init (ram_addr_t ram_size,hw_error ("Only 6xx bus is supported on PREP machine\n" ); } i8259 =i8259_init (first_cpu->irq_inputs[PPC6xx_INPUT_INT]); - pci_bus =pci_prep_init (i8259,get_system_memory ()); + pci_bus =pci_prep_init (i8259,get_system_memory (),get_system_io ());/* Hmm, prep has no pci-isa bridge ??? */ isa_bus_new (NULL );isa_bus_irqs (i8259);
hw/ppce500_pci.c +4 -3
@@ -282,7 +282,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev)PPCE500PCIState *s;PCIBus *b;int i; -MemoryRegion *address_space =get_system_memory (); +MemoryRegion *address_space_mem =get_system_memory (); +MemoryRegion *address_space_io =get_system_io (); h =FROM_SYSBUS (PCIHostState,sysbus_from_qdev (dev)); s =DO_UPCAST (PPCE500PCIState, pci_state, h);
@@ -292,8 +293,8 @@ static int e500_pcihost_initfn(SysBusDevice *dev) } b =pci_register_bus (&s->pci_state.busdev.qdev,NULL , mpc85xx_pci_set_irq, - mpc85xx_pci_map_irq, s->irq, address_space, -PCI_DEVFN (0x11 ,0 ),4 ); + mpc85xx_pci_map_irq, s->irq, address_space_mem, + address_space_io,PCI_DEVFN (0x11 ,0 ),4 ); s->pci_state.bus = b;pci_create_simple (b,0 ,"e500-host-bridge" );
hw/prep_pci.c +6 -2
@@ -110,7 +110,9 @@ static void prep_set_irq(void *opaque, int irq_num, int level)qemu_set_irq (pic[(irq_num &1 ) ?11 :9 ] , level); } -PCIBus *pci_prep_init (qemu_irq *pic,MemoryRegion *address_space) +PCIBus *pci_prep_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io) {PREPPCIState *s;PCIDevice *d;
@@ -119,7 +121,9 @@ PCIBus *pci_prep_init(qemu_irq *pic, MemoryRegion *address_space) s =qemu_mallocz (sizeof (PREPPCIState)); s->bus =pci_register_bus (NULL ,"pci" , prep_set_irq, prep_map_irq, pic, - address_space,0 ,4 ); + address_space_mem, + address_space_io, +0 ,4 );pci_host_conf_register_ioport (0xcf8 , s);
hw/prep_pci.h +3 -1
@@ -4,6 +4,8 @@#include "qemu-common.h" #include "memory.h" -PCIBus *pci_prep_init (qemu_irq *pic,MemoryRegion *address_space); +PCIBus *pci_prep_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io);#endif
hw/sh_pci.c +3 -1
@@ -128,7 +128,9 @@ static int sh_pci_init_device(SysBusDevice *dev) } s->bus =pci_register_bus (&s->busdev.qdev,"pci" , sh_pci_set_irq, sh_pci_map_irq, - s->irq,get_system_memory (), + s->irq, +get_system_memory (), +get_system_io (),PCI_DEVFN (0 ,0 ),4 ); s->memconfig =cpu_register_io_memory (sh_pci_reg.r, sh_pci_reg.w, s,DEVICE_NATIVE_ENDIAN );
hw/unin_pci.c +12 -4
@@ -201,7 +201,9 @@ static int pci_unin_internal_init_device(SysBusDevice *dev)return 0 ; } -PCIBus *pci_pmac_init (qemu_irq *pic,MemoryRegion *address_space) +PCIBus *pci_pmac_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io) {DeviceState *dev;SysBusDevice *s;
@@ -215,7 +217,9 @@ PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space) d =FROM_SYSBUS (UNINState, s); d->host_state.bus =pci_register_bus (&d->busdev.qdev,"pci" , pci_unin_set_irq, pci_unin_map_irq, - pic, address_space, + pic, + address_space_mem, + address_space_io,PCI_DEVFN (11 ,0 ),4 );#if 0
@@ -253,7 +257,9 @@ PCIBus *pci_pmac_init(qemu_irq *pic, MemoryRegion *address_space)return d->host_state.bus; } -PCIBus *pci_pmac_u3_init (qemu_irq *pic,MemoryRegion *address_space) +PCIBus *pci_pmac_u3_init (qemu_irq *pic, +MemoryRegion *address_space_mem, +MemoryRegion *address_space_io) {DeviceState *dev;SysBusDevice *s;
@@ -268,7 +274,9 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic, MemoryRegion *address_space) d->host_state.bus =pci_register_bus (&d->busdev.qdev,"pci" , pci_unin_set_irq, pci_unin_map_irq, - pic, address_space, + pic, + address_space_mem, + address_space_io,PCI_DEVFN (11 ,0 ),4 );sysbus_mmio_map (s,0 ,0xf0800000 );
hw/versatile_pci.c +1 -1
@@ -112,7 +112,7 @@ static int pci_vpb_init(SysBusDevice *dev) } bus =pci_register_bus (&dev->qdev,"pci" , pci_vpb_set_irq, pci_vpb_map_irq, s->irq, -get_system_memory (), +get_system_memory (),get_system_io (),PCI_DEVFN (11 ,0 ),4 );/* ??? Register memory space. */
Signature · 1 line
1.7.5.3
PATCH v4 12/39 pci: allow I/O BARs to be registered with pci_register_bar_region()
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 43 +++++++++++++++++++++++-------------------- hw/pci.h | 1 + hw/pci_internals.h | 3 ++- 3 files changed, 26 insertions(+), 21 deletions(-)
hw/pci.c +23 -20
@@ -271,7 +271,8 @@ void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,qbus_create_inplace (&bus->qbus, &pci_bus_info, parent, name);assert (PCI_FUNC (devfn_min) ==0 ); bus->devfn_min = devfn_min; - bus->address_space = address_space_mem; + bus->address_space_mem = address_space_mem; + bus->address_space_io = address_space_io;/* host bridge */ QLIST_INIT (&bus->child);
@@ -847,12 +848,11 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev) r = &pci_dev->io_regions[i];if (!r->size || r->addr ==PCI_BAR_UNMAPPED )continue ; -if (r->type ==PCI_BASE_ADDRESS_SPACE_IO ) { -isa_unassign_ioport (r->addr, r->filtered_size); +if (r->memory) { +memory_region_del_subregion (r->address_space, r->memory); }else { -if (r->memory) { -memory_region_del_subregion (pci_dev->bus->address_space, - r->memory); +if (r->type ==PCI_BASE_ADDRESS_SPACE_IO ) { +isa_unassign_ioport (r->addr, r->filtered_size); }else { cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus, r->addr),
@@ -934,9 +934,11 @@ static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num, pcibus_t addr, pcibus_t size, int type) { - memory_region_add_subregion_overlap(pci_dev->bus->address_space, + PCIIORegion *r = &pci_dev->io_regions[region_num]; + +memory_region_add_subregion_overlap (r->address_space, addr, - pci_dev->io_regions[region_num].memory, + r->memory,1 ); }
@@ -953,9 +955,13 @@ void pci_register_bar_region(PCIDevice *pci_dev, int region_num, uint8_t attr, MemoryRegion *memory) {pci_register_bar (pci_dev ,region_num ,memory_region_size (memory ), - PCI_BASE_ADDRESS_SPACE_MEMORY | attr, +attr ,pci_simple_bar_mapfunc_region ); pci_dev->io_regions[region_num].memory = memory; + pci_dev->io_regions[region_num].address_space + = attr &PCI_BASE_ADDRESS_SPACE_IO + ? pci_dev->bus->address_space_io + : pci_dev->bus->address_space_mem; }pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num)
@@ -1090,7 +1096,9 @@ static void pci_update_mappings(PCIDevice *d)/* now do the real mapping */ if (r->addr !=PCI_BAR_UNMAPPED ) { -if (r->type &PCI_BASE_ADDRESS_SPACE_IO ) { +if (r->memory) { +memory_region_del_subregion (r->address_space, r->memory); + }else if (r->type &PCI_BASE_ADDRESS_SPACE_IO ) {int class;/* NOTE: specific hack for IDE in PC case: only one byte must be mapped. */
@@ -1101,16 +1109,11 @@ static void pci_update_mappings(PCIDevice *d)isa_unassign_ioport (r->addr, r->filtered_size); } }else { -if (r->memory) { -memory_region_del_subregion (d->bus->address_space, - r->memory); - }else { -cpu_register_physical_memory (pci_to_cpu_addr (d->bus, - r->addr), - r->filtered_size, -IO_MEM_UNASSIGNED ); -qemu_unregister_coalesced_mmio (r->addr, r->filtered_size); - } +cpu_register_physical_memory (pci_to_cpu_addr (d->bus, + r->addr), + r->filtered_size, +IO_MEM_UNASSIGNED ); +qemu_unregister_coalesced_mmio (r->addr, r->filtered_size); } } r->addr = new_addr;
hw/pci.h +1 -0
@@ -95,6 +95,7 @@ typedef struct PCIIORegion {PCIMapIORegionFunc *map_func;ram_addr_t ram_addr;MemoryRegion *memory; +MemoryRegion *address_space; } PCIIORegion;#define PCI_ROM_SLOT 6
hw/pci_internals.h +2 -1
@@ -25,7 +25,8 @@ struct PCIBus {PCIDevice *devices[PCI_SLOT_MAX *PCI_FUNC_MAX ];PCIDevice *parent_dev;target_phys_addr_t mem_base; -MemoryRegion *address_space; +MemoryRegion *address_space_mem; +MemoryRegion *address_space_io; QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */QLIST_ENTRY (PCIBus) sibling;/* this will be replaced by qdev later */
Signature · 1 line
1.7.5.3
PATCH v4 13/39 rtl8139: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/rtl8139.c | 72 ++++++++++++++++++++++++++++++--------------------------- 1 files changed, 38 insertions(+), 34 deletions(-)
hw/rtl8139.c +38 -34
@@ -474,7 +474,6 @@ typedef struct RTL8139State {NICState *nic;NICConf conf; -int rtl8139_mmio_io_addr;/* C ring mode */ uint32_t currTxDesc;
@@ -506,6 +505,9 @@ typedef struct RTL8139State {QEMUTimer *timer;int64_t TimerExpire; +MemoryRegion bar_io; +MemoryRegion bar_mem; +/* Support migration to/from old versions */ int rtl8139_mmio_io_addr_dummy; } RTL8139State;
@@ -3283,7 +3285,7 @@ static void rtl8139_pre_save(void *opaque)rtl8139_set_next_tctr_time (s, current_time); s->TCTR =muldiv64 (current_time - s->TCTR_base,PCI_FREQUENCY ,get_ticks_per_sec ()); - s->rtl8139_mmio_io_addr_dummy = s->rtl8139_mmio_io_addr; + s->rtl8139_mmio_io_addr_dummy =0 ; }static const VMStateDescription vmstate_rtl8139 = {
@@ -3379,31 +3381,35 @@ static const VMStateDescription vmstate_rtl8139 = {/***********************************************************/ /* PCI RTL8139 definitions */ -static void rtl8139_ioport_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -RTL8139State *s =DO_UPCAST (RTL8139State, dev, pci_dev); - -register_ioport_write (addr,0x100 ,1 , rtl8139_ioport_writeb, s); -register_ioport_read ( addr,0x100 ,1 , rtl8139_ioport_readb, s); - -register_ioport_write (addr,0x100 ,2 , rtl8139_ioport_writew, s); -register_ioport_read ( addr,0x100 ,2 , rtl8139_ioport_readw, s); - -register_ioport_write (addr,0x100 ,4 , rtl8139_ioport_writel, s); -register_ioport_read ( addr,0x100 ,4 , rtl8139_ioport_readl, s); -} +static const MemoryRegionPortio rtl8139_portio[] = { + {0 ,0x100 ,1 , .read = rtl8139_ioport_readb, }, + {0 ,0x100 ,1 , .write = rtl8139_ioport_writeb, }, + {0 ,0x100 ,2 , .read = rtl8139_ioport_readw, }, + {0 ,0x100 ,2 , .write = rtl8139_ioport_writew, }, + {0 ,0x100 ,4 , .read = rtl8139_ioport_readl, }, + {0 ,0x100 ,4 , .write = rtl8139_ioport_writel, }, +PORTIO_END_OF_LIST () +}; -static CPUReadMemoryFunc *const rtl8139_mmio_read[3 ] = { - rtl8139_mmio_readb, - rtl8139_mmio_readw, - rtl8139_mmio_readl, +static const MemoryRegionOps rtl8139_io_ops = { + .old_portio = rtl8139_portio, + .endianness =DEVICE_LITTLE_ENDIAN , }; -static CPUWriteMemoryFunc *const rtl8139_mmio_write[3 ] = { - rtl8139_mmio_writeb, - rtl8139_mmio_writew, - rtl8139_mmio_writel, +static const MemoryRegionOps rtl8139_mmio_ops = { + .old_mmio = { + .read = { + rtl8139_mmio_readb, + rtl8139_mmio_readw, + rtl8139_mmio_readl, + }, + .write = { + rtl8139_mmio_writeb, + rtl8139_mmio_writew, + rtl8139_mmio_writel, + }, + }, + .endianness =DEVICE_LITTLE_ENDIAN , };static void rtl8139_timer (void *opaque)
@@ -3432,7 +3438,8 @@ static int pci_rtl8139_uninit(PCIDevice *dev) {RTL8139State *s =DO_UPCAST (RTL8139State, dev, dev); -cpu_unregister_io_memory (s->rtl8139_mmio_io_addr); +memory_region_destroy (&s->bar_io); +memory_region_destroy (&s->bar_mem);if (s->cplus_txbuffer) {qemu_free (s->cplus_txbuffer); s->cplus_txbuffer =NULL ;
@@ -3462,15 +3469,12 @@ static int pci_rtl8139_init(PCIDevice *dev)* list bit in status register, and offset 0xdc seems unused. */ pci_conf[PCI_CAPABILITY_LIST ] =0xdc ; -/* I/O handler for memory-mapped I/O */ - s->rtl8139_mmio_io_addr = -cpu_register_io_memory (rtl8139_mmio_read, rtl8139_mmio_write, s, -DEVICE_LITTLE_ENDIAN ); - -pci_register_bar (&s->dev,0 ,0x100 , -PCI_BASE_ADDRESS_SPACE_IO , rtl8139_ioport_map); - -pci_register_bar_simple (&s->dev,1 ,0x100 ,0 , s->rtl8139_mmio_io_addr); +memory_region_init_io (&s->bar_io, &rtl8139_io_ops, s,"rtl8139" ,0x100 ); +memory_region_init_io (&s->bar_mem, &rtl8139_mmio_ops, s,"rtl8139" ,0x100 ); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , + &s->bar_io); +pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->bar_mem);qemu_macaddr_default_if_unset (&s->conf.macaddr);
Signature · 1 line
1.7.5.3
PATCH v4 14/39 ac97: convert to memory API
In reply to Avi Kivityfixes BAR sizing as well.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ac97.c | 89 +++++++++++++++++++++++++++++++++++------------------------- 1 files changed, 52 insertions(+), 37 deletions(-)
hw/ac97.c +52 -37
@@ -160,8 +160,9 @@ typedef struct AC97LinkState {SWVoiceIn *voice_mc;int invalid_freq[3 ];uint8_t silence[128 ]; -uint32_t base[2 ];int bup_flag; +MemoryRegion io_nam; +MemoryRegion io_nabm; } AC97LinkState;enum {
@@ -583,7 +584,7 @@ static uint32_t nam_readw (void *opaque, uint32_t addr) {AC97LinkState *s = opaque;uint32_t val = ~0U ; -uint32_t index = addr - s->base[0 ]; +uint32_t index = addr; s->cas =0 ; val =mixer_load (s, index);return val;
@@ -611,7 +612,7 @@ static void nam_writeb (void *opaque, uint32_t addr, uint32_t val)static void nam_writew (void *opaque,uint32_t addr,uint32_t val) {AC97LinkState *s = opaque; -uint32_t index = addr - s->base[0 ]; +uint32_t index = addr; s->cas =0 ;switch (index) {case AC97_Reset:
@@ -714,7 +715,7 @@ static uint32_t nabm_readb (void *opaque, uint32_t addr) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;uint32_t val = ~0U ;switch (index) {
@@ -769,7 +770,7 @@ static uint32_t nabm_readw (void *opaque, uint32_t addr) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;uint32_t val = ~0U ;switch (index) {
@@ -798,7 +799,7 @@ static uint32_t nabm_readl (void *opaque, uint32_t addr) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;uint32_t val = ~0U ;switch (index) {
@@ -848,7 +849,7 @@ static void nabm_writeb (void *opaque, uint32_t addr, uint32_t val) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;switch (index) {case PI_LVI :case PO_LVI :
@@ -904,7 +905,7 @@ static void nabm_writew (void *opaque, uint32_t addr, uint32_t val) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;switch (index) {case PI_SR :case PO_SR :
@@ -924,7 +925,7 @@ static void nabm_writel (void *opaque, uint32_t addr, uint32_t val) {AC97LinkState *s = opaque;AC97BusMasterRegs *r =NULL ; -uint32_t index = addr - s->base[1 ]; +uint32_t index = addr;switch (index) {case PI_BDBAR :case PO_BDBAR :
@@ -1230,31 +1231,33 @@ static const VMStateDescription vmstate_ac97 = { } }; -static void ac97_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -AC97LinkState *s =DO_UPCAST (AC97LinkState, dev, pci_dev); -PCIDevice *d = &s->dev; - -if (!region_num) { - s->base[0 ] = addr; -register_ioport_read (addr,256 *1 ,1 , nam_readb, d); -register_ioport_read (addr,256 *2 ,2 , nam_readw, d); -register_ioport_read (addr,256 *4 ,4 , nam_readl, d); -register_ioport_write (addr,256 *1 ,1 , nam_writeb, d); -register_ioport_write (addr,256 *2 ,2 , nam_writew, d); -register_ioport_write (addr,256 *4 ,4 , nam_writel, d); - } -else { - s->base[1 ] = addr; -register_ioport_read (addr,64 *1 ,1 , nabm_readb, d); -register_ioport_read (addr,64 *2 ,2 , nabm_readw, d); -register_ioport_read (addr,64 *4 ,4 , nabm_readl, d); -register_ioport_write (addr,64 *1 ,1 , nabm_writeb, d); -register_ioport_write (addr,64 *2 ,2 , nabm_writew, d); -register_ioport_write (addr,64 *4 ,4 , nabm_writel, d); - } -} +static const MemoryRegionPortio nam_portio[] = { + {0 ,256 *1 ,1 , .read = nam_readb, }, + {0 ,256 *2 ,2 , .read = nam_readw, }, + {0 ,256 *4 ,4 , .read = nam_readl, }, + {0 ,256 *1 ,1 , .write = nam_writeb, }, + {0 ,256 *2 ,2 , .write = nam_writew, }, + {0 ,256 *4 ,4 , .write = nam_writel, }, +PORTIO_END_OF_LIST (), +}; + +static const MemoryRegionOps ac97_io_nam_ops = { + .old_portio = nam_portio, +}; + +static const MemoryRegionPortio nabm_portio[] = { + {0 ,64 *1 ,1 , .read = nabm_readb, }, + {0 ,64 *2 ,2 , .read = nabm_readw, }, + {0 ,64 *4 ,4 , .read = nabm_readl, }, + {0 ,64 *1 ,1 , .write = nabm_writeb, }, + {0 ,64 *2 ,2 , .write = nabm_writew, }, + {0 ,64 *4 ,4 , .write = nabm_writel, }, +PORTIO_END_OF_LIST () +}; + +static const MemoryRegionOps ac97_io_nabm_ops = { + .old_portio = nabm_portio, +};static void ac97_on_reset (void *opaque) {
@@ -1311,15 +1314,26 @@ static int ac97_initfn (PCIDevice *dev)/* TODO: RST# value should be 0. */ c[PCI_INTERRUPT_PIN ] =0x01 ;/* intr_pn interrupt pin ro */ -pci_register_bar (&s->dev,0 ,256 *4 ,PCI_BASE_ADDRESS_SPACE_IO , - ac97_map); -pci_register_bar (&s->dev,1 ,64 *4 ,PCI_BASE_ADDRESS_SPACE_IO , ac97_map); +memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s,"ac97-nam" ,1024 ); +memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s,"ac97-nabm" ,256 ); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_nam); +pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , + &s->io_nabm);qemu_register_reset (ac97_on_reset, s);AUD_register_card ("ac97" , &s->card);ac97_on_reset (s);return 0 ; } +static int ac97_exitfn (PCIDevice *dev) +{ +AC97LinkState *s =DO_UPCAST (AC97LinkState, dev, dev); + +memory_region_destroy (&s->io_nam); +memory_region_destroy (&s->io_nabm); +return 0 ; +} +int ac97_init (PCIBus *bus) {pci_create_simple (bus,-1 ,"AC97" );
@@ -1332,6 +1346,7 @@ static PCIDeviceInfo ac97_info = { .qdev.size = sizeof (AC97LinkState), .qdev.vmsd = &vmstate_ac97, .init = ac97_initfn, + .exit = ac97_exitfn, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801AA_5, .revision = 0x01,
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 14/39] ac97: convert to memory API
Quoted 1 line · Avi Kivity
fixes BAR sizing as well.
I'm fine with this version, thanks.
[..snip..]
Signature · 1 line
mailto:[email protected]
PATCH v4 15/39 e1000: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/e1000.c | 114 +++++++++++++++++++++++++---------------------------------- 1 files changed, 48 insertions(+), 66 deletions(-)
hw/e1000.c +48 -66
@@ -82,7 +82,8 @@ typedef struct E1000State_st {PCIDevice dev;NICState *nic;NICConf conf; -int mmio_index; +MemoryRegion mmio; +MemoryRegion io;uint32_t mac_reg[0x8000 ];uint16_t phy_reg[0x20 ];
@@ -151,14 +152,6 @@ static const char phy_regcap[0x20] = { };static void -ioport_map (PCIDevice *pci_dev,int region_num,pcibus_t addr, -pcibus_t size,int type) -{ -DBGOUT (IO ,"e1000_ioport_map addr=0x%04" FMT_PCIBUS -" size=0x%08" FMT_PCIBUS "\n" , addr, size); -} - -static void set_interrupt_cause (E1000State *s,int index,uint32_t val) {if (val)
@@ -905,7 +898,8 @@ static void (*macreg_writeops[])(E1000State *, int, uint32_t) = {enum {NWRITEOPS =ARRAY_SIZE (macreg_writeops) };static void -e1000_mmio_writel (void *opaque,target_phys_addr_t addr,uint32_t val) +e1000_mmio_write (void *opaque,target_phys_addr_t addr,uint64_t val, +unsigned size) {E1000State *s = opaque;unsigned int index = (addr &0x1ffff ) >>2 ;
@@ -913,31 +907,15 @@ e1000_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)if (index <NWRITEOPS && macreg_writeops[index]) { macreg_writeops[index](s, index, val); }else if (index <NREADOPS && macreg_readops[index]) { -DBGOUT (MMIO ,"e1000_mmio_writel RO %x: 0x%04x\n" , index<<2 , val); +DBGOUT (MMIO ,"e1000_mmio_writel RO %x: 0x%04" PRIx64"\n" , index<<2 , val); }else { -DBGOUT (UNKNOWN ,"MMIO unknown write addr=0x%08x,val=0x%08x\n" , +DBGOUT (UNKNOWN ,"MMIO unknown write addr=0x%08x,val=0x%08" PRIx64"\n" , index<<2 , val); } } -static void -e1000_mmio_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -// emulate hw without byte enables: no RMW -e1000_mmio_writel (opaque, addr & ~3 , - (val &0xffff ) << (8 *(addr &3 ))); -} - -static void -e1000_mmio_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -// emulate hw without byte enables: no RMW -e1000_mmio_writel (opaque, addr & ~3 , - (val &0xff ) << (8 *(addr &3 ))); -} - -static uint32_t -e1000_mmio_readl (void *opaque,target_phys_addr_t addr) +static uint64_t +e1000_mmio_read (void *opaque,target_phys_addr_t addr,unsigned size) {E1000State *s = opaque;unsigned int index = (addr &0x1ffff ) >>2 ;
@@ -950,20 +928,39 @@ e1000_mmio_readl(void *opaque, target_phys_addr_t addr)return 0 ; } -static uint32_t -e1000_mmio_readb (void *opaque,target_phys_addr_t addr) +static const MemoryRegionOps e1000_mmio_ops = { + .read = e1000_mmio_read, + .write = e1000_mmio_write, + .endianness =DEVICE_LITTLE_ENDIAN , + .impl = { + .min_access_size =4 , + .max_access_size =4 , + }, +}; + +static uint64_t e1000_io_read (void *opaque,target_phys_addr_t addr, +unsigned size) { -return ((e1000_mmio_readl (opaque, addr & ~3 )) >> - (8 * (addr &3 ))) &0xff ; +E1000State *s = opaque; + + (void )s; +return 0 ; } -static uint32_t -e1000_mmio_readw (void *opaque,target_phys_addr_t addr) +static void e1000_io_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) { -return ((e1000_mmio_readl (opaque, addr & ~3 )) >> - (8 * (addr &3 ))) &0xffff ; +E1000State *s = opaque; + + (void )s; } +static const MemoryRegionOps e1000_io_ops = { + .read = e1000_io_read, + .write = e1000_io_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; +static bool is_version_1 (void *opaque,int version_id) {return version_id ==1 ;
@@ -1083,36 +1080,22 @@ static const uint32_t mac_reg_init[] = {/* PCI interface */ -static CPUWriteMemoryFunc *const e1000_mmio_write[] = { - e1000_mmio_writeb, e1000_mmio_writew, e1000_mmio_writel -}; - -static CPUReadMemoryFunc *const e1000_mmio_read[] = { - e1000_mmio_readb, e1000_mmio_readw, e1000_mmio_readl -}; -static void -e1000_mmio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) +e1000_mmio_setup (E1000State *d) { -E1000State *d =DO_UPCAST (E1000State, dev, pci_dev);int i;const uint32_t excluded_regs[] = {E1000_MDIC ,E1000_ICR ,E1000_ICS ,E1000_IMS ,E1000_IMC ,E1000_TCTL ,E1000_TDT ,PNPMMIO_SIZE }; - -DBGOUT (MMIO ,"e1000_mmio_map addr=0x%08" FMT_PCIBUS " 0x%08" FMT_PCIBUS "\n" , - addr, size); - -cpu_register_physical_memory (addr,PNPMMIO_SIZE , d->mmio_index); -qemu_register_coalesced_mmio (addr, excluded_regs[0 ]); - +memory_region_init_io (&d->mmio, &e1000_mmio_ops, d,"e1000-mmio" , +PNPMMIO_SIZE ); +memory_region_add_coalescing (&d->mmio,0 , excluded_regs[0 ]);for (i =0 ; excluded_regs[i] !=PNPMMIO_SIZE ; i++) -qemu_register_coalesced_mmio (addr + excluded_regs[i] +4 , - excluded_regs[i +1 ] - - excluded_regs[i] -4 ); +memory_region_add_coalescing (&d->mmio, excluded_regs[i] +4 , + excluded_regs[i+1 ] - excluded_regs[i] -4 ); +memory_region_init_io (&d->io, &e1000_io_ops, d,"e1000-io" ,IOPORT_SIZE ); } static void
@@ -1128,7 +1111,8 @@ pci_e1000_uninit(PCIDevice *dev) {E1000State *d =DO_UPCAST (E1000State, dev, dev); -cpu_unregister_io_memory (d->mmio_index); +memory_region_destroy (&d->mmio); +memory_region_destroy (&d->io);qemu_del_vlan_client (&d->nic->nc);return 0 ; }
@@ -1172,14 +1156,12 @@ static int pci_e1000_init(PCIDevice *pci_dev)/* TODO: RST# value should be 0 if programmable, PCI spec 6.2.4 */ pci_conf[PCI_INTERRUPT_PIN ] =1 ;// interrupt pin 0 - d->mmio_index =cpu_register_io_memory (e1000_mmio_read, - e1000_mmio_write, d,DEVICE_LITTLE_ENDIAN ); +e1000_mmio_setup (d); -pci_register_bar (&d->dev,0 ,PNPMMIO_SIZE , -PCI_BASE_ADDRESS_SPACE_MEMORY , e1000_mmio_map); +pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &d->mmio); -pci_register_bar (&d->dev,1 ,IOPORT_SIZE , -PCI_BASE_ADDRESS_SPACE_IO , ioport_map); +pci_register_bar_region (&d->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &d->io);memmove (d->eeprom_data, e1000_eeprom_template,sizeof e1000_eeprom_template);
Signature · 1 line
1.7.5.3
PATCH v4 16/39 eepro100: convert to memory API
In reply to Avi KivityNote: the existing code aliases the flash BAR into the MMIO bar. This is probably a bug. This patch does not correct the problem.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/eepro100.c | 182 ++++++++++++--------------------------------------------- 1 files changed, 37 insertions(+), 145 deletions(-)
hw/eepro100.c +37 -145
@@ -228,13 +228,14 @@ typedef struct {PCIDevice dev;/* Hash register (multicast mask array, multiple individual addresses). */ uint8_t mult[8 ]; -int mmio_index; +MemoryRegion mmio_bar; +MemoryRegion io_bar; +MemoryRegion flash_bar;NICState *nic;NICConf conf;uint8_t scb_stat;/* SCB stat/ack byte */ uint8_t int_stat;/* PCI interrupt status */ /* region must not be saved by nic_save. */ -uint32_t region1;/* PCI region 1 address */ uint16_t mdimem[32 ];eeprom_t *eeprom;uint32_t device;/* device variant */
@@ -1584,147 +1585,36 @@ static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val) } } -/***************************************************************************** -* -* Port mapped I/O. -* -****************************************************************************/ - -static uint32_t ioport_read1 (void *opaque,uint32_t addr) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s\n" ,regname (addr)); -#endif -return eepro100_read1 (s, addr - s->region1); -} - -static uint32_t ioport_read2 (void *opaque,uint32_t addr) -{ -EEPRO100State *s = opaque; -return eepro100_read2 (s, addr - s->region1); -} - -static uint32_t ioport_read4 (void *opaque,uint32_t addr) -{ -EEPRO100State *s = opaque; -return eepro100_read4 (s, addr - s->region1); -} - -static void ioport_write1 (void *opaque,uint32_t addr,uint32_t val) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s val=0x%02x\n" ,regname (addr), val); -#endif -eepro100_write1 (s, addr - s->region1, val); -} - -static void ioport_write2 (void *opaque,uint32_t addr,uint32_t val) -{ -EEPRO100State *s = opaque; -eepro100_write2 (s, addr - s->region1, val); -} - -static void ioport_write4 (void *opaque,uint32_t addr,uint32_t val) -{ -EEPRO100State *s = opaque; -eepro100_write4 (s, addr - s->region1, val); -} - -/***********************************************************/ -/* PCI EEPRO100 definitions */ - -static void pci_map (PCIDevice * pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -EEPRO100State *s =DO_UPCAST (EEPRO100State, dev, pci_dev); - -TRACE (OTHER ,logout ("region %d, addr=0x%08" FMT_PCIBUS ", " -"size=0x%08" FMT_PCIBUS ", type=%d\n" , - region_num, addr, size, type)); - -assert (region_num ==1 ); -register_ioport_write (addr, size,1 , ioport_write1, s); -register_ioport_read (addr, size,1 , ioport_read1, s); -register_ioport_write (addr, size,2 , ioport_write2, s); -register_ioport_read (addr, size,2 , ioport_read2, s); -register_ioport_write (addr, size,4 , ioport_write4, s); -register_ioport_read (addr, size,4 , ioport_read4, s); - - s->region1 = addr; -} - -/***************************************************************************** -* -* Memory mapped I/O. -* -****************************************************************************/ - -static void pci_mmio_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s val=0x%02x\n" ,regname (addr), val); -#endif -eepro100_write1 (s, addr, val); -} - -static void pci_mmio_writew (void *opaque,target_phys_addr_t addr,uint32_t val) +static uint64_t eepro100_read (void *opaque,target_phys_addr_t addr, +unsigned size) {EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s val=0x%02x\n" ,regname (addr), val); -#endif -eepro100_write2 (s, addr, val); -} -static void pci_mmio_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s val=0x%02x\n" ,regname (addr), val); -#endif -eepro100_write4 (s, addr, val); -} - -static uint32_t pci_mmio_readb (void *opaque,target_phys_addr_t addr) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s\n" ,regname (addr)); -#endif -return eepro100_read1 (s, addr); +switch (size) { +case 1 :return eepro100_read1 (s, addr); +case 2 :return eepro100_read2 (s, addr); +case 4 :return eepro100_read4 (s, addr); +default :abort (); + } } -static uint32_t pci_mmio_readw (void *opaque,target_phys_addr_t addr) +static void eepro100_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) {EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s\n" ,regname (addr)); -#endif -return eepro100_read2 (s, addr); -} -static uint32_t pci_mmio_readl (void *opaque,target_phys_addr_t addr) -{ -EEPRO100State *s = opaque; -#if 0 -logout ("addr=%s\n" ,regname (addr)); -#endif -return eepro100_read4 (s, addr); +switch (size) { +case 1 :return eepro100_write1 (s, addr, data); +case 2 :return eepro100_write2 (s, addr, data); +case 4 :return eepro100_write4 (s, addr, data); +default :abort (); + } } -static CPUWriteMemoryFunc *const pci_mmio_write[] = { - pci_mmio_writeb, - pci_mmio_writew, - pci_mmio_writel -}; - -static CPUReadMemoryFunc *const pci_mmio_read[] = { - pci_mmio_readb, - pci_mmio_readw, - pci_mmio_readl +static const MemoryRegionOps eepro100_ops = { + .read = eepro100_read, + .write = eepro100_write, + .endianness =DEVICE_LITTLE_ENDIAN , };static int nic_can_receive (VLANClientState *nc)
@@ -1953,7 +1843,9 @@ static int pci_nic_uninit(PCIDevice *pci_dev) {EEPRO100State *s =DO_UPCAST (EEPRO100State, dev, pci_dev); -cpu_unregister_io_memory (s->mmio_index); +memory_region_destroy (&s->mmio_bar); +memory_region_destroy (&s->io_bar); +memory_region_destroy (&s->flash_bar);vmstate_unregister (&pci_dev->qdev, s->vmstate, s);eeprom93xx_free (&pci_dev->qdev, s->eeprom);qemu_del_vlan_client (&s->nic->nc);
@@ -1985,20 +1877,20 @@ static int e100_nic_init(PCIDevice *pci_dev) s->eeprom =eeprom93xx_new (&pci_dev->qdev,EEPROM_SIZE );/* Handler for memory-mapped I/O */ - s->mmio_index = -cpu_register_io_memory (pci_mmio_read, pci_mmio_write, s, -DEVICE_LITTLE_ENDIAN ); - -pci_register_bar_simple (&s->dev,0 ,PCI_MEM_SIZE , -PCI_BASE_ADDRESS_MEM_PREFETCH , s->mmio_index); - -pci_register_bar (&s->dev,1 ,PCI_IO_SIZE ,PCI_BASE_ADDRESS_SPACE_IO , - pci_map); -pci_register_bar_simple (&s->dev,2 ,PCI_FLASH_SIZE ,0 , s->mmio_index); +memory_region_init_io (&s->mmio_bar, &eepro100_ops, s,"eepro100-mmio" , +PCI_MEM_SIZE ); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , + &s->mmio_bar); +memory_region_init_io (&s->io_bar, &eepro100_ops, s,"eepro100-io" , +PCI_IO_SIZE ); +pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar); +/* FIXME: flash aliases to mmio?! */ +memory_region_init_io (&s->flash_bar, &eepro100_ops, s,"eepro100-flash" , +PCI_FLASH_SIZE ); +pci_register_bar_region (&s->dev,2 ,0 , &s->flash_bar);qemu_macaddr_default_if_unset (&s->conf.macaddr);logout ("macaddr: %s\n" ,nic_dump (&s->conf.macaddr.a[0 ],6 )); -assert (s->region1 ==0 );nic_reset (s);
Signature · 1 line
1.7.5.3
PATCH v4 17/39 es1370: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/es1370.c | 43 +++++++++++++++++++++++++------------------ 1 files changed, 25 insertions(+), 18 deletions(-)
hw/es1370.c +25 -18
@@ -268,6 +268,7 @@ struct chan { typedef struct ES1370State { PCIDevice dev; QEMUSoundCard card; + MemoryRegion io; struct chan chan[NB_CHANNELS]; SWVoiceOut *dac_voice[2]; SWVoiceIn *adc_voice;
@@ -775,7 +776,6 @@ IO_READ_PROTO (es1370_readl)return val; } -static void es1370_transfer_audio (ES1370State *s,struct chan *d,int loop_sel,int max,int *irq) {
@@ -906,23 +906,20 @@ static void es1370_adc_callback (void *opaque, int avail)es1370_run_channel (s,ADC_CHANNEL , avail); } -static void es1370_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -ES1370State *s =DO_UPCAST (ES1370State, dev, pci_dev); - - (void ) region_num; - (void ) size; - (void ) type; - -register_ioport_write (addr,0x40 *4 ,1 , es1370_writeb, s); -register_ioport_write (addr,0x40 *2 ,2 , es1370_writew, s); -register_ioport_write (addr,0x40 ,4 , es1370_writel, s); +static const MemoryRegionPortio es1370_portio[] = { + {0 ,0x40 *4 ,1 , .write = es1370_writeb, }, + {0 ,0x40 *2 ,2 , .write = es1370_writew, }, + {0 ,0x40 ,4 , .write = es1370_writel, }, + {0 ,0x40 *4 ,1 , .read = es1370_readb, }, + {0 ,0x40 *2 ,2 , .read = es1370_readw, }, + {0 ,0x40 ,4 , .read = es1370_readl, }, +PORTIO_END_OF_LIST () +}; -register_ioport_read (addr,0x40 *4 ,1 , es1370_readb, s); -register_ioport_read (addr,0x40 *2 ,2 , es1370_readw, s); -register_ioport_read (addr,0x40 ,4 , es1370_readl, s); -} +static const MemoryRegionOps es1370_io_ops = { + .old_portio = es1370_portio, + .endianness =DEVICE_LITTLE_ENDIAN , +};static const VMStateDescription vmstate_es1370_channel = { .name ="es1370_channel" ,
@@ -1011,7 +1008,8 @@ static int es1370_initfn (PCIDevice *dev) c[PCI_MIN_GNT ] =0x0c ; c[PCI_MAX_LAT ] =0x80 ; -pci_register_bar (&s->dev,0 ,256 ,PCI_BASE_ADDRESS_SPACE_IO , es1370_map); +memory_region_init_io (&s->io, &es1370_io_ops, s,"es1370" ,256 ); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io);qemu_register_reset (es1370_on_reset, s);AUD_register_card ("es1370" , &s->card);
@@ -1019,6 +1017,14 @@ static int es1370_initfn (PCIDevice *dev)return 0 ; } +static int es1370_exitfn (PCIDevice *dev) +{ +ES1370State *s =DO_UPCAST (ES1370State, dev, dev); + +memory_region_destroy (&s->io); +return 0 ; +} +int es1370_init (PCIBus *bus) {pci_create_simple (bus,-1 ,"ES1370" );
@@ -1031,6 +1037,7 @@ static PCIDeviceInfo es1370_info = { .qdev.size = sizeof (ES1370State), .qdev.vmsd = &vmstate_es1370, .init = es1370_initfn, + .exit = es1370_exitfn, .vendor_id = PCI_VENDOR_ID_ENSONIQ, .device_id = PCI_DEVICE_ID_ENSONIQ_ES1370, .class_id = PCI_CLASS_MULTIMEDIA_AUDIO,
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 17/39] es1370: convert to memory API
On Mon, 8 Aug 2011, Avi Kivity wrote:
Fine with this too, thanks.
[..snip..]
Signature · 1 line
mailto:[email protected]
PATCH v4 18/39 ide: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ide/cmd646.c | 208 +++++++++++++++++++++++++++++++++++-------------------- hw/ide/pci.c | 25 ++++--- hw/ide/pci.h | 19 ++++- hw/ide/piix.c | 64 +++++++++++++---- hw/ide/via.c | 65 +++++++++++++---- 5 files changed, 261 insertions(+), 120 deletions(-)
hw/ide/cmd646.c +134 -74
@@ -44,35 +44,95 @@static void cmd646_update_irq (PCIIDEState *d); -static void ide_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) +static uint64_t cmd646_cmd_read (void *opaque,target_phys_addr_t addr, +unsigned size) { -PCIIDEState *d =DO_UPCAST (PCIIDEState, dev, pci_dev); -IDEBus *bus; - -if (region_num <=3 ) { - bus = &d->bus[(region_num >>1 )]; -if (region_num &1 ) { -register_ioport_read (addr +2 ,1 ,1 , ide_status_read, bus); -register_ioport_write (addr +2 ,1 ,1 , ide_cmd_write, bus); +CMD646BAR *cmd646bar = opaque; + +if (addr !=2 || size !=1 ) { +return ((uint64_t )1 << (size *8 )) -1 ; + } +return ide_status_read (cmd646bar->bus, addr +2 ); +} + +static void cmd646_cmd_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) +{ +CMD646BAR *cmd646bar = opaque; + +if (addr !=2 || size !=1 ) { +return ; + } +ide_cmd_write (cmd646bar->bus, addr +2 , data); +} + +static MemoryRegionOps cmd646_cmd_ops = { + .read = cmd646_cmd_read, + .write = cmd646_cmd_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; + +static uint64_t cmd646_data_read (void *opaque,target_phys_addr_t addr, +unsigned size) +{ +CMD646BAR *cmd646bar = opaque; + +if (size ==1 ) { +return ide_ioport_read (cmd646bar->bus, addr); + }else if (addr ==0 ) { +if (size ==2 ) { +return ide_data_readw (cmd646bar->bus, addr); }else { -register_ioport_write (addr,8 ,1 , ide_ioport_write, bus); -register_ioport_read (addr,8 ,1 , ide_ioport_read, bus); - -/* data ports */ -register_ioport_write (addr,2 ,2 , ide_data_writew, bus); -register_ioport_read (addr,2 ,2 , ide_data_readw, bus); -register_ioport_write (addr,4 ,4 , ide_data_writel, bus); -register_ioport_read (addr,4 ,4 , ide_data_readl, bus); +return ide_data_readl (cmd646bar->bus, addr); } } +return ((uint64_t )1 << (size *8 )) -1 ; } -static uint32_t bmdma_readb_common (PCIIDEState *pci_dev,BMDMAState *bm, -uint32_t addr) +static void cmd646_data_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned size) { +CMD646BAR *cmd646bar = opaque; + +if (size ==1 ) { +return ide_ioport_write (cmd646bar->bus, addr, data); + }else if (addr ==0 ) { +if (size ==2 ) { +return ide_data_writew (cmd646bar->bus, addr, data); + }else { +return ide_data_writel (cmd646bar->bus, addr, data); + } + } +} + +static MemoryRegionOps cmd646_data_ops = { + .read = cmd646_data_read, + .write = cmd646_data_write, + .endianness =DEVICE_LITTLE_ENDIAN , +}; + +static void setup_cmd646_bar (PCIIDEState *d,int bus_num) +{ +IDEBus *bus = &d->bus[bus_num]; +CMD646BAR *bar = &d->cmd646_bar[bus_num]; + + bar->bus = bus; + bar->pci_dev = d; +memory_region_init_io (&bar->cmd, &cmd646_cmd_ops, bar,"cmd646-cmd" ,4 ); +memory_region_init_io (&bar->data, &cmd646_data_ops, bar,"cmd646-data" ,8 ); +} + +static uint64_t bmdma_read (void *opaque,target_phys_addr_t addr, +unsigned size) +{ +BMDMAState *bm = opaque; +PCIIDEState *pci_dev = bm->pci_dev;uint32_t val; +if (size !=1 ) { +return ((uint64_t )1 << (size *8 )) -1 ; + } +switch (addr &3 ) {case 0 : val = bm->cmd;
@@ -100,31 +160,22 @@ static uint32_t bmdma_readb_common(PCIIDEState *pci_dev, BMDMAState *bm,return val; } -static uint32_t bmdma_readb_0 (void *opaque,uint32_t addr) +static void bmdma_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) { -PCIIDEState *pci_dev = opaque; -BMDMAState *bm = &pci_dev->bmdma[0 ]; - -return bmdma_readb_common (pci_dev, bm, addr); -} +BMDMAState *bm = opaque; +PCIIDEState *pci_dev = bm->pci_dev; -static uint32_t bmdma_readb_1 (void *opaque,uint32_t addr) -{ -PCIIDEState *pci_dev = opaque; -BMDMAState *bm = &pci_dev->bmdma[1 ]; - -return bmdma_readb_common (pci_dev, bm, addr); -} +if (size !=1 ) { +return ; + } -static void bmdma_writeb_common (PCIIDEState *pci_dev,BMDMAState *bm, -uint32_t addr,uint32_t val) -{#ifdef DEBUG_IDE printf ("bmdma: writeb 0x%02x : 0x%02x\n" , addr, val);#endif switch (addr &3 ) {case 0 : -bmdma_cmd_writeb (bm, addr, val); +bmdma_cmd_writeb (bm, val);break ;case 1 : pci_dev->dev.config[MRDMODE] =
@@ -143,42 +194,25 @@ static void bmdma_writeb_common(PCIIDEState *pci_dev, BMDMAState *bm, } } -static void bmdma_writeb_0 (void *opaque,uint32_t addr,uint32_t val) -{ -PCIIDEState *pci_dev = opaque; -BMDMAState *bm = &pci_dev->bmdma[0 ]; - -bmdma_writeb_common (pci_dev, bm, addr, val); -} - -static void bmdma_writeb_1 (void *opaque,uint32_t addr,uint32_t val) -{ -PCIIDEState *pci_dev = opaque; -BMDMAState *bm = &pci_dev->bmdma[1 ]; - -bmdma_writeb_common (pci_dev, bm, addr, val); -} +static MemoryRegionOps cmd646_bmdma_ops = { + .read = bmdma_read, + .write = bmdma_write, +}; -static void bmdma_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) +static void bmdma_setup_bar (PCIIDEState *d) { -PCIIDEState *d =DO_UPCAST (PCIIDEState, dev, pci_dev); +BMDMAState *bm;int i; +memory_region_init (&d->bmdma_bar,"cmd646-bmdma" ,16 );for (i =0 ;i <2 ; i++) { -BMDMAState *bm = &d->bmdma[i]; - -if (i ==0 ) { -register_ioport_write (addr,4 ,1 , bmdma_writeb_0, d); -register_ioport_read (addr,4 ,1 , bmdma_readb_0, d); - }else { -register_ioport_write (addr,4 ,1 , bmdma_writeb_1, d); -register_ioport_read (addr,4 ,1 , bmdma_readb_1, d); - } - -iorange_init (&bm->addr_ioport, &bmdma_addr_ioport_ops, addr +4 ,4 ); -ioport_register (&bm->addr_ioport); - addr +=8 ; + bm = &d->bmdma[i]; +memory_region_init_io (&bm->extra_io, &cmd646_bmdma_ops, bm, +"cmd646-bmdma-bus" ,4 ); +memory_region_add_subregion (&d->bmdma_bar, i *8 , &bm->extra_io); +memory_region_init_io (&bm->addr_ioport, &bmdma_addr_ioport_ops, bm, +"cmd646-bmdma-ioport" ,4 ); +memory_region_add_subregion (&d->bmdma_bar, i *8 +4 , &bm->addr_ioport); } }
@@ -234,11 +268,18 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev) pci_conf[0x51 ] |=0x08 ;/* enable IDE1 */ } -pci_register_bar (dev,0 ,0x8 ,PCI_BASE_ADDRESS_SPACE_IO , ide_map); -pci_register_bar (dev,1 ,0x4 ,PCI_BASE_ADDRESS_SPACE_IO , ide_map); -pci_register_bar (dev,2 ,0x8 ,PCI_BASE_ADDRESS_SPACE_IO , ide_map); -pci_register_bar (dev,3 ,0x4 ,PCI_BASE_ADDRESS_SPACE_IO , ide_map); -pci_register_bar (dev,4 ,0x10 ,PCI_BASE_ADDRESS_SPACE_IO , bmdma_map); +setup_cmd646_bar (d,0 ); +setup_cmd646_bar (d,1 ); +pci_register_bar_region (dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , + &d->cmd646_bar[0 ].data); +pci_register_bar_region (dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , + &d->cmd646_bar[0 ].cmd); +pci_register_bar_region (dev,2 ,PCI_BASE_ADDRESS_SPACE_IO , + &d->cmd646_bar[1 ].data); +pci_register_bar_region (dev,3 ,PCI_BASE_ADDRESS_SPACE_IO , + &d->cmd646_bar[1 ].cmd); +bmdma_setup_bar (d); +pci_register_bar_region (dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bmdma_bar);/* TODO: RST# value should be 0 */ pci_conf[PCI_INTERRUPT_PIN ] =0x01 ;// interrupt on pin 1
@@ -248,7 +289,7 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)ide_bus_new (&d->bus[i], &d->dev.qdev, i);ide_init2 (&d->bus[i], irq[i]); -bmdma_init (&d->bus[i], &d->bmdma[i]); +bmdma_init (&d->bus[i], &d->bmdma[i], d); d->bmdma[i].bus = &d->bus[i];qemu_add_vm_change_state_handler (d->bus[i].dma->ops->restart_cb, &d->bmdma[i].dma);
@@ -259,6 +300,24 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)return 0 ; } +static int pci_cmd646_ide_exitfn (PCIDevice *dev) +{ +PCIIDEState *d =DO_UPCAST (PCIIDEState, dev, dev); +unsigned i; + +for (i =0 ; i <2 ; ++i) { +memory_region_del_subregion (&d->bmdma_bar, &d->bmdma[i].extra_io); +memory_region_destroy (&d->bmdma[i].extra_io); +memory_region_del_subregion (&d->bmdma_bar, &d->bmdma[i].addr_ioport); +memory_region_destroy (&d->bmdma[i].addr_ioport); +memory_region_destroy (&d->cmd646_bar[i].cmd); +memory_region_destroy (&d->cmd646_bar[i].data); + } +memory_region_destroy (&d->bmdma_bar); + +return 0 ; +} +void pci_cmd646_ide_init (PCIBus *bus,DriveInfo **hd_table,int secondary_ide_enabled) {
@@ -276,6 +335,7 @@ static PCIDeviceInfo cmd646_ide_info[] = { .qdev.name = "cmd646-ide", .qdev.size = sizeof(PCIIDEState), .init = pci_cmd646_ide_initfn, + .exit = pci_cmd646_ide_exitfn, .vendor_id = PCI_VENDOR_ID_CMD, .device_id = PCI_DEVICE_ID_CMD_646, .revision = 0x07, // IDE controller revision
hw/ide/pci.c +14 -11
@@ -287,9 +287,8 @@ static void bmdma_irq(void *opaque, int n, int level)qemu_set_irq (bm->irq, level); } -void bmdma_cmd_writeb (void *opaque,uint32_t addr,uint32_t val) +void bmdma_cmd_writeb (BMDMAState *bm,uint32_t val) { -BMDMAState *bm = opaque;#ifdef DEBUG_IDE printf ("%s: 0x%08x\n" , __func__, val);#endif
@@ -328,22 +327,24 @@ void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val) bm->cmd = val &0x09 ; } -static void bmdma_addr_read (IORange *ioport,uint64_t addr, -unsigned width,uint64_t *data) +static uint64_t bmdma_addr_read (void *opaque,target_phys_addr_t addr, +unsigned width) { -BMDMAState *bm =container_of (ioport, BMDMAState, addr_ioport); +BMDMAState *bm = opaque;uint32_t mask = (1ULL << (width *8 )) -1 ; +uint64_t data; - *data = (bm->addr >> (addr *8 )) & mask; + data = (bm->addr >> (addr *8 )) & mask;#ifdef DEBUG_IDE printf ("%s: 0x%08x\n" , __func__, (unsigned )*data);#endif +return data; } -static void bmdma_addr_write (IORange *ioport,uint64_t addr, -unsigned width,uint64_t data) +static void bmdma_addr_write (void *opaque,target_phys_addr_t addr, +uint64_t data,unsigned width) { -BMDMAState *bm =container_of (ioport, BMDMAState, addr_ioport); +BMDMAState *bm = opaque;int shift = addr *8 ;uint32_t mask = (1ULL << (width *8 )) -1 ;
@@ -354,9 +355,10 @@ static void bmdma_addr_write(IORange *ioport, uint64_t addr, bm->addr |= ((data & mask) << shift) & ~3 ; } -const IORangeOps bmdma_addr_ioport_ops = { +MemoryRegionOps bmdma_addr_ioport_ops = { .read = bmdma_addr_read, .write = bmdma_addr_write, + .endianness =DEVICE_LITTLE_ENDIAN , };static bool ide_bmdma_current_needed (void *opaque)
@@ -514,7 +516,7 @@ static const struct IDEDMAOps bmdma_ops = { .reset = bmdma_reset, }; -void bmdma_init (IDEBus *bus,BMDMAState *bm) +void bmdma_init (IDEBus *bus,BMDMAState *bm,PCIIDEState *d) {qemu_irq *irq;
@@ -527,4 +529,5 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm) bm->irq = bus->irq; irq =qemu_allocate_irqs (bmdma_irq, bm,1 ); bus->irq = *irq; + bm->pci_dev = d; }
hw/ide/pci.h +15 -4
@@ -19,20 +19,31 @@ typedef struct BMDMAState {BlockDriverCompletionFunc *dma_cb;int64_t sector_num;uint32_t nsector; -IORange addr_ioport; +MemoryRegion addr_ioport; +MemoryRegion extra_io;QEMUBH *bh;qemu_irq irq;/* Bit 0-2 and 7: BM status register * Bit 3-6: bus->error_status */ uint8_t migration_compat_status; +struct PCIIDEState *pci_dev; } BMDMAState; +typedef struct CMD646BAR { +MemoryRegion cmd; +MemoryRegion data; +IDEBus *bus; +struct PCIIDEState *pci_dev; +}CMD646BAR ; +typedef struct PCIIDEState {PCIDevice dev;IDEBus bus[2 ];BMDMAState bmdma[2 ];uint32_t secondary;/* used only for cmd646 */ +MemoryRegion bmdma_bar; +CMD646BAR cmd646_bar[2 ];/* used only for cmd646 */ }PCIIDEState ;
@@ -43,9 +54,9 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma) } -void bmdma_init (IDEBus *bus,BMDMAState *bm); -void bmdma_cmd_writeb (void *opaque,uint32_t addr,uint32_t val); -extern const IORangeOps bmdma_addr_ioport_ops; +void bmdma_init (IDEBus *bus,BMDMAState *bm,PCIIDEState *d); +void bmdma_cmd_writeb (BMDMAState *bm,uint32_t val); +extern MemoryRegionOps bmdma_addr_ioport_ops;void pci_ide_create_devs (PCIDevice *dev,DriveInfo **hd_table);extern const VMStateDescription vmstate_ide_pci;
hw/ide/piix.c +49 -15
128 lines not on this page · raw message
hw/ide/via.c +49 -16
123 lines not on this page · raw message
Signature · 1 line
1.7.5.3
PATCH v4 19/39 ivshmem: convert to memory API
In reply to Avi Kivityexcluding msix.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ivshmem.c | 148 ++++++++++++++++++++-------------------------------------- 1 files changed, 50 insertions(+), 98 deletions(-)
hw/ivshmem.c +50 -98
@@ -56,11 +56,15 @@ typedef struct IVShmemState {CharDriverState **eventfd_chr;CharDriverState *server_chr; -int ivshmem_mmio_io_addr; +MemoryRegion ivshmem_mmio;pcibus_t mmio_addr; -pcibus_t shm_pci_addr; -uint64_t ivshmem_offset; +/* We might need to register the BAR before we actually have the memory. +* So prepare a container MemoryRegion for the BAR immediately and +* add a subregion when we have the memory. +*/ +MemoryRegion bar; +MemoryRegion ivshmem;uint64_t ivshmem_size;/* size of shared memory region */ int shm_fd;/* shared memory file descriptor */
@@ -96,23 +100,6 @@ static inline bool is_power_of_two(uint64_t x) {return (x & (x -1 )) ==0 ; } -static void ivshmem_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -IVShmemState *s =DO_UPCAST (IVShmemState, dev, pci_dev); - - s->shm_pci_addr = addr; - -if (s->ivshmem_offset >0 ) { -cpu_register_physical_memory (s->shm_pci_addr, s->ivshmem_size, - s->ivshmem_offset); - } - -IVSHMEM_DPRINTF ("guest pci addr = %" FMT_PCIBUS ", guest h/w addr = %" - PRIu64", size = %" FMT_PCIBUS "\n" , addr, s->ivshmem_offset, size); - -} -/* accessing registers - based on rtl8139 */ static void ivshmem_update_irq (IVShmemState *s,int val) {
@@ -168,15 +155,8 @@ static uint32_t ivshmem_IntrStatus_read(IVShmemState *s)return ret; } -static void ivshmem_io_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ - -IVSHMEM_DPRINTF ("We shouldn't be writing words\n" ); -} - -static void ivshmem_io_writel (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void ivshmem_io_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {IVShmemState *s = opaque;
@@ -219,20 +199,8 @@ static void ivshmem_io_writel(void *opaque, target_phys_addr_t addr, } } -static void ivshmem_io_writeb (void *opaque,target_phys_addr_t addr, -uint32_t val) -{ -IVSHMEM_DPRINTF ("We shouldn't be writing bytes\n" ); -} - -static uint32_t ivshmem_io_readw (void *opaque,target_phys_addr_t addr) -{ - -IVSHMEM_DPRINTF ("We shouldn't be reading words\n" ); -return 0 ; -} - -static uint32_t ivshmem_io_readl (void *opaque,target_phys_addr_t addr) +static uint64_t ivshmem_io_read (void *opaque,target_phys_addr_t addr, +unsigned size) {IVShmemState *s = opaque;
@@ -265,23 +233,14 @@ static uint32_t ivshmem_io_readl(void *opaque, target_phys_addr_t addr)return ret; } -static uint32_t ivshmem_io_readb (void *opaque,target_phys_addr_t addr) -{ -IVSHMEM_DPRINTF ("We shouldn't be reading bytes\n" ); - -return 0 ; -} - -static CPUReadMemoryFunc *const ivshmem_mmio_read[3 ] = { - ivshmem_io_readb, - ivshmem_io_readw, - ivshmem_io_readl, -}; - -static CPUWriteMemoryFunc *const ivshmem_mmio_write[3 ] = { - ivshmem_io_writeb, - ivshmem_io_writew, - ivshmem_io_writel, +static const MemoryRegionOps ivshmem_mmio_ops = { + .read = ivshmem_io_read, + .write = ivshmem_io_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .impl = { + .min_access_size =4 , + .max_access_size =4 , + }, };static void ivshmem_receive (void *opaque,const uint8_t *buf,int size)
@@ -371,12 +330,12 @@ static void create_shared_memory_BAR(IVShmemState *s, int fd) { ptr =mmap (0 , s->ivshmem_size,PROT_READ |PROT_WRITE ,MAP_SHARED , fd,0 ); - s->ivshmem_offset =qemu_ram_alloc_from_ptr (&s->dev.qdev,"ivshmem.bar2" , - s->ivshmem_size, ptr); +memory_region_init_ram_ptr (&s->ivshmem, &s->dev.qdev,"ivshmem.bar2" , + s->ivshmem_size, ptr); +memory_region_add_subregion (&s->bar,0 , &s->ivshmem);/* region for shared memory */ -pci_register_bar (&s->dev,2 , s->ivshmem_size, -PCI_BASE_ADDRESS_SPACE_MEMORY , ivshmem_map); +pci_register_bar_region (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar); }static void close_guest_eventfds (IVShmemState *s,int posn)
@@ -401,8 +360,12 @@ static void setup_ioeventfds(IVShmemState *s) {for (i =0 ; i <= s->max_peer; i++) {for (j =0 ; j < s->peers[i].nb_eventfds; j++) { -kvm_set_ioeventfd_mmio_long (s->peers[i].eventfds[j], - s->mmio_addr +DOORBELL , (i <<16 ) | j,1 ); +memory_region_add_eventfd (&s->ivshmem_mmio, +DOORBELL , +4 , + true, + (i <<16 ) | j, + s->peers[i].eventfds[j]); } } }
@@ -483,18 +446,13 @@ static void ivshmem_read(void *opaque, const uint8_t * buf, int flags)/* mmap the region and map into the BAR2 */ map_ptr =mmap (0 , s->ivshmem_size,PROT_READ |PROT_WRITE ,MAP_SHARED , incoming_fd,0 ); - s->ivshmem_offset =qemu_ram_alloc_from_ptr (&s->dev.qdev, -"ivshmem.bar2" , s->ivshmem_size, map_ptr); +memory_region_init_ram_ptr (&s->ivshmem, &s->dev.qdev, +"ivshmem.bar2" , s->ivshmem_size, map_ptr); -IVSHMEM_DPRINTF ("guest pci addr = %" FMT_PCIBUS ", guest h/w addr = %" - PRIu64", size = %" PRIu64"\n" , s->shm_pci_addr, +IVSHMEM_DPRINTF ("guest h/w addr = %" PRIu64", size = %" PRIu64"\n" , s->ivshmem_offset, s->ivshmem_size); -if (s->shm_pci_addr >0 ) { -/* map memory into BAR2 */ -cpu_register_physical_memory (s->shm_pci_addr, s->ivshmem_size, - s->ivshmem_offset); - } +memory_region_add_subregion (&s->bar,0 , &s->ivshmem);/* only store the fd if it is successfully mapped */ s->shm_fd = incoming_fd;
@@ -549,20 +507,6 @@ static void ivshmem_reset(DeviceState *d)return ; } -static void ivshmem_mmio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -IVShmemState *s =DO_UPCAST (IVShmemState, dev, pci_dev); - - s->mmio_addr = addr; -cpu_register_physical_memory (addr +0 ,IVSHMEM_REG_BAR_SIZE , - s->ivshmem_mmio_io_addr); - -if (ivshmem_has_feature (s,IVSHMEM_IOEVENTFD )) { -setup_ioeventfds (s); - } -} -static uint64_t ivshmem_get_size (IVShmemState * s) {uint64_t value;
@@ -710,15 +654,20 @@ static int pci_ivshmem_init(PCIDevice *dev)pci_config_set_interrupt_pin (pci_conf,1 ); - s->shm_pci_addr =0 ; - s->ivshmem_offset =0 ; s->shm_fd =0 ; - s->ivshmem_mmio_io_addr =cpu_register_io_memory (ivshmem_mmio_read, - ivshmem_mmio_write, s,DEVICE_NATIVE_ENDIAN ); +memory_region_init_io (&s->ivshmem_mmio, &ivshmem_mmio_ops, s, +"ivshmem-mmio" ,IVSHMEM_REG_BAR_SIZE ); + +if (ivshmem_has_feature (s,IVSHMEM_IOEVENTFD )) { +setup_ioeventfds (s); + } +/* region for registers*/ -pci_register_bar (&s->dev,0 ,IVSHMEM_REG_BAR_SIZE , -PCI_BASE_ADDRESS_SPACE_MEMORY , ivshmem_mmio_map); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->ivshmem_mmio); + +memory_region_init (&s->bar,"ivshmem-bar2-container" , s->ivshmem_size);if ((s->server_chr !=NULL ) && (strncmp (s->server_chr->filename,"unix:" ,5 ) ==0 )) {
@@ -744,8 +693,8 @@ static int pci_ivshmem_init(PCIDevice *dev)/* allocate/initialize space for interrupt handling */ s->peers =qemu_mallocz (s->nb_peers *sizeof (Peer)); -pci_register_bar (&s->dev,2 , s->ivshmem_size, -PCI_BASE_ADDRESS_SPACE_MEMORY , ivshmem_map); +pci_register_bar_region (&s->dev,2 , +PCI_BASE_ADDRESS_SPACE_MEMORY , &s->ivshmem); s->eventfd_chr =qemu_mallocz (s->vectors *sizeof (CharDriverState *));
@@ -792,7 +741,10 @@ static int pci_ivshmem_uninit(PCIDevice *dev) {IVShmemState *s =DO_UPCAST (IVShmemState, dev, dev); -cpu_unregister_io_memory (s->ivshmem_mmio_io_addr); +memory_region_destroy (&s->ivshmem_mmio); +memory_region_del_subregion (&s->bar, &s->ivshmem); +memory_region_destroy (&s->ivshmem); +memory_region_destroy (&s->bar);unregister_savevm (&dev->qdev,"ivshmem" , s);return 0 ;
Signature · 1 line
1.7.5.3
PATCH v4 20/39 virtio-pci: convert to memory API
In reply to Avi Kivityexcept msix.
[jan: fix build]
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/virtio-pci.c | 71 +++++++++++++++++++++---------------------------------- hw/virtio-pci.h | 2 +- 2 files changed, 28 insertions(+), 45 deletions(-)
hw/virtio-pci.c +27 -44
@@ -162,7 +162,8 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, {VirtQueue *vq =virtio_get_queue (proxy->vdev, n);EventNotifier *notifier =virtio_queue_get_host_notifier (vq); -int r; +int r =0 ; +if (assign) { r =event_notifier_init (notifier,1 );if (r <0 ) {
@@ -170,24 +171,11 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, __func__, r);return r; } - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r <0 ) { -error_report ("%s: unable to map ioeventfd: %d" , - __func__, r); -event_notifier_cleanup (notifier); - } +memory_region_add_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier)); }else { - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r <0 ) { -error_report ("%s: unable to unmap ioeventfd: %d" , - __func__, r); -return r; - } - +memory_region_del_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier));/* Handle the race condition where the guest kicked and we deassigned * before we got around to handling the kick. */
@@ -424,7 +412,6 @@ static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -435,7 +422,6 @@ static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -446,7 +432,6 @@ static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -457,7 +442,6 @@ static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -470,7 +454,6 @@ static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -483,7 +466,6 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -492,30 +474,26 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)virtio_config_writel (proxy->vdev, addr, val); } -static void virtio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -VirtIOPCIProxy *proxy =container_of (pci_dev, VirtIOPCIProxy, pci_dev); -VirtIODevice *vdev = proxy->vdev; -unsigned config_len =VIRTIO_PCI_REGION_SIZE (pci_dev) + vdev->config_len; - - proxy->addr = addr; - -register_ioport_write (addr, config_len,1 , virtio_pci_config_writeb, proxy); -register_ioport_write (addr, config_len,2 , virtio_pci_config_writew, proxy); -register_ioport_write (addr, config_len,4 , virtio_pci_config_writel, proxy); -register_ioport_read (addr, config_len,1 , virtio_pci_config_readb, proxy); -register_ioport_read (addr, config_len,2 , virtio_pci_config_readw, proxy); -register_ioport_read (addr, config_len,4 , virtio_pci_config_readl, proxy); +const MemoryRegionPortio virtio_portio[] = { + {0 ,0x10000 ,1 , .write = virtio_pci_config_writeb, }, + {0 ,0x10000 ,2 , .write = virtio_pci_config_writew, }, + {0 ,0x10000 ,4 , .write = virtio_pci_config_writel, }, + {0 ,0x10000 ,1 , .read = virtio_pci_config_readb, }, + {0 ,0x10000 ,2 , .read = virtio_pci_config_readw, }, + {0 ,0x10000 ,4 , .read = virtio_pci_config_readl, }, +PORTIO_END_OF_LIST () +}; -if (vdev->config_len) - vdev->get_config (vdev, vdev->config); -} +static const MemoryRegionOps virtio_pci_config_ops = { + .old_portio = virtio_portio, + .endianness =DEVICE_LITTLE_ENDIAN , +};static void virtio_write_config (PCIDevice *pci_dev,uint32_t address,uint32_t val,int len) {VirtIOPCIProxy *proxy =DO_UPCAST (VirtIOPCIProxy, pci_dev, pci_dev); +VirtIODevice *vdev = proxy->vdev;pci_default_write_config (pci_dev, address, val, len);
@@ -678,8 +656,10 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)if (size & (size-1 )) size =1 <<qemu_fls (size); -pci_register_bar (&proxy->pci_dev,0 , size,PCI_BASE_ADDRESS_SPACE_IO , - virtio_map); +memory_region_init_io (&proxy->bar, &virtio_pci_config_ops, proxy, +"virtio-pci" , size); +pci_register_bar_region (&proxy->pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , + &proxy->bar);if (!kvm_has_many_ioeventfds ()) { proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD ;
@@ -714,6 +694,9 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)static int virtio_exit_pci (PCIDevice *pci_dev) { +VirtIOPCIProxy *proxy =DO_UPCAST (VirtIOPCIProxy, pci_dev, pci_dev); + +memory_region_destroy (&proxy->bar);return msix_uninit (pci_dev); }
hw/virtio-pci.h +1 -1
@@ -21,8 +21,8 @@ typedef struct { PCIDevice pci_dev; VirtIODevice *vdev; + MemoryRegion bar; uint32_t flags; - uint32_t addr; uint32_t class_code; uint32_t nvectors; BlockConf block;
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 20/39] virtio-pci: convert to memory API
Quoted 3 lines · Avi Kivity
except msix.
[jan: fix build]
This actually breaks the build:
CC libhw64/virtio-pci.o
cc1: warnings being treated as errors /home/anthony/git/qemu/hw/virtio-pci.c: In function ‘virtio_write_config’:/home/anthony/git/qemu/hw/virtio-pci.c:496:19: error: unused variable ‘vdev’ make[1]: *** [virtio-pci.o] Error 1
make: *** [subdir-libhw64] Error 2
Quoted 132 lines
Reviewed-by Richard Henderson<[email protected]>Reviewed-by Anthony Liguori<[email protected]>Signed-off-by Avi Kivity<[email protected]>--- hw/virtio-pci.c | 71 +++++++++++++++++++++---------------------------------- hw/virtio-pci.h | 2 +- 2 files changed, 28 insertions(+), 45 deletions(-)hw/virtio-pci.c +15
-42@@ -162,7 +162,8 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, {VirtQueue *vq =virtio_get_queue (proxy->vdev, n);EventNotifier *notifier =virtio_queue_get_host_notifier (vq); -int r; +int r =0 ; +if (assign) { r =event_notifier_init (notifier,1 );if (r<0 ) {@@ -170,24 +171,11 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, __func__, r);return r; } - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r<0 ) { -error_report ("%s: unable to map ioeventfd: %d" , - __func__, r); -event_notifier_cleanup (notifier); - } +memory_region_add_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier)); }else { - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r<0 ) { -error_report ("%s: unable to unmap ioeventfd: %d" , - __func__, r); -return r; - } - +memory_region_del_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier));/* Handle the race condition where the guest kicked and we deassigned * before we got around to handling the kick. */ @@ -424,7 +412,6 @@ static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config)return virtio_ioport_read (proxy, addr); addr -= config;@@ -435,7 +422,6 @@ static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config)return virtio_ioport_read (proxy, addr); addr -= config;@@ -446,7 +432,6 @@ static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config)return virtio_ioport_read (proxy, addr); addr -= config;@@ -457,7 +442,6 @@ static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config) {virtio_ioport_write (proxy, addr, val);return ;@@ -470,7 +454,6 @@ static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config) {virtio_ioport_write (proxy, addr, val);return ;@@ -483,7 +466,6 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr< config) {virtio_ioport_write (proxy, addr, val);return ;@@ -492,30 +474,26 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)virtio_config_writel (proxy->vdev, addr, val); } -static void virtio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -VirtIOPCIProxy *proxy =container_of (pci_dev, VirtIOPCIProxy, pci_dev); -VirtIODevice *vdev = proxy->vdev; -unsigned config_len =VIRTIO_PCI_REGION_SIZE (pci_dev) + vdev->config_len; - - proxy->addr = addr; - -register_ioport_write (addr, config_len,1 , virtio_pci_config_writeb, proxy); -register_ioport_write (addr, config_len,2 , virtio_pci_config_writew, proxy); -register_ioport_write (addr, config_len,4 , virtio_pci_config_writel, proxy); -register_ioport_read (addr, config_len,1 , virtio_pci_config_readb, proxy); -register_ioport_read (addr, config_len,2 , virtio_pci_config_readw, proxy); -register_ioport_read (addr, config_len,4 , virtio_pci_config_readl, proxy); +const MemoryRegionPortio virtio_portio[] = { + {0 ,0x10000 ,1 , .write = virtio_pci_config_writeb, }, + {0 ,0x10000 ,2 , .write = virtio_pci_config_writew, }, + {0 ,0x10000 ,4 , .write = virtio_pci_config_writel, }, + {0 ,0x10000 ,1 , .read = virtio_pci_config_readb, }, + {0 ,0x10000 ,2 , .read = virtio_pci_config_readw, }, + {0 ,0x10000 ,4 , .read = virtio_pci_config_readl, }, +PORTIO_END_OF_LIST () +}; -if (vdev->config_len) - vdev->get_config (vdev, vdev->config); -}
hw/virtio-pci.c static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) · line 496
Quoted 10 lines
hw/virtio-pci.c +5
-0+static const MemoryRegionOps virtio_pci_config_ops = { + .old_portio = virtio_portio, + .endianness =DEVICE_LITTLE_ENDIAN , +};static void virtio_write_config (PCIDevice *pci_dev,uint32_t address,uint32_t val,int len) {VirtIOPCIProxy *proxy =DO_UPCAST (VirtIOPCIProxy, pci_dev, pci_dev); +VirtIODevice *vdev = proxy->vdev;
This variable isn't needed. I'll remove it.
Regards,
Anthony Liguori
PATCH v4 20/39 virtio-pci: convert to memory API
except msix.
[jan: fix build]
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
---
v4.1: drop unused variable
hw/virtio-pci.c | 70 ++++++++++++++++++++---------------------------------- hw/virtio-pci.h | 2 +- 2 files changed, 27 insertions(+), 45 deletions(-)
hw/virtio-pci.c +26 -44
@@ -162,7 +162,8 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, {VirtQueue *vq =virtio_get_queue (proxy->vdev, n);EventNotifier *notifier =virtio_queue_get_host_notifier (vq); -int r; +int r =0 ; +if (assign) { r =event_notifier_init (notifier,1 );if (r <0 ) {
@@ -170,24 +171,11 @@ static int virtio_pci_set_host_notifier_internal(VirtIOPCIProxy *proxy, __func__, r);return r; } - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r <0 ) { -error_report ("%s: unable to map ioeventfd: %d" , - __func__, r); -event_notifier_cleanup (notifier); - } +memory_region_add_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier)); }else { - r =kvm_set_ioeventfd_pio_word (event_notifier_get_fd (notifier), - proxy->addr +VIRTIO_PCI_QUEUE_NOTIFY , - n, assign); -if (r <0 ) { -error_report ("%s: unable to unmap ioeventfd: %d" , - __func__, r); -return r; - } - +memory_region_del_eventfd (&proxy->bar,VIRTIO_PCI_QUEUE_NOTIFY ,2 , + true, n,event_notifier_get_fd (notifier));/* Handle the race condition where the guest kicked and we deassigned * before we got around to handling the kick. */
@@ -424,7 +412,6 @@ static uint32_t virtio_pci_config_readb(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -435,7 +422,6 @@ static uint32_t virtio_pci_config_readw(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -446,7 +432,6 @@ static uint32_t virtio_pci_config_readl(void *opaque, uint32_t addr) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config)return virtio_ioport_read (proxy, addr); addr -= config;
@@ -457,7 +442,6 @@ static void virtio_pci_config_writeb(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -470,7 +454,6 @@ static void virtio_pci_config_writew(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -483,7 +466,6 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val) {VirtIOPCIProxy *proxy = opaque;uint32_t config =VIRTIO_PCI_CONFIG (&proxy->pci_dev); - addr -= proxy->addr;if (addr < config) {virtio_ioport_write (proxy, addr, val);return ;
@@ -492,25 +474,20 @@ static void virtio_pci_config_writel(void *opaque, uint32_t addr, uint32_t val)virtio_config_writel (proxy->vdev, addr, val); } -static void virtio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -VirtIOPCIProxy *proxy =container_of (pci_dev, VirtIOPCIProxy, pci_dev); -VirtIODevice *vdev = proxy->vdev; -unsigned config_len =VIRTIO_PCI_REGION_SIZE (pci_dev) + vdev->config_len; - - proxy->addr = addr; - -register_ioport_write (addr, config_len,1 , virtio_pci_config_writeb, proxy); -register_ioport_write (addr, config_len,2 , virtio_pci_config_writew, proxy); -register_ioport_write (addr, config_len,4 , virtio_pci_config_writel, proxy); -register_ioport_read (addr, config_len,1 , virtio_pci_config_readb, proxy); -register_ioport_read (addr, config_len,2 , virtio_pci_config_readw, proxy); -register_ioport_read (addr, config_len,4 , virtio_pci_config_readl, proxy); +const MemoryRegionPortio virtio_portio[] = { + {0 ,0x10000 ,1 , .write = virtio_pci_config_writeb, }, + {0 ,0x10000 ,2 , .write = virtio_pci_config_writew, }, + {0 ,0x10000 ,4 , .write = virtio_pci_config_writel, }, + {0 ,0x10000 ,1 , .read = virtio_pci_config_readb, }, + {0 ,0x10000 ,2 , .read = virtio_pci_config_readw, }, + {0 ,0x10000 ,4 , .read = virtio_pci_config_readl, }, +PORTIO_END_OF_LIST () +}; -if (vdev->config_len) - vdev->get_config (vdev, vdev->config); -} +static const MemoryRegionOps virtio_pci_config_ops = { + .old_portio = virtio_portio, + .endianness =DEVICE_LITTLE_ENDIAN , +};static void virtio_write_config (PCIDevice *pci_dev,uint32_t address,uint32_t val,int len)
@@ -678,8 +655,10 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)if (size & (size-1 )) size =1 <<qemu_fls (size); -pci_register_bar (&proxy->pci_dev,0 , size,PCI_BASE_ADDRESS_SPACE_IO , - virtio_map); +memory_region_init_io (&proxy->bar, &virtio_pci_config_ops, proxy, +"virtio-pci" , size); +pci_register_bar_region (&proxy->pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , + &proxy->bar);if (!kvm_has_many_ioeventfds ()) { proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD ;
@@ -714,6 +693,9 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)static int virtio_exit_pci (PCIDevice *pci_dev) { +VirtIOPCIProxy *proxy =DO_UPCAST (VirtIOPCIProxy, pci_dev, pci_dev); + +memory_region_destroy (&proxy->bar);return msix_uninit (pci_dev); }
hw/virtio-pci.h +1 -1
@@ -21,8 +21,8 @@ typedef struct { PCIDevice pci_dev; VirtIODevice *vdev; + MemoryRegion bar; uint32_t flags; - uint32_t addr; uint32_t class_code; uint32_t nvectors; BlockConf block;
Signature · 1 line
1.7.5.3
PATCH v4 21/39 ahci: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ide/ahci.c | 31 +++++++++++++------------------ hw/ide/ahci.h | 2 +- hw/ide/ich.c | 3 +-- 3 files changed, 15 insertions(+), 21 deletions(-)
hw/ide/ahci.c +13 -18
@@ -276,12 +276,12 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) } } -static uint32_t ahci_mem_readl (void *ptr,target_phys_addr_t addr) +static uint64_t ahci_mem_read (void *opaque,target_phys_addr_t addr, +unsigned size) { -AHCIState *s = ptr; +AHCIState *s = opaque;uint32_t val =0 ; - addr = addr &0xfff ;if (addr <AHCI_GENERIC_HOST_CONTROL_REGS_MAX_ADDR ) {switch (addr) {case HOST_CAP :
@@ -314,10 +314,10 @@ static uint32_t ahci_mem_readl(void *ptr, target_phys_addr_t addr) -static void ahci_mem_writel (void *ptr,target_phys_addr_t addr,uint32_t val) +static void ahci_mem_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) { -AHCIState *s = ptr; - addr = addr &0xfff ; +AHCIState *s = opaque;/* Only aligned reads are allowed on AHCI */ if (addr &3 ) {
@@ -364,16 +364,10 @@ static void ahci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val) } -static CPUReadMemoryFunc *const ahci_readfn[3 ]={ - ahci_mem_readl, - ahci_mem_readl, - ahci_mem_readl -}; - -static CPUWriteMemoryFunc *const ahci_writefn[3 ]={ - ahci_mem_writel, - ahci_mem_writel, - ahci_mem_writel +static MemoryRegionOps ahci_mem_ops = { + .read = ahci_mem_read, + .write = ahci_mem_write, + .endianness =DEVICE_LITTLE_ENDIAN , };static void ahci_reg_init (AHCIState *s)
@@ -1131,8 +1125,8 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports) s->ports = ports; s->dev =qemu_mallocz (sizeof (AHCIDevice) * ports);ahci_reg_init (s); - s->mem =cpu_register_io_memory (ahci_readfn, ahci_writefn, s, -DEVICE_LITTLE_ENDIAN ); +/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ +memory_region_init_io (&s->mem, &ahci_mem_ops, s,"ahci" ,0x1000 ); irqs =qemu_allocate_irqs (ahci_irq_set, s, s->ports);for (i =0 ; i < s->ports; i++) {
@@ -1151,6 +1145,7 @@ void ahci_init(AHCIState *s, DeviceState *qdev, int ports)void ahci_uninit (AHCIState *s) { +memory_region_destroy (&s->mem);qemu_free (s->dev); }
hw/ide/ahci.h +1 -1
@@ -289,7 +289,7 @@ struct AHCIDevice {typedef struct AHCIState {AHCIDevice *dev;AHCIControlRegs control_regs; -int mem; +MemoryRegion mem;int ports;qemu_irq irq; }AHCIState ;
hw/ide/ich.c +1 -2
@@ -98,8 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)msi_init (dev,0x50 ,1 , true, false); d->ahci.irq = d->card.irq[0 ]; -/* XXX BAR size should be 1k, but that breaks, so bump it to 4k for now */ -pci_register_bar_simple (&d->card,5 ,0x1000 ,0 , d->ahci.mem); +pci_register_bar_region (&d->card,5 ,0 , &d->ahci.mem);return 0 ; }
Signature · 1 line
1.7.5.3
PATCH v4 22/39 intel-hda: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/intel-hda.c | 35 +++++++++++++++++++---------------- 1 files changed, 19 insertions(+), 16 deletions(-)
hw/intel-hda.c +19 -16
@@ -177,7 +177,7 @@ struct IntelHDAState {IntelHDAStream st[8 ];/* state */ -int mmio_addr; +MemoryRegion mmio;uint32_t rirb_count;int64_t wall_base_ns;
@@ -1084,16 +1084,20 @@ static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr)return intel_hda_reg_read (d, reg,0xffffffff ); } -static CPUReadMemoryFunc *const intel_hda_mmio_read[3 ] = { - intel_hda_mmio_readb, - intel_hda_mmio_readw, - intel_hda_mmio_readl, -}; - -static CPUWriteMemoryFunc *const intel_hda_mmio_write[3 ] = { - intel_hda_mmio_writeb, - intel_hda_mmio_writew, - intel_hda_mmio_writel, +static const MemoryRegionOps intel_hda_mmio_ops = { + .old_mmio = { + .read = { + intel_hda_mmio_readb, + intel_hda_mmio_readw, + intel_hda_mmio_readl, + }, + .write = { + intel_hda_mmio_writeb, + intel_hda_mmio_writew, + intel_hda_mmio_writel, + }, + }, + .endianness =DEVICE_NATIVE_ENDIAN , };/* --------------------------------------------------------------------- */
@@ -1130,10 +1134,9 @@ static int intel_hda_init(PCIDevice *pci)/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */ conf[0x40 ] =0x01 ; - d->mmio_addr =cpu_register_io_memory (intel_hda_mmio_read, - intel_hda_mmio_write, d, -DEVICE_NATIVE_ENDIAN ); -pci_register_bar_simple (&d->pci,0 ,0x4000 ,0 , d->mmio_addr); +memory_region_init_io (&d->mmio, &intel_hda_mmio_ops, d, +"intel-hda" ,0x4000 ); +pci_register_bar_region (&d->pci,0 ,0 , &d->mmio);if (d->msi) {msi_init (&d->pci,0x50 ,1 , true, false); }
@@ -1149,7 +1152,7 @@ static int intel_hda_exit(PCIDevice *pci)IntelHDAState *d =DO_UPCAST (IntelHDAState, pci, pci);msi_uninit (&d->pci); -cpu_unregister_io_memory (d->mmio_addr); +memory_region_destroy (&d->mmio);return 0 ; }
Signature · 1 line
1.7.5.3
PATCH v4 23/39 lsi53c895a: convert to memory API
In reply to Avi KivityAn optimization that fast-pathed DMA reads from the SCRIPTS memory was removed int the process. Likely it breaks with iommus anyway.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/lsi53c895a.c | 258 ++++++++++++------------------------------------------- 1 files changed, 56 insertions(+), 202 deletions(-)
hw/lsi53c895a.c +56 -202
@@ -185,9 +185,9 @@ typedef struct lsi_request { typedef struct { PCIDevice dev; - int mmio_io_addr; - int ram_io_addr; - uint32_t script_ram_base; + MemoryRegion mmio_io; + MemoryRegion ram_io; + MemoryRegion io_io; int carry; /* ??? Should this be an a visible register somewhere? */ int status;
@@ -391,10 +391,9 @@ static inline uint32_t read_dword(LSIState *s, uint32_t addr) {uint32_t buf; -/* Optimize reading from SCRIPTS RAM. */ -if ((addr &0xffffe000 ) == s->script_ram_base) { -return s->script_ram[(addr &0x1fff ) >>2 ]; - } +/* XXX: an optimization here used to fast-path the read from scripts +* memory. But that bypasses any iommu. +*/ cpu_physical_memory_read (addr, (uint8_t *)&buf,4 );return cpu_to_le32 (buf); }
@@ -1899,232 +1898,90 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)#undef CASE_SET_REG32 } -static void lsi_mmio_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void lsi_mmio_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;lsi_reg_writeb (s, addr &0xff , val); } -static void lsi_mmio_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -} - -static void lsi_mmio_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -lsi_reg_writeb (s, addr +2 , (val >>16 ) &0xff ); -lsi_reg_writeb (s, addr +3 , (val >>24 ) &0xff ); -} - -static uint32_t lsi_mmio_readb (void *opaque,target_phys_addr_t addr) +static uint64_t lsi_mmio_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;return lsi_reg_readb (s, addr &0xff ); } -static uint32_t lsi_mmio_readw (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; -return val; -} - -static uint32_t lsi_mmio_readl (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; - val |=lsi_reg_readb (s, addr +2 ) <<16 ; - val |=lsi_reg_readb (s, addr +3 ) <<24 ; -return val; -} - -static CPUReadMemoryFunc *const lsi_mmio_readfn[3 ] = { - lsi_mmio_readb, - lsi_mmio_readw, - lsi_mmio_readl, -}; - -static CPUWriteMemoryFunc *const lsi_mmio_writefn[3 ] = { - lsi_mmio_writeb, - lsi_mmio_writew, - lsi_mmio_writel, +static const MemoryRegionOps lsi_mmio_ops = { + .read = lsi_mmio_read, + .write = lsi_mmio_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, }; -static void lsi_ram_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void lsi_ram_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;uint32_t newval; +uint32_t mask;int shift; - addr &=0x1fff ; newval = s->script_ram[addr >>2 ]; shift = (addr &3 ) *8 ; - newval &= ~(0xff << shift); + mask = ((uint64_t )1 << (size *8 )) -1 ; + newval &= ~(mask << shift); newval |= val << shift; s->script_ram[addr >>2 ] = newval; } -static void lsi_ram_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; -uint32_t newval; - - addr &=0x1fff ; - newval = s->script_ram[addr >>2 ]; -if (addr &2 ) { - newval = (newval &0xffff ) | (val <<16 ); - }else { - newval = (newval &0xffff0000 ) | val; - } - s->script_ram[addr >>2 ] = newval; -} - - -static void lsi_ram_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0x1fff ; - s->script_ram[addr >>2 ] = val; -} - -static uint32_t lsi_ram_readb (void *opaque,target_phys_addr_t addr) +static uint64_t lsi_ram_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;uint32_t val; +uint32_t mask; - addr &=0x1fff ; val = s->script_ram[addr >>2 ]; + mask = ((uint64_t )1 << (size *8 )) -1 ; val >>= (addr &3 ) *8 ; -return val &0xff ; -} - -static uint32_t lsi_ram_readw (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - - addr &=0x1fff ; - val = s->script_ram[addr >>2 ]; -if (addr &2 ) - val >>=16 ; -return val; -} - -static uint32_t lsi_ram_readl (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; - - addr &=0x1fff ; -return s->script_ram[addr >>2 ]; +return val & mask; } -static CPUReadMemoryFunc *const lsi_ram_readfn[3 ] = { - lsi_ram_readb, - lsi_ram_readw, - lsi_ram_readl, +static const MemoryRegionOps lsi_ram_ops = { + .read = lsi_ram_read, + .write = lsi_ram_write, + .endianness =DEVICE_NATIVE_ENDIAN , }; -static CPUWriteMemoryFunc *const lsi_ram_writefn[3 ] = { - lsi_ram_writeb, - lsi_ram_writew, - lsi_ram_writel, -}; - -static uint32_t lsi_io_readb (void *opaque,uint32_t addr) +static uint64_t lsi_io_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;return lsi_reg_readb (s, addr &0xff ); } -static uint32_t lsi_io_readw (void *opaque,uint32_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; -return val; -} - -static uint32_t lsi_io_readl (void *opaque,uint32_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; - val |=lsi_reg_readb (s, addr +2 ) <<16 ; - val |=lsi_reg_readb (s, addr +3 ) <<24 ; -return val; -} - -static void lsi_io_writeb (void *opaque,uint32_t addr,uint32_t val) +static void lsi_io_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;lsi_reg_writeb (s, addr &0xff , val); } -static void lsi_io_writew (void *opaque,uint32_t addr,uint32_t val) -{ -LSIState *s = opaque; - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -} - -static void lsi_io_writel (void *opaque,uint32_t addr,uint32_t val) -{ -LSIState *s = opaque; - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -lsi_reg_writeb (s, addr +2 , (val >>16 ) &0xff ); -lsi_reg_writeb (s, addr +3 , (val >>24 ) &0xff ); -} - -static void lsi_io_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -LSIState *s =DO_UPCAST (LSIState, dev, pci_dev); - -DPRINTF ("Mapping IO at %08" FMT_PCIBUS "\n" , addr); - -register_ioport_write (addr,256 ,1 , lsi_io_writeb, s); -register_ioport_read (addr,256 ,1 , lsi_io_readb, s); -register_ioport_write (addr,256 ,2 , lsi_io_writew, s); -register_ioport_read (addr,256 ,2 , lsi_io_readw, s); -register_ioport_write (addr,256 ,4 , lsi_io_writel, s); -register_ioport_read (addr,256 ,4 , lsi_io_readl, s); -} - -static void lsi_ram_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -LSIState *s =DO_UPCAST (LSIState, dev, pci_dev); - -DPRINTF ("Mapping ram at %08" FMT_PCIBUS "\n" , addr); - s->script_ram_base = addr; -cpu_register_physical_memory (addr +0 ,0x2000 , s->ram_io_addr); -} +static const MemoryRegionOps lsi_io_ops = { + .read = lsi_io_read, + .write = lsi_io_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, +};static void lsi_scsi_reset (DeviceState *dev) {
@@ -2231,8 +2088,9 @@ static int lsi_scsi_uninit(PCIDevice *d) {LSIState *s =DO_UPCAST (LSIState, dev, d); -cpu_unregister_io_memory (s->mmio_io_addr); -cpu_unregister_io_memory (s->ram_io_addr); +memory_region_destroy (&s->mmio_io); +memory_region_destroy (&s->ram_io); +memory_region_destroy (&s->io_io);return 0 ; }
@@ -2256,18 +2114,14 @@ static int lsi_scsi_init(PCIDevice *dev)/* Interrupt pin 1 */ pci_conf[PCI_INTERRUPT_PIN ] =0x01 ; - s->mmio_io_addr =cpu_register_io_memory (lsi_mmio_readfn, - lsi_mmio_writefn, s, -DEVICE_NATIVE_ENDIAN ); - s->ram_io_addr =cpu_register_io_memory (lsi_ram_readfn, - lsi_ram_writefn, s, -DEVICE_NATIVE_ENDIAN ); - -pci_register_bar (&s->dev,0 ,256 , -PCI_BASE_ADDRESS_SPACE_IO , lsi_io_mapfunc); -pci_register_bar_simple (&s->dev,1 ,0x400 ,0 , s->mmio_io_addr); -pci_register_bar (&s->dev,2 ,0x2000 , -PCI_BASE_ADDRESS_SPACE_MEMORY , lsi_ram_mapfunc); +memory_region_init_io (&s->mmio_io, &lsi_mmio_ops, s,"lsi-mmio" ,0x400 ); +memory_region_init_io (&s->ram_io, &lsi_ram_ops, s,"lsi-ram" ,0x2000 ); +memory_region_init_io (&s->io_io, &lsi_io_ops, s,"lsi-io" ,256 ); + +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_io); +pci_register_bar_region (&s->dev,1 ,0 , &s->mmio_io); +pci_register_bar_region (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->ram_io);QTAILQ_INIT (&s->queue);scsi_bus_new (&s->bus, &dev->qdev,1 ,LSI_MAX_DEVS , &lsi_scsi_ops);
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 23/39] lsi53c895a: convert to memory API
Hello Avi,
qemu/qemu-kvm doesn't boot any more with LSI option rom (-option-rom 8xx_64.rom). Guess it comes from changes of the memory API. Also latest git version from seabios.
Sorry, no further details currently available.
Ciao,
Gerhard
Quoted 357 lines · Avi Kivity
An optimization that fast-pathed DMA reads from the SCRIPTS memory was removed int the process. Likely it breaks with iommus anyway.
Reviewed-by Richard Henderson <[email protected]>Reviewed-by Anthony Liguori <[email protected]>Signed-off-by Avi Kivity <[email protected]>---
hw/lsi53c895a.c| 258 ++++++++++++-------------------------------------------1 files changed, 56 insertions(+), 202 deletions(-)hw/lsi53c895a.c +56
-202@@ -185,9 +185,9 @@ typedef struct lsi_request { typedef struct { PCIDevice dev; - int mmio_io_addr; - int ram_io_addr; - uint32_t script_ram_base; + MemoryRegion mmio_io; + MemoryRegion ram_io; + MemoryRegion io_io; int carry; /* ??? Should this be an a visible register somewhere? */ int status;@@ -391,10 +391,9 @@ static inline uint32_t read_dword(LSIState *s, uint32_t addr) {uint32_t buf; -/* Optimize reading from SCRIPTS RAM. */ -if ((addr &0xffffe000 ) == s->script_ram_base) { -return s->script_ram[(addr &0x1fff ) >>2 ]; - } +/* XXX: an optimization here used to fast-path the read from scripts +* memory. But that bypasses any iommu. +*/ cpu_physical_memory_read (addr, (uint8_t *)&buf,4 );return cpu_to_le32 (buf); }@@ -1899,232 +1898,90 @@ static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)#undef CASE_SET_REG32 } -static void lsi_mmio_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void lsi_mmio_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;lsi_reg_writeb (s, addr &0xff , val); } -static void lsi_mmio_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -} - -static void lsi_mmio_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -lsi_reg_writeb (s, addr +2 , (val >>16 ) &0xff ); -lsi_reg_writeb (s, addr +3 , (val >>24 ) &0xff ); -} - -static uint32_t lsi_mmio_readb (void *opaque,target_phys_addr_t addr) +static uint64_t lsi_mmio_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;return lsi_reg_readb (s, addr &0xff ); } -static uint32_t lsi_mmio_readw (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; -return val; -} - -static uint32_t lsi_mmio_readl (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; - val |=lsi_reg_readb (s, addr +2 ) <<16 ; - val |=lsi_reg_readb (s, addr +3 ) <<24 ; -return val; -} - -static CPUReadMemoryFunc *const lsi_mmio_readfn[3 ] = { - lsi_mmio_readb, - lsi_mmio_readw, - lsi_mmio_readl, -}; - -static CPUWriteMemoryFunc *const lsi_mmio_writefn[3 ] = { - lsi_mmio_writeb, - lsi_mmio_writew, - lsi_mmio_writel, +static const MemoryRegionOps lsi_mmio_ops = { + .read = lsi_mmio_read, + .write = lsi_mmio_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, }; -static void lsi_ram_writeb (void *opaque,target_phys_addr_t addr,uint32_t val) +static void lsi_ram_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;uint32_t newval; +uint32_t mask;int shift; - addr &=0x1fff ; newval = s->script_ram[addr >>2 ]; shift = (addr &3 ) *8 ; - newval &= ~(0xff << shift); + mask = ((uint64_t )1 << (size *8 )) -1 ; + newval &= ~(mask << shift); newval |= val << shift; s->script_ram[addr >>2 ] = newval; } -static void lsi_ram_writew (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; -uint32_t newval; - - addr &=0x1fff ; - newval = s->script_ram[addr >>2 ]; -if (addr &2 ) { - newval = (newval &0xffff ) | (val <<16 ); - }else { - newval = (newval &0xffff0000 ) | val; - } - s->script_ram[addr >>2 ] = newval; -} - - -static void lsi_ram_writel (void *opaque,target_phys_addr_t addr,uint32_t val) -{ -LSIState *s = opaque; - - addr &=0x1fff ; - s->script_ram[addr >>2 ] = val; -} - -static uint32_t lsi_ram_readb (void *opaque,target_phys_addr_t addr) +static uint64_t lsi_ram_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;uint32_t val; +uint32_t mask; - addr &=0x1fff ; val = s->script_ram[addr >>2 ]; + mask = ((uint64_t )1 << (size *8 )) -1 ; val >>= (addr &3 ) *8 ; -return val &0xff ; -} - -static uint32_t lsi_ram_readw (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; -uint32_t val; - - addr &=0x1fff ; - val = s->script_ram[addr >>2 ]; -if (addr &2 ) - val >>=16 ; -return val; -} - -static uint32_t lsi_ram_readl (void *opaque,target_phys_addr_t addr) -{ -LSIState *s = opaque; - - addr &=0x1fff ; -return s->script_ram[addr >>2 ]; +return val & mask; } -static CPUReadMemoryFunc *const lsi_ram_readfn[3 ] = { - lsi_ram_readb, - lsi_ram_readw, - lsi_ram_readl, +static const MemoryRegionOps lsi_ram_ops = { + .read = lsi_ram_read, + .write = lsi_ram_write, + .endianness =DEVICE_NATIVE_ENDIAN , }; -static CPUWriteMemoryFunc *const lsi_ram_writefn[3 ] = { - lsi_ram_writeb, - lsi_ram_writew, - lsi_ram_writel, -}; - -static uint32_t lsi_io_readb (void *opaque,uint32_t addr) +static uint64_t lsi_io_read (void *opaque,target_phys_addr_t addr, +unsigned size) {LSIState *s = opaque;return lsi_reg_readb (s, addr &0xff ); } -static uint32_t lsi_io_readw (void *opaque,uint32_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; -return val; -} - -static uint32_t lsi_io_readl (void *opaque,uint32_t addr) -{ -LSIState *s = opaque; -uint32_t val; - addr &=0xff ; - val =lsi_reg_readb (s, addr); - val |=lsi_reg_readb (s, addr +1 ) <<8 ; - val |=lsi_reg_readb (s, addr +2 ) <<16 ; - val |=lsi_reg_readb (s, addr +3 ) <<24 ; -return val; -} - -static void lsi_io_writeb (void *opaque,uint32_t addr,uint32_t val) +static void lsi_io_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {LSIState *s = opaque;lsi_reg_writeb (s, addr &0xff , val); } -static void lsi_io_writew (void *opaque,uint32_t addr,uint32_t val) -{ -LSIState *s = opaque; - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -} - -static void lsi_io_writel (void *opaque,uint32_t addr,uint32_t val) -{ -LSIState *s = opaque; - addr &=0xff ; -lsi_reg_writeb (s, addr, val &0xff ); -lsi_reg_writeb (s, addr +1 , (val >>8 ) &0xff ); -lsi_reg_writeb (s, addr +2 , (val >>16 ) &0xff ); -lsi_reg_writeb (s, addr +3 , (val >>24 ) &0xff ); -} - -static void lsi_io_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -LSIState *s =DO_UPCAST (LSIState, dev, pci_dev); - -DPRINTF ("Mapping IO at %08" FMT_PCIBUS "\n" , addr); - -register_ioport_write (addr,256 ,1 , lsi_io_writeb, s); -register_ioport_read (addr,256 ,1 , lsi_io_readb, s); -register_ioport_write (addr,256 ,2 , lsi_io_writew, s); -register_ioport_read (addr,256 ,2 , lsi_io_readw, s); -register_ioport_write (addr,256 ,4 , lsi_io_writel, s); -register_ioport_read (addr,256 ,4 , lsi_io_readl, s); -} - -static void lsi_ram_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -LSIState *s =DO_UPCAST (LSIState, dev, pci_dev); - -DPRINTF ("Mapping ram at %08" FMT_PCIBUS "\n" , addr); - s->script_ram_base = addr; -cpu_register_physical_memory (addr +0 ,0x2000 , s->ram_io_addr); -} +static const MemoryRegionOps lsi_io_ops = { + .read = lsi_io_read, + .write = lsi_io_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .impl = { + .min_access_size =1 , + .max_access_size =1 , + }, +};static void lsi_scsi_reset (DeviceState *dev) {@@ -2231,8 +2088,9 @@ static int lsi_scsi_uninit(PCIDevice *d) {LSIState *s =DO_UPCAST (LSIState, dev, d); -cpu_unregister_io_memory (s->mmio_io_addr); -cpu_unregister_io_memory (s->ram_io_addr); +memory_region_destroy (&s->mmio_io); +memory_region_destroy (&s->ram_io); +memory_region_destroy (&s->io_io);return 0 ; }@@ -2256,18 +2114,14 @@ static int lsi_scsi_init(PCIDevice *dev)/* Interrupt pin 1 */ pci_conf[PCI_INTERRUPT_PIN ] =0x01 ; - s->mmio_io_addr =cpu_register_io_memory (lsi_mmio_readfn, - lsi_mmio_writefn, s, -DEVICE_NATIVE_ENDIAN ); - s->ram_io_addr =cpu_register_io_memory (lsi_ram_readfn, - lsi_ram_writefn, s, -DEVICE_NATIVE_ENDIAN ); - -pci_register_bar (&s->dev,0 ,256 , -PCI_BASE_ADDRESS_SPACE_IO , lsi_io_mapfunc); -pci_register_bar_simple (&s->dev,1 ,0x400 ,0 , s->mmio_io_addr); -pci_register_bar (&s->dev,2 ,0x2000 , -PCI_BASE_ADDRESS_SPACE_MEMORY , lsi_ram_mapfunc); +memory_region_init_io (&s->mmio_io, &lsi_mmio_ops, s,"lsi-mmio" ,0x400 ); +memory_region_init_io (&s->ram_io, &lsi_ram_ops, s,"lsi-ram" ,0x2000 ); +memory_region_init_io (&s->io_io, &lsi_io_ops, s,"lsi-io" ,256 ); + +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_io); +pci_register_bar_region (&s->dev,1 ,0 , &s->mmio_io); +pci_register_bar_region (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->ram_io);QTAILQ_INIT (&s->queue);scsi_bus_new (&s->bus, &dev->qdev,1 ,LSI_MAX_DEVS , &lsi_scsi_ops);Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 23/39] lsi53c895a: convert to memory API
Quoted 6 lines · Gerhard Wiesinger
Hello Avi,
qemu/qemu-kvm doesn't boot any more with LSI option rom (-option-rom 8xx_64.rom). Guess it comes from changes of the memory API. Also latest git version from seabios.
Sorry, no further details currently available.
Thanks for your report. I was able to reproduce the problem and will send out patches shortly.
Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
PATCH v4 24/39 ppc: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/cuda.c | 6 ++- hw/escc.c | 42 +++++++++++++-------------- hw/escc.h | 2 +- hw/heathrow_pic.c | 29 ++++++++---------- hw/ide.h | 2 +- hw/ide/macio.c | 36 ++++++++++++----------- hw/mac_dbdma.c | 32 ++++++++++---------- hw/mac_dbdma.h | 4 ++- hw/mac_nvram.c | 39 ++++++++++--------------- hw/macio.c | 74 +++++++++++++++++++++++------------------------- hw/openpic.c | 81 +++++++++++++++++++++++++---------------------------- hw/openpic.h | 2 +- hw/ppc_mac.h | 16 ++++++---- hw/ppc_newworld.c | 30 +++++++++---------- hw/ppc_oldworld.c | 23 +++++++-------- 15 files changed, 201 insertions(+), 217 deletions(-)
hw/cuda.c +4 -2
@@ -117,6 +117,7 @@ typedef struct CUDATimer { } CUDATimer; typedef struct CUDAState { + MemoryRegion mem; /* cuda registers */ uint8_t b; /* B-side data */ uint8_t a; /* A-side data */
@@ -722,7 +723,7 @@ static void cuda_reset(void *opaque)set_counter (s, &s->timers[1 ],0xffff ); } -void cuda_init (int *cuda_mem_index,qemu_irq irq) +void cuda_init (MemoryRegion **cuda_mem,qemu_irq irq) {struct tm tm;CUDAState *s = &cuda_state;
@@ -738,8 +739,9 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq) s->tick_offset = (uint32_t )mktimegm (&tm) +RTC_OFFSET ; s->adb_poll_timer =qemu_new_timer_ns (vm_clock, cuda_adb_poll, s); - *cuda_mem_index =cpu_register_io_memory (cuda_read, cuda_write, s, +cpu_register_io_memory (cuda_read, cuda_write, s,DEVICE_NATIVE_ENDIAN ); + *cuda_mem = &s->mem;vmstate_register (NULL ,-1 , &vmstate_cuda, s);qemu_register_reset (cuda_reset, s); }
hw/escc.c +20 -22
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hw/escc.h +1 -1
@@ -1,6 +1,6 @@/* escc.c */ #define ESCC_SIZE 4 -int escc_init (target_phys_addr_t base,qemu_irq irqA,qemu_irq irqB, +MemoryRegion *escc_init (target_phys_addr_t base,qemu_irq irqA,qemu_irq irqB,CharDriverState *chrA,CharDriverState *chrB,int clock,int it_shift);
hw/heathrow_pic.c +13 -16
@@ -43,6 +43,7 @@ typedef struct HeathrowPIC { } HeathrowPIC;typedef struct HeathrowPICS { +MemoryRegion mem;HeathrowPIC pics[2 ];qemu_irq *irqs; }HeathrowPICS ;
@@ -62,7 +63,8 @@ static void heathrow_pic_update(HeathrowPICS *s) } } -static void pic_writel (void *opaque,target_phys_addr_t addr,uint32_t value) +static void pic_write (void *opaque,target_phys_addr_t addr, +uint64_t value,unsigned size) {HeathrowPICS *s = opaque;HeathrowPIC *pic;
@@ -89,7 +91,8 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) } } -static uint32_t pic_readl (void *opaque,target_phys_addr_t addr) +static uint64_t pic_read (void *opaque,target_phys_addr_t addr, +unsigned size) {HeathrowPICS *s = opaque;HeathrowPIC *pic;
@@ -120,19 +123,12 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)return value; } -static CPUWriteMemoryFunc *const pic_write[] = { - &pic_writel, - &pic_writel, - &pic_writel, +static const MemoryRegionOps heathrow_pic_ops = { + .read = pic_read, + .write = pic_write, + .endianness =DEVICE_NATIVE_ENDIAN , }; -static CPUReadMemoryFunc *const pic_read[] = { - &pic_readl, - &pic_readl, - &pic_readl, -}; - -static void heathrow_pic_set_irq (void *opaque,int num,int level) {HeathrowPICS *s = opaque;
@@ -201,7 +197,7 @@ static void heathrow_pic_reset(void *opaque) s->pics[1 ].level_triggered =0x1ff00000 ; } -qemu_irq *heathrow_pic_init (int *pmem_index, +qemu_irq *heathrow_pic_init (MemoryRegion **pmem,int nb_cpus,qemu_irq **irqs) {HeathrowPICS *s;
@@ -209,8 +205,9 @@ qemu_irq *heathrow_pic_init(int *pmem_index, s =qemu_mallocz (sizeof (HeathrowPICS));/* only 1 CPU */ s->irqs = irqs[0 ]; - *pmem_index =cpu_register_io_memory (pic_read, pic_write, s, -DEVICE_LITTLE_ENDIAN ); +memory_region_init_io (&s->mem, &heathrow_pic_ops, s, +"heathrow-pic" ,0x1000 ); + *pmem = &s->mem;vmstate_register (NULL ,-1 , &vmstate_heathrow_pic, s);qemu_register_reset (heathrow_pic_reset, s);
hw/ide.h +1 -1
@@ -19,7 +19,7 @@ PCIDevice *pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn);void vt82c686b_ide_init (PCIBus *bus,DriveInfo **hd_table,int devfn);/* ide-macio.c */ -int pmac_ide_init (DriveInfo **hd_table,qemu_irq irq, +MemoryRegion *pmac_ide_init (DriveInfo **hd_table,qemu_irq irq,void *dbdma,int channel,qemu_irq dma_irq);/* ide-mmio.c */
hw/ide/macio.c +19 -17
@@ -35,6 +35,7 @@/* MacIO based PowerPC IDE */ typedef struct MACIOIDEState { +MemoryRegion mem;IDEBus bus;BlockDriverAIOCB *aiocb; }MACIOIDEState ;
@@ -281,16 +282,20 @@ static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)return retval; } -static CPUWriteMemoryFunc *const pmac_ide_write[] = { - pmac_ide_writeb, - pmac_ide_writew, - pmac_ide_writel, -}; - -static CPUReadMemoryFunc *const pmac_ide_read[] = { - pmac_ide_readb, - pmac_ide_readw, - pmac_ide_readl, +static MemoryRegionOps pmac_ide_ops = { + .old_mmio = { + .write = { + pmac_ide_writeb, + pmac_ide_writew, + pmac_ide_writel, + }, + .read = { + pmac_ide_readb, + pmac_ide_readw, + pmac_ide_readl, + }, + }, + .endianness =DEVICE_NATIVE_ENDIAN , };static const VMStateDescription vmstate_pmac = {
@@ -315,11 +320,10 @@ static void pmac_ide_reset(void *opaque)/* hd_table must contain 4 block drivers */ /* PowerMac uses memory mapped registers, not I/O. Return the memory I/O index to access the ide. */ -int pmac_ide_init (DriveInfo **hd_table,qemu_irq irq, -void *dbdma,int channel,qemu_irq dma_irq) +MemoryRegion *pmac_ide_init (DriveInfo **hd_table,qemu_irq irq, +void *dbdma,int channel,qemu_irq dma_irq) {MACIOIDEState *d; -int pmac_ide_memory; d =qemu_mallocz (sizeof (MACIOIDEState));ide_init2_with_non_qdev_drives (&d->bus, hd_table[0 ], hd_table[1 ], irq);
@@ -327,11 +331,9 @@ int pmac_ide_init (DriveInfo **hd_table, qemu_irq irq,if (dbdma)DBDMA_register_channel (dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d); - pmac_ide_memory =cpu_register_io_memory (pmac_ide_read, - pmac_ide_write, d, -DEVICE_NATIVE_ENDIAN ); +memory_region_init_io (&d->mem, &pmac_ide_ops, d,"pmac-ide" ,0x1000 );vmstate_register (NULL ,0 , &vmstate_pmac, d);qemu_register_reset (pmac_ide_reset, d); -return pmac_ide_memory; +return &d->mem; }
hw/mac_dbdma.c +16 -16
@@ -166,6 +166,7 @@ typedef struct DBDMA_channel { } DBDMA_channel;typedef struct { +MemoryRegion mem;DBDMA_channel channels[DBDMA_CHANNELS ]; }DBDMAState ;
@@ -703,8 +704,8 @@ dbdma_control_write(DBDMA_channel *ch) ch->flush (&ch->io); } -static void dbdma_writel (void *opaque, -target_phys_addr_t addr,uint32_t value) +static void dbdma_write (void *opaque,target_phys_addr_t addr, +uint64_t value,unsigned size) {int channel = addr >>DBDMA_CHANNEL_SHIFT ;DBDMAState *s = opaque;
@@ -753,7 +754,8 @@ static void dbdma_writel (void *opaque, } } -static uint32_t dbdma_readl (void *opaque,target_phys_addr_t addr) +static uint64_t dbdma_read (void *opaque,target_phys_addr_t addr, +unsigned size) {uint32_t value;int channel = addr >>DBDMA_CHANNEL_SHIFT ;
@@ -798,16 +800,14 @@ static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)return value; } -static CPUWriteMemoryFunc *const dbdma_write[] = { -NULL , -NULL , - dbdma_writel, -}; - -static CPUReadMemoryFunc *const dbdma_read[] = { -NULL , -NULL , - dbdma_readl, +static const MemoryRegionOps dbdma_ops = { + .read = dbdma_read, + .write = dbdma_write, + .endianness =DEVICE_LITTLE_ENDIAN , + .valid = { + .min_access_size =4 , + .max_access_size =4 , + }, };static const VMStateDescription vmstate_dbdma_channel = {
@@ -842,14 +842,14 @@ static void dbdma_reset(void *opaque)memset (s->channels[i].regs,0 ,DBDMA_SIZE ); } -void *DBDMA_init (int *dbdma_mem_index) +void *DBDMA_init (MemoryRegion **dbdma_mem) {DBDMAState *s; s =qemu_mallocz (sizeof (DBDMAState)); - *dbdma_mem_index =cpu_register_io_memory (dbdma_read, dbdma_write, s, -DEVICE_LITTLE_ENDIAN ); +memory_region_init_io (&s->mem, &dbdma_ops, s,"dbdma" ,0x1000 ); + *dbdma_mem = &s->mem;vmstate_register (NULL ,-1 , &vmstate_dbdma, s);qemu_register_reset (dbdma_reset, s);
hw/mac_dbdma.h +3 -1
@@ -20,6 +20,8 @@* THE SOFTWARE. */ +#include "memory.h" +typedef struct DBDMA_io DBDMA_io ;typedef void (*DBDMA_flush )(DBDMA_io *io);
@@ -40,4 +42,4 @@ void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, DBDMA_rw rw, DBDMA_flush flush, void *opaque);void DBDMA_schedule (void ); -void *DBDMA_init (int *dbdma_mem_index); +void *DBDMA_init (MemoryRegion **dbdma_mem);
hw/mac_nvram.c +15 -24
@@ -39,7 +39,7 @@struct MacIONVRAMState {uint32_t size; -int mem_index; +MemoryRegion mem;unsigned int it_shift;uint8_t *data; };
@@ -71,8 +71,8 @@ void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val) }/* macio style NVRAM device */ -static void macio_nvram_writeb (void *opaque, -target_phys_addr_t addr,uint32_t value) +static void macio_nvram_writeb (void *opaque,target_phys_addr_t addr, +uint64_t value,unsigned size) {MacIONVRAMState *s = opaque;
@@ -81,7 +81,8 @@ static void macio_nvram_writeb (void *opaque,NVR_DPRINTF ("writeb addr %04x val %x\n" , (int )addr, value); } -static uint32_t macio_nvram_readb (void *opaque,target_phys_addr_t addr) +static uint64_t macio_nvram_readb (void *opaque,target_phys_addr_t addr, +unsigned size) {MacIONVRAMState *s = opaque;uint32_t value;
@@ -93,16 +94,10 @@ static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)return value; } -static CPUWriteMemoryFunc *const nvram_write[] = { - &macio_nvram_writeb, - &macio_nvram_writeb, - &macio_nvram_writeb, -}; - -static CPUReadMemoryFunc *const nvram_read[] = { - &macio_nvram_readb, - &macio_nvram_readb, - &macio_nvram_readb, +static const MemoryRegionOps macio_nvram_ops = { + .read = macio_nvram_readb, + .write = macio_nvram_writeb, + .endianness =DEVICE_NATIVE_ENDIAN , };static const VMStateDescription vmstate_macio_nvram = {
@@ -121,7 +116,7 @@ static void macio_nvram_reset(void *opaque) { } -MacIONVRAMState *macio_nvram_init (int *mem_index,target_phys_addr_t size, +MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,unsigned int it_shift) {MacIONVRAMState *s;
@@ -131,22 +126,18 @@ MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size, s->size = size; s->it_shift = it_shift; - s->mem_index =cpu_register_io_memory (nvram_read, nvram_write, s, -DEVICE_NATIVE_ENDIAN ); - *mem_index = s->mem_index; +memory_region_init_io (&s->mem, &macio_nvram_ops, s,"macio-nvram" , + size << it_shift);vmstate_register (NULL ,-1 , &vmstate_macio_nvram, s);qemu_register_reset (macio_nvram_reset, s);return s; } -void macio_nvram_map (void *opaque,target_phys_addr_t mem_base) +void macio_nvram_setup_bar (MacIONVRAMState *s,MemoryRegion *bar, +target_phys_addr_t mem_base) { -MacIONVRAMState *s; - - s = opaque; -cpu_register_physical_memory (mem_base, s->size << s->it_shift, - s->mem_index); +memory_region_add_subregion (bar, mem_base, &s->mem); }/* Set up a system OpenBIOS NVRAM partition */
hw/macio.c +36 -38
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hw/openpic.c +38 -43
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hw/openpic.h +1 -1
@@ -11,7 +11,7 @@ enum { OPENPIC_OUTPUT_NB, }; -qemu_irq *openpic_init (PCIBus *bus,int *pmem_index,int nb_cpus, +qemu_irq *openpic_init (PCIBus *bus,MemoryRegion **pmem,int nb_cpus,qemu_irq **irqs,qemu_irq irq_out);qemu_irq *mpic_init (target_phys_addr_t base,int nb_cpus,qemu_irq **irqs,qemu_irq irq_out);
hw/ppc_mac.h +9 -7
@@ -42,15 +42,16 @@#define ESCC_CLOCK 3686400/* Cuda */ -void cuda_init (int *cuda_mem_index,qemu_irq irq); +void cuda_init (MemoryRegion **cuda_mem,qemu_irq irq);/* MacIO */ -void macio_init (PCIBus *bus,int device_id,int is_oldworld,int pic_mem_index, -int dbdma_mem_index,int cuda_mem_index,void *nvram, -int nb_ide,int *ide_mem_index,int escc_mem_index); +void macio_init (PCIBus *bus,int device_id,int is_oldworld, +MemoryRegion *pic_mem,MemoryRegion *dbdma_mem, +MemoryRegion *cuda_mem,void *nvram, +int nb_ide,MemoryRegion **ide_mem,MemoryRegion *escc_mem);/* Heathrow PIC */ -qemu_irq *heathrow_pic_init (int *pmem_index, +qemu_irq *heathrow_pic_init (MemoryRegion **pmem,int nb_cpus,qemu_irq **irqs);/* Grackle PCI */
@@ -69,9 +70,10 @@ PCIBus *pci_pmac_u3_init(qemu_irq *pic,/* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState ; -MacIONVRAMState *macio_nvram_init (int *mem_index,target_phys_addr_t size, +MacIONVRAMState *macio_nvram_init (target_phys_addr_t size,unsigned int it_shift); -void macio_nvram_map (void *opaque,target_phys_addr_t mem_base); +void macio_nvram_setup_bar (MacIONVRAMState *s,MemoryRegion *bar, +target_phys_addr_t mem_base);void pmac_format_nvram_partition (MacIONVRAMState *nvr,int len);uint32_t macio_nvram_read (void *opaque,uint32_t addr);void macio_nvram_write (void *opaque,uint32_t addr,uint32_t val);
hw/ppc_newworld.c +14 -16
@@ -144,10 +144,9 @@ static void ppc_core99_init (ram_addr_t ram_size,long kernel_size, initrd_size;PCIBus *pci_bus;MacIONVRAMState *nvr; -int nvram_mem_index;int bios_size; -int pic_mem_index, dbdma_mem_index, cuda_mem_index, escc_mem_index; -int ide_mem_index[3 ]; +MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem, *escc_mem; +MemoryRegion *ide_mem[3 ];int ppc_boot_device;DriveInfo *hd[MAX_IDE_BUS *MAX_IDE_DEVS ];void *fw_cfg;
@@ -315,7 +314,7 @@ static void ppc_core99_init (ram_addr_t ram_size,exit (1 ); } } - pic =openpic_init (NULL , &pic_mem_index, smp_cpus, openpic_irqs,NULL ); + pic =openpic_init (NULL , &pic_mem, smp_cpus, openpic_irqs,NULL );if (PPC_INPUT (env) ==PPC_FLAGS_INPUT_970 ) {/* 970 gets a U3 bus */ pci_bus =pci_pmac_u3_init (pic,get_system_memory (),get_system_io ());
@@ -327,32 +326,31 @@ static void ppc_core99_init (ram_addr_t ram_size,/* init basic PC hardware */ pci_vga_init (pci_bus); - escc_mem_index =escc_init (0x80013000 , pic[0x25 ], pic[0x24 ], - serial_hds[0 ], serial_hds[1 ],ESCC_CLOCK ,4 ); + escc_mem =escc_init (0x80013000 , pic[0x25 ], pic[0x24 ], + serial_hds[0 ], serial_hds[1 ],ESCC_CLOCK ,4 );for (i =0 ; i < nb_nics; i++)pci_nic_init_nofail (&nd_table[i],"ne2k_pci" ,NULL );ide_drive_get (hd,MAX_IDE_BUS ); - dbdma =DBDMA_init (&dbdma_mem_index); + dbdma =DBDMA_init (&dbdma_mem);/* We only emulate 2 out of 3 IDE controllers for now */ - ide_mem_index[0 ] =-1 ; - ide_mem_index[1 ] =pmac_ide_init (hd, pic[0x0d ], dbdma,0x16 , pic[0x02 ]); - ide_mem_index[2 ] =pmac_ide_init (&hd[MAX_IDE_DEVS ], pic[0x0e ], dbdma,0x1a , pic[0x02 ]); + ide_mem[0 ] =NULL ; + ide_mem[1 ] =pmac_ide_init (hd, pic[0x0d ], dbdma,0x16 , pic[0x02 ]); + ide_mem[2 ] =pmac_ide_init (&hd[MAX_IDE_DEVS ], pic[0x0e ], dbdma,0x1a , pic[0x02 ]);/* cuda also initialize ADB */ if (machine_arch ==ARCH_MAC99_U3 ) { usb_enabled =1 ; } -cuda_init (&cuda_mem_index, pic[0x19 ]); +cuda_init (&cuda_mem, pic[0x19 ]);adb_kbd_init (&adb_bus);adb_mouse_init (&adb_bus); -macio_init (pci_bus,PCI_DEVICE_ID_APPLE_UNI_N_KEYL ,0 , pic_mem_index, - dbdma_mem_index, cuda_mem_index,NULL ,3 , ide_mem_index, - escc_mem_index); +macio_init (pci_bus,PCI_DEVICE_ID_APPLE_UNI_N_KEYL ,0 , pic_mem, + dbdma_mem, cuda_mem,NULL ,3 , ide_mem, escc_mem);if (usb_enabled) {usb_ohci_init_pci (pci_bus,-1 );
@@ -369,9 +367,9 @@ static void ppc_core99_init (ram_addr_t ram_size, graphic_depth =15 ;/* The NewWorld NVRAM is not located in the MacIO device */ - nvr =macio_nvram_init (&nvram_mem_index,0x2000 ,1 ); + nvr =macio_nvram_init (0x2000 ,1 );pmac_format_nvram_partition (nvr,0x2000 ); -macio_nvram_map (nvr,0xFFF04000 ); +macio_nvram_setup_bar (nvr,get_system_memory (),0xFFF04000 );/* No PCI init: the BIOS will do it */ fw_cfg =fw_cfg_init (0 ,0 ,CFG_ADDR ,CFG_ADDR +2 );
hw/ppc_oldworld.c +11 -12
@@ -82,8 +82,8 @@ static void ppc_heathrow_init (ram_addr_t ram_size,PCIBus *pci_bus;MacIONVRAMState *nvr;int bios_size; -int pic_mem_index, nvram_mem_index, dbdma_mem_index, cuda_mem_index; -int escc_mem_index, ide_mem_index[2 ]; +MemoryRegion *pic_mem, *dbdma_mem, *cuda_mem; +MemoryRegion *escc_mem, *ide_mem[2 ];uint16_t ppc_boot_device;DriveInfo *hd[MAX_IDE_BUS *MAX_IDE_DEVS ];void *fw_cfg;
@@ -233,13 +233,13 @@ static void ppc_heathrow_init (ram_addr_t ram_size,if (PPC_INPUT (env) != PPC_FLAGS_INPUT_6xx) {hw_error ("Only 6xx bus is supported on heathrow machine\n" ); } - pic =heathrow_pic_init (&pic_mem_index,1 , heathrow_irqs); + pic =heathrow_pic_init (&pic_mem,1 , heathrow_irqs); pci_bus =pci_grackle_init (0xfec00000 , pic,get_system_memory (),get_system_io ());pci_vga_init (pci_bus); - escc_mem_index =escc_init (0x80013000 , pic[0x0f ], pic[0x10 ], serial_hds[0 ], + escc_mem =escc_init (0x80013000 , pic[0x0f ], pic[0x10 ], serial_hds[0 ], serial_hds[1 ],ESCC_CLOCK ,4 );for (i =0 ; i < nb_nics; i++)
@@ -249,9 +249,9 @@ static void ppc_heathrow_init (ram_addr_t ram_size,ide_drive_get (hd,MAX_IDE_BUS );/* First IDE channel is a MAC IDE on the MacIO bus */ - dbdma =DBDMA_init (&dbdma_mem_index); - ide_mem_index[0 ] =-1 ; - ide_mem_index[1 ] =pmac_ide_init (hd, pic[0x0D ], dbdma,0x16 , pic[0x02 ]); + dbdma =DBDMA_init (&dbdma_mem); + ide_mem[0 ] =NULL ; + ide_mem[1 ] =pmac_ide_init (hd, pic[0x0D ], dbdma,0x16 , pic[0x02 ]);/* Second IDE channel is a CMD646 on the PCI bus */ hd[0 ] = hd[MAX_IDE_DEVS ];
@@ -260,17 +260,16 @@ static void ppc_heathrow_init (ram_addr_t ram_size,pci_cmd646_ide_init (pci_bus, hd,0 );/* cuda also initialize ADB */ -cuda_init (&cuda_mem_index, pic[0x12 ]); +cuda_init (&cuda_mem, pic[0x12 ]);adb_kbd_init (&adb_bus);adb_mouse_init (&adb_bus); - nvr =macio_nvram_init (&nvram_mem_index,0x2000 ,4 ); + nvr =macio_nvram_init (0x2000 ,4 );pmac_format_nvram_partition (nvr,0x2000 ); -macio_init (pci_bus,PCI_DEVICE_ID_APPLE_343S1201 ,1 , pic_mem_index, - dbdma_mem_index, cuda_mem_index, nvr,2 , ide_mem_index, - escc_mem_index); +macio_init (pci_bus,PCI_DEVICE_ID_APPLE_343S1201 ,1 , pic_mem, + dbdma_mem, cuda_mem, nvr,2 , ide_mem, escc_mem);if (usb_enabled) {usb_ohci_init_pci (pci_bus,-1 );
Signature · 1 line
1.7.5.3
Re: [Qemu-devel] [PATCH v4 24/39] ppc: convert to memory API
[dropping kvm@vger because my mail server refuses to send mails there]
Quoted 43 lines · Avi Kivity
Reviewed-by Richard Henderson <[email protected]>Reviewed-by Anthony Liguori <[email protected]>Signed-off-by Avi Kivity <[email protected]>---
hw/cuda.c | 6 ++- hw/escc.c | 42 +++++++++++++-------------- hw/escc.h | 2 +- hw/heathrow_pic.c | 29 ++++++++---------- hw/ide.h | 2 +- hw/ide/macio.c | 36 ++++++++++++----------- hw/mac_dbdma.c | 32 ++++++++++---------- hw/mac_dbdma.h | 4 ++- hw/mac_nvram.c | 39 ++++++++++--------------- hw/macio.c | 74 +++++++++++++++++++++++------------------------- hw/openpic.c | 81 +++++++++++++++++++++++++---------------------------- hw/openpic.h | 2 +- hw/ppc_mac.h | 16 ++++++---- hw/ppc_newworld.c | 30 +++++++++---------- hw/ppc_oldworld.c | 23 +++++++-------- 15 files changed, 201 insertions(+), 217 deletions(-)hw/cuda.c +2
-1@@ -117,6 +117,7 @@ typedef struct CUDATimer { } CUDATimer; typedef struct CUDAState { + MemoryRegion mem; /* cuda registers */ uint8_t b; /* B-side data */ uint8_t a; /* A-side data */@@ -722,7 +723,7 @@ static void cuda_reset(void *opaque)set_counter (s, &s->timers[1 ],0xffff ); } -void cuda_init (int *cuda_mem_index,qemu_irq irq) +void cuda_init (MemoryRegion **cuda_mem,qemu_irq irq) {struct tm tm;CUDAState *s = &cuda_state;
hw/cuda.c void cuda_init (int *cuda_mem_index, qemu_irq irq) · line 744
Quoted 7 lines
hw/cuda.c +2
-1@@ -738,8 +739,9 @@ void cuda_init (int *cuda_mem_index, qemu_irq irq) s->tick_offset = (uint32_t )mktimegm (&tm) +RTC_OFFSET ; s->adb_poll_timer =qemu_new_timer_ns (vm_clock, cuda_adb_poll, s); - *cuda_mem_index =cpu_register_io_memory (cuda_read, cuda_write, s, +cpu_register_io_memory (cuda_read, cuda_write, s,DEVICE_NATIVE_ENDIAN ); + *cuda_mem = &s->mem;
Just stumbled over this while debugging why the Mac machines don't boot anymore. Are you sure this part is correct? We're not registering the region (and its callbacks) anymore now, right?
Alex
Re: [Qemu-devel] [PATCH v4 24/39] ppc: convert to memory API
In reply to Avi KivityQuoted 22 lines · Avi Kivity
Reviewed-by Richard Henderson <[email protected]>Reviewed-by Anthony Liguori <[email protected]>Signed-off-by Avi Kivity <[email protected]>---
hw/cuda.c | 6 ++- hw/escc.c | 42 +++++++++++++-------------- hw/escc.h | 2 +- hw/heathrow_pic.c | 29 ++++++++---------- hw/ide.h | 2 +- hw/ide/macio.c | 36 ++++++++++++----------- hw/mac_dbdma.c | 32 ++++++++++---------- hw/mac_dbdma.h | 4 ++- hw/mac_nvram.c | 39 ++++++++++--------------- hw/macio.c | 74 +++++++++++++++++++++++------------------------- hw/openpic.c | 81 +++++++++++++++++++++++++---------------------------- hw/openpic.h | 2 +- hw/ppc_mac.h | 16 ++++++---- hw/ppc_newworld.c | 30 +++++++++---------- hw/ppc_oldworld.c | 23 +++++++-------- 15 files changed, 201 insertions(+), 217 deletions(-)
[...]
Quoted 12 lines
hw/heathrow_pic.c +2
-1@@ -89,7 +91,8 @@ static void pic_writel (void *opaque, target_phys_addr_t addr, uint32_t value) } } -static uint32_t pic_readl (void *opaque,target_phys_addr_t addr) +static uint64_t pic_read (void *opaque,target_phys_addr_t addr, +unsigned size) {HeathrowPICS *s = opaque;HeathrowPIC *pic;@@ -120,19 +123,12 @@ static uint32_t pic_readl (void *opaque, target_phys_addr_t addr)return value;
hw/heathrow_pic.c static uint32_t pic_readl (void *opaque, target_phys_addr_t addr) · line 129
Quoted 10 lines
hw/heathrow_pic.c +4
-4} -static CPUWriteMemoryFunc *const pic_write[] = { - &pic_writel, - &pic_writel, - &pic_writel, +static const MemoryRegionOps heathrow_pic_ops = { + .read = pic_read, + .write = pic_write, + .endianness =DEVICE_NATIVE_ENDIAN ,
native endian
Quoted 22 lines
hw/heathrow_pic.c +1
-8}; -static CPUReadMemoryFunc *const pic_read[] = { - &pic_readl, - &pic_readl, - &pic_readl, -}; - -static void heathrow_pic_set_irq (void *opaque,int num,int level) {HeathrowPICS *s = opaque;@@ -201,7 +197,7 @@ static void heathrow_pic_reset(void *opaque) s->pics[1 ].level_triggered =0x1ff00000 ; } -qemu_irq *heathrow_pic_init (int *pmem_index, +qemu_irq *heathrow_pic_init (MemoryRegion **pmem,int nb_cpus,qemu_irq **irqs) {HeathrowPICS *s;
hw/heathrow_pic.c qemu_irq *heathrow_pic_init(int *pmem_index, · line 213
Quoted 5 lines
hw/heathrow_pic.c +0
-2@@ -209,8 +205,9 @@ qemu_irq *heathrow_pic_init(int *pmem_index, s =qemu_mallocz (sizeof (HeathrowPICS));/* only 1 CPU */ s->irqs = irqs[0 ]; - *pmem_index =cpu_register_io_memory (pic_read, pic_write, s, -DEVICE_LITTLE_ENDIAN );
little endian. So you're changing the endianness of the calls? Not nice.
Alex
PATCH v4 25/39 ne2000: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ne2000-isa.c | 13 ++------- hw/ne2000.c | 77 +++++++++++++++++++++++++++++++++++++----------------- hw/ne2000.h | 8 +---- 3 files changed, 58 insertions(+), 40 deletions(-)
hw/ne2000-isa.c +3 -10
@@ -27,6 +27,7 @@#include "qdev.h" #include "net.h" #include "ne2000.h" +#include "exec-memory.h" typedef struct ISANE2000State { ISADevice dev;
@@ -66,19 +67,11 @@ static int isa_ne2000_initfn(ISADevice *dev)ISANE2000State *isa =DO_UPCAST (ISANE2000State, dev, dev);NE2000State *s = &isa->ne2000; -register_ioport_write (isa->iobase,16 ,1 , ne2000_ioport_write, s); -register_ioport_read (isa->iobase,16 ,1 , ne2000_ioport_read, s); +ne2000_setup_io (s,0x20 );isa_init_ioport_range (dev, isa->iobase,16 ); - -register_ioport_write (isa->iobase +0x10 ,1 ,1 , ne2000_asic_ioport_write, s); -register_ioport_read (isa->iobase +0x10 ,1 ,1 , ne2000_asic_ioport_read, s); -register_ioport_write (isa->iobase +0x10 ,2 ,2 , ne2000_asic_ioport_write, s); -register_ioport_read (isa->iobase +0x10 ,2 ,2 , ne2000_asic_ioport_read, s);isa_init_ioport_range (dev, isa->iobase +0x10 ,2 ); - -register_ioport_write (isa->iobase +0x1f ,1 ,1 , ne2000_reset_ioport_write, s); -register_ioport_read (isa->iobase +0x1f ,1 ,1 , ne2000_reset_ioport_read, s);isa_init_ioport (dev, isa->iobase +0x1f ); +memory_region_add_subregion (get_system_io (), isa->iobase, &s->io);isa_init_irq (dev, &s->irq, isa->isairq);
hw/ne2000.c +53 -24
135 lines not on this page · raw message
hw/ne2000.h +2 -6
@@ -4,6 +4,7 @@#define NE2000_MEM_SIZE NE2000_PMEM_END typedef struct NE2000State { + MemoryRegion io; uint8_t cmd; uint32_t start; uint32_t stop;
@@ -27,12 +28,7 @@ typedef struct NE2000State {uint8_t mem[NE2000_MEM_SIZE ]; } NE2000State; -void ne2000_ioport_write (void *opaque,uint32_t addr,uint32_t val); -uint32_t ne2000_ioport_read (void *opaque,uint32_t addr); -void ne2000_asic_ioport_write (void *opaque,uint32_t addr,uint32_t val); -uint32_t ne2000_asic_ioport_read (void *opaque,uint32_t addr); -void ne2000_reset_ioport_write (void *opaque,uint32_t addr,uint32_t val); -uint32_t ne2000_reset_ioport_read (void *opaque,uint32_t addr); +void ne2000_setup_io (NE2000State *s,unsigned size);extern const VMStateDescription vmstate_ne2000;void ne2000_reset (NE2000State *s);int ne2000_can_receive (VLANClientState *vc);
Signature · 1 line
1.7.5.3
PATCH v4 26/39 pcnet: convert to memory API
In reply to Avi KivityAlso related chips.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/lance.c | 31 ++++++++++------------- hw/pcnet-pci.c | 74 +++++++++++++++++++++++++++++++++---------------------- hw/pcnet.h | 4 ++- 3 files changed, 61 insertions(+), 48 deletions(-)
hw/lance.c +14 -17
@@ -55,8 +55,8 @@ static void parent_lance_reset(void *opaque, int irq, int level)pcnet_h_reset (&d->state); } -static void lance_mem_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void lance_mem_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {SysBusPCNetState *d = opaque;
@@ -64,7 +64,8 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr,pcnet_ioport_writew (&d->state, addr, val &0xffff ); } -static uint32_t lance_mem_readw (void *opaque,target_phys_addr_t addr) +static uint64_t lance_mem_read (void *opaque,target_phys_addr_t addr, +unsigned size) {SysBusPCNetState *d = opaque;uint32_t val;
@@ -74,16 +75,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)return val &0xffff ; } -static CPUReadMemoryFunc *const lance_mem_read[3 ] = { -NULL , - lance_mem_readw, -NULL , -}; - -static CPUWriteMemoryFunc *const lance_mem_write[3 ] = { -NULL , - lance_mem_writew, -NULL , +static const MemoryRegionOps lance_mem_ops = { + .read = lance_mem_read, + .write = lance_mem_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .valid = { + .min_access_size =2 , + .max_access_size =2 , + }, };static void lance_cleanup (VLANClientState *nc)
@@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev)SysBusPCNetState *d =FROM_SYSBUS (SysBusPCNetState, dev);PCNetState *s = &d->state; - s->mmio_index = -cpu_register_io_memory (lance_mem_read, lance_mem_write, d, -DEVICE_NATIVE_ENDIAN ); +memory_region_init_io (&s->mmio, &lance_mem_ops, s,"lance-mmio" ,4 );qdev_init_gpio_in (&dev->qdev, parent_lance_reset,1 ); -sysbus_init_mmio (dev,4 , s->mmio_index); +sysbus_init_mmio_region (dev, &s->mmio);sysbus_init_irq (dev, &s->irq);
hw/pcnet-pci.c +44 -30
112 lines not on this page · raw message
hw/pcnet.h +3 -1
@@ -4,6 +4,7 @@#define PCNET_LOOPTEST_CRC 1#define PCNET_LOOPTEST_NOCRC 2 +#include "memory.h" typedef struct PCNetState_st PCNetState ;
@@ -17,7 +18,8 @@ struct PCNetState_st {uint16_t csr[128 ];uint16_t bcr[32 ];uint64_t timer; -int mmio_index, xmit_pos; +MemoryRegion mmio; +int xmit_pos;uint8_t buffer[4096 ];int tx_busy;qemu_irq irq;
Signature · 1 line
1.7.5.3
Re: [PATCH v4 26/39] pcnet: convert to memory API
Quoted 62 lines · Avi Kivity
Also related chips.
Reviewed-by Richard Henderson <[email protected]>Reviewed-by Anthony Liguori <[email protected]>Signed-off-by Avi Kivity <[email protected]>--- hw/lance.c | 31 ++++++++++------------- hw/pcnet-pci.c | 74 +++++++++++++++++++++++++++++++++---------------------- hw/pcnet.h | 4 ++- 3 files changed, 61 insertions(+), 48 deletions(-)hw/lance.c +12
-13@@ -55,8 +55,8 @@ static void parent_lance_reset(void *opaque, int irq, int level)pcnet_h_reset (&d->state); } -static void lance_mem_writew (void *opaque,target_phys_addr_t addr, -uint32_t val) +static void lance_mem_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) {SysBusPCNetState *d = opaque;@@ -64,7 +64,8 @@ static void lance_mem_writew(void *opaque, target_phys_addr_t addr,pcnet_ioport_writew (&d->state, addr, val &0xffff ); } -static uint32_t lance_mem_readw (void *opaque,target_phys_addr_t addr) +static uint64_t lance_mem_read (void *opaque,target_phys_addr_t addr, +unsigned size) {SysBusPCNetState *d = opaque;uint32_t val;@@ -74,16 +75,14 @@ static uint32_t lance_mem_readw(void *opaque, target_phys_addr_t addr)return val &0xffff ; } -static CPUReadMemoryFunc *const lance_mem_read[3 ] = { -NULL , - lance_mem_readw, -NULL , -}; - -static CPUWriteMemoryFunc *const lance_mem_write[3 ] = { -NULL , - lance_mem_writew, -NULL , +static const MemoryRegionOps lance_mem_ops = { + .read = lance_mem_read, + .write = lance_mem_write, + .endianness =DEVICE_NATIVE_ENDIAN , + .valid = { + .min_access_size =2 , + .max_access_size =2 , + }, };static void lance_cleanup (VLANClientState *nc)
hw/lance.c static int lance_init(SysBusDevice *dev) · line 119
Quoted 7 lines
hw/lance.c +1
-3@@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev)SysBusPCNetState *d =FROM_SYSBUS (SysBusPCNetState, dev);PCNetState *s = &d->state; - s->mmio_index = -cpu_register_io_memory (lance_mem_read, lance_mem_write, d, -DEVICE_NATIVE_ENDIAN ); +memory_region_init_io (&s->mmio, &lance_mem_ops, s,"lance-mmio" ,4 );
You've switched up d and s here, so anything that tries to talk to the ethernet, such as a sparc32 guest, will now cause Qemu to segfault.
Bob
Re: [Qemu-devel] [PATCH v4 26/39] pcnet: convert to memory API
Quoted 5 lines · Bob Breuer
Quoted 5 lines
static void
lance_cleanup(VLANClientState *nc)
@@ -117,13 +116,11 @@ static intlance_init(SysBusDevice *dev)SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); PCNetState *s =&d->state;
Quoted 9 lines
Quoted 4 lines
-
s->mmio_index=
- cpu_register_io_memory(lance_mem_read,lance_mem_write, d,
-DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(&s->mmio,&lance_mem_ops, s, "lance-mmio", 4);You've switched up d and s here, so anything that tries to talk to the ethernet, such as a sparc32 guest, will now cause Qemu to segfault.
Good catch; will post a fix.
Maybe keeping the opaque wasn't such a good idea.
Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
Re: [Qemu-devel] [PATCH v4 26/39] pcnet: convert to memory API
Quoted 11 lines · Avi Kivity
Quoted 10 lines · Bob Breuer
Quoted 9 lines
static void
lance_cleanup(VLANClientState *nc)
@@ -117,13 +116,11 @@ static intlance_init(SysBusDevice *dev)SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); PCNetState *s =&d->state;-
s->mmio_index=
- cpu_register_io_memory(lance_mem_read,lance_mem_write, d,
-DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(&s->mmio,&lance_mem_ops, s, "lance-mmio", 4);
Quoted 8 lines
Quoted 4 lines
You've switched up d and s here, so anything that tries to talk to the ethernet, such as a sparc32 guest, will now cause Qemu to segfault.
Good catch; will post a fix.
Maybe keeping the opaque wasn't such a good idea.
Yes, we typically can get from the mmio to the device state using container_of.
Quoted 3 lines
Signature · 2 lines
I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.
Re: [Qemu-devel] [PATCH v4 26/39] pcnet: convert to memory API
Quoted 17 lines · Michael S. Tsirkin
Quoted 16 lines · Avi Kivity
Quoted 14 lines · Bob Breuer
Quoted 9 lines
static void lance_cleanup(VLANClientState *nc) @@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev) SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); PCNetState *s =&d->state;-
s->mmio_index=
- cpu_register_io_memory(lance_mem_read,lance_mem_write, d,
-DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(&s->mmio,&lance_mem_ops, s, "lance-mmio", 4);You've switched up d and s here, so anything that tries to talk to the ethernet, such as a sparc32 guest, will now cause Qemu to segfault.
Quoted 8 lines
Quoted 3 lines
Good catch; will post a fix.
Maybe keeping the opaque wasn't such a good idea.
Yes, we typically can get from the mmio to the device state using
container_of.
But in some cases, we can't, and the it's a pain having to wrap MemoryRegion in another structure containing an opaque.
Maybe a good compromise is to:
- keep MemoryRegion::opaque
- pass a MemoryRegion *mr to callbacks instead of opaque
- use container_of() when possible
- use mr->opaque otherwise
Signature · 1 line
error compiling committee.c: too many arguments to function
Re: [Qemu-devel] [PATCH v4 26/39] pcnet: convert to memory API
Quoted 22 lines · Avi Kivity
Quoted 21 lines · Michael S. Tsirkin
Quoted 19 lines · Avi Kivity
Quoted 5 lines · Bob Breuer
Quoted 5 lines
static void lance_cleanup(VLANClientState *nc) @@ -117,13 +116,11 @@ static int lance_init(SysBusDevice *dev) SysBusPCNetState *d = FROM_SYSBUS(SysBusPCNetState, dev); PCNetState *s =&d->state;Quoted 9 lines
Quoted 4 lines
-
s->mmio_index=
- cpu_register_io_memory(lance_mem_read,lance_mem_write, d,
-DEVICE_NATIVE_ENDIAN);
+memory_region_init_io(&s->mmio,&lance_mem_ops, s, "lance-mmio", 4);You've switched up d and s here, so anything that tries to talk to the ethernet, such as a sparc32 guest, will now cause Qemu to segfault.
Good catch; will post a fix.
Maybe keeping the opaque wasn't such a good idea.
Quoted 7 lines
Quoted 4 lines
Yes, we typically can get from the mmio to the device state using
container_of.But in some cases, we can't, and the it's a pain having to wrap MemoryRegion in another structure containing an opaque.
I guess, even though that wrapping structure would use a proper type, not an opaque.
Quoted 6 lines
Maybe a good compromise is to:
- keep
MemoryRegion::opaque
- pass a MemoryRegion *mr to callbacks instead of opaque
- usecontainer_of()when possible
- usemr->opaqueotherwise
Right. This even saves a memory dereference when opaque is unused.
Quoted 2 lines
Signature · 1 line
error compiling committee.c: too many arguments to function
Re: [Qemu-devel] [PATCH v4 26/39] pcnet: convert to memory API
Quoted 6 lines · Michael S. Tsirkin
Quoted 3 lines
But in some cases, we can't, and the it's a pain having to wrap MemoryRegion in another structure containing an opaque.
I guess, even though that wrapping structure would use a proper type, not an opaque.
Yes, of course - that's what the first version did.
Quoted 10 lines
Quoted 6 lines
Maybe a good compromise is to:
- keep
MemoryRegion::opaque
- pass a MemoryRegion *mr to callbacks instead of opaque
- usecontainer_of()when possible
- usemr->opaqueotherwiseRight. This even saves a memory dereference when opaque is unused.
I'll put this on the TODO (as well as writing the TODO).
Signature · 1 line
error compiling committee.c: too many arguments to function
PATCH v4 27/39 i6300esb: convert to memory API
In reply to Avi KivityAlso add missing destructor.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/wdt_i6300esb.c | 43 +++++++++++++++++++++++++++++-------------- 1 files changed, 29 insertions(+), 14 deletions(-)
hw/wdt_i6300esb.c +29 -14
@@ -66,6 +66,7 @@/* Device state. */ struct I6300State {PCIDevice dev; +MemoryRegion io_mem;int reboot_enabled;/* "Reboot" on timer expiry. The real action * performed depends on the -watchdog-action
@@ -355,6 +356,22 @@ static void i6300esb_mem_writel(void *vp, target_phys_addr_t addr, uint32_t val) } } +static const MemoryRegionOps i6300esb_ops = { + .old_mmio = { + .read = { + i6300esb_mem_readb, + i6300esb_mem_readw, + i6300esb_mem_readl, + }, + .write = { + i6300esb_mem_writeb, + i6300esb_mem_writew, + i6300esb_mem_writel, + }, + }, + .endianness =DEVICE_NATIVE_ENDIAN , +}; +static const VMStateDescription vmstate_i6300esb = { .name ="i6300esb_wdt" , .version_id =sizeof (I6300State),
@@ -381,31 +398,28 @@ static const VMStateDescription vmstate_i6300esb = {static int i6300esb_init (PCIDevice *dev) {I6300State *d =DO_UPCAST (I6300State, dev, dev); -int io_mem; -static CPUReadMemoryFunc *const mem_read[3 ] = { - i6300esb_mem_readb, - i6300esb_mem_readw, - i6300esb_mem_readl, - }; -static CPUWriteMemoryFunc *const mem_write[3 ] = { - i6300esb_mem_writeb, - i6300esb_mem_writew, - i6300esb_mem_writel, - };i6300esb_debug ("I6300State = %p\n" , d); d->timer =qemu_new_timer_ns (vm_clock, i6300esb_timer_expired, d); d->previous_reboot_flag =0 ; - io_mem =cpu_register_io_memory (mem_read, mem_write, d, -DEVICE_NATIVE_ENDIAN ); -pci_register_bar_simple (&d->dev,0 ,0x10 ,0 , io_mem); +memory_region_init_io (&d->io_mem, &i6300esb_ops, d,"i6300esb" ,0x10 ); +pci_register_bar_region (&d->dev,0 ,0 , &d->io_mem);/* qemu_register_coalesced_mmio (addr, 0x10); ? */ return 0 ; } +static int i6300esb_exit (PCIDevice *dev) +{ +I6300State *d =DO_UPCAST (I6300State, dev, dev); + +memory_region_destroy (&d->io_mem); + +return 0 ; +} +static WatchdogTimerModel model = { .wdt_name ="i6300esb" , .wdt_description ="Intel 6300ESB" ,
@@ -419,6 +433,7 @@ static PCIDeviceInfo i6300esb_info = { .config_read = i6300esb_config_read, .config_write = i6300esb_config_write, .init = i6300esb_init, + .exit = i6300esb_exit, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_ESB_9, .class_id = PCI_CLASS_SYSTEM_OTHER,
Signature · 1 line
1.7.5.3
PATCH v4 28/39 isa-mmio: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/isa.h | 2 ++ hw/isa_mmio.c | 29 ++++++++++++++--------------- 2 files changed, 16 insertions(+), 15 deletions(-)
hw/isa.h +2 -0
@@ -4,6 +4,7 @@/* ISA bus */ #include "ioport.h" +#include "memory.h" #include "qdev.h" typedef struct ISABus ISABus ;
@@ -37,6 +38,7 @@ ISADevice *isa_create_simple(const char *name);extern target_phys_addr_t isa_mem_base; +void isa_mmio_setup (MemoryRegion *mr,target_phys_addr_t size);void isa_mmio_init (target_phys_addr_t base,target_phys_addr_t size);/* dma.c */
hw/isa_mmio.c +14 -15
@@ -24,6 +24,7 @@#include "hw.h" #include "isa.h" +#include "exec-memory.h" static void isa_mmio_writeb (void *opaque,target_phys_addr_t addr,uint32_t val)
@@ -58,25 +59,23 @@ static uint32_t isa_mmio_readl(void *opaque, target_phys_addr_t addr)return cpu_inl (addr &IOPORTS_MASK ); } -static CPUWriteMemoryFunc *const isa_mmio_write[] = { - &isa_mmio_writeb, - &isa_mmio_writew, - &isa_mmio_writel, +static const MemoryRegionOps isa_mmio_ops = { + .old_mmio = { + .write = { isa_mmio_writeb, isa_mmio_writew, isa_mmio_writel }, + .read = { isa_mmio_readb, isa_mmio_readw, isa_mmio_readl, }, + }, + .endianness =DEVICE_LITTLE_ENDIAN , }; -static CPUReadMemoryFunc *const isa_mmio_read[] = { - &isa_mmio_readb, - &isa_mmio_readw, - &isa_mmio_readl, -}; +void isa_mmio_setup (MemoryRegion *mr,target_phys_addr_t size) +{ +memory_region_init_io (mr, &isa_mmio_ops,NULL ,"isa-mmio" , size); +}void isa_mmio_init (target_phys_addr_t base,target_phys_addr_t size) { -int isa_mmio_iomemtype; +MemoryRegion *mr =qemu_malloc (sizeof (*mr)); - isa_mmio_iomemtype =cpu_register_io_memory (isa_mmio_read, - isa_mmio_write, -NULL , -DEVICE_LITTLE_ENDIAN ); -cpu_register_physical_memory (base, size, isa_mmio_iomemtype); +isa_mmio_setup (mr, size); +memory_region_add_subregion (get_system_memory (), base, mr); }
Signature · 1 line
1.7.5.3
PATCH v4 29/39 sun4u: convert to memory API
In reply to Avi Kivityfixes memory leak on repeated BAR map/unmap
Reviewed-by Richard Henderson <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/sun4u.c | 55 +++++++++++++++++++++++++------------------------------ 1 files changed, 25 insertions(+), 30 deletions(-)
hw/sun4u.c +23 -28
@@ -91,6 +91,12 @@ struct hwdef {uint64_t console_serial_base; }; +typedef struct EbusState { +PCIDevice pci_dev; +MemoryRegion bar0; +MemoryRegion bar1; +}EbusState ; +int DMA_get_channel_mode (int nchan) {return 0 ;
@@ -518,21 +524,6 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) } } -static void ebus_mmio_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -EBUS_DPRINTF ("Mapping region %d registers at %" FMT_PCIBUS "\n" , - region_num, addr); -switch (region_num) { -case 0 : -isa_mmio_init (addr,0x1000000 ); -break ; -case 1 : -isa_mmio_init (addr,0x800000 ); -break ; - } -} -static void dummy_isa_irq_handler (void *opaque,int n,int level) { }
@@ -549,27 +540,31 @@ pci_ebus_init(PCIBus *bus, int devfn) }static int -pci_ebus_init1 (PCIDevice *s) +pci_ebus_init1 (PCIDevice *pci_dev) { -isa_bus_new (&s->qdev); +EbusState *s =DO_UPCAST (EbusState, pci_dev, pci_dev); + +isa_bus_new (&pci_dev->qdev); - s->config[0x04 ] =0x06 ;// command = bus master, pci mem - s->config[0x05 ] =0x00 ; - s->config[0x06 ] =0xa0 ;// status = fast back-to-back, 66MHz, no error - s->config[0x07 ] =0x03 ;// status = medium devsel - s->config[0x09 ] =0x00 ;// programming i/f - s->config[0x0D ] =0x0a ;// latency_timer + pci_dev->config[0x04 ] =0x06 ;// command = bus master, pci mem + pci_dev->config[0x05 ] =0x00 ; + pci_dev->config[0x06 ] =0xa0 ;// status = fast back-to-back, 66MHz, no error + pci_dev->config[0x07 ] =0x03 ;// status = medium devsel + pci_dev->config[0x09 ] =0x00 ;// programming i/f + pci_dev->config[0x0D ] =0x0a ;// latency_timer -pci_register_bar (s,0 ,0x1000000 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - ebus_mmio_mapfunc); -pci_register_bar (s,1 ,0x800000 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - ebus_mmio_mapfunc); +isa_mmio_setup (&s->bar0,0x1000000 ); +pci_register_bar_region (pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->bar0); +isa_mmio_setup (&s->bar1,0x800000 ); +pci_register_bar_region (pci_dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->bar1);return 0 ; }static PCIDeviceInfo ebus_info = { .qdev.name ="ebus" , - .qdev.size =sizeof (PCIDevice), + .qdev.size =sizeof (EbusState), .init = pci_ebus_init1, .vendor_id =PCI_VENDOR_ID_SUN , .device_id =PCI_DEVICE_ID_SUN_EBUS ,
Signature · 1 line
1.7.5.3
PATCH v4 30/39 ehci: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/usb-ehci.c | 36 +++++++++--------------------------- 1 files changed, 9 insertions(+), 27 deletions(-)
hw/usb-ehci.c +9 -27
@@ -370,8 +370,7 @@ struct EHCIState {PCIDevice dev;USBBus bus;qemu_irq irq; -target_phys_addr_t mem_base; -int mem; +MemoryRegion mem;int companion_count;/* properties */
@@ -2179,29 +2178,15 @@ static void ehci_frame_timer(void *opaque)qemu_mod_timer (ehci->frame_timer, expire_time); } -static CPUReadMemoryFunc *ehci_readfn[3 ]={ - ehci_mem_readb, - ehci_mem_readw, - ehci_mem_readl -}; -static CPUWriteMemoryFunc *ehci_writefn[3 ]={ - ehci_mem_writeb, - ehci_mem_writew, - ehci_mem_writel +static const MemoryRegionOps ehci_mem_ops = { + .old_mmio = { + .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl }, + .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel }, + }, + .endianness =DEVICE_LITTLE_ENDIAN , }; -static void ehci_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -EHCIState *s =(EHCIState *)pci_dev; - -DPRINTF ("ehci_map: region %d, addr %08" PRIx64", size %" PRId64", s->mem %08X\n" , - region_num, addr, size, s->mem); - s->mem_base = addr; -cpu_register_physical_memory (addr, size, s->mem); -} -static int usb_ehci_initfn (PCIDevice *dev);static USBPortOps ehci_port_ops = {
@@ -2316,11 +2301,8 @@ static int usb_ehci_initfn(PCIDevice *dev)qemu_register_reset (ehci_reset, s); - s->mem =cpu_register_io_memory (ehci_readfn, ehci_writefn, s, -DEVICE_LITTLE_ENDIAN ); - -pci_register_bar (&s->dev,0 ,MMIO_SIZE ,PCI_BASE_ADDRESS_SPACE_MEMORY , - ehci_map); +memory_region_init_io (&s->mem, &ehci_mem_ops, s,"ehci" ,MMIO_SIZE ); +pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->mem);fprintf (stderr,"*** EHCI support is under development ***\n" );
Signature · 1 line
1.7.5.3
PATCH v4 31/39 uhci: convert to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/usb-uhci.c | 42 ++++++++++++++++++++++++++++-------------- 1 files changed, 28 insertions(+), 14 deletions(-)
hw/usb-uhci.c +28 -14
@@ -129,6 +129,7 @@ typedef struct UHCIPort {struct UHCIState {PCIDevice dev; +MemoryRegion io_bar;USBBus bus;/* Note unused when we're a companion controller */ uint16_t cmd;/* cmd register */ uint16_t status;
@@ -1096,18 +1097,19 @@ static void uhci_frame_timer(void *opaque)qemu_mod_timer (s->frame_timer, s->expire_time); } -static void uhci_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -UHCIState *s = (UHCIState *)pci_dev; - -register_ioport_write (addr,32 ,2 , uhci_ioport_writew, s); -register_ioport_read (addr,32 ,2 , uhci_ioport_readw, s); -register_ioport_write (addr,32 ,4 , uhci_ioport_writel, s); -register_ioport_read (addr,32 ,4 , uhci_ioport_readl, s); -register_ioport_write (addr,32 ,1 , uhci_ioport_writeb, s); -register_ioport_read (addr,32 ,1 , uhci_ioport_readb, s); -} +static const MemoryRegionPortio uhci_portio[] = { + {0 ,32 ,2 , .write = uhci_ioport_writew, }, + {0 ,32 ,2 , .read = uhci_ioport_readw, }, + {0 ,32 ,4 , .write = uhci_ioport_writel, }, + {0 ,32 ,4 , .read = uhci_ioport_readl, }, + {0 ,32 ,1 , .write = uhci_ioport_writeb, }, + {0 ,32 ,1 , .read = uhci_ioport_readb, }, +PORTIO_END_OF_LIST () +}; + +static const MemoryRegionOps uhci_ioport_ops = { + .old_portio = uhci_portio, +};static USBPortOps uhci_port_ops = { .attach = uhci_attach,
@@ -1154,10 +1156,11 @@ static int usb_uhci_common_initfn(PCIDevice *dev)qemu_register_reset (uhci_reset, s); +memory_region_init_io (&s->io_bar, &uhci_ioport_ops, s,"uhci" ,0x20 );/* Use region 4 for consistency with real hardware. BSD guests seem to rely on this. */ -pci_register_bar (&s->dev,4 ,0x20 , -PCI_BASE_ADDRESS_SPACE_IO , uhci_map); +pci_register_bar_region (&s->dev,4 , +PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar);return 0 ; }
@@ -1177,6 +1180,14 @@ static int usb_uhci_vt82c686b_initfn(PCIDevice *dev)return usb_uhci_common_initfn (dev); } +static int usb_uhci_exit (PCIDevice *dev) +{ +UHCIState *s =DO_UPCAST (UHCIState, dev, dev); + +memory_region_destroy (&s->io_bar); +return 0 ; +} +static Property uhci_properties[] = {DEFINE_PROP_STRING ("masterbus" , UHCIState, masterbus),DEFINE_PROP_UINT32 ("firstport" , UHCIState, firstport,0 ),
@@ -1189,6 +1200,7 @@ static PCIDeviceInfo uhci_info[] = { .qdev.size = sizeof(UHCIState), .qdev.vmsd = &vmstate_uhci, .init = usb_uhci_common_initfn, + .exit = usb_uhci_exit, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, .revision = 0x01,
@@ -1199,6 +1211,7 @@ static PCIDeviceInfo uhci_info[] = { .qdev.size = sizeof(UHCIState), .qdev.vmsd = &vmstate_uhci, .init = usb_uhci_common_initfn, + .exit = usb_uhci_exit, .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, .revision = 0x01,
@@ -1209,6 +1222,7 @@ static PCIDeviceInfo uhci_info[] = { .qdev.size = sizeof(UHCIState), .qdev.vmsd = &vmstate_uhci, .init = usb_uhci_vt82c686b_initfn, + .exit = usb_uhci_exit, .vendor_id = PCI_VENDOR_ID_VIA, .device_id = PCI_DEVICE_ID_VIA_UHCI, .revision = 0x01,
Signature · 1 line
1.7.5.3
PATCH v4 32/39 xen-platform: convert to memory API
In reply to Avi KivitySince this device bypasses PCI and registers I/O ports directly with the system bus, it needs further attention.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/xen_platform.c | 83 ++++++++++++++++++++++++++++++++--------------------- 1 files changed, 50 insertions(+), 33 deletions(-)
hw/xen_platform.c +50 -33
@@ -32,8 +32,8 @@#include "xen_common.h" #include "net.h" #include "xen_backend.h" -#include "rwhandler.h" #include "trace.h" +#include "exec-memory.h" #include <xenguest.h>
@@ -51,6 +51,9 @@ typedef struct PCIXenPlatformState { PCIDevice pci_dev; + MemoryRegion fixed_io; + MemoryRegion bar; + MemoryRegion mmio_bar; uint8_t flags; /* used only for version_id == 2 */ int drivers_blacklisted; uint16_t driver_product_version;
@@ -221,21 +224,32 @@ static void platform_fixed_ioport_reset(void *opaque)platform_fixed_ioport_writeb (s,XEN_PLATFORM_IOPORT ,0 ); } +const MemoryRegionPortio xen_platform_ioport[] = { + {0 ,16 ,4 , .write = platform_fixed_ioport_writel, }, + {0 ,16 ,2 , .write = platform_fixed_ioport_writew, }, + {0 ,16 ,1 , .write = platform_fixed_ioport_writeb, }, + {0 ,16 ,2 , .read = platform_fixed_ioport_readw, }, + {0 ,16 ,1 , .read = platform_fixed_ioport_readb, }, +PORTIO_END_OF_LIST () +}; + +static const MemoryRegionOps platform_fixed_io_ops = { + .old_portio = xen_platform_ioport, + .endianness =DEVICE_NATIVE_ENDIAN , +}; +static void platform_fixed_ioport_init (PCIXenPlatformState * s) { -register_ioport_write (XEN_PLATFORM_IOPORT ,16 ,4 , platform_fixed_ioport_writel, s); -register_ioport_write (XEN_PLATFORM_IOPORT ,16 ,2 , platform_fixed_ioport_writew, s); -register_ioport_write (XEN_PLATFORM_IOPORT ,16 ,1 , platform_fixed_ioport_writeb, s); -register_ioport_read (XEN_PLATFORM_IOPORT ,16 ,2 , platform_fixed_ioport_readw, s); -register_ioport_read (XEN_PLATFORM_IOPORT ,16 ,1 , platform_fixed_ioport_readb, s); +memory_region_init_io (&s->fixed_io, &platform_fixed_io_ops, s, +"xen-fixed" ,16 ); +memory_region_add_subregion (get_system_io (),XEN_PLATFORM_IOPORT , + &s->fixed_io); }/* Xen Platform PCI Device */ static uint32_t xen_platform_ioport_readb (void *opaque,uint32_t addr) { - addr &=0xff ; -if (addr ==0 ) {return platform_fixed_ioport_readb (opaque,XEN_PLATFORM_IOPORT ); }else {
@@ -247,9 +261,6 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val {PCIXenPlatformState *s = opaque; - addr &=0xff ; - val &=0xff ; -switch (addr) {case 0 :/* Platform flags */ platform_fixed_ioport_writeb (opaque,XEN_PLATFORM_IOPORT , val);
@@ -262,15 +273,23 @@ static void xen_platform_ioport_writeb(void *opaque, uint32_t addr, uint32_t val } } -static void platform_ioport_map (PCIDevice *pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type) -{ -PCIXenPlatformState *d =DO_UPCAST (PCIXenPlatformState, pci_dev, pci_dev); +static MemoryRegionPortio xen_pci_portio[] = { + {0 ,0x100 ,1 , .read = xen_platform_ioport_readb, }, + {0 ,0x100 ,1 , .write = xen_platform_ioport_writeb, }, +PORTIO_END_OF_LIST () +}; + +static const MemoryRegionOps xen_pci_io_ops = { + .old_portio = xen_pci_portio, +}; -register_ioport_write (addr, size,1 , xen_platform_ioport_writeb, d); -register_ioport_read (addr, size,1 , xen_platform_ioport_readb, d); +static void platform_ioport_bar_setup (PCIXenPlatformState *d) +{ +memory_region_init_io (&d->bar, &xen_pci_io_ops, d,"xen-pci" ,0x100 ); } -static uint32_t platform_mmio_read (ReadWriteHandler *handler,pcibus_t addr,int len) +static uint64_t platform_mmio_read (void *opaque,target_phys_addr_t addr, +unsigned size) {DPRINTF ("Warning: attempted read from physical address " "0x" TARGET_FMT_plx" in xen platform mmio space\n" , addr);
@@ -278,28 +297,24 @@ static uint32_t platform_mmio_read(ReadWriteHandler *handler, pcibus_t addr, intreturn 0 ; } -static void platform_mmio_write (ReadWriteHandler *handler,pcibus_t addr, -uint32_t val,int len) +static void platform_mmio_write (void *opaque,target_phys_addr_t addr, +uint64_t val,unsigned size) { -DPRINTF ("Warning: attempted write of 0x%x to physical " +DPRINTF ("Warning: attempted write of 0x%" PRIx64" to physical " "address 0x" TARGET_FMT_plx" in xen platform mmio space\n" , val, addr); } -static ReadWriteHandler platform_mmio_handler = { +static const MemoryRegionOps platform_mmio_handler = { .read = &platform_mmio_read, .write = &platform_mmio_write, + .endianness =DEVICE_NATIVE_ENDIAN , }; -static void platform_mmio_map (PCIDevice *d,int region_num, -pcibus_t addr,pcibus_t size,int type) +static void platform_mmio_setup (PCIXenPlatformState *d) { -int mmio_io_addr; - - mmio_io_addr =cpu_register_io_memory_simple (&platform_mmio_handler, -DEVICE_NATIVE_ENDIAN ); - -cpu_register_physical_memory (addr, size, mmio_io_addr); +memory_region_init_io (&d->mmio_bar, &platform_mmio_handler, d, +"xen-mmio" ,0x1000000 ); }static int xen_platform_post_load (void *opaque,int version_id)
@@ -337,12 +352,14 @@ static int xen_platform_initfn(PCIDevice *dev) pci_conf[PCI_INTERRUPT_PIN ] =1 ; -pci_register_bar (&d->pci_dev,0 ,0x100 , -PCI_BASE_ADDRESS_SPACE_IO , platform_ioport_map); +platform_ioport_bar_setup (d); +pci_register_bar_region (&d->pci_dev,0 , +PCI_BASE_ADDRESS_SPACE_IO , &d->bar);/* reserve 16MB mmio address for share memory*/ -pci_register_bar (&d->pci_dev,1 ,0x1000000 , -PCI_BASE_ADDRESS_MEM_PREFETCH , platform_mmio_map); +platform_mmio_setup (d); +pci_register_bar_region (&d->pci_dev,1 , +PCI_BASE_ADDRESS_MEM_PREFETCH , &d->mmio_bar);platform_fixed_ioport_init (d);
Signature · 1 line
1.7.5.3
PATCH v4 33/39 msix: convert to memory API
In reply to Avi KivityThe msix table is defined as a subregion, to allow for a BAR that mixes device specific regions with the msix table.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ivshmem.c | 11 +++++---- hw/msix.c | 64 +++++++++++++++++++------------------------------------ hw/msix.h | 6 +--- hw/pci.h | 2 +- hw/virtio-pci.c | 16 ++++++++----- hw/virtio-pci.h | 1 + 6 files changed, 42 insertions(+), 58 deletions(-)
hw/ivshmem.c +6 -5
@@ -65,6 +65,7 @@ typedef struct IVShmemState {*/ MemoryRegion bar;MemoryRegion ivshmem; +MemoryRegion msix_bar;uint64_t ivshmem_size;/* size of shared memory region */ int shm_fd;/* shared memory file descriptor */
@@ -540,11 +541,11 @@ static void ivshmem_setup_msi(IVShmemState * s) {/* allocate the MSI-X vectors */ -if (!msix_init (&s->dev, s->vectors,1 ,0 )) { -pci_register_bar (&s->dev,1 , -msix_bar_size (&s->dev), -PCI_BASE_ADDRESS_SPACE_MEMORY , - msix_mmio_map); +memory_region_init (&s->msix_bar,"ivshmem-msix" ,4096 ); +if (!msix_init (&s->dev, s->vectors, &s->msix_bar,1 ,0 )) { +pci_register_bar_region (&s->dev,1 , +PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->msix_bar);IVSHMEM_DPRINTF ("msix initialized (%d vectors)\n" , s->vectors); }else {IVSHMEM_DPRINTF ("msix initialization failed\n" );
hw/msix.c +22 -42
131 lines not on this page · raw message
hw/msix.h +2 -4
@@ -5,15 +5,13 @@#include "pci.h" int msix_init (PCIDevice *pdev,unsigned short nentries, +MemoryRegion *bar,unsigned bar_nr,unsigned bar_size);void msix_write_config (PCIDevice *pci_dev,uint32_t address,uint32_t val,int len); -void msix_mmio_map (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type); - -int msix_uninit (PCIDevice *d); +int msix_uninit (PCIDevice *d,MemoryRegion *bar);void msix_save (PCIDevice *dev,QEMUFile *f);void msix_load (PCIDevice *dev,QEMUFile *f);
hw/pci.h +1 -1
@@ -176,7 +176,7 @@ struct PCIDevice {/* Space to store MSIX table */ uint8_t *msix_table_page;/* MMIO index used to map MSIX table and pending bit entries. */ -int msix_mmio_index; +MemoryRegion msix_mmio;/* Reference-count for entries actually in use by driver. */ unsigned *msix_entry_used;/* Region including the MSI-X table */
hw/virtio-pci.c +10 -6
@@ -642,11 +642,12 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)pci_set_word (config +0x2e , vdev->device_id); config[0x3d ] =1 ; -if (vdev->nvectors && !msix_init (&proxy->pci_dev, vdev->nvectors,1 ,0 )) { -pci_register_bar (&proxy->pci_dev,1 , -msix_bar_size (&proxy->pci_dev), -PCI_BASE_ADDRESS_SPACE_MEMORY , - msix_mmio_map); +memory_region_init (&proxy->msix_bar,"virtio-msix" ,4096 ); +if (vdev->nvectors && !msix_init (&proxy->pci_dev, vdev->nvectors, + &proxy->msix_bar,1 ,0 )) { +pci_register_bar_region (&proxy->pci_dev,1 , +PCI_BASE_ADDRESS_SPACE_MEMORY , + &proxy->msix_bar); }else vdev->nvectors =0 ;
@@ -695,9 +696,12 @@ static int virtio_blk_init_pci(PCIDevice *pci_dev)static int virtio_exit_pci (PCIDevice *pci_dev) {VirtIOPCIProxy *proxy =DO_UPCAST (VirtIOPCIProxy, pci_dev, pci_dev); +int r;memory_region_destroy (&proxy->bar); -return msix_uninit (pci_dev); + r =msix_uninit (pci_dev, &proxy->msix_bar); +memory_region_destroy (&proxy->msix_bar); +return r; }static int virtio_blk_exit_pci (PCIDevice *pci_dev)
hw/virtio-pci.h +1 -0
@@ -22,6 +22,7 @@ typedef struct {PCIDevice pci_dev;VirtIODevice *vdev;MemoryRegion bar; +MemoryRegion msix_bar;uint32_t flags;uint32_t class_code;uint32_t nvectors;
Signature · 1 line
1.7.5.3
PATCH v4 34/39 pci: remove pci_register_bar_simple()
In reply to Avi KivitySuperceded by pci_register_bar_region().
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 17 ----------------- hw/pci.h | 3 --- 2 files changed, 0 insertions(+), 20 deletions(-)
hw/pci.c +0 -17
@@ -903,7 +903,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r->filtered_size = size; r->type = type; r->map_func = map_func; - r->ram_addr =IO_MEM_UNASSIGNED ; r->memory =NULL ; wmask = ~(size -1 );
@@ -923,13 +922,6 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, } } -static void pci_simple_bar_mapfunc (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size,int type) -{ -cpu_register_physical_memory (addr, size, - pci_dev->io_regions[region_num].ram_addr); -} -static void pci_simple_bar_mapfunc_region (PCIDevice *pci_dev,int region_num,pcibus_t addr,pcibus_t size,int type)
@@ -942,15 +934,6 @@ static void pci_simple_bar_mapfunc_region(PCIDevice *pci_dev, int region_num, 1); } -void pci_register_bar_simple (PCIDevice *pci_dev,int region_num, -pcibus_t size,uint8_t attr,ram_addr_t ram_addr) -{ -pci_register_bar (pci_dev, region_num, size, -PCI_BASE_ADDRESS_SPACE_MEMORY | attr, - pci_simple_bar_mapfunc); - pci_dev->io_regions[region_num].ram_addr = ram_addr; -} -void pci_register_bar_region (PCIDevice *pci_dev,int region_num,uint8_t attr,MemoryRegion *memory) {
hw/pci.h +0 -3
@@ -93,7 +93,6 @@ typedef struct PCIIORegion {pcibus_t filtered_size;uint8_t type;PCIMapIORegionFunc *map_func; -ram_addr_t ram_addr;MemoryRegion *memory;MemoryRegion *address_space; } PCIIORegion;
@@ -204,8 +203,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name,void pci_register_bar (PCIDevice *pci_dev,int region_num,pcibus_t size,uint8_t type,PCIMapIORegionFunc *map_func); -void pci_register_bar_simple (PCIDevice *pci_dev,int region_num, -pcibus_t size,uint8_t attr,ram_addr_t ram_addr);void pci_register_bar_region (PCIDevice *pci_dev,int region_num,uint8_t attr,MemoryRegion *memory);pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num);
Signature · 1 line
1.7.5.3
PATCH v4 35/39 pci: convert pci rom to memory API
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 20 +++++++------------- hw/pci.h | 3 ++- 2 files changed, 9 insertions(+), 14 deletions(-)
hw/pci.c +7 -13
@@ -1855,11 +1855,6 @@ static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,return next; } -static void pci_map_option_rom (PCIDevice *pdev,int region_num,pcibus_t addr,pcibus_t size,int type) -{ -cpu_register_physical_memory (addr, size, pdev->rom_offset); -} -/* Patch the PCI vendor and device ids in a PCI rom image if necessary. This is needed for an option rom which is used for more than one device. */ static void pci_patch_ids (PCIDevice *pdev,uint8_t *ptr,int size)
@@ -1963,9 +1958,9 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)snprintf (name,sizeof (name),"%s.rom" , pdev->qdev.info->vmsd->name); else snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name); - pdev->rom_offset =qemu_ram_alloc (&pdev->qdev, name, size); - - ptr =qemu_get_ram_ptr (pdev->rom_offset); + pdev->has_rom = true; +memory_region_init_ram (&pdev->rom, &pdev->qdev, name, size); + ptr =memory_region_get_ram_ptr (&pdev->rom);load_image (path, ptr);qemu_free (path);
@@ -1976,19 +1971,18 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)qemu_put_ram_ptr (ptr); -pci_register_bar (pdev,PCI_ROM_SLOT , size, -0 , pci_map_option_rom); +pci_register_bar_region (pdev,PCI_ROM_SLOT ,0 , &pdev->rom);return 0 ; }static void pci_del_option_rom (PCIDevice *pdev) { -if (!pdev->rom_offset) +if (!pdev->has_rom)return ; -qemu_ram_free (pdev->rom_offset); - pdev->rom_offset =0 ; +memory_region_destroy (&pdev->rom); + pdev->has_rom = false; }/*
hw/pci.h +2 -1
@@ -191,7 +191,8 @@ struct PCIDevice {/* Location of option rom */ char *romfile; -ram_addr_t rom_offset; +bool has_rom; +MemoryRegion rom;uint32_t rom_bar; };
Signature · 1 line
1.7.5.3
PATCH v4 36/39 pci: remove pci_register_bar()
In reply to Avi KivitySuperceded by pci_register_bar_region(). The implementations are folded together.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 42 +++++++++++++++++------------------------- hw/pci.h | 3 --- 2 files changed, 17 insertions(+), 28 deletions(-)
hw/pci.c +17 -25
@@ -881,13 +881,25 @@ static int pci_unregister_device(DeviceState *dev)return 0 ; } -void pci_register_bar (PCIDevice *pci_dev,int region_num, -pcibus_t size,uint8_t type, -PCIMapIORegionFunc *map_func) +static void pci_simple_bar_mapfunc_region (PCIDevice *pci_dev,int region_num, +pcibus_t addr,pcibus_t size, +int type) +{ +PCIIORegion *r = &pci_dev->io_regions[region_num]; + +memory_region_add_subregion_overlap (r->address_space, + addr, + r->memory, +1 ); +} + +void pci_register_bar_region (PCIDevice *pci_dev,int region_num, +uint8_t type,MemoryRegion *memory) {PCIIORegion *r;uint32_t addr;uint64_t wmask; +pcibus_t size =memory_region_size (memory);assert (region_num >=0 );assert (region_num <PCI_NUM_REGIONS );
@@ -902,7 +914,7 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num, r->size = size; r->filtered_size = size; r->type = type; - r->map_func = map_func; + r->map_func = pci_simple_bar_mapfunc_region; r->memory =NULL ; wmask = ~(size -1 );
@@ -920,29 +932,9 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,pci_set_long (pci_dev->wmask + addr, wmask &0xffffffff );pci_set_long (pci_dev->cmask + addr,0xffffffff ); } -} - -static void pci_simple_bar_mapfunc_region (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size, -int type) -{ -PCIIORegion *r = &pci_dev->io_regions[region_num]; - -memory_region_add_subregion_overlap (r->address_space, - addr, - r->memory, -1 ); -} - -void pci_register_bar_region (PCIDevice *pci_dev,int region_num, -uint8_t attr,MemoryRegion *memory) -{ -pci_register_bar (pci_dev, region_num,memory_region_size (memory), - attr, - pci_simple_bar_mapfunc_region); pci_dev->io_regions[region_num].memory = memory; pci_dev->io_regions[region_num].address_space - = attr &PCI_BASE_ADDRESS_SPACE_IO + = type &PCI_BASE_ADDRESS_SPACE_IO ? pci_dev->bus->address_space_io : pci_dev->bus->address_space_mem; }
hw/pci.h +0 -3
@@ -201,9 +201,6 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name, PCIConfigReadFunc *config_read, PCIConfigWriteFunc *config_write); -void pci_register_bar (PCIDevice *pci_dev,int region_num, -pcibus_t size,uint8_t type, -PCIMapIORegionFunc *map_func);void pci_register_bar_region (PCIDevice *pci_dev,int region_num,uint8_t attr,MemoryRegion *memory);pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num);
Signature · 1 line
1.7.5.3
PATCH v4 37/39 pci: fold BAR mapping function into its caller
In reply to Avi KivityThere is only one function, so no need for a function pointer.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 25 +++++++++---------------- hw/pci.h | 1 - 2 files changed, 9 insertions(+), 17 deletions(-)
hw/pci.c +9 -16
@@ -881,18 +881,6 @@ static int pci_unregister_device(DeviceState *dev)return 0 ; } -static void pci_simple_bar_mapfunc_region (PCIDevice *pci_dev,int region_num, -pcibus_t addr,pcibus_t size, -int type) -{ -PCIIORegion *r = &pci_dev->io_regions[region_num]; - -memory_region_add_subregion_overlap (r->address_space, - addr, - r->memory, -1 ); -} -void pci_register_bar_region (PCIDevice *pci_dev,int region_num,uint8_t type,MemoryRegion *memory) {
@@ -914,7 +902,6 @@ void pci_register_bar_region(PCIDevice *pci_dev, int region_num, r->size = size; r->filtered_size = size; r->type = type; - r->map_func = pci_simple_bar_mapfunc_region; r->memory =NULL ; wmask = ~(size -1 );
@@ -1102,10 +1089,16 @@ static void pci_update_mappings(PCIDevice *d)* addr & (size - 1) != 0. */ if (r->type &PCI_BASE_ADDRESS_SPACE_IO ) { - r->map_func (d, i, r->addr, r->filtered_size, r->type); +memory_region_add_subregion_overlap (r->address_space, + r->addr, + r->memory, +1 ); }else { - r->map_func (d, i,pci_to_cpu_addr (d->bus, r->addr), - r->filtered_size, r->type); +memory_region_add_subregion_overlap (r->address_space, +pci_to_cpu_addr (d->bus, + r->addr), + r->memory, +1 ); } } }
hw/pci.h +0 -1
@@ -92,7 +92,6 @@ typedef struct PCIIORegion {pcibus_t size;pcibus_t filtered_size;uint8_t type; -PCIMapIORegionFunc *map_func;MemoryRegion *memory;MemoryRegion *address_space; } PCIIORegion;
Signature · 1 line
1.7.5.3
PATCH v4 38/39 pci: rename pci_register_bar_region() to pci_register_bar()
In reply to Avi KivityReviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/ac97.c | 5 ++--- hw/cirrus_vga.c | 5 ++--- hw/e1000.c | 5 ++--- hw/eepro100.c | 7 +++---- hw/es1370.c | 2 +- hw/ide/cmd646.c | 14 +++++--------- hw/ide/ich.c | 2 +- hw/ide/piix.c | 3 +-- hw/ide/via.c | 3 +-- hw/intel-hda.c | 2 +- hw/ivshmem.c | 15 +++++++-------- hw/lsi53c895a.c | 7 +++---- hw/macio.c | 3 +-- hw/ne2000.c | 2 +- hw/openpic.c | 4 ++-- hw/pci.c | 6 +++--- hw/pci.h | 4 ++-- hw/pcnet-pci.c | 4 ++-- hw/qxl.c | 16 ++++++++-------- hw/rtl8139.c | 6 ++---- hw/sun4u.c | 6 ++---- hw/usb-ehci.c | 2 +- hw/usb-ohci.c | 2 +- hw/usb-uhci.c | 3 +-- hw/vga-pci.c | 3 +-- hw/virtio-pci.c | 9 ++++----- hw/vmware_vga.c | 8 ++++---- hw/wdt_i6300esb.c | 2 +- hw/xen_platform.c | 7 +++---- 29 files changed, 68 insertions(+), 89 deletions(-)
hw/ac97.c +2 -3
@@ -1316,9 +1316,8 @@ static int ac97_initfn (PCIDevice *dev)memory_region_init_io (&s->io_nam, &ac97_io_nam_ops, s,"ac97-nam" ,1024 );memory_region_init_io (&s->io_nabm, &ac97_io_nabm_ops, s,"ac97-nabm" ,256 ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_nam); -pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , - &s->io_nabm); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_nam); +pci_register_bar (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_nabm);qemu_register_reset (ac97_on_reset, s);AUD_register_card ("ac97" , &s->card);ac97_on_reset (s);
hw/cirrus_vga.c +2 -3
@@ -2948,10 +2948,9 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev)/* memory #0 LFB */ /* memory #1 memory-mapped I/O */ /* XXX: s->vga.vram_size must be a power of two */ -pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , - &s->pci_bar); +pci_register_bar (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , &s->pci_bar);if (device_id ==CIRRUS_ID_CLGD5446 ) { -pci_register_bar_region (&d->dev,1 ,0 , &s->cirrus_mmio_io); +pci_register_bar (&d->dev,1 ,0 , &s->cirrus_mmio_io); }return 0 ; }
hw/e1000.c +2 -3
@@ -1158,10 +1158,9 @@ static int pci_e1000_init(PCIDevice *pci_dev)e1000_mmio_setup (d); -pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &d->mmio); +pci_register_bar (&d->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &d->mmio); -pci_register_bar_region (&d->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &d->io); +pci_register_bar (&d->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &d->io);memmove (d->eeprom_data, e1000_eeprom_template,sizeof e1000_eeprom_template);
hw/eepro100.c +3 -4
@@ -1879,15 +1879,14 @@ static int e100_nic_init(PCIDevice *pci_dev)/* Handler for memory-mapped I/O */ memory_region_init_io (&s->mmio_bar, &eepro100_ops, s,"eepro100-mmio" ,PCI_MEM_SIZE ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , - &s->mmio_bar); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , &s->mmio_bar);memory_region_init_io (&s->io_bar, &eepro100_ops, s,"eepro100-io" ,PCI_IO_SIZE ); -pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar); +pci_register_bar (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar);/* FIXME: flash aliases to mmio?! */ memory_region_init_io (&s->flash_bar, &eepro100_ops, s,"eepro100-flash" ,PCI_FLASH_SIZE ); -pci_register_bar_region (&s->dev,2 ,0 , &s->flash_bar); +pci_register_bar (&s->dev,2 ,0 , &s->flash_bar);qemu_macaddr_default_if_unset (&s->conf.macaddr);logout ("macaddr: %s\n" ,nic_dump (&s->conf.macaddr.a[0 ],6 ));
hw/es1370.c +1 -1
@@ -1009,7 +1009,7 @@ static int es1370_initfn (PCIDevice *dev) c[PCI_MAX_LAT ] =0x80 ;memory_region_init_io (&s->io, &es1370_io_ops, s,"es1370" ,256 ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io);qemu_register_reset (es1370_on_reset, s);AUD_register_card ("es1370" , &s->card);
hw/ide/cmd646.c +5 -9
@@ -270,16 +270,12 @@ static int pci_cmd646_ide_initfn(PCIDevice *dev)setup_cmd646_bar (d,0 );setup_cmd646_bar (d,1 ); -pci_register_bar_region (dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->cmd646_bar[0 ].data); -pci_register_bar_region (dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->cmd646_bar[0 ].cmd); -pci_register_bar_region (dev,2 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->cmd646_bar[1 ].data); -pci_register_bar_region (dev,3 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->cmd646_bar[1 ].cmd); +pci_register_bar (dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &d->cmd646_bar[0 ].data); +pci_register_bar (dev,1 ,PCI_BASE_ADDRESS_SPACE_IO , &d->cmd646_bar[0 ].cmd); +pci_register_bar (dev,2 ,PCI_BASE_ADDRESS_SPACE_IO , &d->cmd646_bar[1 ].data); +pci_register_bar (dev,3 ,PCI_BASE_ADDRESS_SPACE_IO , &d->cmd646_bar[1 ].cmd);bmdma_setup_bar (d); -pci_register_bar_region (dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bmdma_bar); +pci_register_bar (dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bmdma_bar);/* TODO: RST# value should be 0 */ pci_conf[PCI_INTERRUPT_PIN ] =0x01 ;// interrupt on pin 1
hw/ide/ich.c +1 -1
@@ -98,7 +98,7 @@ static int pci_ich9_ahci_init(PCIDevice *dev)msi_init (dev,0x50 ,1 , true, false); d->ahci.irq = d->card.irq[0 ]; -pci_register_bar_region (&d->card,5 ,0 , &d->ahci.mem); +pci_register_bar (&d->card,5 ,0 , &d->ahci.mem);return 0 ; }
hw/ide/piix.c +1 -2
@@ -155,8 +155,7 @@ static int pci_piix_ide_initfn(PCIDevice *dev)qemu_register_reset (piix3_reset, d);bmdma_setup_bar (d); -pci_register_bar_region (&d->dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->bmdma_bar); +pci_register_bar (&d->dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bmdma_bar);vmstate_register (&d->dev.qdev,0 , &vmstate_ide_pci, d);
hw/ide/via.c +1 -2
@@ -180,8 +180,7 @@ static int vt82c686b_ide_initfn(PCIDevice *dev)qemu_register_reset (via_reset, d);bmdma_setup_bar (d); -pci_register_bar_region (&d->dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , - &d->bmdma_bar); +pci_register_bar (&d->dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bmdma_bar);vmstate_register (&dev->qdev,0 , &vmstate_ide_pci, d);
hw/intel-hda.c +1 -1
@@ -1136,7 +1136,7 @@ static int intel_hda_init(PCIDevice *pci)memory_region_init_io (&d->mmio, &intel_hda_mmio_ops, d,"intel-hda" ,0x4000 ); -pci_register_bar_region (&d->pci,0 ,0 , &d->mmio); +pci_register_bar (&d->pci,0 ,0 , &d->mmio);if (d->msi) {msi_init (&d->pci,0x50 ,1 , true, false); }
hw/ivshmem.c +7 -8
@@ -336,7 +336,7 @@ static void create_shared_memory_BAR(IVShmemState *s, int fd) {memory_region_add_subregion (&s->bar,0 , &s->ivshmem);/* region for shared memory */ -pci_register_bar_region (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar); +pci_register_bar (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar); }static void close_guest_eventfds (IVShmemState *s,int posn)
@@ -543,9 +543,8 @@ static void ivshmem_setup_msi(IVShmemState * s) {memory_region_init (&s->msix_bar,"ivshmem-msix" ,4096 );if (!msix_init (&s->dev, s->vectors, &s->msix_bar,1 ,0 )) { -pci_register_bar_region (&s->dev,1 , -PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->msix_bar); +pci_register_bar (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->msix_bar);IVSHMEM_DPRINTF ("msix initialized (%d vectors)\n" , s->vectors); }else {IVSHMEM_DPRINTF ("msix initialization failed\n" );
@@ -665,8 +664,8 @@ static int pci_ivshmem_init(PCIDevice *dev) }/* region for registers*/ -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->ivshmem_mmio); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &s->ivshmem_mmio);memory_region_init (&s->bar,"ivshmem-bar2-container" , s->ivshmem_size);
@@ -694,8 +693,8 @@ static int pci_ivshmem_init(PCIDevice *dev)/* allocate/initialize space for interrupt handling */ s->peers =qemu_mallocz (s->nb_peers *sizeof (Peer)); -pci_register_bar_region (&s->dev,2 , -PCI_BASE_ADDRESS_SPACE_MEMORY , &s->ivshmem); +pci_register_bar (&s->dev,2 , +PCI_BASE_ADDRESS_SPACE_MEMORY , &s->ivshmem); s->eventfd_chr =qemu_mallocz (s->vectors *sizeof (CharDriverState *));
hw/lsi53c895a.c +3 -4
@@ -2118,10 +2118,9 @@ static int lsi_scsi_init(PCIDevice *dev)memory_region_init_io (&s->ram_io, &lsi_ram_ops, s,"lsi-ram" ,0x2000 );memory_region_init_io (&s->io_io, &lsi_io_ops, s,"lsi-io" ,256 ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_io); -pci_register_bar_region (&s->dev,1 ,0 , &s->mmio_io); -pci_register_bar_region (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->ram_io); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_io); +pci_register_bar (&s->dev,1 ,0 , &s->mmio_io); +pci_register_bar (&s->dev,2 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->ram_io);QTAILQ_INIT (&s->queue);scsi_bus_new (&s->bus, &dev->qdev,1 ,LSI_MAX_DEVS , &lsi_scsi_ops);
hw/macio.c +1 -2
@@ -111,6 +111,5 @@ void macio_init (PCIBus *bus, int device_id, int is_oldworld, d->config[0x3d ] =0x01 ;// interrupt on pin 1 macio_bar_setup (macio_state); -pci_register_bar_region (d,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &macio_state->bar); +pci_register_bar (d,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &macio_state->bar); }
hw/ne2000.c +1 -1
@@ -754,7 +754,7 @@ static int pci_ne2000_init(PCIDevice *pci_dev) s = &d->ne2000;ne2000_setup_io (s,0x100 ); -pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io); +pci_register_bar (&d->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io); s->irq = d->dev.irq[0 ];qemu_macaddr_default_if_unset (&s->c.macaddr);
hw/openpic.c +2 -2
@@ -1177,8 +1177,8 @@ qemu_irq *openpic_init (PCIBus *bus, MemoryRegion **pmem, int nb_cpus,#endif /* Register I/O spaces */ -pci_register_bar_region (&opp->pci_dev,0 , -PCI_BASE_ADDRESS_SPACE_MEMORY , &opp->mem); +pci_register_bar (&opp->pci_dev,0 , +PCI_BASE_ADDRESS_SPACE_MEMORY , &opp->mem); }else { opp =qemu_mallocz (sizeof (openpic_t));memory_region_init_io (&opp->mem, &openpic_ops, opp,"openpic" ,0x40000 );
hw/pci.c +3 -3
@@ -881,8 +881,8 @@ static int pci_unregister_device(DeviceState *dev)return 0 ; } -void pci_register_bar_region (PCIDevice *pci_dev,int region_num, -uint8_t type,MemoryRegion *memory) +void pci_register_bar (PCIDevice *pci_dev,int region_num, +uint8_t type,MemoryRegion *memory) {PCIIORegion *r;uint32_t addr;
@@ -1956,7 +1956,7 @@ static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)qemu_put_ram_ptr (ptr); -pci_register_bar_region (pdev,PCI_ROM_SLOT ,0 , &pdev->rom); +pci_register_bar (pdev,PCI_ROM_SLOT ,0 , &pdev->rom);return 0 ; }
hw/pci.h +2 -2
@@ -200,8 +200,8 @@ PCIDevice *pci_register_device(PCIBus *bus, const char *name, PCIConfigReadFunc *config_read, PCIConfigWriteFunc *config_write); -void pci_register_bar_region (PCIDevice *pci_dev,int region_num, -uint8_t attr,MemoryRegion *memory); +void pci_register_bar (PCIDevice *pci_dev,int region_num, +uint8_t attr,MemoryRegion *memory);pcibus_t pci_get_bar_addr (PCIDevice *pci_dev,int region_num); int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
hw/pcnet-pci.c +2 -2
@@ -295,9 +295,9 @@ static int pci_pcnet_init(PCIDevice *pci_dev)memory_region_init_io (&d->io_bar, &pcnet_io_ops, d,"pcnet-io" ,PCNET_IOPORT_SIZE ); -pci_register_bar_region (pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &d->io_bar); +pci_register_bar (pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &d->io_bar); -pci_register_bar_region (pci_dev,1 ,0 , &s->mmio); +pci_register_bar (pci_dev,1 ,0 , &s->mmio); s->irq = pci_dev->irq[0 ]; s->phys_mem_read = pci_physical_memory_read;
hw/qxl.c +8 -8
@@ -1564,17 +1564,17 @@ static int qxl_init_common(PCIQXLDevice *qxl) } -pci_register_bar_region (&qxl->pci,QXL_IO_RANGE_INDEX , -PCI_BASE_ADDRESS_SPACE_IO , &qxl->io_bar); +pci_register_bar (&qxl->pci,QXL_IO_RANGE_INDEX , +PCI_BASE_ADDRESS_SPACE_IO , &qxl->io_bar); -pci_register_bar_region (&qxl->pci,QXL_ROM_RANGE_INDEX , -PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->rom_bar); +pci_register_bar (&qxl->pci,QXL_ROM_RANGE_INDEX , +PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->rom_bar); -pci_register_bar_region (&qxl->pci,QXL_RAM_RANGE_INDEX , -PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->vga.vram); +pci_register_bar (&qxl->pci,QXL_RAM_RANGE_INDEX , +PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->vga.vram); -pci_register_bar_region (&qxl->pci,QXL_VRAM_RANGE_INDEX , -PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->vram_bar); +pci_register_bar (&qxl->pci,QXL_VRAM_RANGE_INDEX , +PCI_BASE_ADDRESS_SPACE_MEMORY , &qxl->vram_bar); qxl->ssd.qxl.base.sif = &qxl_interface.base; qxl->ssd.qxl.id = qxl->id;
hw/rtl8139.c +2 -4
@@ -3471,10 +3471,8 @@ static int pci_rtl8139_init(PCIDevice *dev)memory_region_init_io (&s->bar_io, &rtl8139_io_ops, s,"rtl8139" ,0x100 );memory_region_init_io (&s->bar_mem, &rtl8139_mmio_ops, s,"rtl8139" ,0x100 ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , - &s->bar_io); -pci_register_bar_region (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->bar_mem); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->bar_io); +pci_register_bar (&s->dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar_mem);qemu_macaddr_default_if_unset (&s->conf.macaddr);
hw/sun4u.c +2 -4
@@ -554,11 +554,9 @@ pci_ebus_init1(PCIDevice *pci_dev) pci_dev->config[0x0D ] =0x0a ;// latency_timer isa_mmio_setup (&s->bar0,0x1000000 ); -pci_register_bar_region (pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->bar0); +pci_register_bar (pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar0);isa_mmio_setup (&s->bar1,0x800000 ); -pci_register_bar_region (pci_dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , - &s->bar1); +pci_register_bar (pci_dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->bar1);return 0 ; }
hw/usb-ehci.c +1 -1
@@ -2302,7 +2302,7 @@ static int usb_ehci_initfn(PCIDevice *dev)qemu_register_reset (ehci_reset, s);memory_region_init_io (&s->mem, &ehci_mem_ops, s,"ehci" ,MMIO_SIZE ); -pci_register_bar_region (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->mem); +pci_register_bar (&s->dev,0 ,PCI_BASE_ADDRESS_SPACE_MEMORY , &s->mem);fprintf (stderr,"*** EHCI support is under development ***\n" );
hw/usb-ohci.c +1 -1
@@ -1790,7 +1790,7 @@ static int usb_ohci_initfn_pci(struct PCIDevice *dev) ohci->state.irq = ohci->pci_dev.irq[0 ];/* TODO: avoid cast below by using dev */ -pci_register_bar_region (&ohci->pci_dev,0 ,0 , &ohci->state.mem); +pci_register_bar (&ohci->pci_dev,0 ,0 , &ohci->state.mem);return 0 ; }
hw/usb-uhci.c +1 -2
@@ -1159,8 +1159,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev)memory_region_init_io (&s->io_bar, &uhci_ioport_ops, s,"uhci" ,0x20 );/* Use region 4 for consistency with real hardware. BSD guests seem to rely on this. */ -pci_register_bar_region (&s->dev,4 , -PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar); +pci_register_bar (&s->dev,4 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar);return 0 ; }
hw/vga-pci.c +1 -2
@@ -60,8 +60,7 @@ static int pci_vga_initfn(PCIDevice *dev) s->screen_dump, s->text_update, s);/* XXX: VGA_RAM_SIZE must be a power of two */ -pci_register_bar_region (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , - &s->vram); +pci_register_bar (&d->dev,0 ,PCI_BASE_ADDRESS_MEM_PREFETCH , &s->vram);if (!dev->rom_bar) {/* compatibility with pc-0.13 and older */
hw/virtio-pci.c +4 -5
@@ -645,9 +645,8 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)memory_region_init (&proxy->msix_bar,"virtio-msix" ,4096 );if (vdev->nvectors && !msix_init (&proxy->pci_dev, vdev->nvectors, &proxy->msix_bar,1 ,0 )) { -pci_register_bar_region (&proxy->pci_dev,1 , -PCI_BASE_ADDRESS_SPACE_MEMORY , - &proxy->msix_bar); +pci_register_bar (&proxy->pci_dev,1 ,PCI_BASE_ADDRESS_SPACE_MEMORY , + &proxy->msix_bar); }else vdev->nvectors =0 ;
@@ -659,8 +658,8 @@ void virtio_init_pci(VirtIOPCIProxy *proxy, VirtIODevice *vdev)memory_region_init_io (&proxy->bar, &virtio_pci_config_ops, proxy,"virtio-pci" , size); -pci_register_bar_region (&proxy->pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , - &proxy->bar); +pci_register_bar (&proxy->pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , + &proxy->bar);if (!kvm_has_many_ioeventfds ()) { proxy->flags &= ~VIRTIO_PCI_FLAG_USE_IOEVENTFD ;
hw/vmware_vga.c +4 -4
@@ -1291,13 +1291,13 @@ static int pci_vmsvga_initfn(PCIDevice *dev)memory_region_init_io (&s->io_bar, &vmsvga_io_ops, &s->chip,"vmsvga-io" ,0x10 ); -pci_register_bar_region (&s->card,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar); +pci_register_bar (&s->card,0 ,PCI_BASE_ADDRESS_SPACE_IO , &s->io_bar);vmsvga_init (&s->chip,VGA_RAM_SIZE ); -pci_register_bar_region (&s->card,1 ,PCI_BASE_ADDRESS_MEM_PREFETCH , iomem); -pci_register_bar_region (&s->card,2 ,PCI_BASE_ADDRESS_MEM_PREFETCH , - &s->chip.fifo_ram); +pci_register_bar (&s->card,1 ,PCI_BASE_ADDRESS_MEM_PREFETCH , iomem); +pci_register_bar (&s->card,2 ,PCI_BASE_ADDRESS_MEM_PREFETCH , + &s->chip.fifo_ram);if (!dev->rom_bar) {/* compatibility with pc-0.13 and older */
hw/wdt_i6300esb.c +1 -1
@@ -405,7 +405,7 @@ static int i6300esb_init(PCIDevice *dev) d->previous_reboot_flag =0 ;memory_region_init_io (&d->io_mem, &i6300esb_ops, d,"i6300esb" ,0x10 ); -pci_register_bar_region (&d->dev,0 ,0 , &d->io_mem); +pci_register_bar (&d->dev,0 ,0 , &d->io_mem);/* qemu_register_coalesced_mmio (addr, 0x10); ? */ return 0 ;
hw/xen_platform.c +3 -4
@@ -353,13 +353,12 @@ static int xen_platform_initfn(PCIDevice *dev) pci_conf[PCI_INTERRUPT_PIN ] =1 ;platform_ioport_bar_setup (d); -pci_register_bar_region (&d->pci_dev,0 , -PCI_BASE_ADDRESS_SPACE_IO , &d->bar); +pci_register_bar (&d->pci_dev,0 ,PCI_BASE_ADDRESS_SPACE_IO , &d->bar);/* reserve 16MB mmio address for share memory*/ platform_mmio_setup (d); -pci_register_bar_region (&d->pci_dev,1 , -PCI_BASE_ADDRESS_MEM_PREFETCH , &d->mmio_bar); +pci_register_bar (&d->pci_dev,1 ,PCI_BASE_ADDRESS_MEM_PREFETCH , + &d->mmio_bar);platform_fixed_ioport_init (d);
Signature · 1 line
1.7.5.3
PATCH v4 39/39 pci: remove support for pre memory API BARs
In reply to Avi KivityNot used anymore.
Reviewed-by Richard Henderson <[email protected]>
Reviewed-by Anthony Liguori <[email protected]>
Signed-off-by Avi Kivity <[email protected]>
--- hw/pci.c | 33 ++------------------------------- 1 files changed, 2 insertions(+), 31 deletions(-)
hw/pci.c +2 -31
@@ -848,18 +848,7 @@ static void pci_unregister_io_regions(PCIDevice *pci_dev) r = &pci_dev->io_regions[i];if (!r->size || r->addr ==PCI_BAR_UNMAPPED )continue ; -if (r->memory) { -memory_region_del_subregion (r->address_space, r->memory); - }else { -if (r->type ==PCI_BASE_ADDRESS_SPACE_IO ) { -isa_unassign_ioport (r->addr, r->filtered_size); - }else { -cpu_register_physical_memory (pci_to_cpu_addr (pci_dev->bus, - r->addr), - r->filtered_size, -IO_MEM_UNASSIGNED ); - } - } +memory_region_del_subregion (r->address_space, r->memory); } }
@@ -1058,25 +1047,7 @@ static void pci_update_mappings(PCIDevice *d)/* now do the real mapping */ if (r->addr !=PCI_BAR_UNMAPPED ) { -if (r->memory) { -memory_region_del_subregion (r->address_space, r->memory); - }else if (r->type &PCI_BASE_ADDRESS_SPACE_IO ) { -int class; -/* NOTE: specific hack for IDE in PC case: -only one byte must be mapped. */ - class =pci_get_word (d->config +PCI_CLASS_DEVICE ); -if (class ==0x0101 && r->size ==4 ) { -isa_unassign_ioport (r->addr +2 ,1 ); - }else { -isa_unassign_ioport (r->addr, r->filtered_size); - } - }else { -cpu_register_physical_memory (pci_to_cpu_addr (d->bus, - r->addr), - r->filtered_size, -IO_MEM_UNASSIGNED ); -qemu_unregister_coalesced_mmio (r->addr, r->filtered_size); - } +memory_region_del_subregion (r->address_space, r->memory); } r->addr = new_addr; r->filtered_size = filtered_size;
Signature · 1 line
1.7.5.3
Quoted 24 lines · Avi Kivity
This is a mostly mindless conversion of all QEMU PCI devices to the memory API. After this patchset is applied, it is no longer possible to create a PCI device using the old API.
An immediate benefit is that PCI BARs that overlap each other are now handled
correctly: currently, the sequencemap BAR 0
map BAR 1 at an overlapping address
unmap either BAR 0 or BAR 1will leave a hole where the overlap exists. With the patchset, the memory map is restored correctly.
Note that overlaps of PCI BARs with memory or non-PCI resources are still not resolved correctly; this will be fixed later on.
The vga patches have ugly intermediate states; however the result is fairly clean.
Changes from v3:
- dropped virtio-pci config patch; will be fixed outside this patchset if necessary
- minor style fixes
Quoted 6 lines
Changes from v2:
- added patch from Michael simplifying virtio-pci config setupChanges from v1:
- cmd646 type fix
- folded a fixlet into its parent
For the series:
Quoted 125 lines
Avi Kivity (39):
memory: renamePORTIO_ENDtoPORTIO_END_OF_LIST
pci: add API to get a BAR's mapped address
vmsvga: don't remember pci BAR address in callback any more
vga: convert vga and its derivatives to the memory API
cirrus: simplify mmio BAR access functions
cirrus: simplify bitblt BAR access functions
cirrus: simplify vga window mmio access functions
vga: simplify vga window mmio access functions
cirrus: simplify linear framebuffer access functions Integrate I/O memory regions into qemu
pci: pass I/O address space to new PCI bus
pci: allow I/O BARs to be registered withpci_register_bar_region()
rtl8139: convert to memory API
ac97: convert to memory API
e1000: convert to memory API
eepro100: convert to memory API
es1370: convert to memory API
ide: convert to memory API
ivshmem: convert to memory API
virtio-pci: convert to memory API
ahci: convert to memory API
intel-hda: convert to memory API
lsi53c895a: convert to memory API
ppc: convert to memory API
ne2000: convert to memory API
pcnet: convert to memory API
i6300esb: convert to memory API
isa-mmio: convert to memory API
sun4u: convert to memory API
ehci: convert to memory API
uhci: convert to memory API
xen-platform: convert to memory API
msix: convert to memory API
pci: removepci_register_bar_simple()
pci: convert pci rom to memory API
pci: removepci_register_bar()
pci: fold BAR mapping function into its caller
pci: renamepci_register_bar_region()topci_register_bar()
pci: remove support for pre memory API BARsexec-memory.h | 5 + exec.c | 10 ++ hw/ac97.c | 88 ++++++----- hw/apb_pci.c | 1 + hw/bonito.c | 1 + hw/cirrus_vga.c | 459 ++++++++++++++++----------------------------------- hw/cuda.c | 6 +- hw/e1000.c | 113 ++++++-------- hw/eepro100.c | 181 ++++----------------- hw/es1370.c | 43 +++-- hw/escc.c | 42 +++--- hw/escc.h | 2 +- hw/grackle_pci.c | 8 +- hw/gt64xxx.c | 4 +- hw/heathrow_pic.c | 29 ++-- hw/ide.h | 2 +- hw/ide/ahci.c | 31 ++-- hw/ide/ahci.h | 2 +- hw/ide/cmd646.c | 204 +++++++++++++++--------- hw/ide/ich.c | 3 +- hw/ide/macio.c | 36 +++-- hw/ide/pci.c | 25 ++-- hw/ide/pci.h | 19 ++- hw/ide/piix.c | 63 ++++++-- hw/ide/via.c | 64 ++++++-- hw/intel-hda.c | 35 +++-- hw/isa.h | 2 + hw/isa_mmio.c | 29 ++-- hw/ivshmem.c | 158 +++++++------------ hw/lance.c | 31 ++-- hw/lsi53c895a.c | 257 +++++++----------------------- hw/mac_dbdma.c | 32 ++-- hw/mac_dbdma.h | 4 +- hw/mac_nvram.c | 39 ++--- hw/macio.c | 73 ++++----- hw/msix.c | 64 +++----- hw/msix.h | 6 +- hw/ne2000-isa.c | 13 +-- hw/ne2000.c | 77 ++++++--- hw/ne2000.h | 8 +- hw/openpic.c | 81 +++++----- hw/openpic.h | 2 +- hw/pc.h | 4 +- hw/pc_piix.c | 6 +- hw/pci.c | 133 +++++----------- hw/pci.h | 26 ++-- hw/pci_internals.h | 3 +- hw/pcnet-pci.c | 74 +++++---- hw/pcnet.h | 4 +- hw/piix_pci.c | 14 +- hw/ppc4xx_pci.c | 1 + hw/ppc_mac.h | 27 ++-- hw/ppc_newworld.c | 34 ++-- hw/ppc_oldworld.c | 27 ++-- hw/ppc_prep.c | 2 +- hw/ppce500_pci.c | 7 +- hw/prep_pci.c | 8 +- hw/prep_pci.h | 4 +- hw/qxl-render.c | 2 +- hw/qxl.c | 129 ++++++---------- hw/qxl.h | 6 +- hw/rtl8139.c | 70 ++++---- hw/sh_pci.c | 4 +- hw/sun4u.c | 53 +++---- hw/unin_pci.c | 16 ++- hw/usb-ehci.c | 36 +--- hw/usb-ohci.c | 2 +- hw/usb-uhci.c | 41 +++-- hw/versatile_pci.c | 2 +- hw/vga-isa-mm.c | 46 ++++-- hw/vga-isa.c | 10 +- hw/vga-pci.c | 27 +--- hw/vga.c | 178 +++++++------------- hw/vga_int.h | 18 +-- hw/virtio-pci.c | 86 ++++------ hw/virtio-pci.h | 3 +- hw/vmware_vga.c | 153 +++++++++--------- hw/wdt_i6300esb.c | 43 ++++-- hw/xen_platform.c | 82 ++++++---- memory.h | 2 +- 80 files changed, 1650 insertions(+), 2085 deletions(-)Signature · 1 line
1.7.5.3
Anthony Liguori
AppliedQuoted 11 lines · Avi Kivity
This is a mostly mindless conversion of all QEMU PCI devices to the memory API. After this patchset is applied, it is no longer possible to create a PCI device using the old API.
An immediate benefit is that PCI BARs that overlap each other are now handled
correctly: currently, the sequencemap BAR 0
map BAR 1 at an overlapping address
unmap either BAR 0 or BAR 1
Quoted 7 lines
will leave a hole where the overlap exists. With the patchset, the memory map is restored correctly.
Note that overlaps of PCI BARs with memory or non-PCI resources are still not resolved correctly; this will be fixed later on.
The vga patches have ugly intermediate states; however the result is fairly clean.
Applied all. Thanks for taking this on, the results are very nice!
Regards,
Anthony Liguori
Quoted 136 lines
Changes from v3:
- dropped virtio-pci config patch; will be fixed outside this patchset if necessary
- minor style fixesChanges from v2:
- added patch from Michael simplifying virtio-pci config setupChanges from v1:
- cmd646 type fix
- folded a fixlet into its parentAvi Kivity (39):
memory: renamePORTIO_ENDtoPORTIO_END_OF_LIST
pci: add API to get a BAR's mapped address
vmsvga: don't remember pci BAR address in callback any more
vga: convert vga and its derivatives to the memory API
cirrus: simplify mmio BAR access functions
cirrus: simplify bitblt BAR access functions
cirrus: simplify vga window mmio access functions
vga: simplify vga window mmio access functions
cirrus: simplify linear framebuffer access functions Integrate I/O memory regions into qemu
pci: pass I/O address space to new PCI bus
pci: allow I/O BARs to be registered withpci_register_bar_region()
rtl8139: convert to memory API
ac97: convert to memory API
e1000: convert to memory API
eepro100: convert to memory API
es1370: convert to memory API
ide: convert to memory API
ivshmem: convert to memory API
virtio-pci: convert to memory API
ahci: convert to memory API
intel-hda: convert to memory API
lsi53c895a: convert to memory API
ppc: convert to memory API
ne2000: convert to memory API
pcnet: convert to memory API
i6300esb: convert to memory API
isa-mmio: convert to memory API
sun4u: convert to memory API
ehci: convert to memory API
uhci: convert to memory API
xen-platform: convert to memory API
msix: convert to memory API
pci: removepci_register_bar_simple()
pci: convert pci rom to memory API
pci: removepci_register_bar()
pci: fold BAR mapping function into its caller
pci: renamepci_register_bar_region()topci_register_bar()
pci: remove support for pre memory API BARsexec-memory.h | 5 + exec.c | 10 ++ hw/ac97.c | 88 ++++++----- hw/apb_pci.c | 1 + hw/bonito.c | 1 + hw/cirrus_vga.c | 459 ++++++++++++++++----------------------------------- hw/cuda.c | 6 +- hw/e1000.c | 113 ++++++-------- hw/eepro100.c | 181 ++++----------------- hw/es1370.c | 43 +++-- hw/escc.c | 42 +++--- hw/escc.h | 2 +- hw/grackle_pci.c | 8 +- hw/gt64xxx.c | 4 +- hw/heathrow_pic.c | 29 ++-- hw/ide.h | 2 +- hw/ide/ahci.c | 31 ++-- hw/ide/ahci.h | 2 +- hw/ide/cmd646.c | 204 +++++++++++++++--------- hw/ide/ich.c | 3 +- hw/ide/macio.c | 36 +++-- hw/ide/pci.c | 25 ++-- hw/ide/pci.h | 19 ++- hw/ide/piix.c | 63 ++++++-- hw/ide/via.c | 64 ++++++-- hw/intel-hda.c | 35 +++-- hw/isa.h | 2 + hw/isa_mmio.c | 29 ++-- hw/ivshmem.c | 158 +++++++------------ hw/lance.c | 31 ++-- hw/lsi53c895a.c | 257 +++++++----------------------- hw/mac_dbdma.c | 32 ++-- hw/mac_dbdma.h | 4 +- hw/mac_nvram.c | 39 ++--- hw/macio.c | 73 ++++----- hw/msix.c | 64 +++----- hw/msix.h | 6 +- hw/ne2000-isa.c | 13 +-- hw/ne2000.c | 77 ++++++--- hw/ne2000.h | 8 +- hw/openpic.c | 81 +++++----- hw/openpic.h | 2 +- hw/pc.h | 4 +- hw/pc_piix.c | 6 +- hw/pci.c | 133 +++++----------- hw/pci.h | 26 ++-- hw/pci_internals.h | 3 +- hw/pcnet-pci.c | 74 +++++---- hw/pcnet.h | 4 +- hw/piix_pci.c | 14 +- hw/ppc4xx_pci.c | 1 + hw/ppc_mac.h | 27 ++-- hw/ppc_newworld.c | 34 ++-- hw/ppc_oldworld.c | 27 ++-- hw/ppc_prep.c | 2 +- hw/ppce500_pci.c | 7 +- hw/prep_pci.c | 8 +- hw/prep_pci.h | 4 +- hw/qxl-render.c | 2 +- hw/qxl.c | 129 ++++++---------- hw/qxl.h | 6 +- hw/rtl8139.c | 70 ++++---- hw/sh_pci.c | 4 +- hw/sun4u.c | 53 +++---- hw/unin_pci.c | 16 ++- hw/usb-ehci.c | 36 +--- hw/usb-ohci.c | 2 +- hw/usb-uhci.c | 41 +++-- hw/versatile_pci.c | 2 +- hw/vga-isa-mm.c | 46 ++++-- hw/vga-isa.c | 10 +- hw/vga-pci.c | 27 +--- hw/vga.c | 178 +++++++------------- hw/vga_int.h | 18 +-- hw/virtio-pci.c | 86 ++++------ hw/virtio-pci.h | 3 +- hw/vmware_vga.c | 153 +++++++++--------- hw/wdt_i6300esb.c | 43 ++++-- hw/xen_platform.c | 82 ++++++---- memory.h | 2 +- 80 files changed, 1650 insertions(+), 2085 deletions(-)