Yet another GIC OF binding series

From: Rob Herring <[email protected]>

In preparation to scan and initialize interrupt controllers from a device-tree, create struct to pass to interrupt controller initialization functions.

irq_base should go away with dynamic linux irq assignment.

Signed-off-by Rob Herring <[email protected]>

---
 include/linux/of_irq.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

include/linux/of_irq.h +0 -0

index cd2e61c..de91ff9 100644

Quoted 21 lines · Rob Herring

From: Rob Herring <[email protected]>

In preparation to scan and initialize interrupt controllers from a device-tree, create struct to pass to interrupt controller initialization functions.

irq_base should go away with dynamic linux irq assignment.

Signed-off-by Rob Herring <[email protected]>

---
 include/linux/of_irq.h |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

include/linux/of_irq.h +0 -0

index cd2e61c..de91ff9 100644
@@ -33,6 +33,12 @@ struct of_irq {
 	u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
 };
 

include/linux/of_irq.h struct of_irq { · line 38

Quoted 3 lines

include/linux/of_irq.h +3 -0

+struct of_intc_desc {
+	struct device_node *controller;
+	struct device_node *parent;

Do we need parent here? I think that of_irq_find_parent() will do the job.

Other than that nit the series looks nice to me.

Jamie

From: Rob Herring <[email protected]>

This adds gic initialization using device tree data. An example device tree binding looks like this:

intc: interrupt-controller at fff11000 {
        compatible = "arm,cortex-a9-gic";
        #interrupt-cells = <1>;
        interrupt-controller;
        reg = <0xfff11000 0x1000>,
              <0xfff10100 0x100>;
};

Quoted 5 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds gic initialization using device tree data. An example device tree binding looks like this:

Quoted 7 lines

intc: interrupt-controller at fff11000 {
        compatible = "arm,cortex-a9-gic";
        #interrupt-cells = <1>;
        interrupt-controller;
        reg = <0xfff11000 0x1000>,
              <0xfff10100 0x100>;
};

I'm afraid I still object to this. PPIs are an important part of the GIC, and this binding totally ignores the per-cpu aspect.

How do you represent the connection between a CPU local timer and the GIC? Even worse, how to represent a device connected to only *one* of the CPUs? PPIs are difficult to represent on the Linux side. But we shouldn't ignore them in the DT binding.

From: Rob Herring <[email protected]>

This adds gic initialization using device tree data. The initialization functions are intended to be called by a generic OF interrupt controller parsing function once the right pieces are in place.

PPI binding support based on work by Marc Zyngier.

Signed-off-by Rob Herring <[email protected]>

---
Changes in v2:
- Add bindings and documentation for PPI
- change interrupt-cells to 2
- Move init of np pointer to after intc_desc ptr NULL check

 Documentation/devicetree/bindings/arm/gic.txt |   62 +++++++++++++++++++++++++
 arch/arm/common/gic.c                         |   41 ++++++++++++++++
 arch/arm/include/asm/hardware/gic.h           |    3 +
 3 files changed, 106 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/gic.txt

Documentation/devicetree/bindings/arm/gic.txt new file +7 -0

new file mode 100644
index 0000000..85be7c9
@@ -0,0 +1,62 @@
+* ARM Generic Interrupt Controller
+
+ARM SMP cores are often associated with a GIC, providing per processor
+interrupts (PPI), shared processor interrupts (SPI) and software
+generated interrupts (SGI).
+
+Primary GIC is attached directly to the CPU and typically has PPIs. Secondary GICs are

Documentation/devicetree/bindings/arm/gic.txt new file +45 -0

+- reg : Specifies base physical address(s) and size of the GIC registers. The
+  first 2 values are the GIC distributor register base and size. The 2nd 2
+  values are the GIC cpu interface register base and size.
+- #size-cells : Shall be <0> as PPIs don't have size for reg property. Optional
+  for secondary GICs.
+
+Optional
+- interrupts	: optional, used on secondary GICs only
+
+PPI sub-nodes required properties:
+
+- compatible : should match the main node with "-ppi" appended. one of:
+	"arm,cortex-a9-gic-ppi"
+	"arm,arm11mp-gic-ppi"
+- interrupt-controller : Identifies the node as an interrupt controller
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source.  The type shall be a <u32> and the value shall be 1 as PPIs
+  don't have edge/level settings.
+- reg : Specifies cpu number the PPIs are attached to.
+
+Example:
+
+	intc: interrupt-controller at fff11000 {
+		compatible = "arm,cortex-a9-gic";
+		#interrupt-cells = <2>;
+		#size-cells = <0>;
+		#address-cells = <1>;
+		interrupt-controller;
+		reg = <0xfff11000 0x1000>,
+		      <0xfff10100 0x100>;
+		      
+		gicppi0: gic-ppi at 0 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0>;
+		};
+		gicppi1: gic-ppi at 1 {
+			compatible = "arm,cortex-a9-gic-ppi";
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <1>;
+		};
+	};
+

arch/arm/common/gic.c +41 -0

index f13298e..a796299 100644
@@ -28,6 +28,10 @@
 #include <linux/smp.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
 
 #include <asm/irq.h>
 #include <asm/mach/irq.h>

@@ -394,3 +398,40 @@ void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 	writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 }
 #endif
+
+#ifdef CONFIG_OF
+static int gic_cnt __initdata = 0;
+
+void __init gic_of_init(struct of_intc_desc *d)
+{
+	struct device_node *np;
+	void __iomem *cpu_base;
+	void __iomem *dist_base;
+	int irq;
+
+	if (WARN_ON(!d || !d->controller))
+		return;
+
+	np = d->controller;
+	dist_base = of_iomap(np, 0);
+	WARN(!dist_base, "unable to map gic dist registers\n");
+
+	cpu_base = of_iomap(np, 1);
+	WARN(!cpu_base, "unable to map gic cpu registers\n");
+
+	gic_init(gic_cnt, d->irq_base, dist_base, cpu_base);
+	irq_domain_add_simple(d->controller, d->irq_base);
+
+	if (d->parent) {
+		irq = irq_of_parse_and_map(np, 0);
+		gic_cascade_irq(gic_cnt, irq);
+	}
+	gic_cnt++;
+}
+
+void __init gic_of_ppi_init(struct of_intc_desc *d)
+{
+	irq_domain_add_simple(d->controller, d->irq_base);
+}
+
+#endif

arch/arm/include/asm/hardware/gic.h +3 -0

index 435d3f8..a6594d4 100644
@@ -37,6 +37,9 @@ extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
+struct of_intc_desc;
+void gic_of_init(struct of_intc_desc *d);
+void gic_of_ppi_init(struct of_intc_desc *d);
 void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);

From: Rob Herring <[email protected]>

Grant,

Here's yet another patch series for GIC binding and init.

You keep saying we should have a common DT function scanning for interrupt controller nodes and calling their initialization functions. But that will not work until we have dynamic assignment of linux irq numbers. So either everyone should just stop trying to do DT bindings for GIC/VIC until that is in place, or we need an interim solution.

This is another attempt at
the latter. I reworked gic_of_init intending for it to be the interrupt controller specific initialization function that DT interrupt controller scanning code would call. For now, it is just called by the platform code. The platform initialization looks something like this:

struct of_intc_desc desc;
memset(&desc, 0, sizeof(desc));
desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); gic_of_init(&desc);

I've addressed your previous comments and in particular initializing more than 1 GIC is supported now.

Rob

Rob Herring (3):
dt: irq: add interrupt controller descriptor struct
ARM: gic: allow irq_start to be 0
ARM: gic: add OF based initialization

 Documentation/devicetree/bindings/arm/gic.txt |   28 +++++++++++++++++++
 arch/arm/common/gic.c                         |   36 ++++++++++++++++++++++++-
 arch/arm/include/asm/hardware/gic.h           |    2 +
 include/linux/of_irq.h                        |    6 ++++
 4 files changed, 71 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/gic.txt

Signature · 7 lines

1.7.4.1


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From: Rob Herring <[email protected]>

Grant,

Here's yet another patch series for GIC binding and init.

You keep saying we should have a common DT function scanning for interrupt controller nodes and calling their initialization functions. But that will not work until we have dynamic assignment of linux irq numbers. So either everyone should just stop trying to do DT bindings for GIC/VIC until that is in place, or we need an interim solution. This is another attempt at the latter. I reworked gic_of_init intending for it to be the interrupt controller specific initialization function that DT interrupt controller scanning code would call. For now, it is just called by the platform code. The platform initialization looks something like this:

struct of_intc_desc desc;
memset(&desc, 0, sizeof(desc));
desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic"); gic_of_init(&desc);

I've addressed your previous comments and in particular initializing more than 1 GIC is supported now.

Rob

Rob Herring (3):
?dt: irq: add interrupt controller descriptor struct ?ARM: gic: allow irq_start to be 0
?ARM: gic: add OF based initialization

?Documentation/devicetree/bindings/arm/gic.txt | ? 28 +++++++++++++++++++
?arch/arm/common/gic.c ? ? ? ? ? ? ? ? ? ? ? ? | ? 36 ++++++++++++++++++++++++-
?arch/arm/include/asm/hardware/gic.h ? ? ? ? ? | ? ?2 +
?include/linux/of_irq.h ? ? ? ? ? ? ? ? ? ? ? ?| ? ?6 ++++

?4 files changed, 71 insertions(+), 1 deletions(-) ?create mode 100644 Documentation/devicetree/bindings/arm/gic.txt

--
1.7.4.1