powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en

PATCH Superseded York Sun 3 participants 20 messages Aug 9, 2011 – Aug 26, 2011

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York Sun

author

2011-08-09 20:50 UTC #0 lore raw

PATCH 1/7 powerpc/mpc8xxx: Fix DDR code for empty first DIMM slot and enable DQS_en

Check second DIMM slot in case the first one is empty. Honor DQS enable option for SDRAM mode register.

Signed-off-by York Sun <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |   19 ++++++++++---------
 arch/powerpc/include/asm/fsl_ddr_sdram.h |    4 ++++
 2 files changed, 14 insertions(+), 9 deletions(-)

arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +10 -9

index 3824aad..eb8d8e3 100644
@@ -146,7 +146,7 @@ static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 		break;
 	case 2:
 		if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
-		   (dimm_number > 1 && dimm_params[dimm_number].n_ranks > 0))
+		   (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 			go_config = 1;
 		break;
 	case 3:

@@ -617,7 +617,7 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int sr_ie = 0;		/* Self-refresh interrupt enable */
 	unsigned int dll_rst_dis;	/* DLL reset disable */
 	unsigned int dqs_cfg;		/* DQS configuration */
-	unsigned int odt_cfg;		/* ODT configuration */
+	unsigned int odt_cfg = 0;	/* ODT configuration */
 	unsigned int num_pr;		/* Number of posted refreshes */
 	unsigned int obc_cfg;		/* On-The-Fly Burst Chop Cfg */
 	unsigned int ap_en;		/* Address Parity Enable */

@@ -625,15 +625,16 @@ static void set_ddr_sdram_cfg_2(fsl_ddr_cfg_regs_t *ddr,
 	unsigned int rcw_en = 0;	/* Register Control Word Enable */
 	unsigned int md_en = 0;		/* Mirrored DIMM Enable */
 	unsigned int qd_en = 0;		/* quad-rank DIMM Enable */
+	int i;
 
 	dll_rst_dis = 1;	/* Make this configurable */
 	dqs_cfg = popts->DQS_config;
-	if (popts->cs_local_opts[0].odt_rd_cfg
-	    || popts->cs_local_opts[0].odt_wr_cfg) {
-		/* FIXME */
-		odt_cfg = 2;
-	} else {
-		odt_cfg = 0;
+	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
+		if (popts->cs_local_opts[i].odt_rd_cfg
+			|| popts->cs_local_opts[i].odt_wr_cfg) {
+			odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
+			break;
+		}
 	}
 
 	num_pr = 1;	/* Make this configurable */

@@ -1018,7 +1019,7 @@ static void set_ddr_sdram_mode(fsl_ddr_cfg_regs_t *ddr,
 #if defined(CONFIG_FSL_DDR2)
 	const unsigned int mclk_ps = get_memory_clk_period_ps();
 #endif
-
+	dqs_en = !popts->DQS_config;
 	rtt = fsl_ddr_get_rtt();
 
 	al = additive_latency;

arch/powerpc/include/asm/fsl_ddr_sdram.h +4 -0

index bc063ea..5b6e8d9 100644
@@ -92,6 +92,10 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 
 #define SDRAM_CFG2_D_INIT		0x00000010
 #define SDRAM_CFG2_ODT_CFG_MASK		0x00600000
+#define SDRAM_CFG2_ODT_NEVER		0
+#define SDRAM_CFG2_ODT_ONLY_WRITE	1
+#define SDRAM_CFG2_ODT_ONLY_READ	2
+#define SDRAM_CFG2_ODT_ALWAYS		3
 
 #define TIMING_CFG_2_CPO_MASK	0x0F800000

Signature · 1 line

1.7.0.4

York Sun

author

2011-08-09 20:50 UTC #1 lore raw

PATCH 2/7 powerpc/mpc8xxx: Add SPD EEPROM address for single controller 2 slots

The two slots on the same controller have different addresses.

Signed-off-by York Sun <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/ddr/main.c |   11 +++++++----
 1 files changed, 7 insertions(+), 4 deletions(-)

arch/powerpc/cpu/mpc8xxx/ddr/main.c +7 -4

index 249fd7d..5699b0c 100644
@@ -34,14 +34,17 @@ extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS,
 };
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
+	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
+	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */
+};
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
 	[1][0] = SPD_EEPROM_ADDRESS2,	/* controller 2 */
 };
-#endif
-#if (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
+#elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
 	[0][0] = SPD_EEPROM_ADDRESS1,	/* controller 1 */
 	[0][1] = SPD_EEPROM_ADDRESS2,	/* controller 1 */

Signature · 1 line

1.7.0.4

York Sun

author

2011-08-09 20:50 UTC #2 lore raw

PATCH 3/7 powerpc/mpc8xxx: Fix picos_to_mclk() and get_memory_clk_period_ps()

In reply to York Sun

Reduce the calculation error to 1ps.

Signed-off-by York Sun <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/ddr/util.c |   26 +++++++++++---------------
 1 files changed, 11 insertions(+), 15 deletions(-)

arch/powerpc/cpu/mpc8xxx/ddr/util.c +11 ~~-15~~

index 104d360..c644131 100644
@@ -20,7 +20,8 @@
 #define ULL_8FS 0xFFFFFFFFULL
 
 /*
- * Round mclk_ps to nearest 10 ps in memory controller code.
+ * Round up mclk_ps to nearest 1 ps in memory controller code
+ * if the error is 0.5ps or more.
  *
  * If an imprecise data rate is too high due to rounding error
  * propagation, compute a suitably rounded mclk_ps to compute

@@ -32,42 +33,37 @@ unsigned int get_memory_clk_period_ps(void)
 	unsigned int result;
 
 	/* Round to nearest 10ps, being careful about 64-bit multiply/divide */
-	unsigned long long mclk_ps = ULL_2E12;
-
-	/* Add 5*data_rate, for rounding */
-	mclk_ps += 5*(unsigned long long)data_rate;
+	unsigned long long rem, mclk_ps = ULL_2E12;
 
 	/* Now perform the big divide, the result fits in 32-bits */
-	do_div(mclk_ps, data_rate);
-	result = mclk_ps;
+	rem = do_div(mclk_ps, data_rate);
+	result = (rem >= (data_rate >> 1)) ? mclk_ps + 1 : mclk_ps;
 
-	/* We still need to round to 10ps */
-	return 10 * (result/10);
+	return result;
 }
 
 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
 unsigned int picos_to_mclk(unsigned int picos)
 {
 	unsigned long long clks, clks_rem;
+	unsigned long data_rate = get_ddr_freq(0);
 
 	/* Short circuit for zero picos */
 	if (!picos)
 		return 0;
 
 	/* First multiply the time by the data rate (32x32 => 64) */
-	clks = picos * (unsigned long long)get_ddr_freq(0);
-
+	clks = picos * (unsigned long long)data_rate;
 	/*
 	 * Now divide by 5^12 and track the 32-bit remainder, then divide
 	 * by 2*(2^12) using shifts (and updating the remainder).
 	 */
 	clks_rem = do_div(clks, UL_5POW12);
-	clks_rem <<= 13;
-	clks_rem |= clks & (UL_2POW13-1);
+	clks_rem += (clks & (UL_2POW13-1)) * UL_5POW12;
 	clks >>= 13;
 
-	/* If we had a remainder, then round up */
-	if (clks_rem)
+	/* If we had a remainder greater than the 1ps error, then round up */
+	if (clks_rem > data_rate)
 		clks++;
 
 	/* Clamp to the maximum representable value */

Signature · 1 line

1.7.0.4

York Sun

author

2011-08-09 20:50 UTC #3 lore raw

PATCH 4/7 powerpc/mpc8xxx: Add DDR2 to unified DDR driver

In reply to York Sun

DDR2 has different ODT table and values. Adding table according to Samsung application note.

Fix additive latency calculation to avoid interger underflow.

Signed-off-by York Sun <[email protected]>

---
 .../cpu/mpc8xxx/ddr/lc_common_dimm_params.c        |    3 +-
 arch/powerpc/cpu/mpc8xxx/ddr/options.c             |  214 +++++++++++++++++++-
 arch/powerpc/include/asm/fsl_ddr_sdram.h           |    7 +
 doc/README.fsl-ddr                                 |   52 +++++
 4 files changed, 274 insertions(+), 2 deletions(-)

arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c +2 -1

index 8132e68..20c7db0 100644
@@ -448,7 +448,8 @@ compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
 
 #if defined(CONFIG_FSL_DDR2)
 	if (lowest_good_caslat < 4) {
-		additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat;
+		additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
+			? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
 		if (mclk_to_picos(additive_latency) > tRCD_ps) {
 			additive_latency = picos_to_mclk(tRCD_ps);
 			debug("setting additive_latency to %u because it was "

arch/powerpc/cpu/mpc8xxx/ddr/options.c +213 -1

233 lines not on this page · raw message

arch/powerpc/include/asm/fsl_ddr_sdram.h +7 -0

index 5b6e8d9..050c840 100644
@@ -31,6 +31,11 @@
 #define DDR3_RTT_20_OHM		4 /* RTT_Nom = RZQ/12 */
 #define DDR3_RTT_30_OHM		5 /* RTT_Nom = RZQ/8 */
 
+#define DDR2_RTT_OFF		0
+#define DDR2_RTT_75_OHM		1
+#define DDR2_RTT_150_OHM	2
+#define DDR2_RTT_50_OHM		3
+
 #if defined(CONFIG_FSL_DDR1)
 #define FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR	(1)
 typedef ddr1_spd_eeprom_t generic_spd_eeprom_t;

@@ -49,6 +54,8 @@ typedef ddr3_spd_eeprom_t generic_spd_eeprom_t;
 #ifndef CONFIG_FSL_SDRAM_TYPE
 #define CONFIG_FSL_SDRAM_TYPE	SDRAM_TYPE_DDR3
 #endif
+#else
+#error "Not defined DDR type"
 #endif	/* #if defined(CONFIG_FSL_DDR1) */
 
 #define FSL_DDR_ODT_NEVER		0x0

doc/README.fsl-ddr +52 -0

55 lines not on this page · raw message

Signature · 1 line

1.7.0.4

York Sun

author

2011-08-09 20:50 UTC #4 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

In reply to York Sun

Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters.

To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition.

Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.

Signed-off-by Kim Phillips <[email protected]>

Signed-off-by York Sun <[email protected]>

---
 Makefile                                 |    1 +
 arch/powerpc/cpu/mpc83xx/Makefile        |   20 +++++-
 arch/powerpc/cpu/mpc83xx/ecc.c           |   18 ++++--
 arch/powerpc/cpu/mpc83xx/law.c           |   61 ++++++++++++++++
 arch/powerpc/cpu/mpc83xx/speed.c         |    9 +++
 arch/powerpc/cpu/mpc85xx/ddr-gen2.c      |    8 ++-
 arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c |    4 +-
 arch/powerpc/cpu/mpc8xxx/ddr/util.c      |    9 ++-
 arch/powerpc/include/asm/config.h        |    5 +-
 arch/powerpc/include/asm/immap_83xx.h    |  117 +++++++++++++++++++++++++++++-
 common/Makefile                          |    8 ++-
 include/common.h                         |    4 +-
 12 files changed, 245 insertions(+), 19 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc83xx/law.c

Makefile +1 -0

index 689fddb..16f015e 100644
@@ -252,6 +252,7 @@ LIBS += drivers/power/libpower.o
 LIBS += drivers/spi/libspi.o
 ifeq ($(CPU),mpc83xx)
 LIBS += drivers/qe/libqe.o
+LIBS += arch/powerpc/cpu/mpc8xxx/ddr/libddr.o
 LIBS += arch/powerpc/cpu/mpc8xxx/lib8xxx.o
 endif
 ifeq ($(CPU),mpc85xx)

arch/powerpc/cpu/mpc83xx/Makefile +19 -1

index 3979b6f..b353036 100644
@@ -34,7 +34,6 @@ COBJS-y += cpu.o
 COBJS-y += cpu_init.o
 COBJS-y += speed.o
 COBJS-y += interrupts.o
-COBJS-y += spd_sdram.o
 COBJS-y += ecc.o
 COBJS-$(CONFIG_QE) += qe_io.o
 COBJS-$(CONFIG_FSL_SERDES) += serdes.o

@@ -42,6 +41,13 @@ COBJS-$(CONFIG_PCI) += pci.o
 COBJS-$(CONFIG_PCIE) += pcie.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
 
+ifdef CONFIG_FSL_DDR2
+COBJS-$(CONFIG_MPC8349) += ddr-gen2.o
+else
+COBJS-y += spd_sdram.o
+endif
+COBJS-$(CONFIG_FSL_DDR2) += law.o
+
 COBJS	:= $(COBJS-y)
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))

@@ -52,6 +58,18 @@ all:	$(obj).depend $(START) $(LIB)
 $(LIB):	$(OBJS)
 	$(call cmd_link_o_target, $(OBJS))
 
+$(obj)ddr-gen1.c:
+	@rm -f $(obj)ddr-gen1.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen1.c $(obj)ddr-gen1.c
+
+$(obj)ddr-gen2.c:
+	@rm -f $(obj)ddr-gen2.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen2.c $(obj)ddr-gen2.c
+
+$(obj)ddr-gen3.c:
+	@rm -f $(obj)ddr-gen3.c
+	ln -sf $(SRCTREE)/arch/powerpc/cpu/mpc85xx/ddr-gen3.c $(obj)ddr-gen3.c
+
 #########################################################################
 
 # defines $(obj).depend target

arch/powerpc/cpu/mpc83xx/ecc.c +13 -5

index f8eab96..717365c 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
  *
  * Dave Liu <[email protected]>
  * based on the contribution of Marian Balakowicz <[email protected]>

@@ -20,8 +20,12 @@
 #if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
 void ecc_print_status(void)
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+	ccsr_ddr_t *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
 
 	printf("\nECC mode: %s\n\n",
 	       (ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");

@@ -100,8 +104,12 @@ void ecc_print_status(void)
 
 int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
-	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-	volatile ddr83xx_t *ddr = &immap->ddr;
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+#ifdef CONFIG_FSL_DDR2
+	ccsr_ddr_t *ddr = &immap->ddr;
+#else
+	ddr83xx_t *ddr = &immap->ddr;
+#endif
 	volatile u32 val;
 	u64 *addr;
 	u32 count;

arch/powerpc/cpu/mpc83xx/law.c new file +61 -0

61 lines not on this page · raw message

arch/powerpc/cpu/mpc83xx/speed.c +9 -0

index 5e616dd..82d2ae5 100644
@@ -504,6 +504,15 @@ ulong get_bus_freq(ulong dummy)
 	return gd->csb_clk;
 }
 
+/********************************************
+ * get_ddr_freq
+ * return ddr bus freq in Hz
+ *********************************************/
+ulong get_ddr_freq(ulong dummy)
+{
+	return gd->mem_clk;
+}
+
 int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 {
 	char buf[32];

arch/powerpc/cpu/mpc85xx/ddr-gen2.c +6 -2

index 655f99c..10f3685 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008-2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License

@@ -18,7 +18,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			     unsigned int ctrl_num)
 {
 	unsigned int i;
-	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_MPC83xx
+	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
+#else
+	ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#endif
 
 	if (ctrl_num) {
 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);

arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c +3 -1

index eb8d8e3..391eb25 100644
@@ -18,7 +18,9 @@
 
 #include "ddr.h"
 
-#ifdef CONFIG_MPC85xx
+#ifdef CONFIG_MPC83xx
+	#define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
+#elif defined(CONFIG_MPC85xx)
 	#define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
 #elif defined(CONFIG_MPC86xx)
 	#define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR

arch/powerpc/cpu/mpc8xxx/ddr/util.c +6 -3

index c644131..eb6a17a 100644
@@ -129,10 +129,13 @@ fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 
 void board_add_ram_info(int use_default)
 {
-#if defined(CONFIG_MPC85xx)
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+#if defined(CONFIG_MPC83xx)
+	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
+	ccsr_ddr_t *ddr = (void *)&immap->ddr;
+#elif defined(CONFIG_MPC85xx)
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 #elif defined(CONFIG_MPC86xx)
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
+	ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 #endif
 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 	uint32_t cs0_config = in_be32(&ddr->cs0_config);

arch/powerpc/include/asm/config.h +4 -1

index c5e5c9c..d138636 100644
@@ -42,7 +42,10 @@
 #define CONFIG_SYS_BOOT_GET_KBD
 
 #ifndef CONFIG_MAX_MEM_MAPPED
-#if defined(CONFIG_4xx) || defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
+#if	defined(CONFIG_4xx)		|| \
+	defined(CONFIG_E500)		|| \
+	defined(CONFIG_MPC86xx)		|| \
+	defined(CONFIG_E300)
 #define CONFIG_MAX_MEM_MAPPED	((phys_size_t)2 << 30)
 #else
 #define CONFIG_MAX_MEM_MAPPED	(256 << 20)

arch/powerpc/include/asm/immap_83xx.h +113 -4

147 lines not on this page · raw message

common/Makefile +7 -1

index 224b7cc..8452d5d 100644
@@ -162,7 +162,13 @@ COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
 COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
 
 # others
-COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+COBJS-$(SPD) += ddr_spd.o
 COBJS-$(CONFIG_HWCONFIG) += hwconfig.o
 COBJS-$(CONFIG_CONSOLE_MUX) += iomux.o
 COBJS-y += flash.o

include/common.h +3 -1

index 1e21b7a..c22068a 100644
@@ -537,10 +537,12 @@ ulong get_PERCLK3(void);
 ulong	get_bus_freq  (ulong);
 int get_serial_clock(void);
 
+#if defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx)
+ulong get_ddr_freq(ulong);
+#endif
 #if defined(CONFIG_MPC85xx)
 typedef MPC85xx_SYS_INFO sys_info_t;
 void	get_sys_info  ( sys_info_t * );
-ulong	get_ddr_freq  (ulong);
 #endif
 #if defined(CONFIG_MPC86xx)
 typedef MPC86xx_SYS_INFO sys_info_t;

Signature · 1 line

1.7.0.4

Wolfgang Denk

2011-08-24 22:36 UTC #5 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 5 lines · In message <[email protected]> you wrote:

Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters.

Quoted 8 lines

To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition.
Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by Kim Phillips <[email protected]>
Signed-off-by York Sun <[email protected]>

Checkpatch says:

WARNING: do not add new typedefs
#408: FILE: arch/powerpc/include/asm/immap_83xx.h:289:
+typedef struct ccsr_ddr {

Please fix.

Best regards,

Wolfgang Denk

Signature · 8 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Every revolutionary idea - in science, politics, art, or  whatever  -
evokes three stages of reaction in a hearer:
  1. It is completely impossible - don't waste my time.
  2. It is possible, but it is not worth doing.
  3. I said it was a good idea all along.

York Sun

author

2011-08-25 20:57 UTC #6 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Wolfgang,

Quoted 17 lines · Wolfgang Denk

Dear York Sun,
Quoted 5 lines · In message <[email protected]> you wrote:
Unified DDR driver is maintained for better performance, robustness and bug fixes. Upgrading to use unified DDR driver for MPC83xx takes advantage of overall improvement. It requires changes for board files to customize platform-dependent parameters.
Quoted 8 lines
To utilize the unified DDR driver, a board needs to define CONFIG_FSL_DDRx in the header file. No more boards will be accepted without such definition.
Note: the workaround for erratum DDR6 for the very old MPC834x Rev 1.0/1.1 and MPC8360 Rev 1.1/1.2 parts is not migrated to unified driver.
Signed-off-by Kim Phillips <[email protected]>
Signed-off-by York Sun <[email protected]>

Quoted 8 lines

Checkpatch says:
WARNING: do not add new typedefs
#408: FILE: arch/powerpc/include/asm/immap_83xx.h:289:
+typedef struct ccsr_ddr {
Please fix.

I can fix the new tyepdef. But this one isn't. It has been used for a long time by 85xx. I am trying to unified the code. It is inevitable to define the same typedef for 83xx.

Regards,

York

Wolfgang Denk

2011-08-25 21:20 UTC #7 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 10 lines · In message <1314305821.29220.21.camel@oslab-l1> you wrote:

Quoted 6 lines
WARNING: do not add new typedefs
#408: FILE: arch/powerpc/include/asm/immap_83xx.h:289:
+typedef struct ccsr_ddr {
Please fix.
I can fix the new tyepdef. But this one isn't. It has been used for a long time by 85xx. I am trying to unified the code. It is inevitable to define the same typedef for 83xx.

Is it? I don't think so. You can, for example, fix the 85xx code as well...

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Our business is run on trust.  We trust you will pay in advance.

York Sun

author

2011-08-25 21:25 UTC #8 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Quoted 8 lines · Wolfgang Denk

Dear York Sun,
Quoted 5 lines · In message <1314305821.29220.21.camel@oslab-l1> you wrote:
Quoted 5 lines
WARNING: do not add new typedefs
#408: FILE: arch/powerpc/include/asm/immap_83xx.h:289:
+typedef struct ccsr_ddr {

Quoted 8 lines

Quoted 5 lines
Quoted 1 line
Please fix.
I can fix the new tyepdef. But this one isn't. It has been used for a long time by 85xx. I am trying to unified the code. It is inevitable to define the same typedef for 83xx.
Is it? I don't think so. You can, for example, fix the 85xx code as well...

Fixing all existing reference to ccs_ddr is a lot of work, comparing with defining it for 83xx. There are many other typedefs in the very same files. Would we fix all of them? I don't think so. The bottom of line is ccsr_ddr is not a new typedef.

York

Wolfgang Denk

2011-08-25 21:30 UTC #9 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 4 lines · In message <1314307500.29220.24.camel@oslab-l1> you wrote:

Fixing all existing reference to ccs_ddr is a lot of work, comparing with defining it for 83xx. There are many other typedefs in the very same files. Would we fix all of them? I don't think so. The bottom of

well, if you could fix all of these while you are at it that would be just great :-)

Quoted 1 line

line is ccsr_ddr is not a new typedef.

But you are adding it new to this file.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Few people do business well who do nothing else.
                                       -- Philip Earl of Chesterfield

York Sun

author

2011-08-25 21:36 UTC #10 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Wolfgang,

Quoted 10 lines · Wolfgang Denk

Dear York Sun,
Quoted 4 lines · In message <1314307500.29220.24.camel@oslab-l1> you wrote:
Fixing all existing reference to ccs_ddr is a lot of work, comparing with defining it for 83xx. There are many other typedefs in the very same files. Would we fix all of them? I don't think so. The bottom of
well, if you could fix all of these while you are at it that would be just great :-)

There are nearly 400 typedefs for powerpc and 52 for immap_85xx.h, not mentioned when they are used by .c files. Too many to fix.

Quoted 4 lines

Quoted 2 lines
line is ccsr_ddr is not a new typedef.
But you are adding it new to this file.

I am introducing it to this file as it is already being used somewhere else. If you are trying to enforce this new policy, please start with brand new files/typedefs, as you pointed out in my another patch. I will be happy to fix that.

York

Wolfgang Denk

2011-08-25 22:31 UTC #11 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 5 lines · In message <1314308192.29220.29.camel@oslab-l1> you wrote:

I am introducing it to this file as it is already being used somewhere else. If you are trying to enforce this new policy, please start with brand new files/typedefs, as you pointed out in my another patch. I will be happy to fix that.

It is in no way a new policy that U-Boot uses the Linux CodingStyle as model. We've been doing this for years. It's just that checkpatch allows for more regular and more strict tests for violations.

Best regards,

Wolfgang Denk

Signature · 7 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
I believe you find life such a problem because you  think  there  are
the  good  people  and the bad people. You're wrong, of course. There
are, always and only, the bad people, but some of them are  on  oppo-
site sides.                      - Terry Pratchett, _Guards! Guards!_

York Sun

author

2011-08-26 17:00 UTC #12 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Wolfgang,

Quoted 4 lines · Wolfgang Denk

Dear York Sun,
Quoted 1 line · In message <1314308192.29220.29.camel@oslab-l1> you wrote:

Quoted 9 lines

Quoted 4 lines
I am introducing it to this file as it is already being used somewhere else. If you are trying to enforce this new policy, please start with brand new files/typedefs, as you pointed out in my another patch. I will be happy to fix that.
It is in no way a new policy that U-Boot uses the Linux CodingStyle as model. We've been doing this for years. It's just that checkpatch allows for more regular and more strict tests for violations.

I am going to follow the style and not to add new typedefs. For the existing typedef, I will keep using them. In this case, it is an existing typedef, just for another platform. Fixing it alone will cause more troubles.

York

Wolfgang Denk

2011-08-26 18:12 UTC #13 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 5 lines · In message <1314378058.20734.25.camel@oslab-l1> you wrote:

I am going to follow the style and not to add new typedefs. For the existing typedef, I will keep using them. In this case, it is an existing typedef, just for another platform. Fixing it alone will cause more troubles.

I understand why you would prefer such an interpretation... But the fact is, you are adding new code that contains typedef's (and it does not matter at all if other code in other places does the same or not).

Please don't misunderstand me - I can accept if you prefer not to fix this problem now, but rather address it later, in a separate patch. But it is technically wrong to claim you were not adding new
typedef's. Checkpatch complains not without reason.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"An organization dries up if you don't challenge it with growth."
       - Mark Shepherd, former President and CEO of Texas Instruments

York Sun

author

2011-08-26 18:15 UTC #14 lore raw

PATCH 5/7 powerpc/mpc83xx: Migrate from spd_sdram to unified DDR driver

Quoted 14 lines · Wolfgang Denk

Dear York Sun,
Quoted 5 lines · In message <1314378058.20734.25.camel@oslab-l1> you wrote:
I am going to follow the style and not to add new typedefs. For the existing typedef, I will keep using them. In this case, it is an existing typedef, just for another platform. Fixing it alone will cause more troubles.
I understand why you would prefer such an interpretation... But the fact is, you are adding new code that contains typedef's (and it does not matter at all if other code in other places does the same or not).

Quoted 5 lines

Please don't misunderstand me - I can accept if you prefer not to fix this problem now, but rather address it later, in a separate patch. But it is technically wrong to claim you were not adding new
typedef's. Checkpatch complains not without reason.

OK. I do prefer not to fix it now if you can accept it. Are you implying we should fix all the existing typedefs? That will be a lot of cleanup.

York

York Sun

author

2011-08-09 20:50 UTC #15 lore raw

PATCH 6/7 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver

In reply to York Sun

Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC.

Signed-off-by York Sun <[email protected]>

Signed-off-by Kim Phillips <[email protected]>

---
 board/freescale/mpc8349emds/Makefile      |    1 +
 board/freescale/mpc8349emds/ddr.c         |   93 +++++++++++++++++++++++++++++
 board/freescale/mpc8349emds/mpc8349emds.c |   26 +++++----
 include/configs/MPC8349EMDS.h             |   16 +++++
 4 files changed, 125 insertions(+), 11 deletions(-)
 create mode 100644 board/freescale/mpc8349emds/ddr.c

board/freescale/mpc8349emds/Makefile +1 -0

index 4f76eab..601c3bf 100644
@@ -27,6 +27,7 @@ LIB	= $(obj)lib$(BOARD).o
 
 COBJS-y += $(BOARD).o
 COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_FSL_DDR2) += ddr.o
 
 COBJS	:= $(COBJS-y)
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)

board/freescale/mpc8349emds/ddr.c new file +93 -0

93 lines not on this page · raw message

board/freescale/mpc8349emds/mpc8349emds.c +15 ~~-11~~

index 365ac37..620540f 100644
@@ -29,7 +29,11 @@
 #include <i2c.h>
 #include <spi.h>
 #include <miiphy.h>
+#ifdef CONFIG_FSL_DDR2
+#include <asm/fsl_ddr_sdram.h>
+#else
 #include <spd_sdram.h>
+#endif
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>

@@ -62,7 +66,7 @@ int board_early_init_f (void)
 phys_size_t initdram (int board_type)
 {
 	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
-	u32 msize = 0;
+	phys_size_t msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;

@@ -70,24 +74,24 @@ phys_size_t initdram (int board_type)
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
-	msize = spd_sdram();
+#ifndef CONFIG_FSL_DDR2
+	msize = spd_sdram() * 1024 * 1024;
+#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
+	ddr_enable_ecc(msize);
+#endif
+#else
+	msize = fsl_ddr_sdram();
+#endif
 #else
-	msize = fixed_sdram();
+	msize = fixed_sdram() * 1024 * 1024;
 #endif
 	/*
 	 * Initialize SDRAM if it is on local bus.
 	 */
 	sdram_init();
 
-#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
-	/*
-	 * Initialize and enable DDR ECC.
-	 */
-	ddr_enable_ecc(msize * 1024 * 1024);
-#endif
-
 	/* return total bus SDRAM size(bytes)  -- DDR */
-	return (msize * 1024 * 1024);
+	return msize;
 }
 
 #if !defined(CONFIG_SPD_EEPROM)

include/configs/MPC8349EMDS.h +16 -0

index 45b6b5f..da2b11d 100644
@@ -78,6 +78,22 @@
 #define CONFIG_SPD_EEPROM		/* use SPD EEPROM for DDR setup*/
 
 /*
+ * define CONFIG_FSL_DDR2 to use unified DDR driver
+ * undefine it to use old spd_sdram.c
+ */
+#define CONFIG_FSL_DDR2
+#ifdef CONFIG_FSL_DDR2
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x52
+#define SPD_EEPROM_ADDRESS2	0x51
+#define CONFIG_NUM_DDR_CONTROLLERS	1
+#define CONFIG_DIMM_SLOTS_PER_CTLR	2
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE	0xDeadBeef
+#endif
+
+/*
  * 32-bit data path mode.
  *
  * Please note that using this mode for devices with the real density of 64-bit

Signature · 1 line

1.7.0.4

Wolfgang Denk

2011-08-24 22:39 UTC #16 lore raw

PATCH 6/7 powerpc/mpc8349emds: Migrate from spd_sdram to unified DDR driver

Dear York Sun,

Quoted 6 lines · In message <[email protected]> you wrote:

Update MPC8349EMDS to use unified DDR driver instead of spd_sdram.c. The unified driver can initialize data using DDR controller. No need to use DMA if just to initialze for ECC.
Signed-off-by York Sun <[email protected]>
Signed-off-by Kim Phillips <[email protected]>

Checkpatch says:

WARNING: do not add new typedefs
#149: FILE: board/freescale/mpc8349emds/ddr.c:14:
+typedef struct {

Please fix.

board/freescale/mpc8349emds/ddr.c line 6

Quoted 8 lines

+++ b/board/freescale/mpc8349emds/ddr.c

board/freescale/mpc8349emds/ddr.c new file +6 -0

@@ -0,0 +1,93 @@
+/*
+ * Copyright 2011 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 as published by the Free Software Foundation.

U-Boot requires GPLv2+ in all new files. Please fix globally.

board/freescale/mpc8349emds/ddr.c line 21

Quoted 8 lines

board/freescale/mpc8349emds/ddr.c new file +8 -0

+typedef struct {
+	u32 datarate_mhz_low;
+	u32 datarate_mhz_high;
+	u32 n_ranks;
+	u32 clk_adjust;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;

We don't allow CamelCaps identifiers. Please fix globally.

board/freescale/mpc8349emds/ddr.c line 67

Quoted 3 lines

board/freescale/mpc8349emds/ddr.c new file +3 -0

+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */

Incorrect multiline comment style. Please fix globally.

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
"One thing they don't tell you about doing  experimental  physics  is
that sometimes you must work under adverse conditions... like a state
of sheer terror."                                    - W. K. Hartmann

York Sun

author

2011-08-09 20:50 UTC #17 lore raw

PATCH 7/7 powerpc/8xxx: Add support for interactive DDR programming interface

In reply to York Sun

Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash.

To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax:

setenv ddr_interactive on

After reset, U-boot prompts before initializing DDR controllers FSL DDR>

The available commands are

print      print SPD and intermediate computed data
reset      reboot machine
recompute  reload SPD and options to default and recompute regs
edit       modify spd, parameter, or option
compute    recompute registers from current next_step to end
next_step  shows current next_step
help       this message
go         program the memory controller and continue with u-boot

The first command should be "compute", which reads data from DIMM SPDs and board options, performs the calculation then stops before setting DDR controller. A user can use "print" and "edit" commands to view and modify anything. "Go" picks up from current step with any modification and compltes the calculation then enables the DDR controller to continue u-boot. "Recompute" does it over from fresh reading.

Signed-off-by York Sun <[email protected]>

---
 arch/powerpc/cpu/mpc8xxx/ddr/Makefile      |    3 +-
 arch/powerpc/cpu/mpc8xxx/ddr/ddr.h         |   40 +-
 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c | 1704 ++++++++++++++++++++++++++++
 arch/powerpc/cpu/mpc8xxx/ddr/main.c        |    9 +-
 doc/README.fsl-ddr                         |   18 +
 5 files changed, 1757 insertions(+), 17 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/ddr/interactive.c

arch/powerpc/cpu/mpc8xxx/ddr/Makefile +2 -1

index d1b4c4b..29523aa 100644
@@ -1,5 +1,5 @@
 #
-# Copyright 2008 Freescale Semiconductor, Inc.
+# Copyright 2008-2011 Freescale Semiconductor, Inc.
 #
 # This program is free software; you can redistribute it and/or
 # modify it under the terms of the GNU General Public License

@@ -30,6 +30,7 @@ COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
 endif
 
+COBJS-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))

arch/powerpc/cpu/mpc8xxx/ddr/ddr.h +27 ~~-13~~

index f59aa33..c8b0f91 100644
@@ -56,32 +56,46 @@ typedef struct {
 #define STEP_PROGRAM_REGS            (1 << 6)
 #define STEP_ALL                     0xFFF
 
-extern unsigned long long
+unsigned long long
 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 				       unsigned int size_only);
 
-extern const char * step_to_string(unsigned int step);
+const char *step_to_string(unsigned int step);
 
-extern unsigned int
-compute_fsl_memctl_config_regs(const memctl_options_t *popts,
+unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts,
 			       fsl_ddr_cfg_regs_t *ddr,
 			       const common_timing_params_t *common_dimm,
 			       const dimm_params_t *dimm_parameters,
 			       unsigned int dbw_capacity_adjust,
 			       unsigned int size_only);
-extern unsigned int
-compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
-				      common_timing_params_t *outpdimm,
-				      unsigned int number_of_dimms);
-extern unsigned int populate_memctl_options(int all_DIMMs_registered,
+unsigned int compute_lowest_common_dimm_parameters(
+				const dimm_params_t *dimm_params,
+				common_timing_params_t *outpdimm,
+				unsigned int number_of_dimms);
+unsigned int populate_memctl_options(int all_DIMMs_registered,
 				memctl_options_t *popts,
 				dimm_params_t *pdimm,
 				unsigned int ctrl_num);
-extern void check_interleaving_options(fsl_ddr_info_t *pinfo);
+void check_interleaving_options(fsl_ddr_info_t *pinfo);
 
-extern unsigned int mclk_to_picos(unsigned int mclk);
-extern unsigned int get_memory_clk_period_ps(void);
-extern unsigned int picos_to_mclk(unsigned int picos);
+unsigned int mclk_to_picos(unsigned int mclk);
+unsigned int get_memory_clk_period_ps(void);
+unsigned int picos_to_mclk(unsigned int picos);
+void fsl_ddr_set_lawbar(
+		const common_timing_params_t *memctl_common_params,
+		unsigned int memctl_interleaved,
+		unsigned int ctrl_num);
+
+unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo);
+void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
+			   unsigned int ctrl_num);
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
+
+/* processor specific function */
+void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
+				   unsigned int ctrl_num);
 
 /* board specific function */
 int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +1704 -0

1,704 lines not on this page · raw message

arch/powerpc/cpu/mpc8xxx/ddr/main.c +6 -3

index 5699b0c..f52ad9f 100644
@@ -135,7 +135,6 @@ void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  *				|  interleaving
  */
 
-#ifdef DEBUG
 const char *step_string_tbl[] = {
 	"STEP_GET_SPD",
 	"STEP_COMPUTE_DIMM_PARMS",

@@ -156,7 +155,6 @@ const char * step_to_string(unsigned int step) {
 
 	return step_string_tbl[s];
 }
-#endif
 
 int step_assign_addresses(fsl_ddr_info_t *pinfo,
 			  unsigned int dbw_cap_adj[],

@@ -499,7 +497,12 @@ phys_size_t fsl_ddr_sdram(void)
 	memset(&info, 0, sizeof(fsl_ddr_info_t));
 
 	/* Compute it once normally. */
-	total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
+#ifdef CONFIG_FSL_DDR_INTERACTIVE
+	if (getenv("ddr_interactive"))
+		total_memory = fsl_ddr_interactive(&info);
+	else
+#endif
+		total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 
 	/* Check for memory controller interleaving. */
 	memctl_interleaved = 0;

doc/README.fsl-ddr +18 -0

index abfb7f1..787c71b 100644
@@ -222,3 +222,21 @@ Single slot system
 
 Reference http://www.samsung.com/global/business/semiconductor/products/dram/downloads/applicationnote/ddr2_odt_control_200603.pdf
 
+
+Interactive DDR debugging
+===========================
+
+For DDR parameter tuning up and debugging, the interactive DDR debugging can
+be activated by saving an environment variable "ddr_interactive". The value
+doesn't matter. Once activated, U-boot prompts "FSL DDR>" before enabling DDR
+controller. The available commands can be seen by typing "help".
+
+The example flow of using interactive debugging is
+type command "compute" to calculate the parameters from the default
+type command "print" with arguments to show SPD, options, registers
+type command "edit" with arguments to change any if desired
+type command "go" to continue calculation and enable DDR controller
+
+Note, check "next_step" to show the flow. For example, after editing registers,
+DDR controller will be enabled with current setting without further
+calculation.

Signature · 1 line

1.7.0.4

Tabi Timur-B04825

2011-08-11 01:29 UTC #18 lore raw

PATCH 7/7 powerpc/8xxx: Add support for interactive DDR programming interface

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c line 29

Quoted 7 lines · York Sun

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +7 -0

+/* Option parameter Structures */
+typedef struct {
+	const char *option_name;
+	size_t offset;
+	unsigned int size;
+	const char printHex;
+} options_strings_t;

Does it make sense for only printHex (which should be "print_hex") and option_name to be const, but nothing else?

Wolfgang Denk

2011-08-24 22:33 UTC #19 lore raw

PATCH 7/7 powerpc/8xxx: Add support for interactive DDR programming interface

In reply to York Sun

Dear York Sun,

Quoted 7 lines · In message <[email protected]> you wrote:

Interactive DDR debugging provides a user interface to view and modify SPD, DIMM parameters, board options and DDR controller registers before DDR is initialized. With this feature, developers can fine-tune DDR for board bringup and other debugging without frequently having to reprogram the flash.
To enable this feature, define CONFIG_FSL_DDR_INTERACTIVE in board header file and set an environment variable to activate it. Syntax:

...

Checkpatch says:

WARNING: do not add new typedefs
WARNING: plain inline is preferred over __inline__
WARNING: do not add new typedefs

Please fix!

...

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c line 28

Quoted 6 lines

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +6 -0

+/* Option parameter Structures */
+typedef struct {
+	const char *option_name;
+	size_t offset;
+	unsigned int size;
+	const char printHex;

We don't allow CamelCase identifiers. Please fix globally.

...

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c line 1395

Quoted 7 lines

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +7 -0

+			/*
+			 * FIXME: For some reason printing this whole
+			 * thing causes the machine to freeze.
+			 * Splitting it into two printfs seems to make
+			 * it work. Does printf() have limits on the
+			 * length of the string?
+			 */

Please fix this before submitting.

Quoted 4 lines

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +4 -0

+			printf(
+	"commands:\n"
+	"print      print SPD and intermediate computed data\n"
+	"reset      reboot machine\n"

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c line 1409

Quoted 10 lines

arch/powerpc/cpu/mpc8xxx/ddr/interactive.c new file +10 -0

+	"recompute  reload SPD and options to default and recompute regs\n");
+			printf(
+	"edit       modify spd, parameter, or option\n");
+			printf(
+	"compute    recompute registers from current next_step to end\n"
+	"next_step  shows current next_step\n"
+	"help       this message\n"
+	"go         program the memory controller and continue with u-boot\n");
+			continue;
+		}

Incorrect indentation.

Best regards,

Wolfgang Denk

Signature · 5 lines

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