mips32: fix wrong loop bound in flush_cache()

The issue is found when calling flush_cache() with zero "size" argument.
The bound of loop is miscalculated in this case and flush_cache() enters a wrong flushing loop. To fix this issue I skipped the operations when "size" is found to be zero.

---
Changes for v2:
- Coding style cleanup
- Move code after declarations to avoid warning
Changes for v3:
- Coding style cleanup
- Add prefix "mips32" to the subject

 arch/mips/cpu/mips32/cpu.c |    4 ++++
 1 files changed, 4 insertions(+), 0 deletions(-)

index 3ae397c..7b49e1b 100644
@@ -56,6 +56,10 @@ void flush_cache(ulong start_addr, ulong size)
 	unsigned long addr = start_addr & ~(lsize - 1);
 	unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
 
+	/* aend will be miscalculated when size is zero, so we return here */
+	if (size == 0)
+		return;
+
 	while (1) {
 		cache_op(Hit_Writeback_Inv_D, addr);
 		cache_op(Hit_Invalidate_I, addr);

1.7.4.1

Hi,

It feels like the last sentence is somewhat redundant (the diff output speaks for itself), so omitted. Other than that, the patch is ok and queued up to u-boot-mips/master. If no MIPS patches come up within a couple of weeks, I'll make a pull request.

Thanks for your report,