arm:cache-l2x0: Fix L2 Cache size calculation.

PATCH New Srinivas KANDAGATLA 3 participants 7 messages Aug 12, 2011 – Aug 15, 2011 Arm (32-bit)

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Srinivas KANDAGATLA

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2011-08-12 09:45 UTC #0 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

From: Srinivas Kandagatla <[email protected]>

This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits.

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations.

I should say this bug does not result in issue but, its just prints incorrect values.

Signed-off-by Srinivas Kandagatla <[email protected]>

---
Hi All,
I found an bug in L2 Cache size calculation in cache-l2x0 code.

According to ARM TRM for L2C-210, L2C-310 and PL310, the Auxiliary Control Register has 3bits [19:17] allocated for Way size,however the existing code only uses 2 bits to get this value from Aux control register. This results in incorrect cache size calculations.

thanks,
srini

 arch/arm/include/asm/hardware/cache-l2x0.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

arch/arm/include/asm/hardware/cache-l2x0.h +1 -1

index 16bd480..bfa706f 100644
@@ -64,7 +64,7 @@
 #define L2X0_AUX_CTRL_MASK			0xc0000fff
 #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT	16
 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT		17
-#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x3 << 17)
+#define L2X0_AUX_CTRL_WAY_SIZE_MASK		(0x7 << 17)
 #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT	22
 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT		26
 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT		27

Signature · 1 line

1.6.3.3

Will Deacon

2011-08-12 10:20 UTC #1 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Quoted 6 lines · Srinivas KANDAGATLA

From: Srinivas Kandagatla <[email protected]>
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits.

Quoted 6 lines

The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations.
I should say this bug does not result in issue but, its just prints incorrect values.

It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small).

Quoted 1 line

Signed-off-by Srinivas Kandagatla <[email protected]>

Acked-by Will Deacon <[email protected]>

Please can you CC stable on this too?

Will

Russell King - ARM Linux

2011-08-13 08:41 UTC #2 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Quoted 18 lines · Will Deacon

Quoted 6 lines · Srinivas KANDAGATLA
From: Srinivas Kandagatla <[email protected]>
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits.
Quoted 6 lines
The Auxiliary Control Register for L2C-210, L2C-310 and PL310 has 3bits [19:17] for Way size, however the existing code only uses 2 bits to get this value. This results in incorrect cachesize calculations.
I should say this bug does not result in issue but, its just prints incorrect values.
It also results in performing operations on the whole cache when we erroneously decide that the range is big enough (due to l2x0_size being too small).

Quoted 5 lines

Quoted 1 line
Signed-off-by Srinivas Kandagatla <[email protected]>
Acked-by Will Deacon <[email protected]>
Please can you CC stable on this too?

It's probably better to ask people to add a Cc: line to the _attributations_ rather than telling them to CC the stable tree with their email, and then get a whinge from the stable maintainers about how that's not how to submit patches for stable trees.

Will Deacon

2011-08-14 20:48 UTC #3 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Hi Russell,

Quoted 7 lines · Russell King - ARM Linux

Quoted 6 lines · Will Deacon
Quoted 5 lines · Srinivas KANDAGATLA
From: Srinivas Kandagatla <[email protected]>
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits.

[...]

Quoted 6 lines

Quoted 1 line
Please can you CC stable on this too?
It's probably better to ask people to add a Cc: line to the _attributations_ rather than telling them to CC the stable tree with their email, and then get a whinge from the stable maintainers about how that's not how to submit patches for stable trees.

Of course, that's what I intended but unfortunately my choice of words was ambiguous.

Srinivas: can you add the CC stable line to your patch please and put it into Russell's patch system?

Thanks,

Will

Srinivas KANDAGATLA

author

2011-08-15 07:49 UTC #4 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Resending the patch with Acked by and CC lines in patch...

Thanks,
--srini

Quoted 36 lines · Will Deacon

Hi Russell,
Quoted 10 lines · Russell King - ARM Linux
Quoted 8 lines · Will Deacon
Quoted 6 lines · Srinivas KANDAGATLA
From: Srinivas Kandagatla <[email protected]>
This patch fixes L2 Cache size calculations for L2C-210, L2C-310 and PL310, by changing the L2X0_AUX_CTRL_WAY_SIZE_MASK from 2 bits to 3 bits.
[...]
Quoted 7 lines
Quoted 2 lines
Please can you CC stable on this too?
It's probably better to ask people to add a Cc: line to the _attributations_ rather than telling them to CC the stable tree with their email, and then get a whinge from the stable maintainers about how that's not how to submit patches for stable trees.
Of course, that's what I intended but unfortunately my choice of words was ambiguous.
Srinivas: can you add the CC stable line to your patch please and put it into Russell's patch system?
Thanks,
Will

Will Deacon

2011-08-15 08:58 UTC #5 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Srinivas,

Quoted 1 line · Srinivas KANDAGATLA

Resending the patch with Acked by and CC lines in patch...

As described here:

http://www.arm.linux.org.uk/developer/patches/info.php

You need to use Russell's patch system to submit this patch. If you're using git, the easiest way to do this is:

(0) Sign up to Russell's patch system (not sure if this required):
http://www.arm.linux.org.uk/developer/patches/add.php

(1) Add an additional KernelVersion: 3.1-rc2 tag to your patch.

(2) Email it to patches at arm.linux.org.uk using git send-email

    --suppress-cc=all.

Thanks,

Will

Russell King - ARM Linux

2011-08-15 10:12 UTC #6 lore raw

PATCH 1/1 arm:cache-l2x0: Fix L2 Cache size calculation.

Quoted 7 lines · Will Deacon

Srinivas,
Quoted 1 line · Srinivas KANDAGATLA
Resending the patch with Acked by and CC lines in patch...
As described here:

Quoted 7 lines

http://www.arm.linux.org.uk/developer/patches/info.php
You need to use Russell's patch system to submit this patch. If you're using git, the easiest way to do this is:
(0) Sign up to Russell's patch system (not sure if this required):
http://www.arm.linux.org.uk/developer/patches/add.php

(0) is not needed if sending email.

Quoted 4 lines

(1) Add an additional KernelVersion: 3.1-rc2 tag to your patch.
(2) Email it to patches at arm.linux.org.uk using git send-email
    --suppress-cc=all.