Initial Calxeda Highbank support

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +11 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.

Hi Rob,

Quoted 48 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +15 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

arch/arm/boot/dts/highbank.dts line 21

Quoted 6 lines

arch/arm/boot/dts/highbank.dts new file +6 -0

+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+

I failed to find the "pen" handling in the whole patch series. Am I missing anything?

Shawn,

Quoted 51 lines · Shawn Guo

Hi Rob,

Quoted 48 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +15 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

Quoted 9 lines

arch/arm/boot/dts/highbank.dts line 21

Quoted 6 lines

arch/arm/boot/dts/highbank.dts new file +6 -0

+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+

I failed to find the "pen" handling in the whole patch series. Am I missing anything?

In highbank.c:

Quoted 66 lines · Rob Herring

Shawn,

Quoted 51 lines · Shawn Guo

Hi Rob,

Quoted 48 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +15 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */

Quoted 9 lines

arch/arm/boot/dts/highbank.dts line 21

Quoted 6 lines

arch/arm/boot/dts/highbank.dts new file +6 -0

+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+

I failed to find the "pen" handling in the whole patch series. Am I missing anything?

In highbank.c:

Review

Quoted 11 lines

(quoted diff) +10 -0

+#define HB_JUMP_TABLE_PHYS(cpu)		(0x40 + (0x10 * (cpu)))
+#define HB_JUMP_TABLE_VIRT(cpu)		phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
+
+void highbank_set_cpu_jump(int cpu, void *jump_addr)
+{
+	writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+	__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
+	outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
+			  HB_JUMP_TABLE_PHYS(cpu) + 15);
+}

Ah, ok, the 'pen' you meant is the entry address of secondary cores. I thought of something like 'pen_release' in plat-versatile/platsmp.c. So you do not need 'boot_lock' and 'pen_release' stuff to sync secondary cores with the primary one (like all other smp platforms do)?

Hi Rob,

Quoted 2 lines · Rob Herring

In highbank.c:

Review

Quoted 10 lines

(quoted diff) +10 -0

+#define HB_JUMP_TABLE_PHYS(cpu)		(0x40 + (0x10 * (cpu)))
+#define HB_JUMP_TABLE_VIRT(cpu)		phys_to_virt(HB_JUMP_TABLE_PHYS(cpu))
+
+void highbank_set_cpu_jump(int cpu, void *jump_addr)
+{
+	writel(BSYM(virt_to_phys(jump_addr)), HB_JUMP_TABLE_VIRT(cpu));
+	__cpuc_flush_dcache_area(HB_JUMP_TABLE_VIRT(cpu), 16);
+	outer_clean_range(HB_JUMP_TABLE_PHYS(cpu),
+			  HB_JUMP_TABLE_PHYS(cpu) + 15);
+}

I don't suppose you guys can boot on a CPU other than 0 can you? That would be really handy for testing my cpu-mapping patch series :)

-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm- kernel-bounces at lists.infradead.org] On Behalf Of Rob Herring
Sent: 16 August 2011 21:35
To: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring
Subject: [PATCH 1/6] ARM: highbank: add devicetree source

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank
platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212
+++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Hi Rob,

Quoted 22 lines

-----Original Message-----
From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm- kernel-bounces at lists.infradead.org] On Behalf Of Rob Herring
Sent: 16 August 2011 21:35
To: linux-arm-kernel at lists.infradead.org
Cc: Rob Herring
Subject: [PATCH 1/6] ARM: highbank: add devicetree source

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank
platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212
+++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

...

arch/arm/boot/dts/highbank.dts line 117

Quoted 7 lines

arch/arm/boot/dts/highbank.dts new file +7 -0

+		L2: l2-cache {
+			compatible = "arm,pl310-cache";
+			reg = <0xfff12000 0x1000>;
+			interrupts = <102>;
+			cache-unified;
+			cache-level = <2>;
+		};

Currently, the binding documentation sitting in Russell's for-next branch doesn't have the interrupts property we discussed previously:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007301.html

I posted a patch to add it to the documentation, but no-one responded:
http://lists.ozlabs.org/pipermail/devicetree-discuss/2011-August/007349.html

Can I take your use of the property as an ack?

How do we get this merged?

Quoted 1 line · Mark Rutland

How do we get this merged?

Add to Russell's patch system or perhaps in Will's tree.

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +46 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+
+/ {
+	model = "Calxeda Highbank";
+	compatible = "calxeda,highbank";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a9";
+			reg = <2>;

Quoted 83 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds the devicetree source and documentation for the Calxeda highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 Documentation/devicetree/bindings/arm/calxeda.txt |    8 +
 arch/arm/boot/dts/highbank.dts                    |  212 +++++++++++++++++++++
 2 files changed, 220 insertions(+), 0 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/arm/calxeda.txt
 create mode 100644 arch/arm/boot/dts/highbank.dts

Documentation/devicetree/bindings/arm/calxeda.txt new file +8 -0

new file mode 100644
index 0000000..4755caa
@@ -0,0 +1,8 @@
+Calxeda Highbank Platforms Device Tree Bindings
+-----------------------------------------------
+
+Boards with Calxeda Cortex-A9 based Highbank SOC shall have the following
+properties.
+
+Required root node properties:
+    - compatible = "calxeda,highbank";

arch/arm/boot/dts/highbank.dts new file +50 -0

new file mode 100644
index 0000000..2dd3b7b
@@ -0,0 +1,212 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/dts-v1/;
+
+/* First 4KB has pen for secondary cores. */
+/memreserve/ 0x00000000 0x0001000;
+
+/ {
+	model = "Calxeda Highbank";
+	compatible = "calxeda,highbank";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 1 {
+			compatible = "arm,cortex-a9";
+			reg = <1>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 2 {
+			compatible = "arm,cortex-a9";
+			reg = <2>;
+			next-level-cache = <&L2>;
+		};
+
+		cpu at 3 {

arch/arm/boot/dts/highbank.dts line 56

Quoted 6 lines

arch/arm/boot/dts/highbank.dts new file +6 -0

+			compatible = "arm,cortex-a9";
+			reg = <3>;
+			next-level-cache = <&L2>;
+		};
+	};
+

I'm not sure if this whole "cpus" stuff is needed, I do not see any code playing with it.

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

Hi Rob,

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

arch/arm/mach-highbank/highbank.c line 120

Quoted 9 lines

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+	int irq;
+	struct device_node *np;
+	void __iomem *timer_base;
+
+	/* Map system registers */
+	np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	sregs_base = of_iomap(np, 0);

Should the return values be checked here? I know that all valid device trees should have these nodes and valid a reg property, but I don't know if the error handling needs to be a bit more explicit. For my platform I have put these checks and panics() if they fail, but I'm not sure if that's the right thing!

arch/arm/Kconfig +4 -0

+config ARCH_HIGHBANK
+	bool "Calxeda Highbank-based"
+	select CPU_V7
+	select AUTO_ZRELADDR

arch/arm/mach-highbank/highbank.c new file +20 -0

+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+

arch/arm/mach-highbank/highbank.c new file +8 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+	int irq;
+	struct device_node *np;
+	void __iomem *timer_base;
+
+	/* Map system registers */
+	np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/include/mach/timex.h new file +5 -0

+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+extern void __iomem *sregs_base;
+

Quoted 9 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+	int irq;
+	struct device_node *np;
+	void __iomem *timer_base;
+
+	/* Map system registers */
+	np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/highbank.c line 130

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+
+	np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+	timer_base = of_iomap(np, 0);
+	irq = irq_of_parse_and_map(np, 0);
+
+	highbank_clocks_init();
+
+	sp804_clocksource_init(timer_base + 0x20, "timer1");
+	sp804_clockevents_init(timer_base, irq, "timer0");
+}

How about moving the sp804 initialization from device tree into the arch/arm/common/timer-sp.c file?

Why do you initialize sregs_base from timer_init?

Quoted 8 lines

arch/arm/mach-highbank/include/mach/timex.h new file +2 -0

new file mode 100644
index 0000000..88dac7a
@@ -0,0 +1,6 @@
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H

arch/arm/mach-highbank/include/mach/timex.h line 6

Quoted 4 lines

arch/arm/mach-highbank/include/mach/timex.h new file +4 -0

+
+#define CLOCK_TICK_RATE		1000000
+
+#endif

In 3.2, we shouldn't need this any more. We'll have to come up with a way to remember removing the new definitions that come in in parallel to the patch that removes the old ones.

Quoted 24 lines · Arnd Bergmann

Quoted 9 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+   int irq;
+   struct device_node *np;
+   void __iomem *timer_base;
+
+   /* Map system registers */
+   np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+   sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/highbank.c line 130

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+
+   np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+   timer_base = of_iomap(np, 0);
+   irq = irq_of_parse_and_map(np, 0);
+
+   highbank_clocks_init();
+
+   sp804_clocksource_init(timer_base + 0x20, "timer1");
+   sp804_clockevents_init(timer_base, irq, "timer0");
+}

How about moving the sp804 initialization from device tree into the arch/arm/common/timer-sp.c file?

Quoted 1 line

Why do you initialize sregs_base from timer_init?

That'd create special cases - ARM platforms need registers twiddled to change the clock rate for the timers from 32kHz to a more sensible 1MHz.

Quoted 8 lines

Quoted 8 lines

arch/arm/mach-highbank/include/mach/timex.h new file +2 -0

new file mode 100644
index 0000000..88dac7a
@@ -0,0 +1,6 @@
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H

Quoted 8 lines

arch/arm/mach-highbank/include/mach/timex.h line 6

Quoted 4 lines

arch/arm/mach-highbank/include/mach/timex.h new file +4 -0

+
+#define CLOCK_TICK_RATE            1000000
+
+#endif

In 3.2, we shouldn't need this any more. We'll have to come up with a way to remember removing the new definitions that come in in parallel to the patch that removes the old ones.

Has anyone really properly evaluated the CLOCK_TICK_RATE issues on things like NTP etc? I have problems with kernels on OMAP4 constantly jumping forwards/back by .5sec when NTP is running which suggests that there's something not quite right _somewhere_.

Given that OMAP uses an untrue value for this, and the platforms I have which do behave properly when running NTP have correct values, I still remain entirely unconvinced about the claims surrounding CLOCK_TICK_RATE not mattering.

Has anyone managed to run NTP on OMAP4 and had it sync successfully over a few days?

Quoted 27 lines · Russell King - ARM Linux

Quoted 25 lines · Arnd Bergmann

Quoted 9 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+   int irq;
+   struct device_node *np;
+   void __iomem *timer_base;
+
+   /* Map system registers */
+   np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+   sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/highbank.c line 130

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+
+   np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+   timer_base = of_iomap(np, 0);
+   irq = irq_of_parse_and_map(np, 0);
+
+   highbank_clocks_init();
+
+   sp804_clocksource_init(timer_base + 0x20, "timer1");
+   sp804_clockevents_init(timer_base, irq, "timer0");
+}

How about moving the sp804 initialization from device tree into the arch/arm/common/timer-sp.c file?

Why do you initialize sregs_base from timer_init?

Quoted 2 lines

That'd create special cases - ARM platforms need registers twiddled to change the clock rate for the timers from 32kHz to a more sensible 1MHz.

Is that a bad thing? Platforms that don't need the special case can simply call sp804_clocksource_init_dt() which scans the device tree, while other platforms do whatever is necessary to the registers and then call the existing sp804_clockevents_init.

Is that a bad thing? Platforms that don't need the special case can simply call sp804_clocksource_init_dt() which scans the device tree, while other platforms do whatever is necessary to the registers and then call the existing sp804_clockevents_init.

Quoted 20 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +20 -0

+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+

arch/arm/mach-highbank/highbank.c line 75

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);
+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}

I really liked the way that Barry moved the io_desc out to the drivers using them, e.g arch/arm/mach-prima2/lluart.c.

Can you do the same thing with your lluart and with the a9_base_addr? I guess it can live locally in platsmp.c.

Quoted 14 lines

arch/arm/mach-highbank/highbank.c new file +13 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);
+	}

arch/arm/mach-highbank/highbank.c line 105

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +5 -0

+
+	for_each_compatible_node(node, NULL, "arm,pl061") {
+		irq_domain_add_simple(node, 160 + (8 * n));
+		n++;
+	}

Where does the "160 + (8 * n)" come from? Is that something that should be in a property of the gic binding?

arch/arm/mach-highbank/highbank.c line 110

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
+}

Hmm, I missed that during the review of the patch that adds l2x0_of_init, but I think the #ifdef should really be in the header file, not in the user, so that calling l2x0_of_init when CONFIG_CACHE_L2X0 is not set automatically turns into an empty stub.

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+	int irq;
+	struct device_node *np;
+	void __iomem *timer_base;
+
+	/* Map system registers */
+	np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/highbank.c line 130

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+
+	np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+	timer_base = of_iomap(np, 0);
+	irq = irq_of_parse_and_map(np, 0);
+
+	highbank_clocks_init();
+
+	sp804_clocksource_init(timer_base + 0x20, "timer1");
+	sp804_clockevents_init(timer_base, irq, "timer0");
+}

How about moving the sp804 initialization from device tree into the arch/arm/common/timer-sp.c file?

Why do you initialize sregs_base from timer_init?

arch/arm/mach-highbank/include/mach/timex.h line 6

Quoted 13 lines

arch/arm/mach-highbank/include/mach/timex.h new file +6 -0

new file mode 100644
index 0000000..88dac7a
@@ -0,0 +1,6 @@
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE		1000000
+
+#endif

In 3.2, we shouldn't need this any more. We'll have to come up with a way to remember removing the new definitions that come in in parallel to the patch that removes the old ones.

Quoted 6 lines

arch/arm/mach-highbank/include/mach/timex.h new file +5 -0

+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+extern void __iomem *sregs_base;
+

arch/arm/mach-highbank/include/mach/timex.h

Quoted 10 lines

arch/arm/mach-highbank/include/mach/timex.h new file +10 -0

+#define HB_SREG_A9_PWR_REQ		0xf00
+#define HB_SREG_A9_BOOT_STAT		0xf04
+#define HB_SREG_A9_BOOT_DATA		0xf08
+
+#define HB_PWR_SUSPEND			0
+#define HB_PWR_SOFT_RESET		1
+#define HB_PWR_HARD_RESET		2
+#define HB_PWR_SHUTDOWN			3
+
+#endif

Do these really need to be global?

I think it's better to put the base address and register definitions into a single file and export functions to be used from elsewhere.

Arnd,

Quoted 36 lines · Arnd Bergmann

Quoted 20 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +20 -0

+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+

arch/arm/mach-highbank/highbank.c line 75

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);
+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}

I really liked the way that Barry moved the io_desc out to the drivers using them, e.g arch/arm/mach-prima2/lluart.c.

Quoted 2 lines

Can you do the same thing with your lluart and with the a9_base_addr? I guess it can live locally in platsmp.c.

Okay.

Quoted 15 lines

Quoted 15 lines

arch/arm/mach-highbank/highbank.c new file +13 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);
+	}

Quoted 8 lines

arch/arm/mach-highbank/highbank.c line 105

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +5 -0

+
+	for_each_compatible_node(node, NULL, "arm,pl061") {
+		irq_domain_add_simple(node, 160 + (8 * n));
+		n++;
+	}

Where does the "160 + (8 * n)" come from? Is that something that should be in a property of the gic binding?

All this should go away once we have dynamic linux irq number assignment. Actually, I should just delete this for now as the pl061 driver doesn't support interrupts yet with DT binding (without platform data).

Quoted 10 lines

arch/arm/mach-highbank/highbank.c line 110

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
+}

Hmm, I missed that during the review of the patch that adds l2x0_of_init, but I think the #ifdef should really be in the header file, not in the user, so that calling l2x0_of_init when CONFIG_CACHE_L2X0 is not set automatically turns into an empty stub.

It's also a problem with l2x0_init. I'll add a patch to do that.

Quoted 24 lines

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +9 -0

+static void __init highbank_timer_init(void)
+{
+	int irq;
+	struct device_node *np;
+	void __iomem *timer_base;
+
+	/* Map system registers */
+	np = of_find_compatible_node(NULL, NULL, "calxeda,hb-sregs");
+	sregs_base = of_iomap(np, 0);

arch/arm/mach-highbank/highbank.c line 130

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+
+	np = of_find_compatible_node(NULL, NULL, "arm,sp804");
+	timer_base = of_iomap(np, 0);
+	irq = irq_of_parse_and_map(np, 0);
+
+	highbank_clocks_init();
+
+	sp804_clocksource_init(timer_base + 0x20, "timer1");
+	sp804_clockevents_init(timer_base, irq, "timer0");
+}

How about moving the sp804 initialization from device tree into the arch/arm/common/timer-sp.c file?

Quoted 1 line

Why do you initialize sregs_base from timer_init?

It will be needed before the clocks are initialized. The clock code is not using it at the moment as I just did a minimal fixed clock implementation until the clock api and DT clock bindings gets sorted out. As there are multiple users, I didn't put it in highbank_clocks_init.

Quoted 17 lines

arch/arm/mach-highbank/include/mach/timex.h line 6

Quoted 13 lines

arch/arm/mach-highbank/include/mach/timex.h new file +6 -0

new file mode 100644
index 0000000..88dac7a
@@ -0,0 +1,6 @@
+#ifndef __MACH_TIMEX_H
+#define __MACH_TIMEX_H
+
+#define CLOCK_TICK_RATE		1000000
+
+#endif

In 3.2, we shouldn't need this any more. We'll have to come up with a way to remember removing the new definitions that come in in parallel to the patch that removes the old ones.

I'm tracking the various clean-ups and we can coordinate the order things go in. I've already made gpio.h empty for example, so gpio will fail to compile if enabled in this series.

Or I can just submit a patch deleting this file later. It will just be dead code and won't conflict.

Quoted 19 lines

Quoted 6 lines

arch/arm/mach-highbank/include/mach/timex.h new file +5 -0

+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+extern void __iomem *sregs_base;
+

arch/arm/mach-highbank/include/mach/timex.h

Quoted 10 lines

arch/arm/mach-highbank/include/mach/timex.h new file +10 -0

+#define HB_SREG_A9_PWR_REQ		0xf00
+#define HB_SREG_A9_BOOT_STAT		0xf04
+#define HB_SREG_A9_BOOT_DATA		0xf08
+
+#define HB_PWR_SUSPEND			0
+#define HB_PWR_SOFT_RESET		1
+#define HB_PWR_HARD_RESET		2
+#define HB_PWR_SHUTDOWN			3
+
+#endif

Do these really need to be global?

Quoted 2 lines

I think it's better to put the base address and register definitions into a single file and export functions to be used from elsewhere.

Yes, sregs are a random collection of functions, so it's going to be a mixture of various users. Just HB_PWR_* alone are in 2 or 3 different places.

Rob

Arnd,

Quoted 42 lines · Rob Herring

Arnd,

Quoted 38 lines · Arnd Bergmann

Quoted 20 lines · Rob Herring

arch/arm/mach-highbank/highbank.c new file +20 -0

+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+

arch/arm/mach-highbank/highbank.c line 75

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);
+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}

I really liked the way that Barry moved the io_desc out to the drivers using them, e.g arch/arm/mach-prima2/lluart.c.

Can you do the same thing with your lluart and with the a9_base_addr? I guess it can live locally in platsmp.c.

Quoted 1 line

Okay.

Looking at this some more, it doesn't work too well. platsmp.c depends on CONFIG_SMP, but the SCU mapping is always needed even for !SMP because the SCU has a power mode register for each core used by the power controller. So putting it in platsmp.c would add ifdefs.

Looking at this some more, it doesn't work too well. platsmp.c depends on CONFIG_SMP, but the SCU mapping is always needed even for !SMP because the SCU has a power mode register for each core used by the power controller. So putting it in platsmp.c would add ifdefs.

So I'll move out the lluart mapping, but keep SCU mapping in highbank.c.

Quoted 18 lines

Quoted 5 lines

arch/arm/mach-highbank/sysregs.h new file +5 -0

+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+extern void __iomem *sregs_base;
+

arch/arm/mach-highbank/sysregs.h line 30

Quoted 10 lines

arch/arm/mach-highbank/sysregs.h new file +10 -0

+#define HB_SREG_A9_PWR_REQ          0xf00
+#define HB_SREG_A9_BOOT_STAT                0xf04
+#define HB_SREG_A9_BOOT_DATA                0xf08
+
+#define HB_PWR_SUSPEND                      0
+#define HB_PWR_SOFT_RESET           1
+#define HB_PWR_HARD_RESET           2
+#define HB_PWR_SHUTDOWN                     3
+
+#endif

Do these really need to be global?

Quoted 2 lines

I think it's better to put the base address and register definitions into a single file and export functions to be used from elsewhere.

Yes, sregs are a random collection of functions, so it's going to be a mixture of various users. Just HB_PWR_* alone are in 2 or 3 different places.

Quoted 21 lines · Rob Herring

Quoted 20 lines

Quoted 5 lines

arch/arm/mach-highbank/sysregs.h new file +5 -0

+#ifndef _MACH_HIGHBANK__SYSREGS_H_
+#define _MACH_HIGHBANK__SYSREGS_H_
+
+extern void __iomem *sregs_base;
+

arch/arm/mach-highbank/sysregs.h line 30

Quoted 10 lines

arch/arm/mach-highbank/sysregs.h new file +10 -0

+#define HB_SREG_A9_PWR_REQ          0xf00
+#define HB_SREG_A9_BOOT_STAT                0xf04
+#define HB_SREG_A9_BOOT_DATA                0xf08
+
+#define HB_PWR_SUSPEND                      0
+#define HB_PWR_SOFT_RESET           1
+#define HB_PWR_HARD_RESET           2
+#define HB_PWR_SHUTDOWN                     3
+
+#endif

Do these really need to be global?

I think it's better to put the base address and register definitions into a single file and export functions to be used from elsewhere.

Quoted 3 lines

Yes, sregs are a random collection of functions, so it's going to be a mixture of various users. Just HB_PWR_* alone are in 2 or 3 different places.

Sorry, I'm not following.

Do you mean 'yes, they need to be global' or 'yes, it's better to export the functions'?

Quoted 4 lines

Do you mean 'yes, they need to be global' or 'yes, it's better to export the functions'?

I meant the former and functions as in h/w functionality, not C functions.

This will mainly be clock control plus a few other things. Is it really desired to add another layer here when these are all just single register writes?

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 arch/arm/Kconfig                                  |   17 ++
 arch/arm/Makefile                                 |    1 +
 arch/arm/mach-highbank/Makefile                   |    1 +
 arch/arm/mach-highbank/Makefile.boot              |    1 +
 arch/arm/mach-highbank/clock.c                    |   63 ++++++++
 arch/arm/mach-highbank/core.h                     |    3 +
 arch/arm/mach-highbank/highbank.c                 |  164 +++++++++++++++++++++
 arch/arm/mach-highbank/include/mach/debug-macro.S |   20 +++
 arch/arm/mach-highbank/include/mach/entry-macro.S |    9 +
 arch/arm/mach-highbank/include/mach/gpio.h        |    1 +
 arch/arm/mach-highbank/include/mach/io.h          |    8 +
 arch/arm/mach-highbank/include/mach/irqs.h        |    6 +
 arch/arm/mach-highbank/include/mach/memory.h      |    1 +
 arch/arm/mach-highbank/include/mach/system.h      |   26 ++++
 arch/arm/mach-highbank/include/mach/timex.h       |    6 +
 arch/arm/mach-highbank/include/mach/uncompress.h  |    9 +
 arch/arm/mach-highbank/include/mach/vmalloc.h     |    6 +
 arch/arm/mach-highbank/sysregs.h                  |   30 ++++
 arch/arm/mach-highbank/system.c                   |   33 ++++
 arch/arm/mm/Kconfig                               |    2 +-
 20 files changed, 406 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-highbank/Makefile
 create mode 100644 arch/arm/mach-highbank/Makefile.boot
 create mode 100644 arch/arm/mach-highbank/clock.c
 create mode 100644 arch/arm/mach-highbank/core.h
 create mode 100644 arch/arm/mach-highbank/highbank.c
 create mode 100644 arch/arm/mach-highbank/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-highbank/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-highbank/include/mach/gpio.h
 create mode 100644 arch/arm/mach-highbank/include/mach/io.h
 create mode 100644 arch/arm/mach-highbank/include/mach/irqs.h
 create mode 100644 arch/arm/mach-highbank/include/mach/memory.h
 create mode 100644 arch/arm/mach-highbank/include/mach/system.h
 create mode 100644 arch/arm/mach-highbank/include/mach/timex.h
 create mode 100644 arch/arm/mach-highbank/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-highbank/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-highbank/sysregs.h
 create mode 100644 arch/arm/mach-highbank/system.c

arch/arm/Kconfig +17 -0

index 5ebc5d9..eecee3d 100644
@@ -318,6 +318,23 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
+config ARCH_HIGHBANK
+	bool "Calxeda Highbank-based"
+	select CPU_V7
+	select AUTO_ZRELADDR
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_GIC
+	select HAVE_ARM_SCU
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select PL330
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select USE_OF
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	help
+	  Support for the Calxeda Highbank SoC based boards.
+
 config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x-based"
 	select CPU_ARM720T

arch/arm/Makefile +1 -0

index 70c424e..451097e 100644
@@ -141,6 +141,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
 machine-$(CONFIG_ARCH_H720X)		:= h720x
+machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x

arch/arm/mach-highbank/Makefile new file +1 -0

new file mode 100644
index 0000000..b5de3b9
@@ -0,0 +1 @@
+obj-y					:= clock.o highbank.o system.o

arch/arm/mach-highbank/Makefile.boot new file +1 -0

new file mode 100644
index 0000000..dae9661
@@ -0,0 +1 @@
+zreladdr-y	:= 0x00008000

arch/arm/mach-highbank/clock.c new file +63 -0

new file mode 100644
index 0000000..8464e14
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+
+
+struct clk {
+	unsigned long rate;
+};
+
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+void clk_disable(struct clk *clk)
+{}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	return clk->rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	return 0;
+}
+
+static struct clk eclk = { .rate = 200000000 };
+static struct clk pclk = { .rate = 150000000 };
+
+static struct clk_lookup lookups[] = {
+	{ .clk = &pclk, .con_id = "apb_pclk", },
+	{ .clk = &pclk, .dev_id = "sp804", },
+	{ .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
+	{ .clk = &pclk, .dev_id = "fff36000.serial", },
+};
+
+void __init highbank_clocks_init(void)
+{
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}

arch/arm/mach-highbank/core.h new file +3 -0

new file mode 100644
index 0000000..b5aa45f
@@ -0,0 +1,3 @@
+extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
+extern void __iomem *a9_base_addr;
+extern void highbank_clocks_init(void);

arch/arm/mach-highbank/highbank.c new file +66 -0

new file mode 100644
index 0000000..49bbd13
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/unified.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+
+#include "core.h"
+#include "sysregs.h"
+
+#define HB_DEBUG_LL_PHYS_BASE	0xfff36000
+
+/* Static virtual mappings */
+#define HB_DEBUG_LL_VIRT_BASE	0xfee36000
+#define HB_MPIC_VIRT_BASE	0xfee00000
+
+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+
+static void __init highbank_map_io(void)

Quoted 5 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

Quoted 8 lines

arch/arm/mach-highbank/highbank.c new file +8 -0

+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);

arch/arm/mach-highbank/highbank.c line 76

Quoted 3 lines

arch/arm/mach-highbank/highbank.c new file +3 -0

+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}
+

It's a great demo that we can get this base address from CA9 itself. However I'm wondering if we have to do so, since this address should be known for given SoC. Can we put this known base into device tree and map it when needed? In that case, we can save another static mapping.

Quoted 6 lines · Shawn Guo

Quoted 5 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

[...]

Quoted 8 lines

Quoted 8 lines

arch/arm/mach-highbank/highbank.c new file +8 -0

+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);

Quoted 9 lines

arch/arm/mach-highbank/highbank.c line 76

Quoted 3 lines

arch/arm/mach-highbank/highbank.c new file +3 -0

+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}
+

It's a great demo that we can get this base address from CA9 itself. However I'm wondering if we have to do so, since this address should be known for given SoC. Can we put this known base into device tree and map it when needed? In that case, we can save another static mapping.

Hmm, if CA9 can figure this address out by itself, why do not we create a init hook in arch/arm/kernel/smp_scu.c to have scu code to get and map the address? Then the parameter "scu_base" in those scu helper functions can be saved.

Quoted 256 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---
 arch/arm/Kconfig                                  |   17 ++
 arch/arm/Makefile                                 |    1 +
 arch/arm/mach-highbank/Makefile                   |    1 +
 arch/arm/mach-highbank/Makefile.boot              |    1 +
 arch/arm/mach-highbank/clock.c                    |   63 ++++++++
 arch/arm/mach-highbank/core.h                     |    3 +
 arch/arm/mach-highbank/highbank.c                 |  164 +++++++++++++++++++++
 arch/arm/mach-highbank/include/mach/debug-macro.S |   20 +++
 arch/arm/mach-highbank/include/mach/entry-macro.S |    9 +
 arch/arm/mach-highbank/include/mach/gpio.h        |    1 +
 arch/arm/mach-highbank/include/mach/io.h          |    8 +
 arch/arm/mach-highbank/include/mach/irqs.h        |    6 +
 arch/arm/mach-highbank/include/mach/memory.h      |    1 +
 arch/arm/mach-highbank/include/mach/system.h      |   26 ++++
 arch/arm/mach-highbank/include/mach/timex.h       |    6 +
 arch/arm/mach-highbank/include/mach/uncompress.h  |    9 +
 arch/arm/mach-highbank/include/mach/vmalloc.h     |    6 +
 arch/arm/mach-highbank/sysregs.h                  |   30 ++++
 arch/arm/mach-highbank/system.c                   |   33 ++++
 arch/arm/mm/Kconfig                               |    2 +-
 20 files changed, 406 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/mach-highbank/Makefile
 create mode 100644 arch/arm/mach-highbank/Makefile.boot
 create mode 100644 arch/arm/mach-highbank/clock.c
 create mode 100644 arch/arm/mach-highbank/core.h
 create mode 100644 arch/arm/mach-highbank/highbank.c
 create mode 100644 arch/arm/mach-highbank/include/mach/debug-macro.S
 create mode 100644 arch/arm/mach-highbank/include/mach/entry-macro.S
 create mode 100644 arch/arm/mach-highbank/include/mach/gpio.h
 create mode 100644 arch/arm/mach-highbank/include/mach/io.h
 create mode 100644 arch/arm/mach-highbank/include/mach/irqs.h
 create mode 100644 arch/arm/mach-highbank/include/mach/memory.h
 create mode 100644 arch/arm/mach-highbank/include/mach/system.h
 create mode 100644 arch/arm/mach-highbank/include/mach/timex.h
 create mode 100644 arch/arm/mach-highbank/include/mach/uncompress.h
 create mode 100644 arch/arm/mach-highbank/include/mach/vmalloc.h
 create mode 100644 arch/arm/mach-highbank/sysregs.h
 create mode 100644 arch/arm/mach-highbank/system.c

arch/arm/Kconfig +17 -0

index 5ebc5d9..eecee3d 100644
@@ -318,6 +318,23 @@ config ARCH_BCMRING
 	help
 	  Support for Broadcom's BCMRing platform.
 
+config ARCH_HIGHBANK
+	bool "Calxeda Highbank-based"
+	select CPU_V7
+	select AUTO_ZRELADDR
+	select ARM_PATCH_PHYS_VIRT
+	select ARM_GIC
+	select HAVE_ARM_SCU
+	select ARM_AMBA
+	select ARM_TIMER_SP804
+	select PL330
+	select CLKDEV_LOOKUP
+	select GENERIC_CLOCKEVENTS
+	select USE_OF
+	select ARCH_WANT_OPTIONAL_GPIOLIB
+	help
+	  Support for the Calxeda Highbank SoC based boards.
+
 config ARCH_CLPS711X
 	bool "Cirrus Logic CLPS711x/EP721x-based"
 	select CPU_ARM720T

arch/arm/Makefile +1 -0

index 70c424e..451097e 100644
@@ -141,6 +141,7 @@ machine-$(CONFIG_ARCH_EBSA110)		:= ebsa110
 machine-$(CONFIG_ARCH_EP93XX)		:= ep93xx
 machine-$(CONFIG_ARCH_GEMINI)		:= gemini
 machine-$(CONFIG_ARCH_H720X)		:= h720x
+machine-$(CONFIG_ARCH_HIGHBANK)		:= highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)	:= integrator
 machine-$(CONFIG_ARCH_IOP13XX)		:= iop13xx
 machine-$(CONFIG_ARCH_IOP32X)		:= iop32x

arch/arm/mach-highbank/Makefile new file +1 -0

new file mode 100644
index 0000000..b5de3b9
@@ -0,0 +1 @@
+obj-y					:= clock.o highbank.o system.o

arch/arm/mach-highbank/Makefile.boot new file +1 -0

new file mode 100644
index 0000000..dae9661
@@ -0,0 +1 @@
+zreladdr-y	:= 0x00008000

arch/arm/mach-highbank/clock.c new file +63 -0

new file mode 100644
index 0000000..8464e14
@@ -0,0 +1,63 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+
+
+struct clk {
+	unsigned long rate;
+};
+
+int clk_enable(struct clk *clk)
+{
+	return 0;
+}
+
+void clk_disable(struct clk *clk)
+{}
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+	return clk->rate;
+}
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+	return clk->rate;
+}
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	return 0;
+}
+
+static struct clk eclk = { .rate = 200000000 };
+static struct clk pclk = { .rate = 150000000 };
+
+static struct clk_lookup lookups[] = {
+	{ .clk = &pclk, .con_id = "apb_pclk", },
+	{ .clk = &pclk, .dev_id = "sp804", },
+	{ .clk = &eclk, .dev_id = "ffe0e000.sdhci", },
+	{ .clk = &pclk, .dev_id = "fff36000.serial", },
+};
+
+void __init highbank_clocks_init(void)
+{
+	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}

arch/arm/mach-highbank/core.h new file +3 -0

new file mode 100644
index 0000000..b5aa45f
@@ -0,0 +1,3 @@
+extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
+extern void __iomem *a9_base_addr;
+extern void highbank_clocks_init(void);

arch/arm/mach-highbank/highbank.c new file +73 -0

new file mode 100644
index 0000000..49bbd13
@@ -0,0 +1,164 @@
+/*
+ * Copyright 2010-2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+
+#include <asm/cacheflush.h>
+#include <asm/unified.h>
+#include <asm/smp_scu.h>
+#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+#include <mach/irqs.h>
+
+#include "core.h"
+#include "sysregs.h"
+
+#define HB_DEBUG_LL_PHYS_BASE	0xfff36000
+
+/* Static virtual mappings */
+#define HB_DEBUG_LL_VIRT_BASE	0xfee36000
+#define HB_MPIC_VIRT_BASE	0xfee00000
+
+void __iomem *a9_base_addr = ((void __iomem *)(HB_MPIC_VIRT_BASE));
+void __iomem *sregs_base;
+
+static struct map_desc highbank_io_desc[] __initdata = {
+	{
+		.virtual	= HB_MPIC_VIRT_BASE,
+		.pfn		= 0, /* run-time */
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#ifdef CONFIG_DEBUG_LL
+	{
+		.virtual	= HB_DEBUG_LL_VIRT_BASE,
+		.pfn		= __phys_to_pfn(HB_DEBUG_LL_PHYS_BASE),
+		.length		= SZ_4K,
+		.type		= MT_DEVICE,
+	},
+#endif
+};
+
+static void __init highbank_map_io(void)
+{
+	unsigned long base;
+
+	/* Get SCU base */
+	asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+	highbank_io_desc[0].pfn = __phys_to_pfn(base);

arch/arm/mach-highbank/highbank.c line 76

Quoted 3 lines

arch/arm/mach-highbank/highbank.c new file +3 -0

+	iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}
+

It's a great demo that we can get this base address from CA9 itself. However I'm wondering if we have to do so, since this address should be known for given SoC. Can we put this known base into device tree and map it when needed? In that case, we can save another static mapping.

Quoted 8 lines

Quoted 8 lines

arch/arm/mach-highbank/highbank.c new file +8 -0

+static void __init highbank_map_io(void)
+{
+   unsigned long base;
+
+   /* Get SCU base */
+   asm("mrc p15, 4, %0, c15, c0, 0" : "=r" (base));
+
+   highbank_io_desc[0].pfn = __phys_to_pfn(base);

Quoted 8 lines

arch/arm/mach-highbank/highbank.c line 76

Quoted 3 lines

arch/arm/mach-highbank/highbank.c new file +3 -0

+   iotable_init(highbank_io_desc, ARRAY_SIZE(highbank_io_desc));
+}
+

It's a great demo that we can get this base address from CA9 itself. However I'm wondering if we have to do so, since this address should be known for given SoC. Can we put this known base into device tree and map it when needed? In that case, we can save another static mapping.

Since device tree is mainly about providing data to describe system components that are not discoverable, maybe it is better after all not to put this address in the device tree.

Discovery feels like the best approach, where possible.

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

arch/arm/mach-highbank/highbank.c new file +9 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);

arch/arm/mach-highbank/highbank.c new file +5 -0

+#ifdef CONFIG_CACHE_L2X0
+	l2x0_of_init(0, ~0UL);
+#endif
+}
+

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

Quoted 14 lines

arch/arm/mach-highbank/highbank.c new file +14 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);
+	}
+

arch/arm/mach-highbank/highbank.c line 106

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +5 -0

+	for_each_compatible_node(node, NULL, "arm,pl061") {
+		irq_domain_add_simple(node, 160 + (8 * n));
+		n++;
+	}
+

160, magic number? I guess it's the GIC IRQ number has been discovered in gic_dist_init(). I'm not sure if we should simply define a macro for it or manage to retrieve it from GIC.

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

arch/arm/mach-highbank/highbank.c new file +13 -0

+
+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;
+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

arch/arm/mach-highbank/highbank.c new file +4 -0

+	.timer		= &highbank_timer,
+	.init_machine	= highbank_init,
+	.dt_compat	= highbank_match,
+MACHINE_END

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

arch/arm/mach-highbank/highbank.c line 160

Quoted 4 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+DT_MACHINE_START(HIGHBANK, "Highbank")
+	.map_io		= highbank_map_io,
+	.init_irq	= highbank_init_irq,
+	.nr_irqs	= NR_IRQS,

Is it really needed?

Quoted 5 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+	.timer		= &highbank_timer,
+	.init_machine	= highbank_init,
+	.dt_compat	= highbank_match,
+MACHINE_END

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

arch/arm/mach-highbank/include/mach/entry-macro.S new file +7 -0

+
+	.macro	disable_fiq
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

arch/arm/mach-highbank/include/mach/entry-macro.S line 2

Quoted 8 lines

arch/arm/mach-highbank/include/mach/entry-macro.S new file +2 -0

new file mode 100644
index 0000000..56be409
@@ -0,0 +1,9 @@
+#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>

It seems that the second file already includes the first one.

Hi Shawn,

Quoted 8 lines · Shawn Guo

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

Quoted 10 lines

arch/arm/mach-highbank/include/mach/entry-macro.S line 2

Quoted 8 lines

arch/arm/mach-highbank/include/mach/entry-macro.S new file +2 -0

new file mode 100644
index 0000000..56be409
@@ -0,0 +1,9 @@
+#include <asm/hardware/gic.h>
+#include <asm/hardware/entry-macro-gic.S>

It seems that the second file already includes the first one.

It's preferred to use explicit includes. From
Documentation/SubmitChecklist:

1: If you use a facility then #include the file that
defines/declares that facility. Don't depend on other header files pulling in ones that you use.

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

arch/arm/mach-highbank/highbank.c new file +4 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

Quoted 4 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;

arch/arm/mach-highbank/highbank.c line 101

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);
+	}
+

I failed to find the implementation of gic_of_ppi_init() in your patch series below.

[RFC PATCH 0/3] Yet another GIC OF binding series

Also one nit: the braces seem redundant.

Quoted 6 lines · Rob Herring

From: Rob Herring <[email protected]>

This adds basic support for the Calxeda Highbank platform.

Signed-off-by Rob Herring <[email protected]>

---

[...]

Quoted 4 lines

arch/arm/mach-highbank/highbank.c new file +4 -0

+void highbank_init_irq(void)
+{
+	struct device_node *node;
+	struct of_intc_desc desc;

arch/arm/mach-highbank/highbank.c line 101

Quoted 10 lines

arch/arm/mach-highbank/highbank.c new file +10 -0

+	int n = 0;
+
+	memset(&desc, 0, sizeof(desc));
+	desc.controller = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+	gic_of_init(&desc);
+	node = desc.controller;
+	for_each_child_of_node(node, desc.controller) {
+		gic_of_ppi_init(&desc);
+	}
+

I failed to find the implementation of gic_of_ppi_init() in your patch series below.

[RFC PATCH 0/3] Yet another GIC OF binding series

Also one nit: the braces seem redundant.

arch/arm/mach-highbank/platsmp.c line 35

Quoted 3 lines · Rob Herring

arch/arm/mach-highbank/platsmp.c new file +3 -0

+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	gic_raise_softirq(cpumask_of(cpu), 1);

Can this raise IPI0 instead of IPI1 ?

arch/arm/mach-highbank/platsmp.c line 48

Quoted 6 lines

arch/arm/mach-highbank/platsmp.c new file +6 -0

+void __init smp_init_cpus(void)
+{
+	void __iomem *scu_base = a9_base_addr;
+	unsigned int i, ncores;
+
+	ncores = scu_base ? scu_get_core_count(scu_base) : 1;

Is scu_base ever NULL?

Quoted 9 lines · Russell King - ARM Linux

arch/arm/mach-highbank/platsmp.c line 48

Quoted 6 lines · Rob Herring

arch/arm/mach-highbank/platsmp.c new file +6 -0

+void __init smp_init_cpus(void)
+{
+	void __iomem *scu_base = a9_base_addr;
+	unsigned int i, ncores;
+
+	ncores = scu_base ? scu_get_core_count(scu_base) : 1;

Is scu_base ever NULL?

Only if something is wrong and the mapping did not get setup. The system should still boot with 1 core without accessing the the SCU in this case.

This BTW is the only reason we need a static mapping of the SCU. So I could just hard code it or use device tree to get the number of cores and eliminate the static mapping.

From: Rob Herring <[email protected]>

Add the platform suspend ops for highbank.

Signed-off-by Rob Herring <[email protected]>

---
 arch/arm/mach-highbank/Makefile |    1 +
 arch/arm/mach-highbank/pm.c     |   55 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 56 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-highbank/pm.c

arch/arm/mach-highbank/Makefile +1 -0

index b8d5d40..2cd4a1b 100644
@@ -2,3 +2,4 @@ obj-y					:= clock.o highbank.o system.o
 obj-$(CONFIG_SMP)			+= platsmp.o
 obj-$(CONFIG_LOCAL_TIMERS)		+= localtimer.o
 obj-$(CONFIG_HOTPLUG_CPU)		+= hotplug.o
+obj-$(CONFIG_PM_SLEEP)			+= pm.o

arch/arm/mach-highbank/pm.c new file +40 -0

new file mode 100644
index 0000000..36c88df
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2011 Calxeda, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/suspend.h>
+
+#include <asm/proc-fns.h>
+#include <asm/smp_scu.h>
+#include <asm/suspend.h>
+
+#include "core.h"
+#include "sysregs.h"
+
+static int highbank_suspend_finish(unsigned long val)
+{
+	cpu_do_idle();
+	return 0;
+}
+
+static int highbank_pm_enter(suspend_state_t state)
+{
+	writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
+	highbank_set_cpu_jump(0, cpu_resume);
+
+	scu_power_mode(a9_base_addr, SCU_PM_POWEROFF);
+	cpu_suspend(0, highbank_suspend_finish);

arch/arm/mach-highbank/pm.c new file +5 -0

+{
+	suspend_set_ops(&highbank_pm_ops);
+	return 0;
+}
+module_init(highbank_pm_init);

Signature · 1 line

1.7.4.1