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Add Cadence GEM support to macb Ethernet driver

PATCH Superseded Dave Aldridge 3 participants 8 messages Aug 18, 2011 – Oct 6, 2011 Network drivers

v1 of 2 Superseded Latest is v2 →

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Dave Aldridge

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#0 lore raw

cover Add Cadence GEM support to macb Ethernet driver

The Cadence GEM Ethernet MAC is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement.

This patch set implements the changes required in order for the macb driver to support Cadence GEM as well.

These changes have been tested on a Picochip picoXcell based development platform.

Dave Aldridge (4):
macb: initial support for Cadence GEM
macb: support higher rate GEM MDIO clock divisors
macb: support DMA bus widths > 32 bits
macb: allow GEM to have configurable receive buffer size

 drivers/net/macb.c |  119 +++++++++++++++++++++++++++++++++++++++++++---------
 drivers/net/macb.h |   90 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 189 insertions(+), 20 deletions(-)
Signature · 1 line
1.7.3.4
author
#1 lore raw

PATCH 1/4 macb: initial support for Cadence GEM

The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.

This handles the new HW address, USRIO and hash register base register locations in GEM.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   18 +++++++++++-----
 drivers/net/macb.h |   55 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+), 6 deletions(-)
drivers/net/macb.c +12 -6
index c63eea9..d52dda0 100644
@@ -88,6 +88,7 @@ struct macb_dma_desc {
 
 struct macb_device {
 	void			*regs;
+        int                     is_gem;
 
 	unsigned int		rx_tail;
 	unsigned int		tx_head;

@@ -473,18 +474,19 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 	defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
 	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
 	defined(CONFIG_AT91SAM9XE)
-	macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN));
+	macb_or_gem_writel(macb, USRIO, (MACB_BIT(RMII) |
+				         MACB_BIT(CLKEN)));
 #else
-	macb_writel(macb, USRIO, 0);
+	macb_or_gem_writel(macb, USRIO, 0);
 #endif
 #else
 #if	defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \
 	defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \
 	defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \
 	defined(CONFIG_AT91SAM9XE)
-	macb_writel(macb, USRIO, MACB_BIT(CLKEN));
+	macb_or_gem_writel(macb, USRIO, MACB_BIT(CLKEN));
 #else
-	macb_writel(macb, USRIO, MACB_BIT(MII));
+	macb_or_gem_writel(macb, USRIO, MACB_BIT(MII));
 #endif
 #endif /* CONFIG_RMII */
 

@@ -524,9 +526,9 @@ static int macb_write_hwaddr(struct eth_device *dev)
 	/* set hardware address */
 	hwaddr_bottom = dev->enetaddr[0] | dev->enetaddr[1] << 8 |
 			dev->enetaddr[2] << 16 | dev->enetaddr[3] << 24;
-	macb_writel(macb, SA1B, hwaddr_bottom);
+	macb_or_gem_writel(macb, SA1B, hwaddr_bottom);
 	hwaddr_top = dev->enetaddr[4] | dev->enetaddr[5] << 8;
-	macb_writel(macb, SA1T, hwaddr_top);
+	macb_or_gem_writel(macb, SA1T, hwaddr_top);
 	return 0;
 }
 

@@ -581,6 +583,10 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
 	macb_writel(macb, NCFGR, ncfgr);
 
+	/* Cadence GEM has a module ID of 2. */
+	if (MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2)
+		macb->is_gem = 1;
+
 	eth_register(netdev);
 
 #if defined(CONFIG_CMD_MII)
drivers/net/macb.h +55 -0

77 lines not on this page · raw message

Signature · 1 line
1.7.3.4
#2 lore raw

PATCH 1/4 macb: initial support for Cadence GEM

Dear Dave Aldrige,

Am 18.08.2011 15:32, schrieb Dave Aldridge:

Quoted 19 lines

The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.

This handles the new HW address, USRIO and hash register base register locations in GEM.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   18 +++++++++++-----
 drivers/net/macb.h |   55 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+), 6 deletions(-)
drivers/net/macb.c +0 -0
index c63eea9..d52dda0 100644

drivers/net/macb.c struct macb_dma_desc { · line 91

Quoted 4 lines
drivers/net/macb.c +1 -0
@@ -88,6 +88,7 @@ struct macb_dma_desc {
 
 struct macb_device {
 	void			*regs;
+        int                     is_gem;

is it required to have a runtime distinction here?
I mean is it possible to have a Cadence GEM type and a old style MACB type of HW on the same device?
If not I would prefer a compile time differentiation here to avoid the macb_or_gem_(read|write) macros (but lets wait for some comments from the custodians)

regards

Andreas Bie?mann

author
#3 lore raw

PATCH 1/4 macb: initial support for Cadence GEM

Quoted 34 lines · Andreas Bie?mann

Dear Dave Aldrige,

Am 18.08.2011 15:32, schrieb Dave Aldridge:

Quoted 19 lines

The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.

This handles the new HW address, USRIO and hash register base register locations in GEM.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   18 +++++++++++-----
 drivers/net/macb.h |   55 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+), 6 deletions(-)
drivers/net/macb.c +0 -0
index c63eea9..d52dda0 100644

drivers/net/macb.c struct macb_dma_desc { · line 91

Quoted 4 lines
drivers/net/macb.c +1 -0
@@ -88,6 +88,7 @@ struct macb_dma_desc {
 
 struct macb_device {
 	void			*regs;
+        int                     is_gem;

is it required to have a runtime distinction here?
I mean is it possible to have a Cadence GEM type and a old style MACB type of HW on the same device?
If not I would prefer a compile time differentiation here to avoid the macb_or_gem_(read|write) macros (but lets wait for some comments from the custodians)

Quoted 3 lines

regards

Andreas Bie?mann

You would either have a macb or a gem implementation (don't think it makes sense to have both types of mac in the same SoC). However at the programmers model level the differences between the two are actually quite small that is the reason for sorting out the differences at run time rather than compile time.

Thanks for adding to the cc list. I did do a trawl before submitting this patch set but was unsure who the most appropriate people were.

Cheers

Dave

#4 lore raw

PATCH 1/4 macb: initial support for Cadence GEM

In reply to Dave Aldridge

Dear Dave Aldridge,

Quoted 5 lines · In message <[email protected]> you wrote:

The Cadence GEM is based on the MACB Ethernet controller but has a few small changes with regards to register and bitfield placement. This patch detects the presence of a GEM by reading the module ID register and setting a flag appropriately.

Quoted 8 lines

This handles the new HW address, USRIO and hash register base register locations in GEM.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   18 +++++++++++-----
 drivers/net/macb.h |   55 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 67 insertions(+), 6 deletions(-)

Checkpatch says:

total: 2 errors, 1 warnings, 128 lines checked

Please clean up and resubmit. Thanks.

Best regards,

Wolfgang Denk

Signature · 5 lines
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
No one wants war.
	-- Kirk, "Errand of Mercy", stardate 3201.7
author
#5 lore raw

PATCH 2/4 macb: support higher rate GEM MDIO clock divisors

In reply to Dave Aldridge

GEM devices support larger clock divisors and have a different range of divisors. Program the MDIO clock divisors based on the device type.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   63 ++++++++++++++++++++++++++++++++++++++--------------
 drivers/net/macb.h |   12 ++++++++++
 2 files changed, 58 insertions(+), 17 deletions(-)
drivers/net/macb.c +46 -17
index d52dda0..fd99cdb 100644
@@ -532,11 +532,52 @@ static int macb_write_hwaddr(struct eth_device *dev)
 	return 0;
 }
 
+static u32 gem_mdc_clk_div(int id)
+{
+	u32 ncfgr;
+	unsigned long pclk_hz = get_macb_pclk_rate(id);
+
+	if (pclk_hz <= 20000000)
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV8);
+	else if (pclk_hz <= 40000000)
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV16);
+	else if (pclk_hz <= 80000000)
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV32);
+	else if (pclk_hz <= 120000000)
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV48);
+	else if (pclk_hz <= 160000000)
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV64);
+	else
+		ncfgr = GEM_BF(CLK, GEM_CLK_DIV96);
+
+	return ncfgr;
+}
+
+static u32 macb_mdc_clk_div(struct macb_device *macb, int id)
+{
+	u32 ncfgr;
+	unsigned long pclk_hz;
+
+	if (macb->is_gem)
+		return gem_mdc_clk_div(id);
+
+	pclk_hz = get_macb_pclk_rate(id);
+	if (pclk_hz <= 20000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
+	else if (pclk_hz <= 40000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
+	else if (pclk_hz <= 80000000)
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
+	else
+		ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
+
+	return ncfgr;
+}
+
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 {
 	struct macb_device *macb;
 	struct eth_device *netdev;
-	unsigned long macb_hz;
 	u32 ncfgr;
 
 	macb = malloc(sizeof(struct macb_device));

@@ -567,26 +608,14 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 	netdev->recv = macb_recv;
 	netdev->write_hwaddr = macb_write_hwaddr;
 
-	/*
-	 * Do some basic initialization so that we at least can talk
-	 * to the PHY
-	 */
-	macb_hz = get_macb_pclk_rate(id);
-	if (macb_hz < 20000000)
-		ncfgr = MACB_BF(CLK, MACB_CLK_DIV8);
-	else if (macb_hz < 40000000)
-		ncfgr = MACB_BF(CLK, MACB_CLK_DIV16);
-	else if (macb_hz < 80000000)
-		ncfgr = MACB_BF(CLK, MACB_CLK_DIV32);
-	else
-		ncfgr = MACB_BF(CLK, MACB_CLK_DIV64);
-
-	macb_writel(macb, NCFGR, ncfgr);
-
 	/* Cadence GEM has a module ID of 2. */
 	if (MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2)
 		macb->is_gem = 1;
 
+	/* Set MII management clock divider */
+	ncfgr = macb_mdc_clk_div(macb, id);
+	macb_writel(macb, NCFGR, ncfgr);
+
 	eth_register(netdev);
 
 #if defined(CONFIG_CMD_MII)
drivers/net/macb.h +12 -0
index a2913f2..b08a057 100644
@@ -147,6 +147,10 @@
 #define MACB_IRXFCS_OFFSET			19
 #define MACB_IRXFCS_SIZE			1
 
+/* GEM specific NCFGR bitfields. */
+#define GEM_CLK_OFFSET				18
+#define GEM_CLK_SIZE				3
+
 /* Bitfields in NSR */
 #define MACB_NSR_LINK_OFFSET			0
 #define MACB_NSR_LINK_SIZE			1

@@ -261,6 +265,14 @@
 #define MACB_CLK_DIV32				2
 #define MACB_CLK_DIV64				3
 
+/* GEM specific constants for CLK. */
+#define GEM_CLK_DIV8				0
+#define GEM_CLK_DIV16				1
+#define GEM_CLK_DIV32				2
+#define GEM_CLK_DIV48				3
+#define GEM_CLK_DIV64				4
+#define GEM_CLK_DIV96				5
+
 /* Constants for MAN register */
 #define MACB_MAN_SOF				1
 #define MACB_MAN_WRITE				1
Signature · 1 line
1.7.3.4
author
#6 lore raw

PATCH 3/4 macb: support DMA bus widths > 32 bits

In reply to Dave Aldridge

Some GEM implementations may support DMA bus widths up to 128 bits. We can get the maximum supported DMA bus width from the design configuration register so use that to program the device up.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   25 +++++++++++++++++++++++++
 drivers/net/macb.h |   18 ++++++++++++++++++
 2 files changed, 43 insertions(+), 0 deletions(-)
drivers/net/macb.c +25 -0
index fd99cdb..41f1dce 100644
@@ -574,6 +574,27 @@ static u32 macb_mdc_clk_div(struct macb_device *macb, int id)
 	return ncfgr;
 }
 
+/*
+ * Get the DMA bus width field of the network configuration register that we
+ * should program.  We find the width from decoding the design configuration
+ * register to find the maximum supported data bus width.
+ */
+static u32 macb_dbw(struct macb_device *macb)
+{
+	if (!macb->is_gem)
+		return 0;
+
+	switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) {
+	case 4:
+		return GEM_BF(DBW, GEM_DBW128);
+	case 2:
+		return GEM_BF(DBW, GEM_DBW64);
+	case 1:
+	default:
+		return GEM_BF(DBW, GEM_DBW32);
+	}
+}
+
 int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 {
 	struct macb_device *macb;

@@ -614,6 +635,10 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr)
 
 	/* Set MII management clock divider */
 	ncfgr = macb_mdc_clk_div(macb, id);
+
+	/* Set up the DMA bus width */
+	ncfgr |= macb_dbw(macb);
+
 	macb_writel(macb, NCFGR, ncfgr);
 
 	eth_register(netdev);
drivers/net/macb.h +18 -0
index b08a057..c0759cf 100644
@@ -80,6 +80,13 @@
 #define GEM_HRT					0x0084
 #define GEM_SA1B				0x0088
 #define GEM_SA1T				0x008C
+#define GEM_DCFG1				0x0280
+#define GEM_DCFG2				0x0284
+#define GEM_DCFG3				0x0288
+#define GEM_DCFG4				0x028c
+#define GEM_DCFG5				0x0290
+#define GEM_DCFG6				0x0294
+#define GEM_DCFG7				0x0298
 
 /* Bitfields in NCR */
 #define MACB_LB_OFFSET				0

@@ -150,6 +157,13 @@
 /* GEM specific NCFGR bitfields. */
 #define GEM_CLK_OFFSET				18
 #define GEM_CLK_SIZE				3
+#define GEM_DBW_OFFSET				21
+#define GEM_DBW_SIZE				2
+
+/* Constants for data bus width. */
+#define GEM_DBW32				0
+#define GEM_DBW64				1
+#define GEM_DBW128				2
 
 /* Bitfields in NSR */
 #define MACB_NSR_LINK_OFFSET			0

@@ -259,6 +273,10 @@
 #define MACB_REV_OFFSET				0
 #define MACB_REV_SIZE				16
 
+/* Bitfields in DCFG1. */
+#define GEM_DBWDEF_OFFSET			25
+#define GEM_DBWDEF_SIZE				3
+
 /* Constants for CLK */
 #define MACB_CLK_DIV8				0
 #define MACB_CLK_DIV16				1
Signature · 1 line
1.7.3.4
author
#7 lore raw

PATCH 4/4 macb: allow GEM to have configurable receive buffer size

In reply to Dave Aldridge

GEM has configurable receive buffer sizes so requires this to be programmed up.

Signed-off-by Dave Aldridge <[email protected]>
---
 drivers/net/macb.c |   19 +++++++++++++++++++
 drivers/net/macb.h |    5 +++++
 2 files changed, 24 insertions(+), 0 deletions(-)
drivers/net/macb.c +19 -0
index 41f1dce..4d21f14 100644
@@ -436,6 +436,23 @@ static int macb_phy_init(struct macb_device *macb)
 	}
 }
 
+/*
+ * Configure the receive DMA engine to use the correct receive buffer size.
+ * This is a configurable parameter for GEM.
+ */
+static void macb_configure_dma(struct macb_device *macb)
+{
+	u32 dmacfg;
+	u32 rx_ring_buf_size = CONFIG_SYS_MACB_RX_BUFFER_SIZE /
+			       CONFIG_SYS_MACB_RX_RING_SIZE;
+
+	if (macb->is_gem) {
+		dmacfg = gem_readl(macb, DMACFG) & ~GEM_BF(RXBS, -1L);
+		dmacfg |= GEM_BF(RXBS, rx_ring_buf_size / 64);
+		gem_writel(macb, DMACFG, dmacfg);
+	}
+}
+
 static int macb_init(struct eth_device *netdev, bd_t *bd)
 {
 	struct macb_device *macb = to_macb(netdev);

@@ -465,6 +482,8 @@ static int macb_init(struct eth_device *netdev, bd_t *bd)
 	}
 	macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
 
+	macb_configure_dma(macb);
+
 	macb_writel(macb, RBQP, macb->rx_ring_dma);
 	macb_writel(macb, TBQP, macb->tx_ring_dma);
drivers/net/macb.h +5 -0
index c0759cf..e0fbd46 100644
@@ -76,6 +76,7 @@
 /* GEM register offsets. */
 #define GEM_NCFGR				0x0004
 #define GEM_USRIO				0x000c
+#define GEM_DMACFG				0x0010
 #define GEM_HRB					0x0080
 #define GEM_HRT					0x0084
 #define GEM_SA1B				0x0088

@@ -165,6 +166,10 @@
 #define GEM_DBW64				1
 #define GEM_DBW128				2
 
+/* Bitfields in DMACFG. */
+#define GEM_RXBS_OFFSET				16
+#define GEM_RXBS_SIZE				8
+
 /* Bitfields in NSR */
 #define MACB_NSR_LINK_OFFSET			0
 #define MACB_NSR_LINK_SIZE			1
Signature · 1 line
1.7.3.4