ARM: Clean arch/arm/lib/cache.c

arch/arm/lib/cache.c is cleaned and no real cache operation will be defined in this file. A new file arch/arm/cpu/arm1136/cache.c is created. This file will define the real cache operations.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V2

    Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136

 arch/arm/cpu/arm1136/Makefile |    2 +-
 arch/arm/cpu/arm1136/cache.c  |   31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm1136/cache.c

arch/arm/cpu/arm1136/Makefile +1 -1

index 930e0d1..5b5f330 100644
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))

arch/arm/cpu/arm1136/cache.c new file +18 -0

new file mode 100644
index 0000000..30aa99d
@@ -0,0 +1,31 @@
+/*
+ * (C) Copyright 2002
+ * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License

arch/arm/cpu/arm1136/cache.c new file +3 -0

+
+	arm1136_cache_flush();
+}

Quoted 20 lines · Hong Xu

arch/arm/lib/cache.c is cleaned and no real cache operation will be defined in this file. A new file arch/arm/cpu/arm1136/cache.c is created. This file will define the real cache operations.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V2

     Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136

  arch/arm/cpu/arm1136/Makefile |    2 +-
  arch/arm/cpu/arm1136/cache.c  |   31 +++++++++++++++++++++++++++++++
  2 files changed, 32 insertions(+), 1 deletions(-)

create mode 100644 arch/arm/cpu/arm1136/cache.c

arch/arm/cpu/arm1136/Makefile +0 -0

index 930e0d1..5b5f330 100644

arch/arm/cpu/arm1136/Makefile

Quoted 7 lines

+ */

arch/arm/cpu/arm1136/Makefile +6 -0

+
+#include<common.h>
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	void arm1136_cache_flush(void);

Whoa this void on the left side is strange ;-)

Quoted 4 lines

arch/arm/cpu/arm1136/Makefile +3 -0

+
+	arm1136_cache_flush();
+}

Hi Marek,

Quoted 22 lines · Marek Vasut

Quoted 21 lines · Hong Xu

arch/arm/lib/cache.c is cleaned and no real cache operation will be defined in this file. A new file arch/arm/cpu/arm1136/cache.c is created. This file will define the real cache operations.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V2

     Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136

  arch/arm/cpu/arm1136/Makefile |    2 +-
  arch/arm/cpu/arm1136/cache.c  |   31 +++++++++++++++++++++++++++++++
  2 files changed, 32 insertions(+), 1 deletions(-)

create mode 100644 arch/arm/cpu/arm1136/cache.c

(quoted diff) +0 -0

b/arch/arm/cpu/arm1136/Makefile index 930e0d1..5b5f330 100644

arch/arm/cpu/arm1136/Makefile +0 -0

[...]

Quoted 9 lines

arch/arm/cpu/arm1136/Makefile

Quoted 7 lines

+ */

arch/arm/cpu/arm1136/Makefile +6 -0

+
+#include<common.h>
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	void arm1136_cache_flush(void);

Whoa this void on the left side is strange ;-)

Just copied from original file. ;-)

Move it out and change to "extern void arm1136_cache_flush(void);", OK for you?

BR,
Eric

Quoted 3 lines

Quoted 3 lines

arch/arm/cpu/arm1136/Makefile +3 -0

+
+	arm1136_cache_flush();
+}

arch/arm/lib/cache.c is cleaned and no real cache operation will be defined in this file. A new file arch/arm/cpu/arm1136/cache.c is created. This file will define the real cache operations.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V2

    Removed redundant ifdef for CONFIG_OMAP2420 || CONFIG_ARM1136

 arch/arm/cpu/arm1136/Makefile |    2 +-
 arch/arm/cpu/arm1136/cache.c  |   31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm1136/cache.c

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

 arch/arm/cpu/arm926ejs/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/cache.c

arch/arm/cpu/arm926ejs/Makefile +1 -1

index 930e0d1..5b5f330 100644
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))

arch/arm/cpu/arm926ejs/cache.c new file +135 -0

new file mode 100644
index 0000000..756c9b1
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLUSH_CACHE_OP		0
+#define INVALIDATE_CACHE_OP	1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+	unsigned long mva;
+
+	if (op > INVALIDATE_CACHE_OP) {
+		printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+			__func__, op);
+		return;
+	}
+
+	mva = start;
+	if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, start,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round up starting address */
+		mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+	}
+	if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, stop,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round down ending address */
+		stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	}
+
+	while (mva < stop) {
+		if (op == FLUSH_CACHE_OP)
+			asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+		else
+			asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+		mva += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	/* Drain WB if necessary */
+	if (op == FLUSH_CACHE_OP)
+		asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+	/*
+	 * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+	 * Clean & Invalidate the entire DCache
+	 */
+	asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+	/* Drain WB */
+	asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, INVALIDATE_CACHE_OP);
+}
+
+void invalidate_dcache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+void flush_cache(unsigned long start, unsigned long size) {}
+void flush_dcache_all(void) {}
+void flush_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_all(void) {}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+void invalidate_icache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
+
+void invalidate_icache_all(void) {}
+#endif

Hi Hong,

Quoted 2 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

How about converting as much as possible of these to armv5/armv6 generic code as I mentioned in this thread:

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=105526

On a quick look everything below except the "flush_dcache_all()" seems to be armv5 generic.

best regards,
Aneesh

Quoted 177 lines

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1

Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

 arch/arm/cpu/arm926ejs/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/cache.c  |  135
 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 136
 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/cache.c

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644

arch/arm/cpu/arm926ejs/Makefile +1 -1

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
 
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 

SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000..756c9b1

arch/arm/cpu/arm926ejs/cache.c new file +40 -0

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLUSH_CACHE_OP		0
+#define INVALIDATE_CACHE_OP	1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int

op) +{

arch/arm/cpu/arm926ejs/cache.c new file +94 -0

+	unsigned long mva;
+
+	if (op > INVALIDATE_CACHE_OP) {
+		printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+			__func__, op);
+		return;
+	}
+
+	mva = start;
+	if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, start,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round up starting address */
+		mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+	}
+	if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, stop,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round down ending address */
+		stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	}
+
+	while (mva < stop) {
+		if (op == FLUSH_CACHE_OP)
+			asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+		else
+			asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+		mva += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	/* Drain WB if necessary */
+	if (op == FLUSH_CACHE_OP)
+		asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+	/*
+	 * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+	 * Clean & Invalidate the entire DCache
+	 */
+	asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+	/* Drain WB */
+	asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, INVALIDATE_CACHE_OP);
+}
+
+void invalidate_dcache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+void flush_cache(unsigned long start, unsigned long size) {}
+void flush_dcache_all(void) {}
+void flush_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_all(void) {}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+void invalidate_icache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
+
+void invalidate_icache_all(void) {}
+#endif

Quoted 9 lines · Aneesh V

Hi Hong,

Quoted 2 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

How about converting as much as possible of these to armv5/armv6 generic code as I mentioned in this thread:

Quoted 4 lines

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=105526

On a quick look everything below except the "flush_dcache_all()" seems to be armv5 generic.

I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are you dead sure it won't break any v5 CPU we support?

Hi Marek,

Quoted 10 lines · Marek Vasut

Quoted 9 lines · Aneesh V

Hi Hong,

Quoted 2 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

How about converting as much as possible of these to armv5/armv6 generic code as I mentioned in this thread:

Quoted 8 lines

Quoted 5 lines

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=1055
26

On a quick look everything below except the "flush_dcache_all()" seems to be armv5 generic.

I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are you dead sure it won't break any v5 CPU we support?

What Hong has used is operations mentioned in the ARMv5 architecture and these are not marked as IMPLEMENTATION DEFINED. So, compliant implementations should implement those CP15 operations. They may enhance the operations by adding their own like ARM926EJS seems to be doing with 'flush d-cache all'.

However, I think that's immaterial. Hong can provide this as a library and define a CONFIG_* flag to enable it. Let the platform maintainers decide whether to use it or not. IMHO, it will definitely be an improvement over what we have today.

best regards,
Aneesh

Quoted 28 lines · Aneesh V

Hi Marek,

Quoted 10 lines · Marek Vasut

Quoted 9 lines · Aneesh V

Hi Hong,

Quoted 2 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

How about converting as much as possible of these to armv5/armv6 generic code as I mentioned in this thread:

Quoted 8 lines

Quoted 5 lines

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=1055
26

On a quick look everything below except the "flush_dcache_all()" seems to be armv5 generic.

I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are you dead sure it won't break any v5 CPU we support?

What Hong has used is operations mentioned in the ARMv5 architecture and these are not marked as IMPLEMENTATION DEFINED. So, compliant implementations should implement those CP15 operations. They may enhance the operations by adding their own like ARM926EJS seems to be doing with 'flush d-cache all'.

Quoted 4 lines

However, I think that's immaterial. Hong can provide this as a library and define a CONFIG_* flag to enable it. Let the platform maintainers decide whether to use it or not. IMHO, it will definitely be an improvement over what we have today.

Hi,

It certainly will, but I'm quite relucant to that as it'll also -- since CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default -- break some things. Even though what I said is not exactly an argument for what you said.

If you're firm all ARMv5 implement it this way, I'm all for it being done the way you suggest it!

Quoted 41 lines · Marek Vasut

Quoted 28 lines · Aneesh V

Hi Marek,

Quoted 10 lines · Marek Vasut

Quoted 9 lines · Aneesh V

Hi Hong,

Quoted 2 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

How about converting as much as possible of these to armv5/armv6 generic code as I mentioned in this thread:

Quoted 8 lines

Quoted 5 lines

http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/105385/focus=10
55 26

On a quick look everything below except the "flush_dcache_all()" seems to be armv5 generic.

I'd be _VERY_ careful here. And this "seems" doesn't sound very convincing. Are you dead sure it won't break any v5 CPU we support?

What Hong has used is operations mentioned in the ARMv5 architecture and these are not marked as IMPLEMENTATION DEFINED. So, compliant implementations should implement those CP15 operations. They may enhance the operations by adding their own like ARM926EJS seems to be doing with 'flush d-cache all'.

Quoted 4 lines

However, I think that's immaterial. Hong can provide this as a library and define a CONFIG_* flag to enable it. Let the platform maintainers decide whether to use it or not. IMHO, it will definitely be an improvement over what we have today.

Hi,

It certainly will, but I'm quite relucant to that as it'll also -- since CONFIG_SYS_DCACHE_OFF and CONFIG_SYS_ICACHE_OFF isn't defined by default -- break some things. Even though what I said is not exactly an argument for what you said.

Quoted 2 lines

If you're firm all ARMv5 implement it this way, I'm all for it being done the way you suggest it!

I can not vouch for all the CPUs. But I checked one more - ARM946ES. This one is also implementing all the standard operations that Hong has used('flush d-cache all' used by Hong is not a standard armv5 operation - that seems to be a 926ejs specific one).

best regards,
Aneesh

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

 arch/arm/cpu/arm926ejs/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/cache.c  |  135
+++++++++++++++++++++++++++++++++++++++ 2 files changed, 136
insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/cache.c

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/Makefile index 930e0d1..5b5f330 100644

arch/arm/cpu/arm926ejs/Makefile +1 -1

@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))

(quoted diff) +0 -0

b/arch/arm/cpu/arm926ejs/cache.c new file mode 100644 index 0000000..756c9b1

arch/arm/cpu/arm926ejs/cache.c new file +40 -0

@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLUSH_CACHE_OP		0
+#define INVALIDATE_CACHE_OP	1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int

op) +{

arch/arm/cpu/arm926ejs/cache.c new file +94 -0

+	unsigned long mva;
+
+	if (op > INVALIDATE_CACHE_OP) {
+		printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+			__func__, op);
+		return;
+	}
+
+	mva = start;
+	if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, start,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round up starting address */
+		mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+	}
+	if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, stop,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round down ending address */
+		stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	}
+
+	while (mva < stop) {
+		if (op == FLUSH_CACHE_OP)
+			asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+		else
+			asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+		mva += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	/* Drain WB if necessary */
+	if (op == FLUSH_CACHE_OP)
+		asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+	/*
+	 * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+	 * Clean & Invalidate the entire DCache
+	 */
+	asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+	/* Drain WB */
+	asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+void flush_cache(unsigned long start, unsigned long size)
+{
+	flush_dcache_range(start, start + size);
+}
+
+/*
+ * The buffer range to be invalidated is [start, stop)
+ */
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, INVALIDATE_CACHE_OP);
+}
+
+void invalidate_dcache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c6, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_DCACHE_OFF */
+
+void flush_cache(unsigned long start, unsigned long size) {}
+void flush_dcache_all(void) {}
+void flush_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_range(unsigned long start, unsigned long stop) {}
+void invalidate_dcache_all(void) {}
+#endif
+
+#ifndef CONFIG_SYS_ICACHE_OFF
+void invalidate_icache_all(void)
+{
+	asm("mcr p15, 0, %0, c7, c5, 0\n" : : "r" (0));
+}
+
+#else /* #ifndef CONFIG_SYS_ICACHE_OFF */
+
+void invalidate_icache_all(void) {}
+#endif

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
? ?Modified copyright line
? ?Fix for compiling warnings
? ?Changed the way to use CONFIG_SYS_CACHELINE_SIZE
? ?When unaligned buffer detected, emit ERROR instead of WARNING

? ?Do not make a common v5,v6 cache file. It seems arm946 is lack of ? ?Test-and-Clean DCache operation. And maybe more differents...

?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +- ?arch/arm/cpu/arm926ejs/cache.c ?| ?135 +++++++++++++++++++++++++++++++++++++++ ?2 files changed, 136 insertions(+), 1 deletions(-)
?create mode 100644 arch/arm/cpu/arm926ejs/cache.c

Hi Hong,

Quoted 13 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Quoted 8 lines

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

  arch/arm/cpu/arm926ejs/Makefile |    2 +-
  arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++
  2 files changed, 136 insertions(+), 1 deletions(-)

create mode 100644 arch/arm/cpu/arm926ejs/cache.c

This patch series don't works for me. My board is also arm926ejs based, and its configure as dkb_config;
The error message as below:
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be30 not aligned to cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c030 not aligned to cache line size(32 bytes)
ERROR: cache_range_op op: 0 - start address 0x1fe7be28 not aligned to cache line size(32 bytes)
ERROR: cache_range_op op: 0 - stop address 0x1fe7c028 not aligned to cache line size(32 bytes)

Do you have any hint for this?

Best regards,
Lei

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
? ?Modified copyright line
? ?Fix for compiling warnings
? ?Changed the way to use CONFIG_SYS_CACHELINE_SIZE
? ?When unaligned buffer detected, emit ERROR instead of WARNING

? ?Do not make a common v5,v6 cache file. It seems arm946 is lack of ? ?Test-and-Clean DCache operation. And maybe more differents...

?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +- ?arch/arm/cpu/arm926ejs/cache.c ?| ?135 +++++++++++++++++++++++++++++++++++++++ ?2 files changed, 136 insertions(+), 1 deletions(-)
?create mode 100644 arch/arm/cpu/arm926ejs/cache.c

arch/arm/cpu/arm926ejs/Makefile +0 -0

index 930e0d1..5b5f330 100644
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk

?LIB ? ?= $(obj)lib$(CPU).o

?START ?= start.o

arch/arm/cpu/arm926ejs/Makefile +1 -1

-COBJS ?= cpu.o
+COBJS ?= cpu.o cache.o

?SRCS ? := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) ?OBJS ? := $(addprefix $(obj),$(COBJS) $(SOBJS))

arch/arm/cpu/arm926ejs/cache.c new file +23 -0

new file mode 100644
index 0000000..756c9b1
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. ?See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>

Hi Hong,

Quoted 18 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

  arch/arm/cpu/arm926ejs/Makefile |    2 +-
  arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++

Quoted 9 lines

arch/arm/cpu/arm926ejs/cache.c new file +9 -0

+#include<common.h>
+
+#define FLUSH_CACHE_OP         0
+#define INVALIDATE_CACHE_OP    1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid

Quoted 2 lines

+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32

I think we shouldn't make such assumption here.
You could refer to Lukasz's patch over armv7:
http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/105772
And you also should export one method as: get_dcache_line_size(), so that we could malloc cache aligned buffer in mmc.c.

Best regards,
Lei

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

 arch/arm/cpu/arm926ejs/Makefile |    2 +-
 arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 136 insertions(+), 1 deletions(-)
 create mode 100644 arch/arm/cpu/arm926ejs/cache.c

arch/arm/cpu/arm926ejs/Makefile +1 -1

index 930e0d1..5b5f330 100644
@@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).o
 
 START	= start.o
-COBJS	= cpu.o
+COBJS	= cpu.o cache.o
 
 SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))

arch/arm/cpu/arm926ejs/cache.c new file +86 -0

new file mode 100644
index 0000000..756c9b1
@@ -0,0 +1,135 @@
+/*
+ * (C) Copyright 2011 Atmel Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#define FLUSH_CACHE_OP		0
+#define INVALIDATE_CACHE_OP	1
+
+#ifndef CONFIG_SYS_CACHELINE_SIZE
+/*
+ * ARM926EJ-S Technical Reference Manual, Chap 2.3.1 Table 2-9
+ * only b'10, aka. 32 bytes cache line len is valid
+ */
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+/*
+ * Flush or Invalidate DCache respectively
+ */
+static void cache_range_op(unsigned long start, unsigned long stop, int op)
+{
+	unsigned long mva;
+
+	if (op > INVALIDATE_CACHE_OP) {
+		printf("ERROR: %s - Invalid cache operation, op: %d!\n",
+			__func__, op);
+		return;
+	}
+
+	mva = start;
+	if ((mva & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - start address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, start,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round up starting address */
+		mva = (mva | (CONFIG_SYS_CACHELINE_SIZE - 1)) + 1;
+	}
+	if ((stop & (CONFIG_SYS_CACHELINE_SIZE - 1)) != 0) {
+		printf("ERROR: %s op: %d - stop address 0x%08lx not aligned "
+			"to cache line size(%d bytes)\n", __func__, op, stop,
+			CONFIG_SYS_CACHELINE_SIZE);
+		/* Round down ending address */
+		stop &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	}
+
+	while (mva < stop) {
+		if (op == FLUSH_CACHE_OP)
+			asm("mcr p15, 0, %0, c7, c14, 1\n" : : "r"(mva));
+		else
+			asm("mcr p15, 0, %0, c7, c6, 1\n" : : "r"(mva));
+
+		mva += CONFIG_SYS_CACHELINE_SIZE;
+	}
+
+	/* Drain WB if necessary */
+	if (op == FLUSH_CACHE_OP)
+		asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));
+}
+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}

Hi Hong,

Quoted 21 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V1
Modified copyright line
Fix for compiling warnings
Changed the way to use CONFIG_SYS_CACHELINE_SIZE When unaligned buffer detected, emit ERROR instead of WARNING

Do not make a common v5,v6 cache file. It seems arm946 is lack of Test-and-Clean DCache operation. And maybe more differents...

  arch/arm/cpu/arm926ejs/Makefile |    2 +-
  arch/arm/cpu/arm926ejs/cache.c  |  135 +++++++++++++++++++++++++++++++++++++++
  2 files changed, 136 insertions(+), 1 deletions(-)

create mode 100644 arch/arm/cpu/arm926ejs/cache.c

Quoted 8 lines

arch/arm/cpu/arm926ejs/cache.c new file +8 -0

+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	cache_range_op(start, stop, FLUSH_CACHE_OP);
+}

arch/arm/cpu/arm926ejs/cache.c line 96

Quoted 10 lines

arch/arm/cpu/arm926ejs/cache.c new file +10 -0

+
+void flush_dcache_all(void)
+{
+	/*
+	 * ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+	 * Clean&  Invalidate the entire DCache
+	 */
+	asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : : "memory");
+	/* Drain WB */
+	asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));

While looking at the manuals for the armv5 compatibility I stumbled upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all implementation is correct? I suspect the above is flushing only one line?

"The test, clean, and invalidate DCache instruction is the same as test and clean DCache,
except that when the entire cache has been cleaned, it is invalidated. This means that
you can use the following loop to clean and invalidate the entire DCache:

tci_loop: MRC p15, 0, r15, c7, c14, 3
BNE tci_loop
"

best regards,
Aneesh

Hi Aneesh,

Quoted 27 lines · Aneesh V

Hi Hong,

Quoted 23 lines · Hong Xu

Add a new file arch/arm/cpu/arm926ejs/cache.c and put cache operations into this file.

Signed-off-by Hong Xu<[email protected]>

Tested-by Elen Song<[email protected]>

CC Albert Aribaud<[email protected]>

---
Since V1
? ? Modified copyright line
? ? Fix for compiling warnings
? ? Changed the way to use CONFIG_SYS_CACHELINE_SIZE
? ? When unaligned buffer detected, emit ERROR instead of WARNING

? ? Do not make a common v5,v6 cache file. It seems arm946 is lack of ? ? Test-and-Clean DCache operation. And maybe more differents...

?arch/arm/cpu/arm926ejs/Makefile | ? ?2 +- ?arch/arm/cpu/arm926ejs/cache.c ?| ?135
+++++++++++++++++++++++++++++++++++++++
?2 files changed, 136 insertions(+), 1 deletions(-) ?create mode 100644 arch/arm/cpu/arm926ejs/cache.c

[...]

Quoted 32 lines

Quoted 16 lines

arch/arm/cpu/arm926ejs/cache.c new file +16 -0

+
+/*
+ * The buffer range to be flushed is [start, stop)
+ */
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+ ? ? ? cache_range_op(start, stop, FLUSH_CACHE_OP);
+}
+
+void flush_dcache_all(void)
+{
+ ? ? ? /*
+ ? ? ? ?* ARM926EJ-S Technical Reference Manual, Chap 2.3.8
+ ? ? ? ?* Clean& ?Invalidate the entire DCache
+ ? ? ? ?*/
+ ? ? ? asm("0: mrc p15, 0, r15, c7, c14, 3\n\t" "bne 0b\n" : : :

Quoted 3 lines

"memory");
+ ? ? ? /* Drain WB */
+ ? ? ? asm("mcr p15, 0, %0, c7, c10, 4\n" : : "r" (0));

While looking at the manuals for the armv5 compatibility I stumbled upon the following in Chapter 2.3.8. Are you sure your flush_dcache_all implementation is correct? I suspect the above is flushing only one line?

"The test, clean, and invalidate DCache instruction is the same as test and clean DCache,
except that when the entire cache has been cleaned, it is invalidated. This means that
you can use the following loop to clean and invalidate the entire DCache:

Quoted 3 lines

tci_loop: ? ? MRC p15, 0, r15, c7, c14, 3
? ? ? ? ? ? ? BNE tci_loop
"

As stated in the manual, we can use a loop to clean and invalidate the entire DCache.

The "asm" statement above is a loop, isn't it? ;-)

The default cache operations defined in arch/arm/lib/cache.c do not perform any real cache operation, and instead a WARNING will be emitted.

Signed-off-by Hong Xu <[email protected]>

Tested-by Elen Song <[email protected]>

CC Albert Aribaud <[email protected]>

---
Since V1
Modified copyright line
Used debug' to replace printf'

 arch/arm/lib/cache.c |   58

+++++++++++++++++++++++++++---------------------- 1 files changed, 32 insertions(+), 26 deletions(-)

arch/arm/lib/cache.c +31 -26

index 92b61a2..ce9b712 100644
@@ -1,6 +1,5 @@
 /*
- * (C) Copyright 2002
- * Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+ * (C) Copyright 2011 Atmel Corporation
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -20,36 +19,43 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+#include <linux/compiler.h>
+#include <common.h>
 
-/* for now: just dummy functions to satisfy the linker */
+#define EMIT_WARNING debug("WARNING: %s - CPU cache operation is not " \
+"implemented!\n", __func__)
 
-#include <common.h>
+/*
+ * Default implementations
+ *
+ * Warn user if CPU code does not implement necessary cache functions
+ */
+void __weak flush_cache(unsigned long start, unsigned long size)
+{
+	EMIT_WARNING;
+}
 
-void  __flush_cache(unsigned long start, unsigned long size)
+void __weak flush_dcache_all(void)
 {
-#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136)
-	void arm1136_cache_flush(void);
+	EMIT_WARNING;
+}
 
-	arm1136_cache_flush();
-#endif
-#ifdef CONFIG_ARM926EJS
-	/* test and clean, page 2-23 of arm926ejs manual */
-	asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
-	/* disable write buffer as well (page 2-22) */
-	asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
-#endif
-	return;
+void __weak flush_dcache_range(unsigned long start, unsigned long stop)
+{
+	EMIT_WARNING;
 }
-void  flush_cache(unsigned long start, unsigned long size)
-	__attribute__((weak, alias("__flush_cache")));
 
-/*
- * Default implementation:
- * do a range flush for the entire range
- */
-void	__flush_dcache_all(void)
+void __weak invalidate_dcache_range(unsigned long start, unsigned long
 stop) +{
+	EMIT_WARNING;
+}
+
+void __weak invalidate_dcache_all(void)
+{
+	EMIT_WARNING;
+}
+
+void __weak invalidate_icache_all(void)
 {
-	flush_cache(0, ~0);
+	EMIT_WARNING;
 }
-void	flush_dcache_all(void)
-	__attribute__((weak, alias("__flush_dcache_all")));