arm: omap4: omap4460 support

PATCH New Aneesh V 5 participants 26 messages Jul 16, 2011 – Aug 20, 2011 Arm (32-bit)

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Aneesh V

author

2011-07-16 16:25 UTC #0 lore raw

cover arm: omap4: omap4460 support

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz

The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

Aneesh V (5):
omap4: add omap4460 revision detection
omap4: sdram init changes for omap4460
omap: reuse omap3 gpio support in omap4
omap4: support TPS programming
omap4: clock init support for omap4460

 arch/arm/cpu/armv7/omap-common/Makefile          |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c |   41 +++----
 arch/arm/cpu/armv7/omap3/Makefile                |    1 -
 arch/arm/cpu/armv7/omap3/board.c                 |   12 ++
 arch/arm/cpu/armv7/omap4/board.c                 |   19 +++
 arch/arm/cpu/armv7/omap4/clocks.c                |  128 +++++++++++++++++++---
 arch/arm/cpu/armv7/omap4/emif.c                  |   39 ++++---
 arch/arm/include/asm/arch-omap3/cpu.h            |   26 +++++
 arch/arm/include/asm/arch-omap3/gpio.h           |   86 ---------------
 arch/arm/include/asm/arch-omap4/clocks.h         |   28 +++++-
 arch/arm/include/asm/arch-omap4/cpu.h            |   26 +++++
 arch/arm/include/asm/arch-omap4/emif.h           |   10 ++-
 arch/arm/include/asm/arch-omap4/mux_omap4.h      |    1 +
 arch/arm/include/asm/arch-omap4/omap4.h          |    9 ++
 arch/arm/include/asm/armv7.h                     |    1 +
 15 files changed, 281 insertions(+), 147 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (76%)
 delete mode 100644 arch/arm/include/asm/arch-omap3/gpio.h

Aneesh V

author

2011-07-16 16:25 UTC #1 lore raw

PATCH 1/5 omap4: add omap4460 revision detection

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/board.c        |    3 +++
 arch/arm/include/asm/arch-omap4/omap4.h |    1 +
 arch/arm/include/asm/armv7.h            |    1 +
 3 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/omap4/board.c +3 -0

index 2e5739a..17e731a 100644
@@ -140,6 +140,9 @@ static void init_omap4_revision(void)
 	case MIDR_CORTEX_A9_R1P3:
 		*omap4_revision = OMAP4430_ES2_3;
 		break;
+	case MIDR_CORTEX_A9_R2P10:
+		*omap4_revision = OMAP4460_ES1_0;
+		break;
 	default:
 		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
 		break;

arch/arm/include/asm/arch-omap4/omap4.h +1 -0

index 563544f..7ff46d7 100644
@@ -143,6 +143,7 @@ struct s32ktimer {
 #define OMAP4430_ES2_1	0x44300210
 #define OMAP4430_ES2_2	0x44300220
 #define OMAP4430_ES2_3	0x44300230
+#define OMAP4460_ES1_0	0x44600100
 
 /* ROM code defines */
 /* Boot device */

arch/arm/include/asm/armv7.h +1 -0

index b5784d8..9adc563 100644
@@ -29,6 +29,7 @@
 #define MIDR_CORTEX_A9_R0P1	0x410FC091
 #define MIDR_CORTEX_A9_R1P2	0x411FC092
 #define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
 
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-16 16:25 UTC #2 lore raw

PATCH 2/5 omap4: sdram init changes for omap4460

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/emif.c        |   39 ++++++++++++++++++--------------
 arch/arm/include/asm/arch-omap4/emif.h |   10 ++++++-
 2 files changed, 30 insertions(+), 19 deletions(-)

arch/arm/cpu/armv7/omap4/emif.c +22 ~~-17~~

index 1234a7e..487ec42 100644
@@ -151,22 +151,13 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->zq_config, &emif->emif_zq_config);
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-	/*
-	 * Workaround:
-	 * In a specific situation, the OCP interface between the DMM and
-	 * EMIF may hang.
-	 * 1. A TILER port is used to perform 2D burst writes of
-	 *       width 1 and height 8
-	 * 2. ELLAn port is used to perform reads
-	 * 3. All accesses are routed to the same EMIF controller
-	 *
-	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
-	 * be kept higher than default 0x7. As per recommondation 0x0A will
-	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
-	 */
-	if (omap_revision() == OMAP4430_ES1_0) {
-		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
-		       &emif->emif_l3_config);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+			&emif->emif_l3_config);
+	} else {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+			&emif->emif_l3_config);
 	}
 }

@@ -504,7 +495,7 @@ static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 {
 	u32 idle = 0, val = 0;
 	if (volt_ramp)
-		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 	else
 		/*Maximum value in normal conditions - suggested by hw team */
 		val = 0x1FF;

@@ -1237,6 +1228,20 @@ static void dmm_init(u32 base)
 		&hw_lisa_map_regs->dmm_lisa_map_1);
 	writel(lisa_map_regs->dmm_lisa_map_0,
 		&hw_lisa_map_regs->dmm_lisa_map_0);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		hw_lisa_map_regs =
+		    (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
+
+		writel(lisa_map_regs->dmm_lisa_map_3,
+			&hw_lisa_map_regs->dmm_lisa_map_3);
+		writel(lisa_map_regs->dmm_lisa_map_2,
+			&hw_lisa_map_regs->dmm_lisa_map_2);
+		writel(lisa_map_regs->dmm_lisa_map_1,
+			&hw_lisa_map_regs->dmm_lisa_map_1);
+		writel(lisa_map_regs->dmm_lisa_map_0,
+			&hw_lisa_map_regs->dmm_lisa_map_0);
+	}
 }
 
 /*

arch/arm/include/asm/arch-omap4/emif.h +8 -2

index a167508..37ad1fd 100644
@@ -248,6 +248,8 @@
 /* OCP_CONFIG */
 #define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
 #define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT		20
+#define OMAP44XX_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
 #define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
 #define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
 #define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0

@@ -472,6 +474,9 @@
 /* DMM */
 #define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
 
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_LISA_MAP_BASE		0x482AF040
+
 /* DMM_LISA_MAP */
 #define OMAP44XX_SYS_ADDR_SHIFT		24
 #define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)

@@ -774,8 +779,9 @@ struct control_lpddr2io_regs {
 	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
 			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
 
-/* EMIF_L3_CONFIG register value for ES1*/
-#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
 /*
  * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
  * All these fields have magic values dependent on frequency and

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-16 16:25 UTC #3 lore raw

PATCH 3/5 omap: reuse omap3 gpio support in omap4

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap-common/Makefile          |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c |   41 ++++------
 arch/arm/cpu/armv7/omap3/Makefile                |    1 -
 arch/arm/cpu/armv7/omap3/board.c                 |   12 +++
 arch/arm/cpu/armv7/omap4/board.c                 |   12 +++
 arch/arm/cpu/armv7/omap4/clocks.c                |    2 +-
 arch/arm/include/asm/arch-omap3/cpu.h            |   26 +++++++
 arch/arm/include/asm/arch-omap3/gpio.h           |   86 ----------------------
 arch/arm/include/asm/arch-omap4/cpu.h            |   26 +++++++
 arch/arm/include/asm/arch-omap4/omap4.h          |    8 ++
 10 files changed, 102 insertions(+), 113 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (76%)
 delete mode 100644 arch/arm/include/asm/arch-omap3/gpio.h

arch/arm/cpu/armv7/omap-common/Makefile +1 -0

index 0708796..ea9f8ec 100644
@@ -29,6 +29,7 @@ SOBJS	:= reset.o
 
 COBJS	:= timer.o
 COBJS	+= utils.o
+COBJS	+= gpio.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl.o

arch/arm/cpu/armv7/omap-common/gpio.c renamed from arch/arm/cpu/armv7/omap3/gpio.c +16 ~~-25~~

112 lines not on this page · raw message

arch/arm/cpu/armv7/omap3/Makefile +0 -1

index 522bcd2..8e85891 100644
@@ -29,7 +29,6 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
-COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o

arch/arm/cpu/armv7/omap3/board.c +12 -0

index 98519a9..4aaf97b 100644
@@ -38,12 +38,24 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <asm/omap_gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

arch/arm/cpu/armv7/omap4/board.c +12 -0

index 17e731a..3c61b1c 100644
@@ -33,12 +33,24 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
+#include <asm/omap_gpio.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * We use static variables because global data is not ready yet.

arch/arm/cpu/armv7/omap4/clocks.c +1 -1

index f1e233a..660b329 100644
@@ -830,9 +830,9 @@ void prcm_init(void)
 	case OMAP_INIT_CONTEXT_SPL:
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
 		scale_vcores();
 		setup_dplls();
-		enable_basic_clocks();
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 		break;

arch/arm/include/asm/arch-omap3/cpu.h +26 -0

index e944de7..08a725d 100644
@@ -498,4 +498,30 @@ struct pm {
 /* MUSB base */
 #define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap3/gpio.h deleted +0 ~~-86~~

86 lines not on this page · raw message

arch/arm/include/asm/arch-omap4/cpu.h +26 -0

index 7d5748a..08b9c99 100644
@@ -142,4 +142,30 @@ struct watchdog {
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/omap4.h +8 -0

index 7ff46d7..9aad0e6 100644
@@ -153,4 +153,12 @@ struct s32ktimer {
 #define DEV_DATA_PTR_OFFSET	0x18
 #define BOOT_MODE_OFFSET	0x8
 
+/* GPIO */
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
+
 #endif

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-16 16:25 UTC #4 lore raw

PATCH 4/5 omap4: support TPS programming

In reply to Aneesh V

TPS62361 is the new power supply used in OMAP4460 that supplies vdd_mpu.

VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies vdd_iva. VCORE3 is not used in OMAP4460.

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/board.c            |    4 ++
 arch/arm/cpu/armv7/omap4/clocks.c           |   65 ++++++++++++++++++++++++---
 arch/arm/include/asm/arch-omap4/clocks.h    |   16 +++++++
 arch/arm/include/asm/arch-omap4/mux_omap4.h |    1 +
 4 files changed, 79 insertions(+), 7 deletions(-)

arch/arm/cpu/armv7/omap4/board.c +4 -0

index 3c61b1c..5943d61 100644
@@ -90,6 +90,10 @@ static void set_muxconf_regs_essential(void)
 	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap_revision() >= OMAP4460_ES1_0)
+		writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
 }
 
 static void set_mux_conf_regs(void)

arch/arm/cpu/armv7/omap4/clocks.c +58 -7

100 lines not on this page · raw message

arch/arm/include/asm/arch-omap4/clocks.h +16 -0

index 37bdcee..5d9cb50 100644
@@ -618,6 +618,7 @@ struct omap4_prcm_regs {
 #define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
 #define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
 
+/* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_VCORE1	0x55
 #define SMPS_REG_ADDR_VCORE2	0x5B

@@ -626,6 +627,21 @@ struct omap4_prcm_regs {
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
 
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
 /* Defines for DPLL setup */
 #define DPLL_LOCKED_FREQ_TOLERANCE_0		0
 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500

arch/arm/include/asm/arch-omap4/mux_omap4.h +1 -0

index 019574b..30bfad7 100644
@@ -341,4 +341,5 @@ struct pad_conf_entry {
 #define CONTROL_SPARE_R		0x0618
 #define CONTROL_SPARE_R_C0		0x061C
 
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
 #endif /* _MUX_OMAP4_H_ */

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-16 16:25 UTC #5 lore raw

PATCH 5/5 omap4: clock init support for omap4460

In reply to Aneesh V

---
 arch/arm/cpu/armv7/omap4/clocks.c        |   61 ++++++++++++++++++++++++++---
 arch/arm/include/asm/arch-omap4/clocks.h |   12 +++++-
 2 files changed, 65 insertions(+), 8 deletions(-)

arch/arm/cpu/armv7/omap4/clocks.c +54 -7

index 0db9d18..eda960c 100644
@@ -66,7 +66,18 @@ static const u32 sys_clk_array[8] = {
  * Please use this tool for creating the table for any new frequency.
  */
 
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
+	{230, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{920, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{219, 3, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{575, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{460, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{920, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{575, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
 static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
 	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
 	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */

@@ -320,6 +331,47 @@ u32 omap4_ddr_clk(void)
 	return ddr_clk;
 }
 
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0	: 600 MHz
+ * 4430 ES2.x	: 792 MHz (OPP Turbo)
+ * 4460		: 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+	const struct dpll_params *params;
+	struct dpll_regs *mpu_dpll_regs;
+	u32 omap4_rev, sysclk_ind;
+
+	omap4_rev = omap_revision();
+	sysclk_ind = get_sys_clk_index();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else if (omap4_rev < OMAP4460_ES1_0)
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1840mhz[sysclk_ind];
+
+	/* DCC and clock divider settings for 4460 */
+	if (omap4_rev >= OMAP4460_ES1_0) {
+		mpu_dpll_regs =
+			(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
+		bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
+		clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+		setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+			CM_CLKSEL_DCC_EN_MASK);
+	}
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
 static void setup_dplls(void)
 {
 	u32 sysclk_ind, temp;

@@ -349,12 +401,7 @@ static void setup_dplls(void)
 	debug("PER DPLL locked\n");
 
 	/* MPU dpll */
-	if (omap_revision() == OMAP4430_ES1_0)
-		params = &mpu_dpll_params_1200mhz[sysclk_ind];
-	else
-		params = &mpu_dpll_params_1584mhz[sysclk_ind];
-	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
-	debug("MPU DPLL locked\n");
+	configure_mpu_dpll();
 }
 
 static void setup_non_essential_dplls(void)

arch/arm/include/asm/arch-omap4/clocks.h +11 -1

index 5d9cb50..374e064 100644
@@ -105,9 +105,11 @@ struct omap4_prcm_regs {
 	u32 cm_ssc_deltamstep_dpll_ddrphy;
 	u32 pad014[5];
 	u32 cm_shadow_freq_config1;
+	u32 pad0141[47];
+	u32 cm_mpu_mpu_clkctrl;
 
 	/* cm1.dsp */
-	u32 pad015[103];
+	u32 pad015[55];
 	u32 cm_dsp_clkstctrl;
 	u32 pad016[7];
 	u32 cm_dsp_dsp_clkctrl;

@@ -515,6 +517,8 @@ struct omap4_prcm_regs {
 #define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
 #define CM_CLKSEL_DPLL_N_SHIFT			0
 #define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
 
 #define OMAP4_DPLL_MAX_N	127

@@ -596,6 +600,12 @@ struct omap4_prcm_regs {
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
 
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6

Signature · 1 line

1.7.0.4

Albert ARIBAUD

2011-07-17 09:05 UTC #6 lore raw

cover arm: omap4: omap4460 support

In reply to Aneesh V

Hi Aneesh,

Le 16/07/2011 18:25, Aneesh V a ?crit :

Quoted 7 lines

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz
The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

Hmm... What's this 'v' doing in the patch subjects?

Amicalement,

Signature · 1 line

Albert.

Aneesh V

author

2011-07-18 09:21 UTC #7 lore raw

cover arm: omap4: omap4460 support

Hi Albert,

Quoted 8 lines · Albert ARIBAUD

Hi Aneesh,
Le 16/07/2011 18:25, Aneesh V a ?crit :
Quoted 5 lines
OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz

Quoted 5 lines

Quoted 3 lines
The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.
Hmm... What's this 'v' doing in the patch subjects?

Oops! That is a script mishap. I have a couple of convenience scripts (wrappers over git format-patch). Used the wrong one here. I didn't notice it until now.

best regards,
Aneesh

Aneesh V

author

2011-07-18 13:32 UTC #8 lore raw

cover arm: omap4: omap4460 support

In reply to Aneesh V

Quoted 7 lines · Aneesh V

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz
The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

Forgot to mention that this series depends on the OMAP4 spl series [1] and the SPL framework series [2]

[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2

br,
Aneesh

Quoted 27 lines

  arch/arm/cpu/armv7/omap-common/Makefile          |    1 +
  arch/arm/cpu/armv7/{omap3 =>  omap-common}/gpio.c |   41 +++----
  arch/arm/cpu/armv7/omap3/Makefile                |    1 -
  arch/arm/cpu/armv7/omap3/board.c                 |   12 ++
  arch/arm/cpu/armv7/omap4/board.c                 |   19 +++
  arch/arm/cpu/armv7/omap4/clocks.c                |  128 +++++++++++++++++++---
  arch/arm/cpu/armv7/omap4/emif.c                  |   39 ++++---
  arch/arm/include/asm/arch-omap3/cpu.h            |   26 +++++
  arch/arm/include/asm/arch-omap3/gpio.h           |   86 ---------------
  arch/arm/include/asm/arch-omap4/clocks.h         |   28 +++++-
  arch/arm/include/asm/arch-omap4/cpu.h            |   26 +++++
  arch/arm/include/asm/arch-omap4/emif.h           |   10 ++-
  arch/arm/include/asm/arch-omap4/mux_omap4.h      |    1 +
  arch/arm/include/asm/arch-omap4/omap4.h          |    9 ++
  arch/arm/include/asm/armv7.h                     |    1 +
  15 files changed, 281 insertions(+), 147 deletions(-)

rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (76%) delete mode 100644 arch/arm/include/asm/arch-omap3/gpio.h

Aneesh V

author

2011-07-20 10:55 UTC #9 lore raw

v2 cover arm: omap4: omap4460 support

In reply to Aneesh V

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz

The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

This series depends on the OMAP4 spl series [1] and the SPL framework series [2]

[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2

Changes in V2:
* Added missing file in the patch 3/5
* Corrected subject lines of patches

 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c   |   41 +++----
 arch/arm/cpu/armv7/omap3/Makefile                  |    1 -
 arch/arm/cpu/armv7/omap3/board.c                   |   12 ++
 arch/arm/cpu/armv7/omap4/board.c                   |   19 +++
 arch/arm/cpu/armv7/omap4/clocks.c                  |  128 +++++++++++++++++---
 arch/arm/cpu/armv7/omap4/emif.c                    |   39 ++++---
 arch/arm/include/asm/arch-omap3/cpu.h              |   26 ++++
 arch/arm/include/asm/arch-omap4/clocks.h           |   28 ++++-
 arch/arm/include/asm/arch-omap4/cpu.h              |   26 ++++
 arch/arm/include/asm/arch-omap4/emif.h             |   10 ++-
 arch/arm/include/asm/arch-omap4/mux_omap4.h        |    1 +
 arch/arm/include/asm/arch-omap4/omap4.h            |    9 ++
 arch/arm/include/asm/armv7.h                       |    1 +
 .../include/asm/{arch-omap3/gpio.h => omap_gpio.h} |   27 +----
 15 files changed, 284 insertions(+), 85 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (76%)
 rename arch/arm/include/asm/{arch-omap3/gpio.h => omap_gpio.h} (67%)

Paulraj

2011-07-20 15:43 UTC #10 lore raw

v2 cover arm: omap4: omap4460 support

Quoted 11 lines

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz
The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

Quoted 5 lines

This series depends on the OMAP4 spl series [1] and the SPL framework series [2]
[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2

Wolfgang, Albert,

If it is OK with you I'd like to pull in all the 3 patch sets into u-boot-ti.

This would also include the patch set to update the SPL framework.

Regards,
Sandeep

Wolfgang Denk

2011-07-20 19:49 UTC #11 lore raw

v2 cover arm: omap4: omap4460 support

Dear "Paulraj, Sandeep",

Quoted 4 lines · In message <[email protected]> you wrote:

Quoted 4 lines
This series depends on the OMAP4 spl series [1] and the SPL framework series [2]

Quoted 8 lines

Quoted 2 lines
[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2
Wolfgang, Albert,
If it is OK with you I'd like to pull in all the 3 patch sets into u-boot-ti.
This would also include the patch set to update the SPL framework.

I can only comment on the SPL series hier.

For this you have my:

Acked-by Wolfgang Denk <[email protected]>

[I have it on my list, too, but a short glace at my desk tells me that you will most probably be much faster than me, so please go ahead. And thanks!]

Best regards,

Wolfgang Denk

Signature · 4 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Brain off-line, please wait.

Paulraj

2011-07-20 20:44 UTC #12 lore raw

v2 cover arm: omap4: omap4460 support

Quoted 19 lines

Dear "Paulraj, Sandeep",
In message <[email protected]> you
Quoted 10 lines · wrote:
Quoted 6 lines
This series depends on the OMAP4 spl series [1] and the SPL framework series [2]
[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2
Wolfgang, Albert,
If it is OK with you I'd like to pull in all the 3 patch sets into u-
boot-ti.
Quoted 1 line

Quoted 8 lines

Quoted 1 line
This would also include the patch set to update the SPL framework.
I can only comment on the SPL series hier.
For this you have my:
Acked-by Wolfgang Denk <[email protected]>

Thanks,

I'll send in a pull request tomorrow morning

Regards,
Sandeep

Paulraj

2011-07-20 20:58 UTC #13 lore raw

v2 cover arm: omap4: omap4460 support

In reply to Aneesh V

Quoted 11 lines

OMAP4460 is the latest addition to the OMAP4 family. OMAP4460 has dual core Cortex-A9 CPUs that can be clocked upto 1.5 GHz
The memory architecture has been improved to provide better performance and there several other minor improvements in various modules.

Quoted 5 lines

This series depends on the OMAP4 spl series [1] and the SPL framework series [2]
[1] http://marc.info/?l=u-boot&m=131082102506002&w=2
[2] http://marc.info/?l=u-boot&m=131056990001719&w=2

There is a v3 version of the SPL framework series. You are pointing to the RFC series.

I hope your patches are based on the v3 patch series of the SPL framework.

--Sandeep

Aneesh V

author

2011-07-20 10:55 UTC #14 lore raw

PATCH v2 1/5 omap4: add omap4460 revision detection

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/board.c        |    3 +++
 arch/arm/include/asm/arch-omap4/omap4.h |    1 +
 arch/arm/include/asm/armv7.h            |    1 +
 3 files changed, 5 insertions(+), 0 deletions(-)

arch/arm/cpu/armv7/omap4/board.c +3 -0

index 2e5739a..17e731a 100644
@@ -140,6 +140,9 @@ static void init_omap4_revision(void)
 	case MIDR_CORTEX_A9_R1P3:
 		*omap4_revision = OMAP4430_ES2_3;
 		break;
+	case MIDR_CORTEX_A9_R2P10:
+		*omap4_revision = OMAP4460_ES1_0;
+		break;
 	default:
 		*omap4_revision = OMAP4430_SILICON_ID_INVALID;
 		break;

arch/arm/include/asm/arch-omap4/omap4.h +1 -0

index 563544f..7ff46d7 100644
@@ -143,6 +143,7 @@ struct s32ktimer {
 #define OMAP4430_ES2_1	0x44300210
 #define OMAP4430_ES2_2	0x44300220
 #define OMAP4430_ES2_3	0x44300230
+#define OMAP4460_ES1_0	0x44600100
 
 /* ROM code defines */
 /* Boot device */

arch/arm/include/asm/armv7.h +1 -0

index b5784d8..9adc563 100644
@@ -29,6 +29,7 @@
 #define MIDR_CORTEX_A9_R0P1	0x410FC091
 #define MIDR_CORTEX_A9_R1P2	0x411FC092
 #define MIDR_CORTEX_A9_R1P3	0x411FC093
+#define MIDR_CORTEX_A9_R2P10	0x412FC09A
 
 /* CCSIDR */
 #define CCSIDR_LINE_SIZE_OFFSET		0

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-20 10:55 UTC #15 lore raw

PATCH v2 2/5 omap4: sdram init changes for omap4460

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/emif.c        |   39 ++++++++++++++++++--------------
 arch/arm/include/asm/arch-omap4/emif.h |   10 ++++++-
 2 files changed, 30 insertions(+), 19 deletions(-)

arch/arm/cpu/armv7/omap4/emif.c +22 ~~-17~~

index 1234a7e..487ec42 100644
@@ -151,22 +151,13 @@ static void emif_update_timings(u32 base, const struct emif_regs *regs)
 	writel(regs->zq_config, &emif->emif_zq_config);
 	writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 	writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
-	/*
-	 * Workaround:
-	 * In a specific situation, the OCP interface between the DMM and
-	 * EMIF may hang.
-	 * 1. A TILER port is used to perform 2D burst writes of
-	 *       width 1 and height 8
-	 * 2. ELLAn port is used to perform reads
-	 * 3. All accesses are routed to the same EMIF controller
-	 *
-	 * Work around to avoid this issue REG_SYS_THRESH_MAX value should
-	 * be kept higher than default 0x7. As per recommondation 0x0A will
-	 * be used for better performance with REG_LL_THRESH_MAX = 0x00
-	 */
-	if (omap_revision() == OMAP4430_ES1_0) {
-		writel(EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00,
-		       &emif->emif_l3_config);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
+			&emif->emif_l3_config);
+	} else {
+		writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
+			&emif->emif_l3_config);
 	}
 }

@@ -504,7 +495,7 @@ static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 {
 	u32 idle = 0, val = 0;
 	if (volt_ramp)
-		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 + 1;
+		val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 	else
 		/*Maximum value in normal conditions - suggested by hw team */
 		val = 0x1FF;

@@ -1237,6 +1228,20 @@ static void dmm_init(u32 base)
 		&hw_lisa_map_regs->dmm_lisa_map_1);
 	writel(lisa_map_regs->dmm_lisa_map_0,
 		&hw_lisa_map_regs->dmm_lisa_map_0);
+
+	if (omap_revision() >= OMAP4460_ES1_0) {
+		hw_lisa_map_regs =
+		    (struct dmm_lisa_map_regs *)OMAP44XX_MA_LISA_MAP_BASE;
+
+		writel(lisa_map_regs->dmm_lisa_map_3,
+			&hw_lisa_map_regs->dmm_lisa_map_3);
+		writel(lisa_map_regs->dmm_lisa_map_2,
+			&hw_lisa_map_regs->dmm_lisa_map_2);
+		writel(lisa_map_regs->dmm_lisa_map_1,
+			&hw_lisa_map_regs->dmm_lisa_map_1);
+		writel(lisa_map_regs->dmm_lisa_map_0,
+			&hw_lisa_map_regs->dmm_lisa_map_0);
+	}
 }
 
 /*

arch/arm/include/asm/arch-omap4/emif.h +8 -2

index a167508..37ad1fd 100644
@@ -248,6 +248,8 @@
 /* OCP_CONFIG */
 #define OMAP44XX_REG_SYS_THRESH_MAX_SHIFT		24
 #define OMAP44XX_REG_SYS_THRESH_MAX_MASK		(0xf << 24)
+#define OMAP44XX_REG_MPU_THRESH_MAX_SHIFT		20
+#define OMAP44XX_REG_MPU_THRESH_MAX_MASK		(0xf << 20)
 #define OMAP44XX_REG_LL_THRESH_MAX_SHIFT		16
 #define OMAP44XX_REG_LL_THRESH_MAX_MASK			(0xf << 16)
 #define OMAP44XX_REG_PR_OLD_COUNT_SHIFT			0

@@ -472,6 +474,9 @@
 /* DMM */
 #define OMAP44XX_DMM_LISA_MAP_BASE	0x4E000040
 
+/* Memory Adapter (4460 onwards) */
+#define OMAP44XX_MA_LISA_MAP_BASE		0x482AF040
+
 /* DMM_LISA_MAP */
 #define OMAP44XX_SYS_ADDR_SHIFT		24
 #define OMAP44XX_SYS_ADDR_MASK		(0xff << 24)

@@ -774,8 +779,9 @@ struct control_lpddr2io_regs {
 	((REG_PD_TIM << OMAP44XX_REG_PD_TIM_SHDW_SHIFT)\
 			& OMAP44XX_REG_PD_TIM_SHDW_MASK))
 
-/* EMIF_L3_CONFIG register value for ES1*/
-#define EMIF_L3_CONFIG_VAL_SYS_THRESH_0A_LL_THRESH_00	0x0A0000FF
+/* EMIF_L3_CONFIG register value */
+#define EMIF_L3_CONFIG_VAL_SYS_10_LL_0	0x0A0000FF
+#define EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0	0x0A300000
 /*
  * Value of bits 12:31 of DDR_PHY_CTRL_1 register:
  * All these fields have magic values dependent on frequency and

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-20 10:55 UTC #16 lore raw

PATCH v2 3/5 omap: reuse omap3 gpio support in omap4

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
V2:
* Added a new file that was accidentally missing in v1

---
 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c   |   41 ++++++++------------
 arch/arm/cpu/armv7/omap3/Makefile                  |    1 -
 arch/arm/cpu/armv7/omap3/board.c                   |   12 ++++++
 arch/arm/cpu/armv7/omap4/board.c                   |   12 ++++++
 arch/arm/cpu/armv7/omap4/clocks.c                  |    2 +-
 arch/arm/include/asm/arch-omap3/cpu.h              |   26 ++++++++++++
 arch/arm/include/asm/arch-omap4/cpu.h              |   26 ++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h            |    8 ++++
 .../include/asm/{arch-omap3/gpio.h => omap_gpio.h} |   27 +-----------
 10 files changed, 105 insertions(+), 51 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (76%)
 rename arch/arm/include/asm/{arch-omap3/gpio.h => omap_gpio.h} (67%)

arch/arm/cpu/armv7/omap-common/Makefile +1 -0

index 0708796..ea9f8ec 100644
@@ -29,6 +29,7 @@ SOBJS	:= reset.o
 
 COBJS	:= timer.o
 COBJS	+= utils.o
+COBJS	+= gpio.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl.o

arch/arm/cpu/armv7/omap-common/gpio.c renamed from arch/arm/cpu/armv7/omap3/gpio.c +16 ~~-25~~

112 lines not on this page · raw message

arch/arm/cpu/armv7/omap3/Makefile +0 -1

index 522bcd2..8e85891 100644
@@ -29,7 +29,6 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
-COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o

arch/arm/cpu/armv7/omap3/board.c +12 -0

index 98519a9..4aaf97b 100644
@@ -38,12 +38,24 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <asm/omap_gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

arch/arm/cpu/armv7/omap4/board.c +12 -0

index 17e731a..3c61b1c 100644
@@ -33,12 +33,24 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
+#include <asm/omap_gpio.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * We use static variables because global data is not ready yet.

arch/arm/cpu/armv7/omap4/clocks.c +1 -1

index f1e233a..660b329 100644
@@ -830,9 +830,9 @@ void prcm_init(void)
 	case OMAP_INIT_CONTEXT_SPL:
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
 		scale_vcores();
 		setup_dplls();
-		enable_basic_clocks();
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 		break;

arch/arm/include/asm/arch-omap3/cpu.h +26 -0

index e944de7..08a725d 100644
@@ -498,4 +498,30 @@ struct pm {
 /* MUSB base */
 #define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/cpu.h +26 -0

index 7d5748a..08b9c99 100644
@@ -142,4 +142,30 @@ struct watchdog {
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/omap4.h +8 -0

index 7ff46d7..9aad0e6 100644
@@ -153,4 +153,12 @@ struct s32ktimer {
 #define DEV_DATA_PTR_OFFSET	0x18
 #define BOOT_MODE_OFFSET	0x8
 
+/* GPIO */
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
+
 #endif

arch/arm/include/asm/omap_gpio.h renamed from arch/arm/include/asm/arch-omap3/gpio.h +3 ~~-24~~

similarity index 67%
rename from arch/arm/include/asm/arch-omap3/gpio.h
rename to arch/arm/include/asm/omap_gpio.h
index 30f633c..3089e1c 100644
@@ -38,36 +38,15 @@
 #ifndef _GPIO_H
 #define _GPIO_H
 
-#define OMAP24XX_GPIO_REVISION		0x0000
-#define OMAP24XX_GPIO_SYSCONFIG		0x0010
-#define OMAP24XX_GPIO_SYSSTATUS		0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
-#define OMAP24XX_GPIO_IRQENABLE2	0x002c
-#define OMAP24XX_GPIO_IRQENABLE1	0x001c
-#define OMAP24XX_GPIO_WAKE_EN		0x0020
-#define OMAP24XX_GPIO_CTRL		0x0030
-#define OMAP24XX_GPIO_OE		0x0034
-#define OMAP24XX_GPIO_DATAIN		0x0038
-#define OMAP24XX_GPIO_DATAOUT		0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
-#define OMAP24XX_GPIO_RISINGDETECT	0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
-#define OMAP24XX_GPIO_SETWKUENA		0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
-#define OMAP24XX_GPIO_SETDATAOUT	0x0094
+#include <asm/arch/cpu.h>
 
 struct gpio_bank {
 	void *base;
 	int method;
 };
 
+extern const struct gpio_bank *const omap_gpio_bank;
+
 #define METHOD_GPIO_24XX	4
 
 /* This is the interface */

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-29 16:40 UTC #17 lore raw

PATCH v2 3/5 omap: reuse omap3 gpio support in omap4

Hi All,

Quoted 5 lines · Aneesh V

Signed-off-by Aneesh V<[email protected]>
---
V2:
* Added a new file that was accidentally missing in v1
---

[snip ..]

Quoted 1 line

  .../include/asm/{arch-omap3/gpio.h =>  omap_gpio.h} |   27 +-----------

I just realized that this change in header file name was breaking some omap3 boards. I had tested only omap3_sdp3430. But some other boards used GPIO functions in the board layer, which I didn't notice.

I will send out a patch shortly to fix this.

br,
Aneesh

Aneesh V

author

2011-07-29 17:03 UTC #18 lore raw

PATCH 3/5 omap: reuse omap3 gpio support in omap4

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
V2:
* Added a new file that was accidentally missing in v1

V3:
* Fix build break for other boards by restoring the old header files <asm/arch/gpio.h>

---
 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c   |   39 +++++--------
 arch/arm/cpu/armv7/omap3/Makefile                  |    1 -
 arch/arm/cpu/armv7/omap3/board.c                   |   12 ++++
 arch/arm/cpu/armv7/omap4/board.c                   |   12 ++++
 arch/arm/cpu/armv7/omap4/clocks.c                  |    2 +-
 arch/arm/include/asm/arch-omap3/cpu.h              |   26 +++++++++
 arch/arm/include/asm/arch-omap3/gpio.h             |   56 ++++----------------
 arch/arm/include/asm/arch-omap3/omap3.h            |    8 ---
 arch/arm/include/asm/arch-omap4/cpu.h              |   26 +++++++++
 arch/arm/include/asm/arch-omap4/gpio.h             |   50 +++++++++++++++++
 .../include/asm/{arch-omap3/gpio.h => omap_gpio.h} |   27 +--------
 board/pandora/pandora.c                            |    1 +
 13 files changed, 157 insertions(+), 104 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (77%)
 create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h
 copy arch/arm/include/asm/{arch-omap3/gpio.h => omap_gpio.h} (67%)

arch/arm/cpu/armv7/omap-common/Makefile +1 -0

index 0708796..ea9f8ec 100644
@@ -29,6 +29,7 @@ SOBJS	:= reset.o
 
 COBJS	:= timer.o
 COBJS	+= utils.o
+COBJS	+= gpio.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl.o

arch/arm/cpu/armv7/omap-common/gpio.c renamed from arch/arm/cpu/armv7/omap3/gpio.c +15 ~~-24~~

similarity index 77%
rename from arch/arm/cpu/armv7/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap-common/gpio.c
index aeb6066..2fcaf5a 100644
@@ -40,20 +40,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
-static struct gpio_bank gpio_bank_34xx[6] = {
-	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
+static inline const struct gpio_bank *get_gpio_bank(int gpio)
 {
-	return &gpio_bank[gpio >> 5];
+	return &omap_gpio_bank[gpio >> 5];
 }
 
 static inline int get_gpio_index(int gpio)

@@ -79,14 +68,15 @@ static int check_gpio(int gpio)
 	return 0;
 }
 
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
+				int is_input)
 {
 	void *reg = bank->base;
 	u32 l;
 
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_OE;
+		reg += OMAP_GPIO_OE;
 		break;
 	default:
 		return;

@@ -101,7 +91,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 
 void omap_set_gpio_direction(int gpio, int is_input)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

@@ -109,7 +99,8 @@ void omap_set_gpio_direction(int gpio, int is_input)
 	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
 }
 
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
+				int enable)
 {
 	void *reg = bank->base;
 	u32 l = 0;

@@ -117,9 +108,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
 		if (enable)
-			reg += OMAP24XX_GPIO_SETDATAOUT;
+			reg += OMAP_GPIO_SETDATAOUT;
 		else
-			reg += OMAP24XX_GPIO_CLEARDATAOUT;
+			reg += OMAP_GPIO_CLEARDATAOUT;
 		l = 1 << gpio;
 		break;
 	default:

@@ -132,7 +123,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 
 void omap_set_gpio_dataout(int gpio, int enable)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

@@ -142,7 +133,7 @@ void omap_set_gpio_dataout(int gpio, int enable)
 
 int omap_get_gpio_datain(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 	void *reg;
 
 	if (check_gpio(gpio) < 0)

@@ -151,7 +142,7 @@ int omap_get_gpio_datain(int gpio)
 	reg = bank->base;
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_DATAIN;
+		reg += OMAP_GPIO_DATAIN;
 		break;
 	default:
 		return -EINVAL;

@@ -160,7 +151,7 @@ int omap_get_gpio_datain(int gpio)
 			& (1 << get_gpio_index(gpio))) != 0;
 }
 
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
+static void _reset_gpio(const struct gpio_bank *bank, int gpio)
 {
 	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
 }

@@ -175,7 +166,7 @@ int omap_request_gpio(int gpio)
 
 void omap_free_gpio(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

arch/arm/cpu/armv7/omap3/Makefile +0 -1

index 522bcd2..8e85891 100644
@@ -29,7 +29,6 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
-COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o

arch/arm/cpu/armv7/omap3/board.c +12 -0

index 98519a9..bce3ee6 100644
@@ -38,12 +38,24 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <asm/arch/gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

arch/arm/cpu/armv7/omap4/board.c +12 -0

index 17e731a..08fc949 100644
@@ -33,12 +33,24 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
+#include <asm/arch/gpio.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * We use static variables because global data is not ready yet.

arch/arm/cpu/armv7/omap4/clocks.c +1 -1

index f1e233a..660b329 100644
@@ -830,9 +830,9 @@ void prcm_init(void)
 	case OMAP_INIT_CONTEXT_SPL:
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
 		scale_vcores();
 		setup_dplls();
-		enable_basic_clocks();
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 		break;

arch/arm/include/asm/arch-omap3/cpu.h +26 -0

index e944de7..08a725d 100644
@@ -498,4 +498,30 @@ struct pm {
 /* MUSB base */
 #define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap3/gpio.h +10 ~~-46~~

62 lines not on this page · raw message

arch/arm/include/asm/arch-omap3/omap3.h +0 -8

index d9d49da..230eaad 100644
@@ -100,14 +100,6 @@ struct s32ktimer {
 
 #endif /* __ASSEMBLY__ */
 
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE		0x48310000
-#define OMAP34XX_GPIO2_BASE		0x49050000
-#define OMAP34XX_GPIO3_BASE		0x49052000
-#define OMAP34XX_GPIO4_BASE		0x49054000
-#define OMAP34XX_GPIO5_BASE		0x49056000
-#define OMAP34XX_GPIO6_BASE		0x49058000
-
 #ifndef __ASSEMBLY__
 struct gpio {
 	unsigned char res1[0x34];

arch/arm/include/asm/arch-omap4/cpu.h +26 -0

index 7d5748a..08b9c99 100644
@@ -142,4 +142,30 @@ struct watchdog {
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/gpio.h new file +50 -0

50 lines not on this page · raw message

arch/arm/include/asm/omap_gpio.h renamed from arch/arm/include/asm/arch-omap3/gpio.h +3 ~~-24~~

similarity index 67%
copy from arch/arm/include/asm/arch-omap3/gpio.h
copy to arch/arm/include/asm/omap_gpio.h
index 30f633c..3089e1c 100644
@@ -38,36 +38,15 @@
 #ifndef _GPIO_H
 #define _GPIO_H
 
-#define OMAP24XX_GPIO_REVISION		0x0000
-#define OMAP24XX_GPIO_SYSCONFIG		0x0010
-#define OMAP24XX_GPIO_SYSSTATUS		0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
-#define OMAP24XX_GPIO_IRQENABLE2	0x002c
-#define OMAP24XX_GPIO_IRQENABLE1	0x001c
-#define OMAP24XX_GPIO_WAKE_EN		0x0020
-#define OMAP24XX_GPIO_CTRL		0x0030
-#define OMAP24XX_GPIO_OE		0x0034
-#define OMAP24XX_GPIO_DATAIN		0x0038
-#define OMAP24XX_GPIO_DATAOUT		0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
-#define OMAP24XX_GPIO_RISINGDETECT	0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
-#define OMAP24XX_GPIO_SETWKUENA		0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
-#define OMAP24XX_GPIO_SETDATAOUT	0x0094
+#include <asm/arch/cpu.h>
 
 struct gpio_bank {
 	void *base;
 	int method;
 };
 
+extern const struct gpio_bank *const omap_gpio_bank;
+
 #define METHOD_GPIO_24XX	4
 
 /* This is the interface */

board/pandora/pandora.c +1 -0

index 992e9f7..fe363b2 100644
@@ -34,6 +34,7 @@
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
 #include <asm/mach-types.h>
 #include "pandora.h"

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-29 17:09 UTC #19 lore raw

PATCH v3 3/5 omap: reuse omap3 gpio support in omap4

Signed-off-by Aneesh V <[email protected]>

---
V2:
* Added a new file that was accidentally missing in v1

V3:
* Fix build break for other boards by restoring the old header files <asm/arch/gpio.h>

Resending with v3 TAG in the subject line.

---
 arch/arm/cpu/armv7/omap-common/Makefile            |    1 +
 arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c   |   39 +++++--------
 arch/arm/cpu/armv7/omap3/Makefile                  |    1 -
 arch/arm/cpu/armv7/omap3/board.c                   |   12 ++++
 arch/arm/cpu/armv7/omap4/board.c                   |   12 ++++
 arch/arm/cpu/armv7/omap4/clocks.c                  |    2 +-
 arch/arm/include/asm/arch-omap3/cpu.h              |   26 +++++++++
 arch/arm/include/asm/arch-omap3/gpio.h             |   56 ++++----------------
 arch/arm/include/asm/arch-omap3/omap3.h            |    8 ---
 arch/arm/include/asm/arch-omap4/cpu.h              |   26 +++++++++
 arch/arm/include/asm/arch-omap4/gpio.h             |   50 +++++++++++++++++
 .../include/asm/{arch-omap3/gpio.h => omap_gpio.h} |   27 +--------
 board/pandora/pandora.c                            |    1 +
 13 files changed, 157 insertions(+), 104 deletions(-)
 rename arch/arm/cpu/armv7/{omap3 => omap-common}/gpio.c (77%)
 create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h
 copy arch/arm/include/asm/{arch-omap3/gpio.h => omap_gpio.h} (67%)

arch/arm/cpu/armv7/omap-common/Makefile +1 -0

index 0708796..ea9f8ec 100644
@@ -29,6 +29,7 @@ SOBJS	:= reset.o
 
 COBJS	:= timer.o
 COBJS	+= utils.o
+COBJS	+= gpio.o
 
 ifdef CONFIG_SPL_BUILD
 COBJS	+= spl.o

arch/arm/cpu/armv7/omap-common/gpio.c renamed from arch/arm/cpu/armv7/omap3/gpio.c +15 ~~-24~~

similarity index 77%
rename from arch/arm/cpu/armv7/omap3/gpio.c
rename to arch/arm/cpu/armv7/omap-common/gpio.c
index aeb6066..2fcaf5a 100644
@@ -40,20 +40,9 @@
 #include <asm/io.h>
 #include <asm/errno.h>
 
-static struct gpio_bank gpio_bank_34xx[6] = {
-	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
-	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
-};
-
-static struct gpio_bank *gpio_bank = &gpio_bank_34xx[0];
-
-static inline struct gpio_bank *get_gpio_bank(int gpio)
+static inline const struct gpio_bank *get_gpio_bank(int gpio)
 {
-	return &gpio_bank[gpio >> 5];
+	return &omap_gpio_bank[gpio >> 5];
 }
 
 static inline int get_gpio_index(int gpio)

@@ -79,14 +68,15 @@ static int check_gpio(int gpio)
 	return 0;
 }
 
-static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
+static void _set_gpio_direction(const struct gpio_bank *bank, int gpio,
+				int is_input)
 {
 	void *reg = bank->base;
 	u32 l;
 
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_OE;
+		reg += OMAP_GPIO_OE;
 		break;
 	default:
 		return;

@@ -101,7 +91,7 @@ static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
 
 void omap_set_gpio_direction(int gpio, int is_input)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

@@ -109,7 +99,8 @@ void omap_set_gpio_direction(int gpio, int is_input)
 	_set_gpio_direction(bank, get_gpio_index(gpio), is_input);
 }
 
-static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
+static void _set_gpio_dataout(const struct gpio_bank *bank, int gpio,
+				int enable)
 {
 	void *reg = bank->base;
 	u32 l = 0;

@@ -117,9 +108,9 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
 		if (enable)
-			reg += OMAP24XX_GPIO_SETDATAOUT;
+			reg += OMAP_GPIO_SETDATAOUT;
 		else
-			reg += OMAP24XX_GPIO_CLEARDATAOUT;
+			reg += OMAP_GPIO_CLEARDATAOUT;
 		l = 1 << gpio;
 		break;
 	default:

@@ -132,7 +123,7 @@ static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
 
 void omap_set_gpio_dataout(int gpio, int enable)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

@@ -142,7 +133,7 @@ void omap_set_gpio_dataout(int gpio, int enable)
 
 int omap_get_gpio_datain(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 	void *reg;
 
 	if (check_gpio(gpio) < 0)

@@ -151,7 +142,7 @@ int omap_get_gpio_datain(int gpio)
 	reg = bank->base;
 	switch (bank->method) {
 	case METHOD_GPIO_24XX:
-		reg += OMAP24XX_GPIO_DATAIN;
+		reg += OMAP_GPIO_DATAIN;
 		break;
 	default:
 		return -EINVAL;

@@ -160,7 +151,7 @@ int omap_get_gpio_datain(int gpio)
 			& (1 << get_gpio_index(gpio))) != 0;
 }
 
-static void _reset_gpio(struct gpio_bank *bank, int gpio)
+static void _reset_gpio(const struct gpio_bank *bank, int gpio)
 {
 	_set_gpio_direction(bank, get_gpio_index(gpio), 1);
 }

@@ -175,7 +166,7 @@ int omap_request_gpio(int gpio)
 
 void omap_free_gpio(int gpio)
 {
-	struct gpio_bank *bank;
+	const struct gpio_bank *bank;
 
 	if (check_gpio(gpio) < 0)
 		return;

arch/arm/cpu/armv7/omap3/Makefile +0 -1

index 522bcd2..8e85891 100644
@@ -29,7 +29,6 @@ SOBJS	:= lowlevel_init.o
 
 COBJS	+= board.o
 COBJS	+= clock.o
-COBJS	+= gpio.o
 COBJS	+= mem.o
 COBJS	+= sys_info.o

arch/arm/cpu/armv7/omap3/board.c +12 -0

index 98519a9..bce3ee6 100644
@@ -38,12 +38,24 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
+#include <asm/arch/gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
 static void omap3_setup_aux_cr(void);
 static void omap3_invalidate_l2_cache_secure(void);
 
+static const struct gpio_bank gpio_bank_34xx[6] = {
+	{ (void *)OMAP34XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP34XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
+
 /******************************************************************************
  * Routine: delay
  * Description: spinning delay to use before udelay works

arch/arm/cpu/armv7/omap4/board.c +12 -0

index 17e731a..08fc949 100644
@@ -33,12 +33,24 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
+#include <asm/arch/gpio.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
 u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV;
 
+static const struct gpio_bank gpio_bank_44xx[6] = {
+	{ (void *)OMAP44XX_GPIO1_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO2_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO3_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO4_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO5_BASE, METHOD_GPIO_24XX },
+	{ (void *)OMAP44XX_GPIO6_BASE, METHOD_GPIO_24XX },
+};
+
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_44xx;
+
 #ifdef CONFIG_SPL_BUILD
 /*
  * We use static variables because global data is not ready yet.

arch/arm/cpu/armv7/omap4/clocks.c +1 -1

index f1e233a..660b329 100644
@@ -830,9 +830,9 @@ void prcm_init(void)
 	case OMAP_INIT_CONTEXT_SPL:
 	case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR:
 	case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH:
+		enable_basic_clocks();
 		scale_vcores();
 		setup_dplls();
-		enable_basic_clocks();
 		setup_non_essential_dplls();
 		enable_non_essential_clocks();
 		break;

arch/arm/include/asm/arch-omap3/cpu.h +26 -0

index e944de7..08a725d 100644
@@ -498,4 +498,30 @@ struct pm {
 /* MUSB base */
 #define MUSB_BASE		(OMAP34XX_CORE_L4_IO_BASE + 0xAB000)
 
+/* OMAP3 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0014
+#define OMAP_GPIO_IRQSTATUS1		0x0018
+#define OMAP_GPIO_IRQSTATUS2		0x0028
+#define OMAP_GPIO_IRQENABLE2		0x002c
+#define OMAP_GPIO_IRQENABLE1		0x001c
+#define OMAP_GPIO_WAKE_EN		0x0020
+#define OMAP_GPIO_CTRL			0x0030
+#define OMAP_GPIO_OE			0x0034
+#define OMAP_GPIO_DATAIN		0x0038
+#define OMAP_GPIO_DATAOUT		0x003c
+#define OMAP_GPIO_LEVELDETECT0		0x0040
+#define OMAP_GPIO_LEVELDETECT1		0x0044
+#define OMAP_GPIO_RISINGDETECT		0x0048
+#define OMAP_GPIO_FALLINGDETECT		0x004c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0050
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0054
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0060
+#define OMAP_GPIO_SETIRQENABLE1		0x0064
+#define OMAP_GPIO_CLEARWKUENA		0x0080
+#define OMAP_GPIO_SETWKUENA		0x0084
+#define OMAP_GPIO_CLEARDATAOUT		0x0090
+#define OMAP_GPIO_SETDATAOUT		0x0094
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap3/gpio.h +10 ~~-46~~

62 lines not on this page · raw message

arch/arm/include/asm/arch-omap3/omap3.h +0 -8

index d9d49da..230eaad 100644
@@ -100,14 +100,6 @@ struct s32ktimer {
 
 #endif /* __ASSEMBLY__ */
 
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE		0x48310000
-#define OMAP34XX_GPIO2_BASE		0x49050000
-#define OMAP34XX_GPIO3_BASE		0x49052000
-#define OMAP34XX_GPIO4_BASE		0x49054000
-#define OMAP34XX_GPIO5_BASE		0x49056000
-#define OMAP34XX_GPIO6_BASE		0x49058000
-
 #ifndef __ASSEMBLY__
 struct gpio {
 	unsigned char res1[0x34];

arch/arm/include/asm/arch-omap4/cpu.h +26 -0

index 7d5748a..08b9c99 100644
@@ -142,4 +142,30 @@ struct watchdog {
 /* MUSB base */
 #define MUSB_BASE		(OMAP44XX_L4_CORE_BASE + 0xAB000)
 
+/* OMAP4 GPIO registers */
+#define OMAP_GPIO_REVISION		0x0000
+#define OMAP_GPIO_SYSCONFIG		0x0010
+#define OMAP_GPIO_SYSSTATUS		0x0114
+#define OMAP_GPIO_IRQSTATUS1		0x0118
+#define OMAP_GPIO_IRQSTATUS2		0x0128
+#define OMAP_GPIO_IRQENABLE2		0x012c
+#define OMAP_GPIO_IRQENABLE1		0x011c
+#define OMAP_GPIO_WAKE_EN		0x0120
+#define OMAP_GPIO_CTRL			0x0130
+#define OMAP_GPIO_OE			0x0134
+#define OMAP_GPIO_DATAIN		0x0138
+#define OMAP_GPIO_DATAOUT		0x013c
+#define OMAP_GPIO_LEVELDETECT0		0x0140
+#define OMAP_GPIO_LEVELDETECT1		0x0144
+#define OMAP_GPIO_RISINGDETECT		0x0148
+#define OMAP_GPIO_FALLINGDETECT		0x014c
+#define OMAP_GPIO_DEBOUNCE_EN		0x0150
+#define OMAP_GPIO_DEBOUNCE_VAL		0x0154
+#define OMAP_GPIO_CLEARIRQENABLE1	0x0160
+#define OMAP_GPIO_SETIRQENABLE1		0x0164
+#define OMAP_GPIO_CLEARWKUENA		0x0180
+#define OMAP_GPIO_SETWKUENA		0x0184
+#define OMAP_GPIO_CLEARDATAOUT		0x0190
+#define OMAP_GPIO_SETDATAOUT		0x0194
+
 #endif /* _CPU_H */

arch/arm/include/asm/arch-omap4/gpio.h new file +50 -0

50 lines not on this page · raw message

arch/arm/include/asm/omap_gpio.h renamed from arch/arm/include/asm/arch-omap3/gpio.h +3 ~~-24~~

similarity index 67%
copy from arch/arm/include/asm/arch-omap3/gpio.h
copy to arch/arm/include/asm/omap_gpio.h
index 30f633c..3089e1c 100644
@@ -38,36 +38,15 @@
 #ifndef _GPIO_H
 #define _GPIO_H
 
-#define OMAP24XX_GPIO_REVISION		0x0000
-#define OMAP24XX_GPIO_SYSCONFIG		0x0010
-#define OMAP24XX_GPIO_SYSSTATUS		0x0014
-#define OMAP24XX_GPIO_IRQSTATUS1	0x0018
-#define OMAP24XX_GPIO_IRQSTATUS2	0x0028
-#define OMAP24XX_GPIO_IRQENABLE2	0x002c
-#define OMAP24XX_GPIO_IRQENABLE1	0x001c
-#define OMAP24XX_GPIO_WAKE_EN		0x0020
-#define OMAP24XX_GPIO_CTRL		0x0030
-#define OMAP24XX_GPIO_OE		0x0034
-#define OMAP24XX_GPIO_DATAIN		0x0038
-#define OMAP24XX_GPIO_DATAOUT		0x003c
-#define OMAP24XX_GPIO_LEVELDETECT0	0x0040
-#define OMAP24XX_GPIO_LEVELDETECT1	0x0044
-#define OMAP24XX_GPIO_RISINGDETECT	0x0048
-#define OMAP24XX_GPIO_FALLINGDETECT	0x004c
-#define OMAP24XX_GPIO_DEBOUNCE_EN	0x0050
-#define OMAP24XX_GPIO_DEBOUNCE_VAL	0x0054
-#define OMAP24XX_GPIO_CLEARIRQENABLE1	0x0060
-#define OMAP24XX_GPIO_SETIRQENABLE1	0x0064
-#define OMAP24XX_GPIO_CLEARWKUENA	0x0080
-#define OMAP24XX_GPIO_SETWKUENA		0x0084
-#define OMAP24XX_GPIO_CLEARDATAOUT	0x0090
-#define OMAP24XX_GPIO_SETDATAOUT	0x0094
+#include <asm/arch/cpu.h>
 
 struct gpio_bank {
 	void *base;
 	int method;
 };
 
+extern const struct gpio_bank *const omap_gpio_bank;
+
 #define METHOD_GPIO_24XX	4
 
 /* This is the interface */

board/pandora/pandora.c +1 -0

index 992e9f7..fe363b2 100644
@@ -34,6 +34,7 @@
 #include <asm/io.h>
 #include <asm/arch/mux.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/arch/gpio.h>
 #include <asm/mach-types.h>
 #include "pandora.h"

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-08-01 06:30 UTC #20 lore raw

PATCH 1/1 omap: fix gpio related build breaks

In reply to Aneesh V

Signed-off-by Aneesh V <[email protected]>

---
Hi Sandeep,
This is an incremental patch to fix the build issues created by "[PATCH 3/5] omap: reuse omap3 gpio support in omap4" in the omap4460 series.

---
 arch/arm/cpu/armv7/omap-common/gpio.c   |    2 +-
 arch/arm/cpu/armv7/omap3/board.c        |    2 +-
 arch/arm/cpu/armv7/omap4/board.c        |    2 +-
 arch/arm/include/asm/arch-omap3/gpio.h  |   50 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap3/omap3.h |    8 -----
 arch/arm/include/asm/arch-omap4/gpio.h  |   50 +++++++++++++++++++++++++++++++
 arch/arm/include/asm/arch-omap4/omap4.h |    8 -----
 board/pandora/pandora.c                 |    1 +
 8 files changed, 104 insertions(+), 19 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-omap3/gpio.h
 create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h

arch/arm/cpu/armv7/omap-common/gpio.c +1 -1

index f4c3479..2fcaf5a 100644
@@ -36,7 +36,7 @@
  * published by the Free Software Foundation.
  */
 #include <common.h>
-#include <asm/omap_gpio.h>
+#include <asm/arch/gpio.h>
 #include <asm/io.h>
 #include <asm/errno.h>

arch/arm/cpu/armv7/omap3/board.c +1 -1

index 4aaf97b..bce3ee6 100644
@@ -38,7 +38,7 @@
 #include <asm/arch/mem.h>
 #include <asm/cache.h>
 #include <asm/armv7.h>
-#include <asm/omap_gpio.h>
+#include <asm/arch/gpio.h>
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;

arch/arm/cpu/armv7/omap4/board.c +1 -1

index 5943d61..8e90545 100644
@@ -33,7 +33,7 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/sizes.h>
 #include <asm/arch/emif.h>
-#include <asm/omap_gpio.h>
+#include <asm/arch/gpio.h>
 #include "omap4_mux_data.h"
 
 DECLARE_GLOBAL_DATA_PTR;

arch/arm/include/asm/arch-omap3/gpio.h new file +50 -0

50 lines not on this page · raw message

arch/arm/include/asm/arch-omap3/omap3.h +0 -8

index d9d49da..230eaad 100644
@@ -100,14 +100,6 @@ struct s32ktimer {
 
 #endif /* __ASSEMBLY__ */
 
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE		0x48310000
-#define OMAP34XX_GPIO2_BASE		0x49050000
-#define OMAP34XX_GPIO3_BASE		0x49052000
-#define OMAP34XX_GPIO4_BASE		0x49054000
-#define OMAP34XX_GPIO5_BASE		0x49056000
-#define OMAP34XX_GPIO6_BASE		0x49058000
-
 #ifndef __ASSEMBLY__
 struct gpio {
 	unsigned char res1[0x34];

arch/arm/include/asm/arch-omap4/gpio.h new file +50 -0

50 lines not on this page · raw message

arch/arm/include/asm/arch-omap4/omap4.h +0 -8

index 9aad0e6..7ff46d7 100644
@@ -153,12 +153,4 @@ struct s32ktimer {
 #define DEV_DATA_PTR_OFFSET	0x18
 #define BOOT_MODE_OFFSET	0x8
 
-/* GPIO */
-#define OMAP44XX_GPIO1_BASE		0x4A310000
-#define OMAP44XX_GPIO2_BASE		0x48055000
-#define OMAP44XX_GPIO3_BASE		0x48057000
-#define OMAP44XX_GPIO4_BASE		0x48059000
-#define OMAP44XX_GPIO5_BASE		0x4805B000
-#define OMAP44XX_GPIO6_BASE		0x4805D000
-
 #endif

board/pandora/pandora.c +1 -0

index 992e9f7..0df4570 100644
@@ -33,6 +33,7 @@
 #include <twl4030.h>
 #include <asm/io.h>
 #include <asm/arch/mux.h>
+#include <asm/arch/gpio.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-types.h>
 #include "pandora.h"

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-08-05 06:43 UTC #21 lore raw

PATCH 1/1 omap: fix gpio related build breaks

Hi Sandeep, Albert, Wolfgang,

Quoted 6 lines · Aneesh V

Signed-off-by Aneesh V<[email protected]>
---
Hi Sandeep,
This is an incremental patch to fix the build issues created by "[PATCH 3/5] omap: reuse omap3 gpio support in omap4" in the omap4460 series.

You will need this patch to prevent build break for some OMAP3 boards. Will you please pull this too if it looks ok?

br,
Aneesh

Dirk Behme

2011-08-08 14:54 UTC #22 lore raw

PATCH 1/1 omap: fix gpio related build breaks

In reply to Aneesh V

Quoted 1 line · Aneesh V

Signed-off-by Aneesh V<[email protected]>

Acked-by Dirk Behme <[email protected]>

Quoted 224 lines

---
Hi Sandeep,
This is an incremental patch to fix the build issues created by "[PATCH 3/5] omap: reuse omap3 gpio support in omap4" in the omap4460 series.

---
  arch/arm/cpu/armv7/omap-common/gpio.c   |    2 +-
  arch/arm/cpu/armv7/omap3/board.c        |    2 +-
  arch/arm/cpu/armv7/omap4/board.c        |    2 +-
  arch/arm/include/asm/arch-omap3/gpio.h  |   50 +++++++++++++++++++++++++++++++
  arch/arm/include/asm/arch-omap3/omap3.h |    8 -----
  arch/arm/include/asm/arch-omap4/gpio.h  |   50 +++++++++++++++++++++++++++++++
  arch/arm/include/asm/arch-omap4/omap4.h |    8 -----
  board/pandora/pandora.c                 |    1 +
  8 files changed, 104 insertions(+), 19 deletions(-)

create mode 100644 arch/arm/include/asm/arch-omap3/gpio.h create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h

arch/arm/cpu/armv7/omap-common/gpio.c +1 -1

index f4c3479..2fcaf5a 100644
@@ -36,7 +36,7 @@
   * published by the Free Software Foundation.
   */
  #include<common.h>
-#include<asm/omap_gpio.h>
+#include<asm/arch/gpio.h>
  #include<asm/io.h>
  #include<asm/errno.h>

arch/arm/cpu/armv7/omap3/board.c +1 -1

index 4aaf97b..bce3ee6 100644
@@ -38,7 +38,7 @@
  #include<asm/arch/mem.h>
  #include<asm/cache.h>
  #include<asm/armv7.h>
-#include<asm/omap_gpio.h>
+#include<asm/arch/gpio.h>
 
  /* Declarations */
  extern omap3_sysinfo sysinfo;

arch/arm/cpu/armv7/omap4/board.c +1 -1

index 5943d61..8e90545 100644
@@ -33,7 +33,7 @@
  #include<asm/arch/sys_proto.h>
  #include<asm/sizes.h>
  #include<asm/arch/emif.h>
-#include<asm/omap_gpio.h>
+#include<asm/arch/gpio.h>
  #include "omap4_mux_data.h"
 
  DECLARE_GLOBAL_DATA_PTR;

arch/arm/include/asm/arch-omap3/gpio.h new file +50 -0

new file mode 100644
index 0000000..8bba3b0
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix<[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrj??l??<[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_OMAP3_H
+#define _GPIO_OMAP3_H
+
+#include<asm/omap_gpio.h>
+
+#define OMAP34XX_GPIO1_BASE		0x48310000
+#define OMAP34XX_GPIO2_BASE		0x49050000
+#define OMAP34XX_GPIO3_BASE		0x49052000
+#define OMAP34XX_GPIO4_BASE		0x49054000
+#define OMAP34XX_GPIO5_BASE		0x49056000
+#define OMAP34XX_GPIO6_BASE		0x49058000
+
+#endif /* _GPIO_OMAP3_H */

arch/arm/include/asm/arch-omap3/omap3.h +0 -8

index d9d49da..230eaad 100644
@@ -100,14 +100,6 @@ struct s32ktimer {
 
  #endif /* __ASSEMBLY__ */
 
-/* OMAP3 GPIO registers */
-#define OMAP34XX_GPIO1_BASE		0x48310000
-#define OMAP34XX_GPIO2_BASE		0x49050000
-#define OMAP34XX_GPIO3_BASE		0x49052000
-#define OMAP34XX_GPIO4_BASE		0x49054000
-#define OMAP34XX_GPIO5_BASE		0x49056000
-#define OMAP34XX_GPIO6_BASE		0x49058000
-
  #ifndef __ASSEMBLY__
  struct gpio {
  	unsigned char res1[0x34];

arch/arm/include/asm/arch-omap4/gpio.h new file +50 -0

new file mode 100644
index 0000000..26f19d1
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2009 Wind River Systems, Inc.
+ * Tom Rix<[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * This work is derived from the linux 2.6.27 kernel source
+ * To fetch, use the kernel repository
+ * git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
+ * Use the v2.6.27 tag.
+ *
+ * Below is the original's header including its copyright
+ *
+ *  linux/arch/arm/plat-omap/gpio.c
+ *
+ * Support functions for OMAP GPIO
+ *
+ * Copyright (C) 2003-2005 Nokia Corporation
+ * Written by Juha Yrj??l??<[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef _GPIO_OMAP4_H
+#define _GPIO_OMAP4_H
+
+#include<asm/omap_gpio.h>
+
+#define OMAP44XX_GPIO1_BASE		0x4A310000
+#define OMAP44XX_GPIO2_BASE		0x48055000
+#define OMAP44XX_GPIO3_BASE		0x48057000
+#define OMAP44XX_GPIO4_BASE		0x48059000
+#define OMAP44XX_GPIO5_BASE		0x4805B000
+#define OMAP44XX_GPIO6_BASE		0x4805D000
+
+#endif /* _GPIO_OMAP4_H */

arch/arm/include/asm/arch-omap4/omap4.h +0 -8

index 9aad0e6..7ff46d7 100644
@@ -153,12 +153,4 @@ struct s32ktimer {
  #define DEV_DATA_PTR_OFFSET	0x18
  #define BOOT_MODE_OFFSET	0x8
 
-/* GPIO */
-#define OMAP44XX_GPIO1_BASE		0x4A310000
-#define OMAP44XX_GPIO2_BASE		0x48055000
-#define OMAP44XX_GPIO3_BASE		0x48057000
-#define OMAP44XX_GPIO4_BASE		0x48059000
-#define OMAP44XX_GPIO5_BASE		0x4805B000
-#define OMAP44XX_GPIO6_BASE		0x4805D000
-
  #endif

board/pandora/pandora.c +1 -0

index 992e9f7..0df4570 100644
@@ -33,6 +33,7 @@
  #include<twl4030.h>
  #include<asm/io.h>
  #include<asm/arch/mux.h>
+#include<asm/arch/gpio.h>
  #include<asm/arch/sys_proto.h>
  #include<asm/mach-types.h>
  #include "pandora.h"

_______________________________________________
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U-Boot at lists.denx.de
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Albert ARIBAUD

2011-08-20 15:30 UTC #23 lore raw

PATCH 1/1 omap: fix gpio related build breaks

In reply to Aneesh V

Hi Aneesh,

Le 01/08/2011 08:30, Aneesh V a ?crit :

Quoted 16 lines

Signed-off-by Aneesh V<[email protected]>

---
Hi Sandeep,
This is an incremental patch to fix the build issues created by "[PATCH 3/5] omap: reuse omap3 gpio support in omap4" in the omap4460 series.

---
  arch/arm/cpu/armv7/omap-common/gpio.c   |    2 +-
  arch/arm/cpu/armv7/omap3/board.c        |    2 +-
  arch/arm/cpu/armv7/omap4/board.c        |    2 +-
  arch/arm/include/asm/arch-omap3/gpio.h  |   50 +++++++++++++++++++++++++++++++
  arch/arm/include/asm/arch-omap3/omap3.h |    8 -----
  arch/arm/include/asm/arch-omap4/gpio.h  |   50 +++++++++++++++++++++++++++++++
  arch/arm/include/asm/arch-omap4/omap4.h |    8 -----
  board/pandora/pandora.c                 |    1 +
  8 files changed, 104 insertions(+), 19 deletions(-)

Quoted 2 lines

create mode 100644 arch/arm/include/asm/arch-omap3/gpio.h create mode 100644 arch/arm/include/asm/arch-omap4/gpio.h

Applied to u-boot-arm/master with Sandeep's agreement, thanks!

Amicalement,

Signature · 1 line

Albert.

Aneesh V

author

2011-07-20 10:55 UTC #24 lore raw

PATCH v2 4/5 omap4: support TPS programming

In reply to Aneesh V

TPS62361 is the new power supply used in OMAP4460 that supplies vdd_mpu.

VCORE1 from Phoenix supplies vdd_core and VCORE2 supplies vdd_iva. VCORE3 is not used in OMAP4460.

Signed-off-by Aneesh V <[email protected]>

---
 arch/arm/cpu/armv7/omap4/board.c            |    4 ++
 arch/arm/cpu/armv7/omap4/clocks.c           |   65 ++++++++++++++++++++++++---
 arch/arm/include/asm/arch-omap4/clocks.h    |   16 +++++++
 arch/arm/include/asm/arch-omap4/mux_omap4.h |    1 +
 4 files changed, 79 insertions(+), 7 deletions(-)

arch/arm/cpu/armv7/omap4/board.c +4 -0

index 3c61b1c..5943d61 100644
@@ -90,6 +90,10 @@ static void set_muxconf_regs_essential(void)
 	do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential,
 		   sizeof(wkup_padconf_array_essential) /
 		   sizeof(struct pad_conf_entry));
+
+	/* gpio_wk7 is used for controlling TPS on 4460 */
+	if (omap_revision() >= OMAP4460_ES1_0)
+		writew(M3, CONTROL_WKUP_PAD1_FREF_CLK4_REQ);
 }
 
 static void set_mux_conf_regs(void)

arch/arm/cpu/armv7/omap4/clocks.c +58 -7

100 lines not on this page · raw message

arch/arm/include/asm/arch-omap4/clocks.h +16 -0

index 37bdcee..5d9cb50 100644
@@ -618,6 +618,7 @@ struct omap4_prcm_regs {
 #define PRM_VC_VAL_BYPASS_DATA_SHIFT		16
 #define PRM_VC_VAL_BYPASS_DATA_MASK		0xFF
 
+/* SMPS */
 #define SMPS_I2C_SLAVE_ADDR	0x12
 #define SMPS_REG_ADDR_VCORE1	0x55
 #define SMPS_REG_ADDR_VCORE2	0x5B

@@ -626,6 +627,21 @@ struct omap4_prcm_regs {
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV		607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV	709000
 
+/* TPS */
+#define TPS62361_I2C_SLAVE_ADDR		0x60
+#define TPS62361_REG_ADDR_SET0		0x0
+#define TPS62361_REG_ADDR_SET1		0x1
+#define TPS62361_REG_ADDR_SET2		0x2
+#define TPS62361_REG_ADDR_SET3		0x3
+#define TPS62361_REG_ADDR_CTRL		0x4
+#define TPS62361_REG_ADDR_TEMP		0x5
+#define TPS62361_REG_ADDR_RMP_CTRL	0x6
+#define TPS62361_REG_ADDR_CHIP_ID	0x8
+#define TPS62361_REG_ADDR_CHIP_ID_2	0x9
+
+#define TPS62361_BASE_VOLT_MV	500
+#define TPS62361_VSEL0_GPIO	7
+
 /* Defines for DPLL setup */
 #define DPLL_LOCKED_FREQ_TOLERANCE_0		0
 #define DPLL_LOCKED_FREQ_TOLERANCE_500_KHZ	500

arch/arm/include/asm/arch-omap4/mux_omap4.h +1 -0

index 019574b..30bfad7 100644
@@ -341,4 +341,5 @@ struct pad_conf_entry {
 #define CONTROL_SPARE_R		0x0618
 #define CONTROL_SPARE_R_C0		0x061C
 
+#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ	0x4A31E05A
 #endif /* _MUX_OMAP4_H_ */

Signature · 1 line

1.7.0.4

Aneesh V

author

2011-07-20 10:55 UTC #25 lore raw

PATCH v2 5/5 omap4: clock init support for omap4460

In reply to Aneesh V

---
 arch/arm/cpu/armv7/omap4/clocks.c        |   61 ++++++++++++++++++++++++++---
 arch/arm/include/asm/arch-omap4/clocks.h |   12 +++++-
 2 files changed, 65 insertions(+), 8 deletions(-)

arch/arm/cpu/armv7/omap4/clocks.c +54 -7

index 0db9d18..eda960c 100644
@@ -66,7 +66,18 @@ static const u32 sys_clk_array[8] = {
  * Please use this tool for creating the table for any new frequency.
  */
 
-/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo) */
+/* dpll locked at 1840 MHz MPU clk at 920 MHz(OPP Turbo 4460) - DCC OFF */
+static const struct dpll_params mpu_dpll_params_1840mhz[NUM_SYS_CLKS] = {
+	{230, 2, 1, -1, -1, -1, -1, -1},	/* 12 MHz   */
+	{920, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */
+	{219, 3, 1, -1, -1, -1, -1, -1},	/* 16.8 MHz */
+	{575, 11, 1, -1, -1, -1, -1, -1},	/* 19.2 MHz */
+	{460, 12, 1, -1, -1, -1, -1, -1},	/* 26 MHz   */
+	{920, 26, 1, -1, -1, -1, -1, -1},	/* 27 MHz   */
+	{575, 23, 1, -1, -1, -1, -1, -1}	/* 38.4 MHz */
+};
+
+/* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
 static const struct dpll_params mpu_dpll_params_1584mhz[NUM_SYS_CLKS] = {
 	{66, 0, 1, -1, -1, -1, -1, -1},		/* 12 MHz   */
 	{792, 12, 1, -1, -1, -1, -1, -1},	/* 13 MHz   */

@@ -320,6 +331,47 @@ u32 omap4_ddr_clk(void)
 	return ddr_clk;
 }
 
+/*
+ * Lock MPU dpll
+ *
+ * Resulting MPU frequencies:
+ * 4430 ES1.0	: 600 MHz
+ * 4430 ES2.x	: 792 MHz (OPP Turbo)
+ * 4460		: 920 MHz (OPP Turbo) - DCC disabled
+ */
+void configure_mpu_dpll(void)
+{
+	const struct dpll_params *params;
+	struct dpll_regs *mpu_dpll_regs;
+	u32 omap4_rev, sysclk_ind;
+
+	omap4_rev = omap_revision();
+	sysclk_ind = get_sys_clk_index();
+
+	if (omap4_rev == OMAP4430_ES1_0)
+		params = &mpu_dpll_params_1200mhz[sysclk_ind];
+	else if (omap4_rev < OMAP4460_ES1_0)
+		params = &mpu_dpll_params_1584mhz[sysclk_ind];
+	else
+		params = &mpu_dpll_params_1840mhz[sysclk_ind];
+
+	/* DCC and clock divider settings for 4460 */
+	if (omap4_rev >= OMAP4460_ES1_0) {
+		mpu_dpll_regs =
+			(struct dpll_regs *)&prcm->cm_clkmode_dpll_mpu;
+		bypass_dpll(&prcm->cm_clkmode_dpll_mpu);
+		clrbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK);
+		setbits_le32(&prcm->cm_mpu_mpu_clkctrl,
+			MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK);
+		clrbits_le32(&mpu_dpll_regs->cm_clksel_dpll,
+			CM_CLKSEL_DCC_EN_MASK);
+	}
+
+	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
+	debug("MPU DPLL locked\n");
+}
+
 static void setup_dplls(void)
 {
 	u32 sysclk_ind, temp;

@@ -349,12 +401,7 @@ static void setup_dplls(void)
 	debug("PER DPLL locked\n");
 
 	/* MPU dpll */
-	if (omap_revision() == OMAP4430_ES1_0)
-		params = &mpu_dpll_params_1200mhz[sysclk_ind];
-	else
-		params = &mpu_dpll_params_1584mhz[sysclk_ind];
-	do_setup_dpll(&prcm->cm_clkmode_dpll_mpu, params, DPLL_LOCK);
-	debug("MPU DPLL locked\n");
+	configure_mpu_dpll();
 }
 
 static void setup_non_essential_dplls(void)

arch/arm/include/asm/arch-omap4/clocks.h +11 -1

index 5d9cb50..374e064 100644
@@ -105,9 +105,11 @@ struct omap4_prcm_regs {
 	u32 cm_ssc_deltamstep_dpll_ddrphy;
 	u32 pad014[5];
 	u32 cm_shadow_freq_config1;
+	u32 pad0141[47];
+	u32 cm_mpu_mpu_clkctrl;
 
 	/* cm1.dsp */
-	u32 pad015[103];
+	u32 pad015[55];
 	u32 cm_dsp_clkstctrl;
 	u32 pad016[7];
 	u32 cm_dsp_dsp_clkctrl;

@@ -515,6 +517,8 @@ struct omap4_prcm_regs {
 #define CM_CLKSEL_DPLL_M_MASK			(0x7FF << 8)
 #define CM_CLKSEL_DPLL_N_SHIFT			0
 #define CM_CLKSEL_DPLL_N_MASK			0x7F
+#define CM_CLKSEL_DCC_EN_SHIFT			22
+#define CM_CLKSEL_DCC_EN_MASK			(1 << 22)
 
 #define OMAP4_DPLL_MAX_N	127

@@ -596,6 +600,12 @@ struct omap4_prcm_regs {
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK	8
 
+/* CM_MPU_MPU_CLKCTRL */
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT	24
+#define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK	(1 << 24)
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_SHIFT	25
+#define MPU_CLKCTRL_CLKSEL_ABE_DIV_MODE_MASK	(1 << 25)
+
 /* Clock frequencies */
 #define OMAP_SYS_CLK_FREQ_38_4_MHZ	38400000
 #define OMAP_SYS_CLK_IND_38_4_MHZ	6

Signature · 1 line

1.7.0.4