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mx53: ddr3: Update DD3 initialization

PATCH New Fabio Estevam 2 participants 2 messages Aug 19, 2011 – Aug 22, 2011 Arm i.MX and Layerscape

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Fabio Estevam

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PATCH 1/1 mx53: ddr3: Update DD3 initialization

Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])

Signed-off-by Lily Zhang <[email protected]>
Signed-off-by Fabio Estevam <[email protected]>
---
 board/freescale/mx53ard/imximage_dd3.cfg |    6 +++---
 board/freescale/mx53loco/imximage.cfg    |    6 +++---
 board/freescale/mx53smd/imximage.cfg     |    6 +++---
 3 files changed, 9 insertions(+), 9 deletions(-)
board/freescale/mx53ard/imximage_dd3.cfg +3 -3
index 0f298ab..50e05af 100644
@@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d
 DATA 4 0x63fd901c 0x00008032
 DATA 4 0x63fd901c 0x00008033
 DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x052080b0
 DATA 4 0x63fd901c 0x04008040
 DATA 4 0x63fd901c 0x0000803a
 DATA 4 0x63fd901c 0x0000803b
 DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9020 0x00005800
 DATA 4 0x63fd9040 0x04b80003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901C 0x00000000
board/freescale/mx53loco/imximage.cfg +3 -3
index ce9c8fc..f30258e 100644
@@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d
 DATA 4 0x63fd901c 0x00008032
 DATA 4 0x63fd901c 0x00008033
 DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x052080b0
 DATA 4 0x63fd901c 0x04008040
 DATA 4 0x63fd901c 0x0000803a
 DATA 4 0x63fd901c 0x0000803b
 DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9020 0x00005800
 DATA 4 0x63fd9040 0x04b80003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901c 0x00000000
board/freescale/mx53smd/imximage.cfg +3 -3
index 0f298ab..50e05af 100644
@@ -83,14 +83,14 @@ DATA 4 0x63fd9004 0x0002002d
 DATA 4 0x63fd901c 0x00008032
 DATA 4 0x63fd901c 0x00008033
 DATA 4 0x63fd901c 0x00028031
-DATA 4 0x63fd901c 0x092080b0
+DATA 4 0x63fd901c 0x052080b0
 DATA 4 0x63fd901c 0x04008040
 DATA 4 0x63fd901c 0x0000803a
 DATA 4 0x63fd901c 0x0000803b
 DATA 4 0x63fd901c 0x00028039
-DATA 4 0x63fd901c 0x09208138
+DATA 4 0x63fd901c 0x05208138
 DATA 4 0x63fd901c 0x04008048
-DATA 4 0x63fd9020 0x00001800
+DATA 4 0x63fd9020 0x00005800
 DATA 4 0x63fd9040 0x04b80003
 DATA 4 0x63fd9058 0x00022227
 DATA 4 0x63fd901C 0x00000000
Signature · 1 line
1.6.0.4
#1 lore raw

PATCH 1/1 mx53: ddr3: Update DD3 initialization

Quoted 5 lines · Fabio Estevam

Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011:

(quoted diff) +0 -2
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from

"0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR])

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
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