ARM: l2x0: make sure I&D are not locked down on init
PATCH v2 1/1 ARM: l2x0: make sure I&D are not locked down on init
From: Linus Walleij <[email protected]>
Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state.
Cc Srinidhi Kasagar <[email protected]>
Cc Rabin Vincent <[email protected]>
Cc Adrian Bunk <[email protected]>
Cc Rob Herring <[email protected]>
Cc Catalin Marinas <[email protected]>
Cc Will Deacon <[email protected]>
Reported-by Jan Rinze <[email protected]>
Tested-by Robert Marklund <[email protected]>
Signed-off-by Linus Walleij <[email protected]>
--- arch/arm/include/asm/hardware/cache-l2x0.h | 9 +++++++-- arch/arm/mm/cache-l2x0.c | 21 +++++++++++++++++++++ 2 files changed, 28 insertions(+), 2 deletions(-)
arch/arm/include/asm/hardware/cache-l2x0.h +7 -2
@@ -45,8 +45,13 @@#define L2X0_CLEAN_INV_LINE_PA 0x7F0#define L2X0_CLEAN_INV_LINE_IDX 0x7F8#define L2X0_CLEAN_INV_WAY 0x7FC -#define L2X0_LOCKDOWN_WAY_D 0x900 -#define L2X0_LOCKDOWN_WAY_I 0x904 +/* +* The lockdown registers repeat 8 times for L310, the L210 has only one +* D and one I lockdown register at 0x0900 and 0x0904. +*/ +#define L2X0_LOCKDOWN_WAY_D_BASE 0x900 +#define L2X0_LOCKDOWN_WAY_I_BASE 0x904 +#define L2X0_LOCKDOWN_STRIDE 0x08#define L2X0_TEST_OPERATION 0xF00#define L2X0_LINE_DATA 0xF10#define L2X0_LINE_TAG 0xF30
arch/arm/mm/cache-l2x0.c +21 -0
@@ -277,6 +277,25 @@ static void l2x0_disable(void)spin_unlock_irqrestore (&l2x0_lock, flags); } +static void __init l2x0_unlock (__u32 cache_id) +{ +int lockregs; +int i; + +if (cache_id ==L2X0_CACHE_ID_PART_L310 ) + lockregs =8 ; +else +/* L210 and unknown types */ + lockregs =1 ; + +for (i =0 ; i < lockregs; i++) { +writel_relaxed (0x0 , l2x0_base +L2X0_LOCKDOWN_WAY_D_BASE + + i *L2X0_LOCKDOWN_STRIDE ); +writel_relaxed (0x0 , l2x0_base +L2X0_LOCKDOWN_WAY_I_BASE + + i *L2X0_LOCKDOWN_STRIDE ); + } +} +void __init l2x0_init (void __iomem *base,__u32 aux_val,__u32 aux_mask) {__u32 aux;
@@ -328,6 +347,8 @@ void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask)* accessing the below registers will fault. */ if (!(readl_relaxed (l2x0_base +L2X0_CTRL ) &1 )) { +/* Make sure that I&D is not locked down when starting */ +l2x0_unlock (cache_id);/* l2x0 controller is disabled */ writel_relaxed (aux, l2x0_base +L2X0_AUX_CTRL );
Signature · 1 line
1.7.3.2
PATCH v2 1/1 ARM: l2x0: make sure I&D are not locked down on init
Quoted 16 lines · Linus Walleij
From: Linus Walleij<[email protected]>
Fighting unfixed U-Boots and other beasts that may the cache in a locked-down state when starting the kernel, we make sure to disable all cache lock-down when initializing the l2x0 so we are in a known state.
Cc Srinidhi Kasagar<[email protected]>Cc Rabin Vincent<[email protected]>Cc Adrian Bunk<[email protected]>Cc Rob Herring<[email protected]>Cc Catalin Marinas<[email protected]>Cc Will Deacon<[email protected]>Reported-by Jan Rinze<[email protected]>Tested-by Robert Marklund<[email protected]>Signed-off-by Linus Walleij<[email protected]>
Quoted 1 line
---
Looks good to me.
Reviewed-by Santosh Shilimkar <[email protected]>
Regards
Santosh