powerpc/mpc8548cds: Fix booting message

PATCH New Zhao Chenhui 7 participants 31 messages Sep 13, 2011 – Nov 8, 2011

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Zhao Chenhui

author

2011-09-13 07:15 UTC #0 lore raw

PATCH 1/9 powerpc/mpc8548cds: Fix booting message

From: chenhui zhao <[email protected]>

Align the output for PCI. Replace "PCI" with "PCI1".

Signed-off-by Zhao Chenhui <[email protected]>

---
 board/freescale/mpc8548cds/mpc8548cds.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

board/freescale/mpc8548cds/mpc8548cds.c +3 -3

index f70a972..8ab9752 100644
@@ -120,7 +120,7 @@ void lbc_sdram_init(void)
 
 	puts("LBC SDRAM: ");
 	print_size(CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024,
-		   "\n       ");
+		   "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers

@@ -236,7 +236,7 @@ void pci_init_board(void)
 			law_size_bits(pci_info.io_size), pci_info.law);
 
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
+		printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
 			(pci_speed == 33333000) ? "33" :
 			(pci_speed == 66666000) ? "66" : "unknown",

@@ -261,7 +261,7 @@ void pci_init_board(void)
 		}
 #endif
 	} else {
-		printf("PCI: disabled\n");
+		printf("PCI1: disabled\n");
 	}
 
 	puts("\n");

Signature · 1 line

1.6.4.1

Zhao Chenhui

author

2011-09-13 07:15 UTC #1 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

From: chenhui zhao <[email protected]>

Use 33333333Hz for 33MHz, 66666666Hz for 66MHz.

Signed-off-by Ebony Zhu <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---
 board/freescale/common/cadmus.c         |    8 ++++----
 board/freescale/mpc8541cds/mpc8541cds.c |    6 +++---
 board/freescale/mpc8548cds/mpc8548cds.c |    4 ++--
 board/freescale/mpc8555cds/mpc8555cds.c |    6 +++---
 4 files changed, 12 insertions(+), 12 deletions(-)

board/freescale/common/cadmus.c +4 -4

index db54bc4..50b6e9f 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -61,12 +61,12 @@ get_clock_freq(void)
 	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
 
 	if (pci1_speed == 0) {
-		return 33000000;
+		return 33333333;
 	} else if (pci1_speed == 1) {
-		return 66000000;
+		return 66666666;
 	} else {
 		/* Really, unknown. Be safe? */
-		return 33000000;
+		return 33333333;
 	}
 }

board/freescale/mpc8541cds/mpc8541cds.c +3 -3

index 0d3752d..a314f5c 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2011 Freescale Semiconductor.
  *
  * (C) Copyright 2002 Scott McNutt <[email protected]>
  *

@@ -222,8 +222,8 @@ int checkboard (void)
 
 	printf("PCI1: %d bit, %s MHz, %s\n",
 		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
+		(pci1_speed == 33333333) ? "33" :
+		(pci1_speed == 66666666) ? "66" : "unknown",
 		pci1_clk_sel ? "sync" : "async");
 
 	if (pci_dual) {

board/freescale/mpc8548cds/mpc8548cds.c +2 -2

index 8ab9752..d9f79b9 100644
@@ -238,8 +238,8 @@ void pci_init_board(void)
 		pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
 		printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
 			(pci_32) ? 32 : 64,
-			(pci_speed == 33333000) ? "33" :
-			(pci_speed == 66666000) ? "66" : "unknown",
+			(pci_speed == 33333333) ? "33" :
+			(pci_speed == 66666666) ? "66" : "unknown",
 			pci_clk_sel ? "sync" : "async",
 			pci_agent ? "agent" : "host",
 			pci_arb ? "arbiter" : "external-arbiter",

board/freescale/mpc8555cds/mpc8555cds.c +3 -3

index 60d1758..4dda331 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004 Freescale Semiconductor.
+ * Copyright 2004, 2011 Freescale Semiconductor.
  *
  * See file CREDITS for list of people who contributed to this
  * project.

@@ -220,8 +220,8 @@ int checkboard (void)
 
 	printf("PCI1: %d bit, %s MHz, %s\n",
 		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
+		(pci1_speed == 33333333) ? "33" :
+		(pci1_speed == 66666666) ? "66" : "unknown",
 		pci1_clk_sel ? "sync" : "async");
 
 	if (pci_dual) {

Signature · 1 line

1.6.4.1

Wolfgang Denk

2011-09-13 09:57 UTC #2 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Dear Zhao Chenhui,

Quoted 3 lines · In message <[email protected]> you…

From: chenhui zhao <[email protected]>
Use 33333333Hz for 33MHz, 66666666Hz for 66MHz.

But that's actually wrong. 33333333 Hz is not 33 MHz, but 33.333333 MHz; on the other hand, 33 MHz is 33000000 Hz and not 33333333 Hz.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Killing is wrong.
	-- Losira, "That Which Survives", stardate unknown

Tabi Timur-B04825

2011-09-13 19:20 UTC #3 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

In reply to Zhao Chenhui

Review int checkboard (void) · line 226

Quoted 8 lines · Zhao Chenhui

(quoted diff) +2 -2

@@ -222,8 +222,8 @@ int checkboard (void)
 
 ? ? ? ?printf("PCI1: %d bit, %s MHz, %s\n",
 ? ? ? ? ? ? ? ?(pci1_32) ? 32 : 64,
- ? ? ? ? ? ? ? (pci1_speed == 33000000) ? "33" :
- ? ? ? ? ? ? ? (pci1_speed == 66000000) ? "66" : "unknown",
+ ? ? ? ? ? ? ? (pci1_speed == 33333333) ? "33" :
+ ? ? ? ? ? ? ? (pci1_speed == 66666666) ? "66" : "unknown",

I already told you on the internal mailing list to fix this, because it can never say "unknown". pci1_speed will always equal either 33333333 or 66666666. There is no way it can be set to anything else.

And Wolfgang is right -- this patch doesn't make any sense. Is the problem that pci1_speed is wrong, or is the problem that it's displaying the wrong value?

Signature · 2 lines

Timur Tabi
Linux kernel developer at Freescale

Scott Wood

2011-09-13 20:02 UTC #4 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 5 lines · On 09/13/2011 02:20 PM, Tabi Timur-B04825 wrote:

Quoted 2 lines · Zhao Chenhui
(quoted diff) +0 -0
@@ -222,8 +222,8 @@ int checkboard (void)
 

Quoted 10 lines

board/freescale/mpc8541cds/mpc8541cds.c int checkboard (void) · line 226
Quoted 6 lines
board/freescale/mpc8541cds/mpc8541cds.c +2 -2
       printf("PCI1: %d bit, %s MHz, %s\n",
               (pci1_32) ? 32 : 64,
-               (pci1_speed == 33000000) ? "33" :
-               (pci1_speed == 66000000) ? "66" : "unknown",
+               (pci1_speed == 33333333) ? "33" :
+               (pci1_speed == 66666666) ? "66" : "unknown",
I already told you on the internal mailing list to fix this, because it can never say "unknown". pci1_speed will always equal either 33333333 or 66666666. There is no way it can be set to anything else.

There's no way it can be 33333000, 66000000, etc. based on the board's crystal?

Not that "unknown" is the right response to those values, of course.

-Scott

Timur Tabi

2011-09-13 20:03 UTC #5 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 2 lines · Scott Wood

There's no way it can be 33333000, 66000000, etc. based on the board's crystal?

There is earlier code that sets pci1_speed to 33333333 if the speed is unknown.
So the actual value of pci1_speed is limited to those two numbers.

Signature · 2 lines

Timur Tabi
Linux kernel developer at Freescale

Scott Wood

2011-09-13 20:14 UTC #6 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 6 lines · Timur Tabi

Quoted 2 lines · Scott Wood
There's no way it can be 33333000, 66000000, etc. based on the board's crystal?
There is earlier code that sets pci1_speed to 33333333 if the speed is unknown.
So the actual value of pci1_speed is limited to those two numbers.

So you'll set the speed to 33333333 if the actual speed is 66000000? Even if it's 33000000, why force it to 33333333?

BTW, the PCI spec says things like "33 MHz" and "66 MHz". Is it compliant to have a bus run at 33333333 Hz (without 66MHz capable cards) or at 66666666 Hz?

-Scott

Timur Tabi

2011-09-13 20:18 UTC #7 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 1 line · Scott Wood

So you'll set the speed to 33333333 if the actual speed is 66000000?

I think so.

Quoted 1 line

Even if it's 33000000, why force it to 33333333?

That's a good question. Since the patch doesn't explain why it's making the change, there's no way for anyone to know. That makes it very difficult for people to review the patch, but I'm sure that Chenhui already knows that.

Signature · 2 lines

Timur Tabi
Linux kernel developer at Freescale

Zhao Chenhui

2011-09-14 11:36 UTC #8 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 4 lines · Timur Tabi

Quoted 1 line · Scott Wood
So you'll set the speed to 33333333 if the actual speed is 66000000?

Quoted 11 lines

I think so.
Quoted 1 line
Even if it's 33000000, why force it to 33333333?
That's a good question. Since the patch doesn't explain why it's making the change, there's no way for anyone to know. That makes it very difficult for people to review the patch, but I'm sure that Chenhui already knows that.
Signature · 2 lines
Timur Tabi
Linux kernel developer at Freescale

OK. I'll rewrite the description in the patch.

-chenhui

Wolfgang Denk

2011-09-13 20:14 UTC #9 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

In reply to Zhao Chenhui

Dear Zhao Chenhui,

In message <[email protected]> you wrote:
...

board/freescale/mpc8541cds/mpc8541cds.c int checkboard (void) · line 227

Quoted 7 lines

board/freescale/mpc8541cds/mpc8541cds.c +2 -2

 	printf("PCI1: %d bit, %s MHz, %s\n",
 		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
+		(pci1_speed == 33333333) ? "33" :
+		(pci1_speed == 66666666) ? "66" : "unknown",
 		pci1_clk_sel ? "sync" : "async");

Why cannot you simply write:

	...
	char buf[32];
	...
	printf("PCI1: %d bit, %s MHz, %ssync\n",
		(pci1_32) ? 32 : 64,
		strmhz(buf, pci1_speed),
		pci1_clk_sel ? "" : "a");

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The only time the world beats a path to your door is when you are  in
the bathroom.

Zhao Chenhui

2011-09-14 10:34 UTC #10 lore raw

PATCH 2/9 powerpc/mpc85xxcds: Fix PCI speed

Quoted 22 lines · Wolfgang Denk

Dear Zhao Chenhui,
In message <[email protected]> you wrote:
...
board/freescale/mpc8541cds/mpc8541cds.c int checkboard (void) · line 227
Quoted 7 lines
board/freescale/mpc8541cds/mpc8541cds.c +2 -2
 	printf("PCI1: %d bit, %s MHz, %s\n",
 		(pci1_32) ? 32 : 64,
-		(pci1_speed == 33000000) ? "33" :
-		(pci1_speed == 66000000) ? "66" : "unknown",
+		(pci1_speed == 33333333) ? "33" :
+		(pci1_speed == 66666666) ? "66" : "unknown",
 		pci1_clk_sel ? "sync" : "async");
Why cannot you simply write:
	...
	char buf[32];
	...
	printf("PCI1: %d bit, %s MHz, %ssync\n",
		(pci1_32) ? 32 : 64,
		strmhz(buf, pci1_speed),
		pci1_clk_sel ? "" : "a");

Quoted 7 lines

?
Best regards,
Wolfgang Denk

Yes. I'll repost it.

-chenhui

Quoted 7 lines

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The only time the world beats a path to your door is when you are  in
the bathroom.

Zhao Chenhui

author

2011-09-13 07:15 UTC #11 lore raw

PATCH 3/9 powerpc/mpc8548: Add workaround for erratum NMG_DDR120

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point.

Signed-off-by Gong Chen <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 ++++
 arch/powerpc/cpu/mpc85xx/ddr-gen2.c       |   22 +++++++++++++++++++++-
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 3 files changed, 26 insertions(+), 1 deletions(-)

arch/powerpc/cpu/mpc85xx/cmd_errata.c +4 -0

index 0478ec1..f0fa0f5 100644
@@ -96,6 +96,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 	puts("Work-around for Erratum IFC A-003399 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG DDR120 enabled\n");
+#endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/ddr-gen2.c +21 -1

index 655f99c..a71fb42 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright 2008 Freescale Semiconductor, Inc.
+ * Copyright 2008, 2011 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License

@@ -8,6 +8,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <asm/processor.h>
 #include <asm/fsl_ddr_sdram.h>
 
 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)

@@ -19,12 +20,31 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 {
 	unsigned int i;
 	volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	uint svr;
+#endif
 
 	if (ctrl_num) {
 		printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 		return;
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+	/*
+	 * Set the DDR IO receiver to an acceptable bias point.
+	 * Fixed in Rev 2.1.
+	 */
+	svr = get_svr();
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0)) {
+		if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) ==
+		   SDRAM_CFG_SDRAM_TYPE_DDR2)
+			out_be32(&gur->ddrioovcr, 0x90000000);
+		else
+			out_be32(&gur->ddrioovcr, 0xA8000000);
+	}
+#endif
+
 	for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 		if (i == 0) {
 			out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

index f9bf80d..a0a12b2 100644
@@ -62,6 +62,7 @@
 #define CONFIG_SYS_FSL_NUM_LAWS		10
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1

Signature · 1 line

1.6.4.1

Kumar Gala

Applied

2011-10-03 13:33 UTC #12 lore raw

PATCH 3/9 powerpc/mpc8548: Add workaround for erratum NMG_DDR120

Quoted 8 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
Erratum NMG_DDR120 (DDR19 in MPC8548 errata document) applies to some early version silicons. The default settings of the DDR IO receiver biasing may not work at cold temperature. When a failure occurs, a DDR input latches an incorrect value. The workaround will set the receiver to an acceptable bias point.

Quoted 7 lines

Signed-off-by Gong Chen <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 ++++
arch/powerpc/cpu/mpc85xx/ddr-gen2.c       |   22 +++++++++++++++++++++-
arch/powerpc/include/asm/config_mpc85xx.h |    1 +
3 files changed, 26 insertions(+), 1 deletions(-)

applied to 85xx

- k

Zhao Chenhui

author

2011-09-13 07:15 UTC #13 lore raw

PATCH 4/9 powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early verion silicons. This workaround detects if the eTSEC Rx logic is properly initialized, and reinitialize the eTSEC Rx logic.

Signed-off-by Gong Chen <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 drivers/net/tsec.c                        |   93 +++++++++++++++++++++++++++++
 3 files changed, 98 insertions(+), 0 deletions(-)

arch/powerpc/cpu/mpc85xx/cmd_errata.c +4 -0

index f0fa0f5..2c468bd 100644
@@ -100,6 +100,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG DDR120 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
+		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
+#endif
 	return 0;
 }

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

index a0a12b2..3e32778 100644
@@ -63,6 +63,7 @@
 #define CONFIG_SYS_FSL_SEC_COMPAT	2
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1

drivers/net/tsec.c +93 -0

123 lines not on this page · raw message

Signature · 1 line

1.6.4.1

Kumar Gala

Applied

2011-11-08 14:32 UTC #14 lore raw

PATCH 4/9 powerpc/mpc8548: Add workaround for erratum NMG_eTSEC129

Quoted 6 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
Erratum NMG_eTSEC129 (eTSEC86 in MPC8548 document) applies to some early verion silicons. This workaround detects if the eTSEC Rx logic is properly initialized, and reinitialize the eTSEC Rx logic.

Quoted 7 lines

Signed-off-by Gong Chen <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    4 +
arch/powerpc/include/asm/config_mpc85xx.h |    1 +
drivers/net/tsec.c                        |   93 +++++++++++++++++++++++++++++
3 files changed, 98 insertions(+), 0 deletions(-)

applied to 85xx

- k

Zhao Chenhui

author

2011-09-13 07:15 UTC #15 lore raw

PATCH 5/9 powerpc/mpc8548cds: Fix network initialization

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init().
Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.

Signed-off-by Ebony Zhu <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---
 board/freescale/mpc8548cds/mpc8548cds.c |   65 +++++++++++++++++++++++++++---
 include/configs/MPC8548CDS.h            |    2 +
 2 files changed, 60 insertions(+), 7 deletions(-)

board/freescale/mpc8548cds/mpc8548cds.c +58 -7

index d9f79b9..99c86ac 100644
@@ -33,6 +33,9 @@
 #include <miiphy.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <tsec.h>
+#include <fsl_mdio.h>
+#include <netdev.h>
 
 #include "../common/cadmus.h"
 #include "../common/eeprom.h"

@@ -287,7 +290,7 @@ void pci_init_board(void)
 	fsl_pcie_init_board(first_free_busno);
 }
 
-int last_stage_init(void)
+void configure_rgmii(void)
 {
 	unsigned short temp;

@@ -295,29 +298,77 @@ int last_stage_init(void)
 	/* This is needed to get the RGMII working for the 1.3+
 	 * CDS cards */
 	if (get_board_version() ==  0x13) {
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 29, 18);
 
-		miiphy_read(CONFIG_TSEC1_NAME,
+		miiphy_read(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, &temp);
 
 		temp = (temp & 0xf03f);
 		temp |= 2 << 9;		/* 36 ohm */
 		temp |= 2 << 6;		/* 39 ohm */
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, temp);
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 29, 3);
 
-		miiphy_write(CONFIG_TSEC1_NAME,
+		miiphy_write(DEFAULT_MII_NAME,
 				TSEC1_PHY_ADDR, 30, 0x8000);
 	}
 
-	return 0;
+	return;
 }
 
+#ifdef CONFIG_TSEC_ENET
+int board_eth_init(bd_t *bis)
+{
+	struct fsl_pq_mdio_info mdio_info;
+	struct tsec_info_struct tsec_info[4];
+	int num = 0;
+
+#ifdef CONFIG_TSEC1
+	SET_STD_TSEC_INFO(tsec_info[num], 1);
+	num++;
+#endif
+#ifdef CONFIG_TSEC2
+	SET_STD_TSEC_INFO(tsec_info[num], 2);
+	num++;
+#endif
+#ifdef CONFIG_TSEC3
+	/* initialize TSEC3 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 3);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+#ifdef CONFIG_TSEC4
+	/* initialize TSEC4 only if Carrier is 1.3 or above on CDS */
+	if (get_board_version() >= 0x13) {
+		SET_STD_TSEC_INFO(tsec_info[num], 4);
+		tsec_info[num].interface = PHY_INTERFACE_MODE_RGMII_ID;
+		num++;
+	}
+#endif
+
+	if (!num) {
+		printf("No TSECs initialized\n");
+
+		return 0;
+	}
+
+	mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
+	mdio_info.name = DEFAULT_MII_NAME;
+	fsl_pq_mdio_init(bis, &mdio_info);
+
+	tsec_eth_init(bis, tsec_info, num);
+	configure_rgmii();
+
+	return pci_eth_init(bis);
+}
+#endif
 
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_pci_setup(void *blob, bd_t *bd)

include/configs/MPC8548CDS.h +2 -0

index aca77ff..64745e1 100644
@@ -405,6 +405,8 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_TSEC4_NAME	"eTSEC3"
 #undef CONFIG_MPC85XX_FEC
 
+#define CONFIG_PHY_MARVELL
+
 #define TSEC1_PHY_ADDR		0
 #define TSEC2_PHY_ADDR		1
 #define TSEC3_PHY_ADDR		2

Signature · 1 line

1.6.4.1

Kumar Gala

Applied

2011-11-08 14:32 UTC #16 lore raw

PATCH 5/9 powerpc/mpc8548cds: Fix network initialization

Quoted 6 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init().
Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3.

Quoted 6 lines

Signed-off-by Ebony Zhu <[email protected]>
Signed-off-by Zhao Chenhui <[email protected]>
---
board/freescale/mpc8548cds/mpc8548cds.c | 65 +++++++++++++++++++++++++++---
include/configs/MPC8548CDS.h | 2 +
2 files changed, 60 insertions(+), 7 deletions(-)

applied to 85xx

- k

Zhao Chenhui

author

2011-09-13 07:15 UTC #17 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

-Increase the size of malloc space.
-Enable e1000 network card.
-Change the location of env address.
-Use hwconfig to turn off ECC.

Signed-off-by Zhao Chenhui <[email protected]>

---
 include/configs/MPC8548CDS.h |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

include/configs/MPC8548CDS.h +11 -3

index 64745e1..2760af0 100644
@@ -86,6 +86,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 #define CONFIG_DDR_SPD
 
+#define CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef

@@ -162,6 +163,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_EMPTY_INFO
 
+#define CONFIG_HWCONFIG			/* enable hwconfig */
 
 /*
  * SDRAM on the Local Bus

@@ -276,7 +278,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */
+#define CONFIG_SYS_MALLOC_LEN	(1024 * 1024)	/* Reserved for malloc */
 
 /* Serial Port */
 #define CONFIG_CONS_INDEX	2

@@ -382,6 +384,7 @@ extern unsigned long get_clock_freq(void);
 
 #undef CONFIG_EEPRO100
 #undef CONFIG_TULIP
+#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
 
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */

@@ -430,8 +433,12 @@ extern unsigned long get_clock_freq(void);
  * Environment
  */
 #define CONFIG_ENV_IS_IN_FLASH	1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
-#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
+#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
+#define CONFIG_ENV_ADDR	0xfff80000
+#else
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#endif
+#define CONFIG_ENV_SECT_SIZE	0x20000	/* 128K for env */
 #define CONFIG_ENV_SIZE		0x2000
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */

@@ -532,6 +539,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_BAUDRATE	115200
 
 #define	CONFIG_EXTRA_ENV_SETTINGS				\
+ "hwconfig=fsl_ddr:ecc=off\0"			\
  "netdev=eth0\0"						\
  "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
  "tftpflash=tftpboot $loadaddr $uboot; "			\

Signature · 1 line

1.6.4.1

Tabi Timur-B04825

2011-09-13 16:09 UTC #18 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

Review

Quoted 6 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>

(quoted diff) +0 -4

-Increase the size of malloc space.
-Enable e1000 network card.
-Change the location of env address.
-Use hwconfig to turn off ECC.

Please repost this patch with a detailed explanation as to why these changes are being made. Why do you need more malloc space? Why enable only the E1000 card? What's wrong with the current environment address? And why does the default hwconfig need to turn off ECC?

Signature · 2 lines

Timur Tabi
Linux kernel developer at Freescale

Wolfgang Denk

2011-10-06 21:33 UTC #19 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

In reply to Zhao Chenhui

Dear Zhao Chenhui,

Quoted 11 lines · In message <[email protected]> you…

From: chenhui zhao <[email protected]>

(quoted diff) +0 -4

-Increase the size of malloc space.
-Enable e1000 network card.
-Change the location of env address.
-Use hwconfig to turn off ECC.

Signed-off-by Zhao Chenhui <[email protected]>

---
 include/configs/MPC8548CDS.h |   14 +++++++++++---
 1 files changed, 11 insertions(+), 3 deletions(-)

Checkpatch says:

total: 0 errors, 1 warnings, 50 lines checked

Please clean up and resubmit. Thanks.

Best regards,

Wolfgang Denk

Signature · 6 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
The day-to-day travails of the IBM programmer are so amusing to  most
of us who are fortunate enough never to have been one - like watching
Charlie Chaplin trying to cook a shoe.

Kumar Gala

2011-10-07 15:11 UTC #20 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

Quoted 17 lines · Wolfgang Denk

Dear Zhao Chenhui,
Quoted 11 lines · In message <[email protected]> you…
From: chenhui zhao <[email protected]>
(quoted diff) +0 -4
-Increase the size of malloc space.
-Enable e1000 network card.
-Change the location of env address.
-Use hwconfig to turn off ECC.
Signed-off-by Zhao Chenhui <[email protected]>
---
include/configs/MPC8548CDS.h | 14 +++++++++++---
1 files changed, 11 insertions(+), 3 deletions(-)
Checkpatch says:

Quoted 7 lines

total: 0 errors, 1 warnings, 50 lines checked
Please clean up and resubmit. Thanks.
Best regards,
Wolfgang Denk

I don't agree with this checkpatch warning. The extra space adds to readability so leaving this alone.

- k

Wolfgang Denk

2011-10-09 18:26 UTC #21 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

Dear Kumar Gala,

Quoted 5 lines · In message <[email protected]> you wrote:

Quoted 2 lines
total: 0 errors, 1 warnings, 50 lines checked
I don't agree with this checkpatch warning. The extra space adds to = readability so leaving this alone.

Indentation must be done by TABs. Single spaces are not allowed.

Please fix.

Best regards,

Wolfgang Denk

Signature · 5 lines

DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Cleverness and Style have no place in getting a project completed.
                                                  -- Tom Christiansen

Kumar Gala

Applied

2011-10-07 15:15 UTC #22 lore raw

PATCH 6/9 powerpc/mpc8548cds: Update config file

In reply to Zhao Chenhui

Quoted 11 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
(quoted diff) +0 -4
-Increase the size of malloc space.
-Enable e1000 network card.
-Change the location of env address.
-Use hwconfig to turn off ECC.
Signed-off-by Zhao Chenhui <[email protected]>
---
include/configs/MPC8548CDS.h | 14 +++++++++++---
1 files changed, 11 insertions(+), 3 deletions(-)

applied to 85xx

- k

Zhao Chenhui

author

2011-09-13 07:15 UTC #23 lore raw

PATCH 7/9 powerpc/mpc8548: Add workaround for erratum NMG_LBC103

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV].

Refer to the erratum LBIU3 of mpc8548.

Signed-off-by Zhao Chenhui <[email protected]>

---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/cpu_init.c       |    3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 3 files changed, 7 insertions(+), 0 deletions(-)

arch/powerpc/cpu/mpc85xx/cmd_errata.c +3 -0

index 2c468bd..6011f66 100644
@@ -104,6 +104,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
 		puts("Work-around for Erratum NMG ETSEC129 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+	puts("Work-around for Erratum NMG_LBC103 enabled\n");
+#endif
 	return 0;
 }

arch/powerpc/cpu/mpc85xx/cpu_init.c +3 -0

index 27f836c..d9e9069 100644
@@ -454,6 +454,9 @@ skip_l2:
 	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
+#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
+	udelay(100);
+#endif
 #endif
 
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE

arch/powerpc/include/asm/config_mpc85xx.h +1 -0

index 3e32778..e961e44 100644
@@ -64,6 +64,7 @@
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
+#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 
 #elif defined(CONFIG_MPC8555)
 #define CONFIG_MAX_CPUS			1

Signature · 1 line

1.6.4.1

Kumar Gala

Applied

2011-10-03 13:39 UTC #24 lore raw

PATCH 7/9 powerpc/mpc8548: Add workaround for erratum NMG_LBC103

Quoted 8 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
The erratum NMG_LBC103 is LBIU3 in MPC8548 errata document. Any local bus transaction may fail during LBIU resynchronization process when the clock divider [CLKDIV] is changing. Ensure there is no transaction on the local bus for at least 100 microseconds after changing clock divider LCRR[CLKDIV].

Quoted 8 lines

Refer to the erratum LBIU3 of mpc8548.

Signed-off-by Zhao Chenhui <[email protected]>

---

arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
arch/powerpc/cpu/mpc85xx/cpu_init.c       |    3 +++
arch/powerpc/include/asm/config_mpc85xx.h |    1 +
3 files changed, 7 insertions(+), 0 deletions(-)

applied to 85xx

- k

Zhao Chenhui

author

2011-09-13 07:15 UTC #25 lore raw

PATCH 8/9 powerpc/mpc8548cds: Fix config according to system address map

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.

Signed-off-by Zhao Chenhui <[email protected]>

---
 board/freescale/mpc8548cds/law.c        |   19 +++++----
 board/freescale/mpc8548cds/mpc8548cds.c |    8 ++--
 board/freescale/mpc8548cds/tlb.c        |   67 ++++++++++++++++---------------
 include/configs/MPC8548CDS.h            |   56 ++++++++++++-------------
 4 files changed, 76 insertions(+), 74 deletions(-)

board/freescale/mpc8548cds/law.c +10 -9

index 5b6943d..f0de509 100644
@@ -31,13 +31,14 @@
  * LAW(Local Access Window) configuration:
  *
  * 0x0000_0000     0x7fff_ffff     DDR                     2G
- * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
+ * 0x8000_0000     0x8fff_ffff     PCI1 MEM                256M
+ * 0x9000_0000     0x9fff_ffff     PCI2 MEM                256M
  * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
  * 0xc000_0000     0xdfff_ffff     RapidIO                 512M
- * 0xe000_0000     0xe000_ffff     CCSR                    1M
- * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
- * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
- * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
+ * 0xe000_0000     0xe00f_ffff     CCSR                    1M
+ * 0xe200_0000     0xe27f_ffff     PCI1 IO                 8M
+ * 0xe280_0000     0xe2ff_ffff     PCI2 IO                 8M
+ * 0xe300_0000     0xe3ff_ffff     PCIe IO                 16M
  * 0xf000_0000     0xf3ff_ffff     SDRAM                   64M
  * 0xf800_0000     0xf80f_ffff     NVRAM/CADMUS (*)        1M
  * 0xff00_0000     0xff7f_ffff     FLASH (2nd bank)        8M

@@ -52,11 +53,11 @@
 
 struct law_entry law_table[] = {
 #ifdef CONFIG_SYS_PCI2_MEM_PHYS
-	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI_2),
 #endif
-	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	/* LBC window - maps 256M */
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);

board/freescale/mpc8548cds/mpc8548cds.c +4 -4

index 99c86ac..65da881 100644
@@ -53,10 +53,10 @@ int checkboard (void)
 
 	uint cpu_board_rev = get_cpu_board_revision ();
 
-	printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
-		get_board_version (), pci_slot);
-
-	printf ("CPU Board Revision %d.%d (0x%04x)\n",
+	puts("Board: MPC8548CDS");
+	printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+			get_board_version(), pci_slot);
+	printf("       Daughtercard Rev: %d.%d (0x%04x)\n",
 		MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
 		MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
 	/*

board/freescale/mpc8548cds/tlb.c +35 ~~-32~~

98 lines not on this page · raw message

include/configs/MPC8548CDS.h +27 ~~-29~~

119 lines not on this page · raw message

Signature · 1 line

1.6.4.1

Kumar Gala

2011-10-07 15:17 UTC #26 lore raw

PATCH 8/9 powerpc/mpc8548cds: Fix config according to system address map

Quoted 6 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.

Quoted 7 lines

Signed-off-by Zhao Chenhui <[email protected]>

---

board/freescale/mpc8548cds/law.c        |   19 +++++----
board/freescale/mpc8548cds/mpc8548cds.c |    8 ++--
board/freescale/mpc8548cds/tlb.c        |   67 ++++++++++++++++---------------
include/configs/MPC8548CDS.h            |   56 ++++++++++++-------------
4 files changed, 76 insertions(+), 74 deletions(-)

with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.

- k

Zhao Chenhui

2011-10-08 07:02 UTC #27 lore raw

PATCH 8/9 powerpc/mpc8548cds: Fix config according to system address map

Quoted 17 lines · Kumar Gala

Quoted 6 lines · Zhao Chenhui
From: chenhui zhao <[email protected]>
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Quoted 7 lines
Signed-off-by Zhao Chenhui <[email protected]>
---
board/freescale/mpc8548cds/law.c        |   19 +++++----
board/freescale/mpc8548cds/mpc8548cds.c |    8 ++--
board/freescale/mpc8548cds/tlb.c        |   67 ++++++++++++++++---------------
include/configs/MPC8548CDS.h            |   56 ++++++++++++-------------
4 files changed, 76 insertions(+), 74 deletions(-)

Quoted 3 lines

with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.
- k

It's "MPC8548E Configurable Development System Reference Manual".
I made some minor changes to address map, including reserving 256M memory space for PCI2, enlarging the size of PCI IO space.

-chenhui

Zhao Chenhui

2011-10-08 07:47 UTC #28 lore raw

PATCH 8/9 powerpc/mpc8548cds: Fix config according to system address map

Quoted 20 lines · Zhao Chenhui

Quoted 19 lines · Kumar Gala
Quoted 6 lines · Zhao Chenhui
From: chenhui zhao <[email protected]>
- Fix config according to system address map in the manual.
- Rework tlb and law tables.
- Remove unnecessary macros.
Quoted 7 lines
Signed-off-by Zhao Chenhui <[email protected]>
---
board/freescale/mpc8548cds/law.c        |   19 +++++----
board/freescale/mpc8548cds/mpc8548cds.c |    8 ++--
board/freescale/mpc8548cds/tlb.c        |   67 ++++++++++++++++---------------
include/configs/MPC8548CDS.h            |   56 ++++++++++++-------------
4 files changed, 76 insertions(+), 74 deletions(-)
with which manual? If its the board manual that isn't correct, the one in the board manual is just an example.

Quoted 7 lines

Quoted 1 line
- k
It's "MPC8548E Configurable Development System Reference Manual".
I made some minor changes to address map, including reserving 256M memory space for PCI2, enlarging the size of PCI IO space.
-chenhui

Fixed typo in the comments of tlb.c and reposted.

-chenhui

Zhao Chenhui

author

2011-09-13 07:15 UTC #29 lore raw

PATCH 9/9 powerpc/mpc8548cds: Add 36-bit support

In reply to Zhao Chenhui

From: chenhui zhao <[email protected]>

Signed-off-by Zhao Chenhui <[email protected]>

---
 boards.cfg                   |    1 +
 include/configs/MPC8548CDS.h |   52 ++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 53 insertions(+), 0 deletions(-)

boards.cfg +1 -0

index 8bf69e3..64a39f8 100644
@@ -568,6 +568,7 @@ MPC8541CDS                   powerpc     mpc85xx     mpc8541cds          freesca
 MPC8541CDS_legacy            powerpc     mpc85xx     mpc8541cds          freescale      -           MPC8541CDS:LEGACY
 MPC8544DS                    powerpc     mpc85xx     mpc8544ds           freescale
 MPC8548CDS                   powerpc     mpc85xx     mpc8548cds          freescale      -           MPC8548CDS
+MPC8548CDS_36BIT             powerpc     mpc85xx     mpc8548cds          freescale      -           MPC8548CDS:36BIT
 MPC8548CDS_legacy            powerpc     mpc85xx     mpc8548cds          freescale      -           MPC8548CDS:LEGACY
 MPC8555CDS                   powerpc     mpc85xx     mpc8555cds          freescale      -           MPC8555CDS
 MPC8555CDS_legacy            powerpc     mpc85xx     mpc8555cds          freescale      -           MPC8555CDS:LEGACY

include/configs/MPC8548CDS.h +52 -0

126 lines not on this page · raw message

Signature · 1 line

1.6.4.1

Kumar Gala

Applied

2011-10-03 13:28 UTC #30 lore raw

PATCH 1/9 powerpc/mpc8548cds: Fix booting message

In reply to Zhao Chenhui

Quoted 8 lines · Zhao Chenhui

From: chenhui zhao <[email protected]>
Align the output for PCI. Replace "PCI" with "PCI1".
Signed-off-by Zhao Chenhui <[email protected]>
---
board/freescale/mpc8548cds/mpc8548cds.c | 6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)

applied to 85xx

- k