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PATCH New Jongpill Lee 2 participants 5 messages Sep 15, 2011 – Sep 18, 2011

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm Samsung Exynos
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#1 lore raw

PATCH 1/3 ARM: EXYNOS4: Modify PMU register setting function

This patch modifies PMU register setting function to support the other Exynos4 series.

Signed-off-by Jongpill Lee <[email protected]>
---
 arch/arm/mach-exynos4/include/mach/pmu.h      |    5 +
 arch/arm/mach-exynos4/include/mach/regs-pmu.h |    1 -
 arch/arm/mach-exynos4/pmu.c                   |  238 +++++++++---------------
 3 files changed, 94 insertions(+), 150 deletions(-)
arch/arm/mach-exynos4/include/mach/pmu.h +5 -0
index a952904..430e917 100644
@@ -20,6 +20,11 @@ enum sys_powerdown {
 	NUM_SYS_POWERDOWN,
 };
 
+struct exynos4_pmu_conf {
+	void __iomem *reg;
+	unsigned long val[NUM_SYS_POWERDOWN];
+};
+
 extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
 
 #endif /* __ASM_ARCH_PMU_H */
arch/arm/mach-exynos4/include/mach/regs-pmu.h +0 -1
index cdf9b47..7fa44b9 100644
@@ -27,7 +27,6 @@
 #define S5P_USE_STANDBY_WFI1			(1 << 17)
 #define S5P_USE_STANDBY_WFE0			(1 << 24)
 #define S5P_USE_STANDBY_WFE1			(1 << 25)
-#define S5P_USE_MASK				((0x3 << 16) | (0x3 << 24))
 
 #define S5P_SWRESET				S5P_PMUREG(0x0400)
arch/arm/mach-exynos4/pmu.c +89 -149

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#2 lore raw

PATCH 1/3 ARM: EXYNOS4: Modify PMU register setting function

Hi Jongpill,

Quoted 14 lines · Jongpill Lee

This patch modifies PMU register setting function to support the other Exynos4 series.

Signed-off-by Jongpill Lee<[email protected]>
---
  arch/arm/mach-exynos4/include/mach/pmu.h      |    5 +
  arch/arm/mach-exynos4/include/mach/regs-pmu.h |    1 -
  arch/arm/mach-exynos4/pmu.c                   |  238 +++++++++---------------
  3 files changed, 94 insertions(+), 150 deletions(-)
arch/arm/mach-exynos4/include/mach/pmu.h +0 -0
index a952904..430e917 100644

arch/arm/mach-exynos4/include/mach/pmu.h enum sys_powerdown { · line 25

Quoted 6 lines
arch/arm/mach-exynos4/include/mach/pmu.h +3 -0
@@ -20,6 +20,11 @@ enum sys_powerdown {
  	NUM_SYS_POWERDOWN,
  };
 
+struct exynos4_pmu_conf {
+	void __iomem *reg;
+	unsigned long val[NUM_SYS_POWERDOWN];

Why unsigned long? It's for the registers value, wouldn't u32 fit better?

Quoted 27 lines
arch/arm/mach-exynos4/include/mach/pmu.h +2 -0
+};
+
  extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
 
  #endif /* __ASM_ARCH_PMU_H */
arch/arm/mach-exynos4/include/mach/regs-pmu.h +0 -1
index cdf9b47..7fa44b9 100644
@@ -27,7 +27,6 @@
  #define S5P_USE_STANDBY_WFI1			(1<<  17)
  #define S5P_USE_STANDBY_WFE0			(1<<  24)
  #define S5P_USE_STANDBY_WFE1			(1<<  25)
-#define S5P_USE_MASK				((0x3<<  16) | (0x3<<  24))
 
  #define S5P_SWRESET				S5P_PMUREG(0x0400)
arch/arm/mach-exynos4/pmu.c +0 -2
index 7ea9eb2..0210231 100644
@@ -16,160 +16,100 @@
  #include<mach/regs-clock.h>
  #include<mach/pmu.h>
 
-static void __iomem *sys_powerdown_reg[] = {
-	S5P_ARM_CORE0_LOWPWR,

...

Quoted 9 lines
arch/arm/mach-exynos4/pmu.c +3 -5
-	S5P_GPS_ALIVE_LOWPWR,
-};
+static struct exynos4_pmu_conf *exynos4_pmu_config;
+
+static unsigned int exynos4_pmu_entry_cnt;
 
-static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
-	/* { AFTR, LPA, SLEEP }*/
-	{ 0, 0, 2 },	/* ARM_CORE0 */

...

Quoted 4 lines
arch/arm/mach-exynos4/pmu.c +3 -1
-	{ 7, 0, 0 },	/* GPS_ALIVE */
+static struct exynos4_pmu_conf exynos4210_pmu_config[] = {
+	/* { .reg = address, .val = { AFTR, LPA, SLEEP } */
+	{ S5P_ARM_CORE0_LOWPWR,			{ 0x0, 0x0, 0x2 } },

...

arch/arm/mach-exynos4/pmu.c line 100

Quoted 7 lines
arch/arm/mach-exynos4/pmu.c +2 -1
+	{ S5P_GPS_ALIVE_LOWPWR,			{ 0x7, 0x0, 0x0 } },
  };
 
  void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
  {
-	unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+	unsigned int count = exynos4_pmu_entry_cnt;

How about using a sentinel at the array end and getting rid of the global 'exynos4_pmu_entry_cnt' variable? For instance an empty entry { } ?

arch/arm/mach-exynos4/pmu.c line 111

Quoted 13 lines

for (; count> 0; count--)

arch/arm/mach-exynos4/pmu.c +9 -2
-		__raw_writel(sys_powerdown_val[count - 1][mode],
-				sys_powerdown_reg[count - 1]);
+		__raw_writel(exynos4_pmu_config[count - 1].val[mode],
+				exynos4_pmu_config[count - 1].reg);
+}
+
+static int __init exynos4_pmu_init(void)
+{
+	exynos4_pmu_config = exynos4210_pmu_config;
+	exynos4_pmu_entry_cnt = ARRAY_SIZE(exynos4210_pmu_config);
+	printk(KERN_INFO "EXYNOS4210 PMU Initialize\n");

"EXYNOS4210 PMU initialized\n", "EXYNOS4210 PMU initialization completed\n" ?

Moreover AFAIK pr_info is preferred.

arch/arm/mach-exynos4/pmu.c line 115

Quoted 4 lines
arch/arm/mach-exynos4/pmu.c +3 -0
+
+	return 0;
  }
+arch_initcall(exynos4_pmu_init);

--
Thanks,
Sylwester

author
#3 lore raw

PATCH 2/3 ARM: EXYNOS4: Add PMU register definition for EXYNOS4212

In reply to Jongpill Lee

This patch adds PMU register definition for Exynos4212

Signed-off-by Jongpill Lee <[email protected]>
---
 arch/arm/mach-exynos4/include/mach/regs-pmu.h |   69 +++++++++++++++++++++----
 1 files changed, 58 insertions(+), 11 deletions(-)
arch/arm/mach-exynos4/include/mach/regs-pmu.h +58 -11
index 7fa44b9..6fab38e 100644
@@ -25,8 +25,10 @@
 
 #define S5P_USE_STANDBY_WFI0			(1 << 16)
 #define S5P_USE_STANDBY_WFI1			(1 << 17)
+#define S5P_USE_STANDBYWFI_ISP_ARM		(1 << 18)
 #define S5P_USE_STANDBY_WFE0			(1 << 24)
 #define S5P_USE_STANDBY_WFE1			(1 << 25)
+#define S5P_USE_STANDBYWFE_ISP_ARM		(1 << 26)
 
 #define S5P_SWRESET				S5P_PMUREG(0x0400)
 

@@ -34,15 +36,11 @@
 #define S5P_EINT_WAKEUP_MASK			S5P_PMUREG(0x0604)
 #define S5P_WAKEUP_MASK				S5P_PMUREG(0x0608)
 
-#define S5P_USBHOST_PHY_CONTROL			S5P_PMUREG(0x0708)
-#define S5P_USBHOST_PHY_ENABLE			(1 << 0)
-
 #define S5P_MIPI_DPHY_CONTROL(n)		S5P_PMUREG(0x0710 + (n) * 4)
 #define S5P_MIPI_DPHY_ENABLE			(1 << 0)
 #define S5P_MIPI_DPHY_SRESETN			(1 << 1)
 #define S5P_MIPI_DPHY_MRESETN			(1 << 2)
 
-#define S5P_PMU_SATA_PHY_CONTROL		S5P_PMUREG(0x0720)
 #define S5P_INFORM0				S5P_PMUREG(0x0800)
 #define S5P_INFORM1				S5P_PMUREG(0x0804)
 #define S5P_INFORM2				S5P_PMUREG(0x0808)

@@ -75,7 +73,6 @@
 #define S5P_CMU_CLKSTOP_MFC_LOWPWR		S5P_PMUREG(0x1148)
 #define S5P_CMU_CLKSTOP_G3D_LOWPWR		S5P_PMUREG(0x114C)
 #define S5P_CMU_CLKSTOP_LCD0_LOWPWR		S5P_PMUREG(0x1150)
-#define S5P_CMU_CLKSTOP_LCD1_LOWPWR		S5P_PMUREG(0x1154)
 #define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR		S5P_PMUREG(0x1158)
 #define S5P_CMU_CLKSTOP_GPS_LOWPWR		S5P_PMUREG(0x115C)
 #define S5P_CMU_RESET_CAM_LOWPWR		S5P_PMUREG(0x1160)

@@ -83,7 +80,6 @@
 #define S5P_CMU_RESET_MFC_LOWPWR		S5P_PMUREG(0x1168)
 #define S5P_CMU_RESET_G3D_LOWPWR		S5P_PMUREG(0x116C)
 #define S5P_CMU_RESET_LCD0_LOWPWR		S5P_PMUREG(0x1170)
-#define S5P_CMU_RESET_LCD1_LOWPWR		S5P_PMUREG(0x1174)
 #define S5P_CMU_RESET_MAUDIO_LOWPWR		S5P_PMUREG(0x1178)
 #define S5P_CMU_RESET_GPS_LOWPWR		S5P_PMUREG(0x117C)
 #define S5P_TOP_BUS_LOWPWR			S5P_PMUREG(0x1180)

@@ -91,14 +87,11 @@
 #define S5P_TOP_PWR_LOWPWR			S5P_PMUREG(0x1188)
 #define S5P_LOGIC_RESET_LOWPWR			S5P_PMUREG(0x11A0)
 #define S5P_ONENAND_MEM_LOWPWR			S5P_PMUREG(0x11C0)
-#define S5P_MODIMIF_MEM_LOWPWR			S5P_PMUREG(0x11C4)
 #define S5P_G2D_ACP_MEM_LOWPWR			S5P_PMUREG(0x11C8)
 #define S5P_USBOTG_MEM_LOWPWR			S5P_PMUREG(0x11CC)
 #define S5P_HSMMC_MEM_LOWPWR			S5P_PMUREG(0x11D0)
 #define S5P_CSSYS_MEM_LOWPWR			S5P_PMUREG(0x11D4)
 #define S5P_SECSS_MEM_LOWPWR			S5P_PMUREG(0x11D8)
-#define S5P_PCIE_MEM_LOWPWR			S5P_PMUREG(0x11E0)
-#define S5P_SATA_MEM_LOWPWR			S5P_PMUREG(0x11E4)
 #define S5P_PAD_RETENTION_DRAM_LOWPWR		S5P_PMUREG(0x1200)
 #define S5P_PAD_RETENTION_MAUDIO_LOWPWR		S5P_PMUREG(0x1204)
 #define S5P_PAD_RETENTION_GPIO_LOWPWR		S5P_PMUREG(0x1220)

@@ -119,7 +112,6 @@
 #define S5P_MFC_LOWPWR				S5P_PMUREG(0x1388)
 #define S5P_G3D_LOWPWR				S5P_PMUREG(0x138C)
 #define S5P_LCD0_LOWPWR				S5P_PMUREG(0x1390)
-#define S5P_LCD1_LOWPWR				S5P_PMUREG(0x1394)
 #define S5P_MAUDIO_LOWPWR			S5P_PMUREG(0x1398)
 #define S5P_GPS_LOWPWR				S5P_PMUREG(0x139C)
 #define S5P_GPS_ALIVE_LOWPWR			S5P_PMUREG(0x13A0)

@@ -155,7 +147,6 @@
 #define S5P_PMU_MFC_CONF			S5P_PMUREG(0x3C40)
 #define S5P_PMU_G3D_CONF			S5P_PMUREG(0x3C60)
 #define S5P_PMU_LCD0_CONF			S5P_PMUREG(0x3C80)
-#define S5P_PMU_LCD1_CONF			S5P_PMUREG(0x3CA0)
 #define S5P_PMU_GPS_CONF			S5P_PMUREG(0x3CE0)
 
 #define S5P_PMU_SATA_PHY_CONTROL_EN		0x1

@@ -164,4 +155,60 @@
 
 #define S5P_CHECK_SLEEP				0x00000BAD
 
+/* Only for EXYNOS4210 */
+#define S5P_USBHOST_PHY_CONTROL		S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE		(1 << 0)
+
+#define S5P_PMU_SATA_PHY_CONTROL	S5P_PMUREG(0x0720)
+
+#define S5P_CMU_CLKSTOP_LCD1_LOWPWR	S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_LCD1_LOWPWR	S5P_PMUREG(0x1174)
+#define S5P_MODIMIF_MEM_LOWPWR		S5P_PMUREG(0x11C4)
+#define S5P_PCIE_MEM_LOWPWR		S5P_PMUREG(0x11E0)
+#define S5P_SATA_MEM_LOWPWR		S5P_PMUREG(0x11E4)
+#define S5P_LCD1_LOWPWR			S5P_PMUREG(0x1394)
+
+#define S5P_PMU_LCD1_CONF		S5P_PMUREG(0x3CA0)
+
+/* Only for EXYNOS4212 */
+#define S5P_ISP_ARM_LOWPWR			S5P_PMUREG(0x1050)
+#define S5P_DIS_IRQ_ISP_ARM_LOCAL_LOWPWR	S5P_PMUREG(0x1054)
+#define S5P_DIS_IRQ_ISP_ARM_CENTRAL_LOWPWR	S5P_PMUREG(0x1058)
+#define S5P_CMU_ACLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1110)
+#define S5P_CMU_SCLKSTOP_COREBLK_LOWPWR		S5P_PMUREG(0x1114)
+#define S5P_CMU_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x111C)
+#define S5P_MPLLUSER_SYSCLK_LOWPWR		S5P_PMUREG(0x1130)
+#define S5P_CMU_CLKSTOP_ISP_LOWPWR		S5P_PMUREG(0x1154)
+#define S5P_CMU_RESET_ISP_LOWPWR		S5P_PMUREG(0x1174)
+#define S5P_TOP_BUS_COREBLK_LOWPWR		S5P_PMUREG(0x1190)
+#define S5P_TOP_RETENTION_COREBLK_LOWPWR	S5P_PMUREG(0x1194)
+#define S5P_TOP_PWR_COREBLK_LOWPWR		S5P_PMUREG(0x1198)
+#define S5P_OSCCLK_GATE_LOWPWR			S5P_PMUREG(0x11A4)
+#define S5P_LOGIC_RESET_COREBLK_LOWPWR		S5P_PMUREG(0x11B0)
+#define S5P_OSCCLK_GATE_COREBLK_LOWPWR		S5P_PMUREG(0x11B4)
+#define S5P_HSI_MEM_LOWPWR			S5P_PMUREG(0x11C4)
+#define S5P_ROTATOR_MEM_LOWPWR			S5P_PMUREG(0x11DC)
+#define S5P_PAD_RETENTION_GPIO_COREBLK_LOWPWR	S5P_PMUREG(0x123C)
+#define S5P_PAD_ISOLATION_COREBLK_LOWPWR	S5P_PMUREG(0x1250)
+#define S5P_GPIO_MODE_COREBLK_LOWPWR		S5P_PMUREG(0x1320)
+#define S5P_TOP_ASB_RESET_LOWPWR		S5P_PMUREG(0x1344)
+#define S5P_TOP_ASB_ISOLATION_LOWPWR		S5P_PMUREG(0x1348)
+#define S5P_ISP_LOWPWR				S5P_PMUREG(0x1394)
+#define S5P_DRAM_FREQ_DOWN_LOWPWR		S5P_PMUREG(0x13B0)
+#define S5P_DDRPHY_DLLOFF_LOWPWR		S5P_PMUREG(0x13B4)
+#define S5P_CMU_SYSCLK_ISP_LOWPWR		S5P_PMUREG(0x13B8)
+#define S5P_CMU_SYSCLK_GPS_LOWPWR		S5P_PMUREG(0x13BC)
+#define S5P_LPDDR_PHY_DLL_LOCK_LOWPWR		S5P_PMUREG(0x13C0)
+
+#define S5P_ARM_L2_0_OPTION			S5P_PMUREG(0x2608)
+#define S5P_ARM_L2_1_OPTION			S5P_PMUREG(0x2628)
+#define S5P_ONENAND_MEM_OPTION			S5P_PMUREG(0x2E08)
+#define S5P_HSI_MEM_OPTION			S5P_PMUREG(0x2E28)
+#define S5P_G2D_ACP_MEM_OPTION			S5P_PMUREG(0x2E48)
+#define S5P_USBOTG_MEM_OPTION			S5P_PMUREG(0x2E68)
+#define S5P_HSMMC_MEM_OPTION			S5P_PMUREG(0x2E88)
+#define S5P_CSSYS_MEM_OPTION			S5P_PMUREG(0x2EA8)
+#define S5P_SECSS_MEM_OPTION			S5P_PMUREG(0x2EC8)
+#define S5P_ROTATOR_MEM_OPTION			S5P_PMUREG(0x2F48)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
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author
#4 lore raw

PATCH 3/3 ARM: EXYNOS4: Support suspend/resume for EXYNOS4212

In reply to Jongpill Lee

This patch adds suspend and resume function for EXYNOS4212.

Signed-off-by Jongpill Lee <[email protected]>
---
 arch/arm/mach-exynos4/pm.c  |    7 +++
 arch/arm/mach-exynos4/pmu.c |  121 +++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 125 insertions(+), 3 deletions(-)
arch/arm/mach-exynos4/pm.c +7 -0
index 62e4f43..509a435 100644
@@ -339,6 +339,13 @@ static int exynos4_pm_suspend(void)
 	tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
 	__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
 
+	if (soc_is_exynos4212()) {
+		tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
+		tmp &= ~(S5P_USE_STANDBYWFI_ISP_ARM |
+			 S5P_USE_STANDBYWFE_ISP_ARM);
+		__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
+	}
+
 	/* Save Power control register */
 	asm ("mrc p15, 0, %0, c15, c0, 0"
 	     : "=r" (tmp) : : "cc");
arch/arm/mach-exynos4/pmu.c +118 -3

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