Remove duplicate functions for power and sleep configuration

292 lines not on this page · raw message

similarity index 63%
rename from arch/arm/include/asm/arch-davinci/am1808_lowlevel.h
rename to arch/arm/include/asm/arch-davinci/da850_lowlevel.h
index 0bc7f76..22a92a3 100644
@@ -1,5 +1,5 @@
 /*
- * SoC-specific lowlevel code for AM1808 and similar chips
+ * SoC-specific lowlevel code for DA850
  *
  * Copyright (C) 2011
  * Heiko Schocher, DENX Software Engineering, hs at denx.de.

@@ -21,24 +21,24 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
-#ifndef __AM1808_LOWLEVEL_H
-#define __AM1808_LOWLEVEL_H
+#ifndef __DA850_LOWLEVEL_H
+#define __DA850_LOWLEVEL_H
 
 /* NOR Boot Configuration Word Field Descriptions */
-#define AM1808_NORBOOT_COPY_XK(X)	((X - 1) << 8)
-#define AM1808_NORBOOT_METHOD_DIRECT	(1 << 4)
-#define AM1808_NORBOOT_16BIT		(1 << 0)
+#define DA850_NORBOOT_COPY_XK(X)	((X - 1) << 8)
+#define DA850_NORBOOT_METHOD_DIRECT	(1 << 4)
+#define DA850_NORBOOT_16BIT		(1 << 0)
 
 #define dv_maskbits(addr, val) \
 	writel((readl(addr) & val), addr)
 
-void am1808_waitloop(unsigned long loopcnt);
-int am1808_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
-void am1808_lpc_transition(unsigned char pscnum, unsigned char module,
+void da850_waitloop(unsigned long loopcnt);
+int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult);
+void da850_lpc_transition(unsigned char pscnum, unsigned char module,
 		unsigned char domain, unsigned char state);
-int am1808_ddr_setup(unsigned int freq);
-void am1808_psc_init(void);
-void am1808_pinmux_ctl(unsigned long offset, unsigned long mask,
+int da850_ddr_setup(unsigned int freq);
+void da850_psc_init(void);
+void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value);
 
-#endif /* #ifndef __AM1808_LOWLEVEL_H */
+#endif /* #ifndef __DA850_LOWLEVEL_H */

index c25d240..d649d43 100644
@@ -43,7 +43,7 @@
 #include <asm/arch/sdmmc_defs.h>
 #include <asm/arch/timer_defs.h>
 #include <asm/io.h>
-#include <asm/arch/am1808_lowlevel.h>
+#include <asm/arch/da850_lowlevel.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 

137 lines not on this page · raw message

index 707fa47..3e92518 100644
@@ -46,7 +46,7 @@
  */
 
 /* Works on Always On power domain only (no PD argument) */
-void lpsc_on(unsigned int id)
+static void lpsc_transition(unsigned int id, unsigned int state)
 {
 	dv_reg_p mdstat, mdctl, ptstat, ptcmd;
 #ifdef CONFIG_SOC_DA8XX

@@ -83,10 +83,10 @@ void lpsc_on(unsigned int id)
 	while (readl(ptstat) & 0x01)
 		continue;
 
-	if ((readl(mdstat) & PSC_MDSTAT_STATE) == 0x03)
-		return; /* Already on and enabled */
+	if ((readl(mdstat) & PSC_MDSTAT_STATE) == state)
+		return; /* Already in that state */
 
-	writel(readl(mdctl) | 0x03, mdctl);
+	writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl);
 
 	switch (id) {
 #ifdef CONFIG_SOC_DM644X

@@ -114,10 +114,20 @@ void lpsc_on(unsigned int id)
 
 	while (readl(ptstat) & 0x01)
 		continue;
-	while ((readl(mdstat) & PSC_MDSTAT_STATE) != 0x03)
+	while ((readl(mdstat) & PSC_MDSTAT_STATE) != state)
 		continue;
 }
 
+void lpsc_on(unsigned int id)
+{
+	lpsc_transition(id, 0x03);
+}
+
+void lpsc_syncreset(unsigned int id)
+{
+	lpsc_transition(id, 0x01);
+}
+
 /* Not all DaVinci chips have a DSP power domain. */
 #ifdef CONFIG_SOC_DM644X
 

index a9c2839..26f17a3 100644
@@ -291,6 +291,7 @@ typedef volatile unsigned int *	dv_reg_p;
 #endif /* CONFIG_SOC_DA8XX */
 
 void lpsc_on(unsigned int id);
+void lpsc_syncreset(unsigned int id);
 void dsp_on(void);
 
 void davinci_enable_uart0(void);

@@ -357,6 +358,7 @@ struct davinci_psc_regs {
 #endif /* CONFIG_SOC_DA8XX */
 
 #define PSC_MDSTAT_STATE		0x3f
+#define PSC_MDCTL_NEXT			0x07
 
 #ifndef CONFIG_SOC_DA8XX
 

index a6f0178..490ef8f 100644
@@ -153,49 +153,12 @@ int da850_pll_init(struct davinci_pllc_regs *reg, unsigned long pllmult)
 	return 0;
 }
 
-void da850_lpc_transition(unsigned char pscnum, unsigned char module,
-		unsigned char domain, unsigned char state)
-{
-	struct davinci_psc_regs	*reg;
-	dv_reg_p mdstat, mdctl;
-
-	if (pscnum == 0) {
-		reg = davinci_psc0_regs;
-		mdstat = &reg->psc0.mdstat[module];
-		mdctl = &reg->psc0.mdctl[module];
-	} else {
-		reg = davinci_psc1_regs;
-		mdstat = &reg->psc1.mdstat[module];
-		mdctl = &reg->psc1.mdctl[module];
-	}
-
-	/* Wait for any outstanding transition to complete */
-	while ((readl(&reg->ptstat) & (0x00000001 << domain)))
-		;
-
-	/* If we are already in that state, just return */
-	if ((readl(mdstat) & 0x1F) == state)
-		return;
-
-	/* Perform transition */
-	writel((readl(mdctl) & 0xFFFFFFE0) | state, mdctl);
-	setbits_le32(&reg->ptcmd, (0x00000001 << domain));
-
-	/* Wait for transition to complete */
-	while (readl(&reg->ptstat) & (0x00000001 << domain))
-		;
-
-	/* Wait and verify the state */
-	while ((readl(mdstat) & 0x1F) != state)
-		;
-}
-
 int da850_ddr_setup(unsigned int freq)
 {
 	unsigned long	tmp;
 
 	/* Enable the Clock to DDR2/mDDR */
-	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 
 	tmp = readl(&davinci_syscfg1_regs->vtpio_ctl);
 	if ((tmp & VTP_POWERDWN) == VTP_POWERDWN) {

@@ -244,9 +207,9 @@ int da850_ddr_setup(unsigned int freq)
 		&dv_ddr2_regs_ctrl->sdrcr);
 
 	/* SyncReset the Clock to EMIF3A SDRAM */
-	da850_lpc_transition(1, 6, 0, PSC_SYNCRESET);
+	lpsc_syncreset(DAVINCI_LPSC_DDR_EMIF);
 	/* Enable the Clock to EMIF3A SDRAM */
-	da850_lpc_transition(1, 6, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_DDR_EMIF);
 
 	/* disable self refresh */
 	clrbits_le32(&dv_ddr2_regs_ctrl->sdrcr, 0xc0000000);

@@ -255,54 +218,6 @@ int da850_ddr_setup(unsigned int freq)
 	return 0;
 }
 
-static void da850_set_mdctl(dv_reg_p mdctl)
-{
-	if ((readl(mdctl) & 0x1F) != PSC_ENABLE)
-		writel(((readl(mdctl) & 0xFFFFFFE0) | PSC_ENABLE), mdctl);
-}
-
-void da850_psc_init(void)
-{
-	struct davinci_psc_regs	*reg;
-	int i;
-
-	/* PSC 0 domain 0 init */
-	reg = davinci_psc0_regs;
-	while ((readl(&reg->ptstat) & 0x00000001))
-		;
-
-	for (i = 3; i <= 4 ; i++)
-		da850_set_mdctl(&reg->psc0.mdctl[i]);
-
-	for (i = 7; i <= 12 ; i++)
-		da850_set_mdctl(&reg->psc0.mdctl[i]);
-
-	/* Do Always-On Power Domain Transitions */
-	setbits_le32(&reg->ptcmd, 0x00000001);
-	while (readl(&reg->ptstat) & 0x00000001)
-		;
-
-	/* PSC1, domain 1 init */
-	reg = davinci_psc1_regs;
-	while ((readl(&reg->ptstat) & 0x00000001))
-		;
-
-	da850_set_mdctl(&reg->psc1.mdctl[3]);
-	da850_set_mdctl(&reg->psc1.mdctl[6]);
-
-	/* UART1 + UART2 */
-	for (i = 12 ; i <= 13 ; i++)
-		da850_set_mdctl(&reg->psc1.mdctl[i]);
-
-	da850_set_mdctl(&reg->psc1.mdctl[26]);
-	da850_set_mdctl(&reg->psc1.mdctl[31]);
-
-	/* Do Always-On Power Domain Transitions */
-	setbits_le32(&reg->ptcmd, 0x00000001);
-	while (readl(&reg->ptstat) & 0x00000001)
-		;
-}
-
 void da850_pinmux_ctl(unsigned long offset, unsigned long mask,
 	unsigned long value)
 {

@@ -368,9 +283,6 @@ int arch_cpu_init(void)
 	dv_maskbits(&davinci_syscfg_regs->suspsrc,
 		((1 << 27) | (1 << 22) | (1 << 20) | (1 << 5) |	(1 << 16)));
 
-	/* System PSC setup - enable all */
-	da850_psc_init();
-
 	/* Setup Pinmux */
 	da850_pinmux_ctl(0, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX0);
 	da850_pinmux_ctl(1, 0xFFFFFFFF, CONFIG_SYS_DA850_PINMUX1);

@@ -404,7 +316,7 @@ int arch_cpu_init(void)
 	writel(CONFIG_SYS_DA850_CS2CFG, &davinci_emif_regs->ab1cr);
 	writel(CONFIG_SYS_DA850_CS3CFG, &davinci_emif_regs->ab2cr);
 
-	da850_lpc_transition(1, 13, 0, PSC_ENABLE);
+	lpsc_on(DAVINCI_LPSC_UART2);
 	NS16550_init((NS16550_t)(CONFIG_SYS_NS16550_COM1),
 			CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);