ARM: Samsung: Add device tree support for GIC and Interrupt Combiner

PATCH Superseded Thomas Abraham 6 participants 18 messages Oct 10, 2011 – Oct 24, 2011

Subsystems (4)

Device tree bindings Arm (32-bit) Arm sub-architectures Arm Samsung Exynos

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Thomas Abraham

author

2011-10-10 08:10 UTC #0 lore raw

cover ARM: Samsung: Add device tree support for GIC and Interrupt Combiner

This patchset adds device tree support for GIC and Interrupt Combiner modules in Exynos4 SoC.

Patch 1 moves the statically mapped timer irqs 11 to 15 to the end of the statically mapped linux irq space for all s5p platforms. This patch is applicable for s5p64x0, s5pc100, s5pv210 and exynos4.

For all these platforms, the five hardware timer irqs are connected to GIC/VIC at some hardware irq number (in exynos it is GIC_ID 69 to 73 for five timers). When any of these hardware interrupt occurs, its interrupt handler calls generic_handle_irq() with linux irq number 11/12/13/14/15 for timer 0/1/2/3/4 as the parameter. The code that needs to be notified about the timer interrupts would have already registered its handler for either of the interrupts 11 to 15.

Instead of using linux irq number 11 to 15 to which consumers of timer interrupt attach their handler, this interrupt range is moved to the end of linux irq space used. So there will be no interrupts statically mapped between 0 to 31.

The GIC/VIC hardware interrupts, which were previously statically mapped to start from linux irq 32 are now moved to start from linux irq 0. In case of exynos, GIC_ID[0] (which is SGI[0]) which was previously at linux irq 32, will not be at linux irq 0. This was required to use Rob Herring's GIC OF bindings patches for Exynos4.

Patch 2 adds a interceptor for all ioremap calls targeted towards any of the statically remapped memory region. This was required because the GIC OF binding's patchset ioremaps the GIC memory-mapped regions in the gic_of_init() function. Without this patch, there would be two separate remap for GIC controller, one statically remapped and the other dynamically remapped by the gic_of_init() function.

Patch 3 adds device tree support for GIC and Interrupt Combiner controllers on Exynos4. For GIC controller, this patch is based on Rob Herring's, "[PATCH 0/3] GIC OF bindings" patchset. The concept of irq domain for interrupt combiner controller is based on Grant's 'simple' irq converter

This patchset is based on the following tree:
https://github.com/kgene/linux-samsung.git branch: for-next

Patch 1 is tested on smdk6450, smdkc100, smdkv210. Patch 1 to 3 are tested on smdkv310.

Thomas Abraham (3):
arm: samsung: move timer irq numbers to end of linux irq space
ARM: Exynos4: Add ioremap interceptor for statically remapped regions
ARM: Exynos4: Add support for dt irq specifier to linux virq conversion

 .../devicetree/bindings/irq/samsung-combiner.txt   |   24 ++++++++++
 arch/arm/mach-exynos4/cpu.c                        |   36 +++++++++++++++-
 arch/arm/mach-exynos4/include/mach/entry-macro.S   |    1 -
 arch/arm/mach-exynos4/include/mach/io.h            |    4 ++
 arch/arm/mach-exynos4/include/mach/irqs.h          |    3 +-
 arch/arm/mach-exynos4/irq-combiner.c               |   45 ++++++++++++++++++++
 arch/arm/mach-s5p64x0/include/mach/irqs.h          |    4 +-
 arch/arm/mach-s5pc100/include/mach/irqs.h          |    3 +-
 arch/arm/mach-s5pv210/include/mach/irqs.h          |    3 +-
 arch/arm/plat-samsung/include/plat/irqs.h          |    7 ++-
 10 files changed, 117 insertions(+), 13 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/irq/samsung-combiner.txt

Thomas Abraham

author

2011-10-10 08:10 UTC #1 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

All of Samsung's s5p platforms have timer irqs statically mapped from linux irq numbers 11 to 15. These timer irqs are moved to end of the statically mapped linux irq space and the hardware irqs, which were statically mapped starting from 32 is moved to start from 0. The NR_IRQS macro is consolidated for all the s5p platforms in this process.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1

index 4c9adbd..5c4fbcc 100644
@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
 
 		.endm

arch/arm/mach-exynos4/include/mach/irqs.h +1 -2

index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3

index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2

index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2

index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/plat-samsung/include/plat/irqs.h +5 -2

index 08d1a7e..b8918b3 100644
@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */
 
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)
 
 #define S5P_IRQ(x)		((x) + S5P_IRQ_OFFSET)

@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)		(S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)		(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)	(11 + (x))
+#define S5P_TIMER_IRQ(x)	(IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0		S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1		S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2		S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3		S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4		S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT		(5)
 
 #define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 					: ((x) - 16 + S5P_EINT_BASE2))

@@ -77,4 +78,6 @@
 #define S5P_IRQ_TYPE_EDGE_RISING	(0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH		(0x04)
 
+#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
 #endif /* __PLAT_SAMSUNG_IRQS_H */

Signature · 1 line

1.6.6.rc2

Rob Herring

2011-10-12 16:10 UTC #2 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

Quoted 21 lines · Thomas Abraham

All of Samsung's s5p platforms have timer irqs statically mapped from linux irq numbers 11 to 15. These timer irqs are moved to end of the statically mapped linux irq space and the hardware irqs, which were statically mapped starting from 32 is moved to start from 0. The NR_IRQS macro is consolidated for all the s5p platforms in this process.
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0
index 4c9adbd..5c4fbcc 100644

arch/arm/mach-exynos4/include/mach/entry-macro.S line 75

Quoted 4 lines

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1

@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32

With this change, can't you now use the common entry-macro-gic.S?

Quoted 62 lines

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0

 		.endm

arch/arm/mach-exynos4/include/mach/irqs.h +1 -2

index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3

index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2

index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2

index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/plat-samsung/include/plat/irqs.h +0 -0

index 08d1a7e..b8918b3 100644

arch/arm/plat-samsung/include/plat/irqs.h line 25

Quoted 5 lines

arch/arm/plat-samsung/include/plat/irqs.h +1 -1

@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */
 
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)

Just remove this.

Quoted 20 lines

arch/arm/plat-samsung/include/plat/irqs.h +2 -1

 #define S5P_IRQ(x)		((x) + S5P_IRQ_OFFSET)

@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)		(S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)		(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)	(11 + (x))
+#define S5P_TIMER_IRQ(x)	(IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0		S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1		S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2		S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3		S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4		S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT		(5)
 
 #define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 					: ((x) - 16 + S5P_EINT_BASE2))

arch/arm/plat-samsung/include/plat/irqs.h line 83

Quoted 6 lines

arch/arm/plat-samsung/include/plat/irqs.h +2 -0

@@ -77,4 +78,6 @@
 #define S5P_IRQ_TYPE_EDGE_RISING	(0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH		(0x04)
 
+#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
 #endif /* __PLAT_SAMSUNG_IRQS_H */

Really these timer irqs should be converted to irq domains and be dynamically allocated in the linux irq space, but this is at least a step in the right direction.

Rob

Thomas Abraham

author

2011-10-12 16:29 UTC #3 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

Quoted 17 lines · Rob Herring

Quoted 16 lines · Thomas Abraham
All of Samsung's s5p platforms have timer irqs statically mapped from linux irq numbers 11 to 15. These timer irqs are moved to end of the statically mapped linux irq space and the hardware irqs, which were statically mapped starting from 32 is moved to start from 0. The NR_IRQS macro is consolidated for all the s5p platforms in this process.
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/include/mach/entry-macro.S | ? ?1 -
?arch/arm/mach-exynos4/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/mach-s5p64x0/include/mach/irqs.h ? ? ? ?| ? ?4 +---
?arch/arm/mach-s5pc100/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/mach-s5pv210/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/plat-samsung/include/plat/irqs.h ? ? ? ?| ? ?7 +++++--
?6 files changed, 9 insertions(+), 12 deletions(-)

Quoted 12 lines

Quoted 9 lines
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0
index 4c9adbd..5c4fbcc 100644
@@ -72,7 +72,6 @@
? ? ? ? ? ? ? cmpcc ? \irqnr, \irqnr
? ? ? ? ? ? ? cmpne ? \irqnr, \tmp
? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
- ? ? ? ? ? ? addne ? \irqnr, \irqnr, #32
With this change, can't you now use the common entry-macro-gic.S?

The get_irqnr_preamble macro is quite different from that in entry-macro-gic.S file. Maybe it is possible to use the common entry-macro-gic.S file with some rework of exynos machine code.

Quoted 67 lines

Quoted 67 lines
? ? ? ? ? ? ? .endm
arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
?#define IRQ_GPIO2_NR_GROUPS ?9
?#define IRQ_GPIO_END ? ? ? ? (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
arch/arm/mach-exynos4/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_GPIO_END + 64)
?#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3
index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 ?#define IRQ_EINT_GROUP(grp, x) ? ? ? (IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
?#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 ?#define S5P_GPIOINT_BASE ? ? (IRQ_EINT(31) + 1)
?#define S5P_GPIOINT_GROUP_MAXNR ? ? ?21
arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
?/* Compatibility */
?#define IRQ_LCD_FIFO ? ? ? ? IRQ_LCD0
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 ?#define S5P_GPIOINT_BASE ? ? (IRQ_EINT(31) + 1)
?#define S5P_GPIOINT_GROUP_MAXNR ? ? ?22
arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
?/* Compatibility */
?#define IRQ_LCD_FIFO ? ? ? ? IRQ_LCD0
arch/arm/plat-samsung/include/plat/irqs.h +0 -0
index 08d1a7e..b8918b3 100644
@@ -22,7 +22,7 @@
? * mulitple of 32 to allow the common code to work ? */

Quoted 4 lines

arch/arm/plat-samsung/include/plat/irqs.h
Quoted 2 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -1
-#define S5P_IRQ_OFFSET ? ? ? ? ? ? ? (32)
+#define S5P_IRQ_OFFSET ? ? ? ? ? ? ? (0)
Just remove this.

Ok.

Quoted 24 lines

?#define S5P_IRQ(x) ? ? ? ? ? ((x) + S5P_IRQ_OFFSET)

arch/arm/plat-samsung/include/plat/irqs.h +2 -1

@@ -44,13 +44,14 @@
 ?#define S5P_IRQ_VIC2(x) ? ? ? ? ? ? ?(S5P_VIC2_BASE + (x))
 ?#define S5P_IRQ_VIC3(x) ? ? ? ? ? ? ?(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x) ? ? (11 + (x))
+#define S5P_TIMER_IRQ(x) ? ? (IRQ_TIMER_BASE + (x))
 
 ?#define IRQ_TIMER0 ? ? ? ? ? S5P_TIMER_IRQ(0)
 ?#define IRQ_TIMER1 ? ? ? ? ? S5P_TIMER_IRQ(1)
 ?#define IRQ_TIMER2 ? ? ? ? ? S5P_TIMER_IRQ(2)
 ?#define IRQ_TIMER3 ? ? ? ? ? S5P_TIMER_IRQ(3)
 ?#define IRQ_TIMER4 ? ? ? ? ? S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT ? ? ? ? ? ? ?(5)
 
 ?#define IRQ_EINT(x) ? ? ? ? ?((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : ((x) - 16 + S5P_EINT_BASE2))

@@ -77,4 +78,6 @@
 ?#define S5P_IRQ_TYPE_EDGE_RISING ? ? (0x03)
 ?#define S5P_IRQ_TYPE_EDGE_BOTH ? ? ? ? ? ? ? (0x04)

Quoted 7 lines

Quoted 3 lines
arch/arm/plat-samsung/include/plat/irqs.h +2 -0
+#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
?#endif /* __PLAT_SAMSUNG_IRQS_H */
Really these timer irqs should be converted to irq domains and be dynamically allocated in the linux irq space, but this is at least a step in the right direction.

Ok.

Thanks for your comments.

Regards,
Thomas.

Quoted 3 lines

Rob

Grant Likely

2011-10-13 00:41 UTC #4 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

In reply to Rob Herring

Quoted 96 lines · Rob Herring

Quoted 21 lines · Thomas Abraham

All of Samsung's s5p platforms have timer irqs statically mapped from linux irq numbers 11 to 15. These timer irqs are moved to end of the statically mapped linux irq space and the hardware irqs, which were statically mapped starting from 32 is moved to start from 0. The NR_IRQS macro is consolidated for all the s5p platforms in this process.
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0
index 4c9adbd..5c4fbcc 100644

arch/arm/mach-exynos4/include/mach/entry-macro.S line 75

Quoted 4 lines

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1

@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32

With this change, can't you now use the common entry-macro-gic.S?

Quoted 65 lines

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0

 		.endm

arch/arm/mach-exynos4/include/mach/irqs.h +1 -2

index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3

index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2

index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2

index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/plat-samsung/include/plat/irqs.h +0 -0

index 08d1a7e..b8918b3 100644
@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */

Quoted 4 lines

arch/arm/plat-samsung/include/plat/irqs.h line 25
Quoted 2 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -1
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)
Just remove this.

One comment on this; Make sure irqs mapping does *not* start at 0. 0 is not supposed to be used.

Changhwan Youn

2011-10-18 08:10 UTC #5 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

In reply to Thomas Abraham

Hi Thomas,

All UART_IRQ_RXD, TXD, ERR of Samsung's platforms are also statically mapped to linux irq numbers 16 to 31. These interrupts also need proper handling.

Best regards,
Changhwan Youn

Quoted 128 lines · Thomas Abraham

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0

exynos4/include/mach/entry-macro.S
index 4c9adbd..5c4fbcc 100644

arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1

@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
 
 		.endm

arch/arm/mach-exynos4/include/mach/irqs.h +1 -2

index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3

index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
 #endif /* __ASM_ARCH_IRQS_H */

arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2

index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2

index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
 
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0

arch/arm/plat-samsung/include/plat/irqs.h +5 -3

index 08d1a7e..b8918b3 100644
@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */
 
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)
 
 #define S5P_IRQ(x)		((x) + S5P_IRQ_OFFSET)

@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)		(S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)		(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)	(11 + (x))
+#define S5P_TIMER_IRQ(x)	(IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0		S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1		S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2		S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3		S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4		S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT		(5)
 
 #define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 					: ((x) - 16 + S5P_EINT_BASE2))

@@ -77,4 +78,6 @@
 #define S5P_IRQ_TYPE_EDGE_RISING	(0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH		(0x04)
 
+#define NR_IRQS			(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
 #endif /* __PLAT_SAMSUNG_IRQS_H */
--

1.6.6.rc2

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Kukjin Kim

2011-10-21 09:56 UTC #6 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

Quoted 5 lines · Changhwan Youn

Hi Thomas,
All UART_IRQ_RXD, TXD, ERR of Samsung's platforms are also statically mapped to linux irq numbers 16 to 31. These interrupts also need proper

handling.

Quoted 4 lines

Best regards,
Changhwan Youn

Hi all,

Hmm, I'd like to apply Thomas' device tree series for EXYNOS4 and Samsung stuff for upcoming merge window but there are still some comments on some stuff and that should be fixed before applying. In addition I need to keep the ordering to apply them to avoid conflicts. But as you know, v3.1 is now close at hand and we don't have enough time for it now :(

I will leave tomorrow morning (KST) for KS. I will talk to Grant Likely about this in Prague :)

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Quoted 2 lines · Thomas Abraham

Quoted 1 line
All of Samsung's s5p platforms have timer irqs statically mapped from

linux

Quoted 1 line

Quoted 1 line
irq numbers 11 to 15. These timer irqs are moved to end of the

statically

Quoted 1 line

Quoted 1 line
mapped linux irq space and the hardware irqs, which were statically

mapped

Quoted 1 line

Quoted 1 line
starting from 32 is moved to start from 0. The NR_IRQS macro is

consolidated

Quoted 12 lines

for all the s5p platforms in this process.

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)

Quoted 1 line

Review
Quoted 1 line
(quoted diff) +0 -0

b/arch/arm/mach-

Quoted 125 lines

arch/arm/mach-
Quoted 13 lines
exynos4/include/mach/entry-macro.S
index 4c9adbd..5c4fbcc 100644
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1
@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
 
 		.endm
 
arch/arm/mach- renamed from arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
exynos4/include/mach/irqs.h
arch/arm/mach-exynos4/include/mach/irqs.h line 164
Quoted 6 lines
index dfd4b7e..43087c3 100644
arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE +
S5P_GPIOINT_COUNT)
arch/arm/mach-
Quoted 7 lines
arch/arm/mach-exynos4/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach- renamed from arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
s5p64x0/include/mach/irqs.h
arch/arm/mach-s5p64x0/include/mach/irqs.h line 142
Quoted 6 lines
index 53982db..bea73cc 100644
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE +
(x))
arch/arm/mach-s5p64x0/include/mach/irqs.h
Quoted 4 lines
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -3
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE +
IRQ_EINT_GROUP8_NR + 1)
arch/arm/mach-s5p64x0/include/mach/irqs.h line 143
Quoted 1 line
arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE +
IRQ_EINT_GROUP8_NR + 1)
arch/arm/mach-
Quoted 3 lines
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
 #endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach- renamed from arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
s5pc100/include/mach/irqs.h
arch/arm/mach-s5pc100/include/mach/irqs.h line 108
Quoted 9 lines
index d2eb475..3a9d300 100644
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -2
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-s5pc100/include/mach/irqs.h line 107
Quoted 1 line
arch/arm/mach-s5pc100/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-
Quoted 4 lines
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
arch/arm/mach- renamed from arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
s5pv210/include/mach/irqs.h
arch/arm/mach-s5pv210/include/mach/irqs.h line 129
Quoted 9 lines
index 5e0de3a..df3173a 100644
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -2
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-s5pv210/include/mach/irqs.h line 128
Quoted 1 line
arch/arm/mach-s5pv210/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/plat-
Quoted 4 lines
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
arch/arm/plat- renamed from arch/arm/plat-samsung/include/plat/irqs.h +0 -0
samsung/include/plat/irqs.h
Quoted 29 lines
index 08d1a7e..b8918b3 100644
arch/arm/plat-samsung/include/plat/irqs.h +3 -2
@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */
 
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)
 
 #define S5P_IRQ(x)		((x) + S5P_IRQ_OFFSET)
 
@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)		(S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)		(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)	(11 + (x))
+#define S5P_TIMER_IRQ(x)	(IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0		S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1		S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2		S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3		S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4		S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT		(5)
 
 #define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 					: ((x) - 16 + S5P_EINT_BASE2))
arch/arm/plat-samsung/include/plat/irqs.h line 81
Quoted 4 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -0
@@ -77,4 +78,6 @@
 #define S5P_IRQ_TYPE_EDGE_RISING	(0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH		(0x04)
 
+#define NR_IRQS			(IRQ_TIMER_BASE +
IRQ_TIMER_COUNT)
Quoted 10 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -1
+
 #endif /* __PLAT_SAMSUNG_IRQS_H */
--
1.6.6.rc2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Grant Likely

2011-10-21 19:45 UTC #7 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

Quoted 14 lines · Kukjin Kim

Quoted 5 lines · Changhwan Youn
Hi Thomas,
All UART_IRQ_RXD, TXD, ERR of Samsung's platforms are also statically mapped to linux irq numbers 16 to 31. These interrupts also need proper
handling.
Quoted 4 lines
Best regards,
Changhwan Youn
Hi all,

Quoted 8 lines

Hmm, I'd like to apply Thomas' device tree series for EXYNOS4 and Samsung stuff for upcoming merge window but there are still some comments on some stuff and that should be fixed before applying. In addition I need to keep the ordering to apply them to avoid conflicts. But as you know, v3.1 is now close at hand and we don't have enough time for it now :(
I will leave tomorrow morning (KST) for KS. I will talk to Grant Likely about this in Prague :)

One of the goals I have for the hacking summit is to get as much of the outstanding DT patches queued up and into linux-next.

Quoted 158 lines

Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
Quoted 2 lines · Thomas Abraham
Quoted 1 line
All of Samsung's s5p platforms have timer irqs statically mapped from
linux
Quoted 1 line
Quoted 1 line
irq numbers 11 to 15. These timer irqs are moved to end of the
statically
Quoted 1 line
Quoted 1 line
mapped linux irq space and the hardware irqs, which were statically
mapped
Quoted 1 line
Quoted 1 line
starting from 32 is moved to start from 0. The NR_IRQS macro is
consolidated
Quoted 12 lines
Quoted 12 lines
for all the s5p platforms in this process.
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos4/include/mach/entry-macro.S |    1 -
 arch/arm/mach-exynos4/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5p64x0/include/mach/irqs.h        |    4 +---
 arch/arm/mach-s5pc100/include/mach/irqs.h        |    3 +--
 arch/arm/mach-s5pv210/include/mach/irqs.h        |    3 +--
 arch/arm/plat-samsung/include/plat/irqs.h        |    7 +++++--
 6 files changed, 9 insertions(+), 12 deletions(-)
Quoted 1 line
Review
Quoted 1 line
(quoted diff) +0 -0
b/arch/arm/mach-
Quoted 125 lines
arch/arm/mach-
Quoted 13 lines
exynos4/include/mach/entry-macro.S
index 4c9adbd..5c4fbcc 100644
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -1
@@ -72,7 +72,6 @@
 		cmpcc	\irqnr, \irqnr
 		cmpne	\irqnr, \tmp
 		cmpcs	\irqnr, \irqnr
-		addne	\irqnr, \irqnr, #32
 
 		.endm
 
arch/arm/mach- renamed from arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
exynos4/include/mach/irqs.h
arch/arm/mach-exynos4/include/mach/irqs.h line 164
Quoted 6 lines
index dfd4b7e..43087c3 100644
arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
@@ -163,7 +163,6 @@
 #define IRQ_GPIO2_NR_GROUPS	9
 #define IRQ_GPIO_END		(S5P_GPIOINT_BASE +
S5P_GPIOINT_COUNT)
arch/arm/mach-
Quoted 7 lines
arch/arm/mach-exynos4/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE		(IRQ_GPIO_END + 64)
 
 #endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach- renamed from arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
s5p64x0/include/mach/irqs.h
arch/arm/mach-s5p64x0/include/mach/irqs.h line 142
Quoted 6 lines
index 53982db..bea73cc 100644
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
@@ -141,8 +141,6 @@
 
 #define IRQ_EINT_GROUP(grp, x)	(IRQ_EINT_GROUP##grp##_BASE +
(x))
arch/arm/mach-s5p64x0/include/mach/irqs.h
Quoted 4 lines
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -3
-/* Set the default NR_IRQS */
-
-#define NR_IRQS			(IRQ_EINT_GROUP8_BASE +
IRQ_EINT_GROUP8_NR + 1)
arch/arm/mach-s5p64x0/include/mach/irqs.h line 143
Quoted 1 line
arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT_GROUP8_BASE +
IRQ_EINT_GROUP8_NR + 1)
arch/arm/mach-
Quoted 3 lines
arch/arm/mach-s5p64x0/include/mach/irqs.h +0 -0
 #endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach- renamed from arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
s5pc100/include/mach/irqs.h
arch/arm/mach-s5pc100/include/mach/irqs.h line 108
Quoted 9 lines
index d2eb475..3a9d300 100644
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -2
@@ -104,8 +104,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	21
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-s5pc100/include/mach/irqs.h line 107
Quoted 1 line
arch/arm/mach-s5pc100/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-
Quoted 4 lines
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
arch/arm/mach- renamed from arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
s5pv210/include/mach/irqs.h
arch/arm/mach-s5pv210/include/mach/irqs.h line 129
Quoted 9 lines
index 5e0de3a..df3173a 100644
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -2
@@ -125,8 +125,7 @@
 #define S5P_GPIOINT_BASE	(IRQ_EINT(31) + 1)
 #define S5P_GPIOINT_GROUP_MAXNR	22
 
-/* Set the default NR_IRQS */
-#define NR_IRQS			(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/mach-s5pv210/include/mach/irqs.h line 128
Quoted 1 line
arch/arm/mach-s5pv210/include/mach/irqs.h +1 -0
+#define IRQ_TIMER_BASE		(IRQ_EINT(31) +
S5P_GPIOINT_COUNT + 1)
arch/arm/plat-
Quoted 4 lines
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
 /* Compatibility */
 #define IRQ_LCD_FIFO		IRQ_LCD0
arch/arm/plat- renamed from arch/arm/plat-samsung/include/plat/irqs.h +0 -0
samsung/include/plat/irqs.h
Quoted 29 lines
index 08d1a7e..b8918b3 100644
arch/arm/plat-samsung/include/plat/irqs.h +3 -2
@@ -22,7 +22,7 @@
  * mulitple of 32 to allow the common code to work
  */
 
-#define S5P_IRQ_OFFSET		(32)
+#define S5P_IRQ_OFFSET		(0)
 
 #define S5P_IRQ(x)		((x) + S5P_IRQ_OFFSET)
 
@@ -44,13 +44,14 @@
 #define S5P_IRQ_VIC2(x)		(S5P_VIC2_BASE + (x))
 #define S5P_IRQ_VIC3(x)		(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x)	(11 + (x))
+#define S5P_TIMER_IRQ(x)	(IRQ_TIMER_BASE + (x))
 
 #define IRQ_TIMER0		S5P_TIMER_IRQ(0)
 #define IRQ_TIMER1		S5P_TIMER_IRQ(1)
 #define IRQ_TIMER2		S5P_TIMER_IRQ(2)
 #define IRQ_TIMER3		S5P_TIMER_IRQ(3)
 #define IRQ_TIMER4		S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT		(5)
 
 #define IRQ_EINT(x)		((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 					: ((x) - 16 + S5P_EINT_BASE2))
arch/arm/plat-samsung/include/plat/irqs.h line 81
Quoted 4 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -0
@@ -77,4 +78,6 @@
 #define S5P_IRQ_TYPE_EDGE_RISING	(0x03)
 #define S5P_IRQ_TYPE_EDGE_BOTH		(0x04)
 
+#define NR_IRQS			(IRQ_TIMER_BASE +
IRQ_TIMER_COUNT)
Quoted 10 lines
arch/arm/plat-samsung/include/plat/irqs.h +1 -1
+
 #endif /* __PLAT_SAMSUNG_IRQS_H */
--
1.6.6.rc2
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Kukjin Kim

2011-10-24 08:09 UTC #8 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

Quoted 21 lines · Grant Likely

Quoted 20 lines · Kukjin Kim
Quoted 5 lines · Changhwan Youn
Hi Thomas,
All UART_IRQ_RXD, TXD, ERR of Samsung's platforms are also statically mapped to linux irq numbers 16 to 31. These interrupts also need proper
handling.
Quoted 4 lines
Best regards,
Changhwan Youn
Hi all,
Hmm, I'd like to apply Thomas' device tree series for EXYNOS4 and Samsung stuff for upcoming merge window but there are still some comments on some stuff and that should be fixed before applying. In addition I need to keep the ordering to apply them to avoid conflicts. But as you know, v3.1 is now close at hand and we don't have enough time for it now :(

Quoted 6 lines

Quoted 2 lines
I will leave tomorrow morning (KST) for KS. I will talk to Grant Likely about this in Prague :)
One of the goals I have for the hacking summit is to get as much of the outstanding DT patches queued up and into linux-next.

OK.

I talked to Grant at ARM Subarch Workshop.

I will apply Thomas' DT patches into Samsung tree and it will be sent to upstream via arm-soc for upcoming merge window v3.2 and if any fixing is required, we will do it during -rc.

Thomas, if any problems during apply, let you know.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.

Thomas Abraham

author

2011-10-21 16:54 UTC #9 lore raw

PATCH 1/3 ARM: Samsung: Move timer irq numbers to end of linux irq space

In reply to Changhwan Youn

Hi Changhwan,

Quoted 4 lines · Changhwan Youn

Hi Thomas,
All UART_IRQ_RXD, TXD, ERR of Samsung's platforms are also statically mapped to linux irq numbers 16 to 31. These interrupts also need proper handling.

A patchset has been submitted to consolidate the uart interrupt handling for Samsung platforms. The following is the link submitted for this patch series.
http://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg06035.html

With this patchset, the linux irq space of 16 to 31 is freed. This patchset has been queued for merge for the 3.2 merge window.

Thanks,
Thomas.

Quoted 135 lines

Best regards,
Changhwan Youn
Quoted 128 lines · Thomas Abraham
All of Samsung's s5p platforms have timer irqs statically mapped from linux irq numbers 11 to 15. These timer irqs are moved to end of the statically mapped linux irq space and the hardware irqs, which were statically mapped starting from 32 is moved to start from 0. The NR_IRQS macro is consolidated for all the s5p platforms in this process.
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/include/mach/entry-macro.S | ? ?1 -
?arch/arm/mach-exynos4/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/mach-s5p64x0/include/mach/irqs.h ? ? ? ?| ? ?4 +---
?arch/arm/mach-s5pc100/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/mach-s5pv210/include/mach/irqs.h ? ? ? ?| ? ?3 +--
?arch/arm/plat-samsung/include/plat/irqs.h ? ? ? ?| ? ?7 +++++--
?6 files changed, 9 insertions(+), 12 deletions(-)
arch/arm/mach- renamed from arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0
exynos4/include/mach/entry-macro.S
index 4c9adbd..5c4fbcc 100644
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -0
@@ -72,7 +72,6 @@
? ? ? ? ? ? ? cmpcc ? \irqnr, \irqnr
? ? ? ? ? ? ? cmpne ? \irqnr, \tmp
? ? ? ? ? ? ? cmpcs ? \irqnr, \irqnr
- ? ? ? ? ? ? addne ? \irqnr, \irqnr, #32
? ? ? ? ? ? ? .endm
arch/arm/mach-exynos4/include/mach/irqs.h +0 -0
index dfd4b7e..43087c3 100644
@@ -163,7 +163,6 @@
?#define IRQ_GPIO2_NR_GROUPS ?9
?#define IRQ_GPIO_END ? ? ? ? (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
arch/arm/mach-exynos4/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_GPIO_END + 64)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_GPIO_END + 64)
?#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5p64x0/include/mach/irqs.h +1 -3
index 53982db..bea73cc 100644
@@ -141,8 +141,6 @@
 
 ?#define IRQ_EINT_GROUP(grp, x) ? ? ? (IRQ_EINT_GROUP##grp##_BASE + (x))
 
-/* Set the default NR_IRQS */
-
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
 
?#endif /* __ASM_ARCH_IRQS_H */
arch/arm/mach-s5pc100/include/mach/irqs.h +0 -0
index d2eb475..3a9d300 100644
@@ -104,8 +104,7 @@
 ?#define S5P_GPIOINT_BASE ? ? (IRQ_EINT(31) + 1)
?#define S5P_GPIOINT_GROUP_MAXNR ? ? ?21
arch/arm/mach-s5pc100/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
?/* Compatibility */
?#define IRQ_LCD_FIFO ? ? ? ? IRQ_LCD0
arch/arm/mach-s5pv210/include/mach/irqs.h +0 -0
index 5e0de3a..df3173a 100644
@@ -125,8 +125,7 @@
 ?#define S5P_GPIOINT_BASE ? ? (IRQ_EINT(31) + 1)
?#define S5P_GPIOINT_GROUP_MAXNR ? ? ?22
arch/arm/mach-s5pv210/include/mach/irqs.h +1 -2
-/* Set the default NR_IRQS */
-#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
+#define IRQ_TIMER_BASE ? ? ? ? ? ? ? (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
?/* Compatibility */
?#define IRQ_LCD_FIFO ? ? ? ? IRQ_LCD0
arch/arm/plat-samsung/include/plat/irqs.h +0 -0
index 08d1a7e..b8918b3 100644
@@ -22,7 +22,7 @@
? * mulitple of 32 to allow the common code to work ? */
arch/arm/plat-samsung/include/plat/irqs.h +1 -1
-#define S5P_IRQ_OFFSET ? ? ? ? ? ? ? (32)
+#define S5P_IRQ_OFFSET ? ? ? ? ? ? ? (0)
?#define S5P_IRQ(x) ? ? ? ? ? ((x) + S5P_IRQ_OFFSET)
arch/arm/plat-samsung/include/plat/irqs.h +4 -1
@@ -44,13 +44,14 @@
 ?#define S5P_IRQ_VIC2(x) ? ? ? ? ? ? ?(S5P_VIC2_BASE + (x))
 ?#define S5P_IRQ_VIC3(x) ? ? ? ? ? ? ?(S5P_VIC3_BASE + (x))
 
-#define S5P_TIMER_IRQ(x) ? ? (11 + (x))
+#define S5P_TIMER_IRQ(x) ? ? (IRQ_TIMER_BASE + (x))
 
 ?#define IRQ_TIMER0 ? ? ? ? ? S5P_TIMER_IRQ(0)
 ?#define IRQ_TIMER1 ? ? ? ? ? S5P_TIMER_IRQ(1)
 ?#define IRQ_TIMER2 ? ? ? ? ? S5P_TIMER_IRQ(2)
 ?#define IRQ_TIMER3 ? ? ? ? ? S5P_TIMER_IRQ(3)
 ?#define IRQ_TIMER4 ? ? ? ? ? S5P_TIMER_IRQ(4)
+#define IRQ_TIMER_COUNT ? ? ? ? ? ? ?(5)
 
 ?#define IRQ_EINT(x) ? ? ? ? ?((x) < 16 ? ((x) + S5P_EINT_BASE1) \
 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : ((x) - 16 + S5P_EINT_BASE2))
@@ -77,4 +78,6 @@
 ?#define S5P_IRQ_TYPE_EDGE_RISING ? ? (0x03)
 ?#define S5P_IRQ_TYPE_EDGE_BOTH ? ? ? ? ? ? ? (0x04)
 
+#define NR_IRQS ? ? ? ? ? ? ? ? ? ? ?(IRQ_TIMER_BASE + IRQ_TIMER_COUNT)
+
?#endif /* __PLAT_SAMSUNG_IRQS_H */
--
1.6.6.rc2
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Thomas Abraham

author

2011-10-10 08:10 UTC #10 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

In reply to Thomas Abraham

ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.

Cc Kukjin Kim <[email protected]>

Signed-off-by Thomas Abraham <[email protected]>

---
 arch/arm/mach-exynos4/cpu.c             |   16 ++++++++++++++++
 arch/arm/mach-exynos4/include/mach/io.h |    4 ++++
 2 files changed, 20 insertions(+), 0 deletions(-)

arch/arm/mach-exynos4/cpu.c +16 -0

index 5b1765b..358624d 100644
@@ -137,6 +137,22 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
 	},
 };
 
+/*
+ * For all ioremap requests of statically mapped regions, intercept ioremap and
+ * return virtual address from the iodesc table.
+ */
+void __iomem *exynos4_ioremap(unsigned long phy, size_t size, unsigned int type)
+{
+	struct map_desc *desc = exynos4_iodesc;
+	unsigned int idx;
+
+	for (idx = 0; idx < ARRAY_SIZE(exynos4_iodesc); idx++, desc++)
+		if (desc->pfn == __phys_to_pfn(phy) && desc->type == type)
+			return (void __iomem *)desc->virtual;
+
+	return __arm_ioremap(phy, size, type);
+}
+
 static void exynos4_idle(void)
 {
 	if (!need_resched())

arch/arm/mach-exynos4/include/mach/io.h +5 -0

index d5478d2..33c2890 100644
@@ -22,5 +22,10 @@
 #define __mem_pci(a)	(a)
 
 #define IO_SPACE_LIMIT (0xFFFFFFFF)
+#define __arch_ioremap	exynos4_ioremap
+#define __arch_iounmap	__iounmap
+
+void __iomem *exynos4_ioremap(unsigned long phy, size_t size,
+					unsigned int type);
 
 #endif /* __ASM_ARM_ARCH_IO_H */

Signature · 1 line

1.6.6.rc2

Rob Herring

2011-10-12 16:13 UTC #11 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

Quoted 11 lines · Thomas Abraham

ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
 arch/arm/mach-exynos4/cpu.c             |   16 ++++++++++++++++
 arch/arm/mach-exynos4/include/mach/io.h |    4 ++++
 2 files changed, 20 insertions(+), 0 deletions(-)

You won't need this with Nico's vmalloc.h clean-up series. It does exactly this but generically for all platforms.

Rob

Thomas Abraham

author

2011-10-12 16:30 UTC #12 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

Quoted 13 lines · Rob Herring

Quoted 11 lines · Thomas Abraham
ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/cpu.c ? ? ? ? ? ? | ? 16 ++++++++++++++++ ?arch/arm/mach-exynos4/include/mach/io.h | ? ?4 ++++ ?2 files changed, 20 insertions(+), 0 deletions(-)

Quoted 2 lines

You won't need this with Nico's vmalloc.h clean-up series. It does exactly this but generically for all platforms.

Ok. Thanks for your suggestion. I will move to using Nico's patches.

Regards,
Thomas.

Quoted 3 lines

Rob

Thomas Abraham

author

2011-10-13 03:28 UTC #13 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

Quoted 18 lines · Thomas Abraham

Quoted 13 lines · Rob Herring
Quoted 11 lines · Thomas Abraham
ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/cpu.c ? ? ? ? ? ? | ? 16 ++++++++++++++++ ?arch/arm/mach-exynos4/include/mach/io.h | ? ?4 ++++ ?2 files changed, 20 insertions(+), 0 deletions(-)
Quoted 2 lines
You won't need this with Nico's vmalloc.h clean-up series. It does exactly this but generically for all platforms.
Ok. Thanks for your suggestion. I will move to using Nico's patches.

Grant Likely

2011-10-13 03:29 UTC #14 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

Quoted 26 lines · Thomas Abraham

Quoted 14 lines · Thomas Abraham
Quoted 13 lines · Rob Herring
Quoted 11 lines · Thomas Abraham
ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/cpu.c ? ? ? ? ? ? | ? 16 ++++++++++++++++ ?arch/arm/mach-exynos4/include/mach/io.h | ? ?4 ++++ ?2 files changed, 20 insertions(+), 0 deletions(-)
Quoted 4 lines
Quoted 2 lines
You won't need this with Nico's vmalloc.h clean-up series. It does exactly this but generically for all platforms.
Ok. Thanks for your suggestion. I will move to using Nico's patches.
From Nico's reply to his pull request of vmalloc cleanup series, it looks like that pull request has been withdrawn (hope I am not missing anything here). Without Nico's series, and gic dt support for exynos4 support requiring this patch, all other workarounds to replace this patch does not seem be correct.

Quoted 3 lines

So is it acceptable to retain this patch and later rework/drop the exynos4 specific ioremap along with Nico's vmalloc patch series when it is merged.

I would say yes, but I don't get to make the decision here.

Nicolas Pitre

2011-10-13 18:52 UTC #15 lore raw

PATCH 2/3 ARM: Exynos4: Add ioremap interceptor for statically remapped regions

In reply to Thomas Abraham

Quoted 15 lines · Thomas Abraham

Quoted 14 lines · Thomas Abraham
Quoted 13 lines · Rob Herring
Quoted 11 lines · Thomas Abraham
ioremap() request for statically remapped regions are intercepted and the statically assigned virtual address is returned. For requests for which there are no statically remapped regions, the requests are let through.
Cc Kukjin Kim <[email protected]>
Signed-off-by Thomas Abraham <[email protected]>
---
?arch/arm/mach-exynos4/cpu.c ? ? ? ? ? ? | ? 16 ++++++++++++++++ ?arch/arm/mach-exynos4/include/mach/io.h | ? ?4 ++++ ?2 files changed, 20 insertions(+), 0 deletions(-)

Quoted 8 lines

Quoted 4 lines
Quoted 2 lines
You won't need this with Nico's vmalloc.h clean-up series. It does exactly this but generically for all platforms.
Ok. Thanks for your suggestion. I will move to using Nico's patches.
From Nico's reply to his pull request of vmalloc cleanup series, it looks like that pull request has been withdrawn (hope I am not missing anything here).

I'm just postponing it because this depends on a large cleanup in the OMAP code which is being pushed to mainline for the next merge window.

Quoted 7 lines

Without Nico's series, and gic dt support for exynos4 support requiring this patch, all other workarounds to replace this patch does not seem be correct.
So is it acceptable to retain this patch and later rework/drop the exynos4 specific ioremap along with Nico's vmalloc patch series when it is merged.

I would guess so. But please CC me on those patches so I know what to look for when rebasing my series.

Nicolas

Thomas Abraham

author

2011-10-10 08:10 UTC #16 lore raw

PATCH 3/3 ARM: Exynos4: Add support for dt irq specifier to linux virq conversion

In reply to Thomas Abraham

Add support for conversion of device tree interrupt specifier to linux virq domain for GIC and Interrupt combiner controllers.

Signed-off-by Thomas Abraham <[email protected]>

---
 .../devicetree/bindings/irq/samsung-combiner.txt   |   24 ++++++++++
 arch/arm/mach-exynos4/cpu.c                        |   20 ++++++++-
 arch/arm/mach-exynos4/irq-combiner.c               |   45 ++++++++++++++++++++
 3 files changed, 88 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/irq/samsung-combiner.txt

Documentation/devicetree/bindings/irq/samsung-combiner.txt new file +24 -0

new file mode 100644
index 0000000..b7d5c30
@@ -0,0 +1,24 @@
+* Exynos4 Interrupt Combiner Controller
+
+Samsung's Exynos4 architecture includes a interrupt combiner which
+can combine interrupt sources as a group and provide a single
+interrupt request for the group. The interrupt request from each
+group are connected to a parent interrupt controller, which is GIC
+in case of Exynos4.
+
+Required properties:
+- compatible: should be "samsung,exynos4-combiner".
+- interrupt-cells: should be <2>. The meaning of the cells are
+    * First Cell: Combiner Group Number.
+    * Second Cell: Interrupt within the group.
+- reg: Base address and size of interrupt combiner registers.
+- interrupt-controller: Identifies the node as an interrupt controller.
+
+Example:
+
+	combiner: interrupt-controller@10440000 {
+		compatible = "samsung,exynos4-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x200>;
+	};

arch/arm/mach-exynos4/cpu.c +19 -1

index 358624d..776e8d4 100644
@@ -10,6 +10,8 @@
 
 #include <linux/sched.h>
 #include <linux/sysdev.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>

@@ -38,6 +40,8 @@ unsigned int gic_bank_offset __read_mostly;
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
 			 unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+extern void combiner_init_dt(struct device_node *node,
+				struct device_node *parent);
 
 /* Initial IO mappings */
 static struct map_desc exynos4_iodesc[] __initdata = {

@@ -229,13 +233,27 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
 			    (gic_bank_offset * smp_processor_id());
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id exynos4_dt_irq_match[] = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "samsung,exynos4-combiner", .data = combiner_init_dt, },
+	{},
+};
+#endif
+
 void __init exynos4_init_irq(void)
 {
 	int irq;
 
 	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 
-	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+	if (of_have_populated_dt())
+		of_irq_init(exynos4_dt_irq_match);
+	else
+#endif
+		gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
 	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;

arch/arm/mach-exynos4/irq-combiner.c +45 -0

55 lines not on this page · raw message

Signature · 1 line

1.6.6.rc2

Grant Likely

2011-10-13 00:54 UTC #17 lore raw

PATCH 3/3 ARM: Exynos4: Add support for dt irq specifier to linux virq conversion

Quoted 77 lines · Thomas Abraham

Add support for conversion of device tree interrupt specifier to linux virq domain for GIC and Interrupt combiner controllers.

Signed-off-by Thomas Abraham <[email protected]>

---
 .../devicetree/bindings/irq/samsung-combiner.txt   |   24 ++++++++++
 arch/arm/mach-exynos4/cpu.c                        |   20 ++++++++-
 arch/arm/mach-exynos4/irq-combiner.c               |   45 ++++++++++++++++++++
 3 files changed, 88 insertions(+), 1 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/irq/samsung-combiner.txt

Documentation/devicetree/bindings/irq/samsung-combiner.txt new file +24 -0

new file mode 100644
index 0000000..b7d5c30
@@ -0,0 +1,24 @@
+* Exynos4 Interrupt Combiner Controller
+
+Samsung's Exynos4 architecture includes a interrupt combiner which
+can combine interrupt sources as a group and provide a single
+interrupt request for the group. The interrupt request from each
+group are connected to a parent interrupt controller, which is GIC
+in case of Exynos4.
+
+Required properties:
+- compatible: should be "samsung,exynos4-combiner".
+- interrupt-cells: should be <2>. The meaning of the cells are
+    * First Cell: Combiner Group Number.
+    * Second Cell: Interrupt within the group.
+- reg: Base address and size of interrupt combiner registers.
+- interrupt-controller: Identifies the node as an interrupt controller.
+
+Example:
+
+	combiner: interrupt-controller at 10440000 {
+		compatible = "samsung,exynos4-combiner";
+		#interrupt-cells = <2>;
+		interrupt-controller;
+		reg = <0x10440000 0x200>;
+	};

arch/arm/mach-exynos4/cpu.c +12 -0

index 358624d..776e8d4 100644
@@ -10,6 +10,8 @@
 
 #include <linux/sched.h>
 #include <linux/sysdev.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
 
 #include <asm/mach/map.h>
 #include <asm/mach/irq.h>

@@ -38,6 +40,8 @@ unsigned int gic_bank_offset __read_mostly;
 extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
 			 unsigned int irq_start);
 extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
+extern void combiner_init_dt(struct device_node *node,
+				struct device_node *parent);
 
 /* Initial IO mappings */
 static struct map_desc exynos4_iodesc[] __initdata = {

@@ -229,13 +233,27 @@ static void exynos4_gic_irq_fix_base(struct irq_data *d)
 			    (gic_bank_offset * smp_processor_id());
 }
 
+#ifdef CONFIG_OF
+static const struct of_device_id exynos4_dt_irq_match[] = {
+	{ .compatible = "arm,cortex-a9-gic", .data = gic_of_init, },
+	{ .compatible = "samsung,exynos4-combiner", .data = combiner_init_dt, },
+	{},
+};
+#endif
+
 void __init exynos4_init_irq(void)
 {

arch/arm/mach-exynos4/cpu.c static void exynos4_gic_irq_fix_base(struct irq_data *d) · line 254

Quoted 10 lines

arch/arm/mach-exynos4/cpu.c +5 -1

 	int irq;
 
 	gic_bank_offset = soc_is_exynos4412() ? 0x4000 : 0x8000;
 
-	gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+#ifdef CONFIG_OF
+	if (of_have_populated_dt())
+		of_irq_init(exynos4_dt_irq_match);
+	else
+#endif

With the proper empty implementations of of_have_populated_dt() and of_irq_init(), the #ifdef block here should probably be removed.

Quoted 54 lines

arch/arm/mach-exynos4/cpu.c +2 -0

+		gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+
 	gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
 	gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
 	gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;

arch/arm/mach-exynos4/irq-combiner.c +33 -0

index 5a2758a..198bd0d 100644
@@ -12,7 +12,12 @@
  * published by the Free Software Foundation.
 */
 
+#include <linux/errno.h>
 #include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/irqdomain.h>
+#include <linux/slab.h>
 
 #include <asm/mach/irq.h>

@@ -122,3 +127,43 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
 		set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 	}
 }
+
+#ifdef CONFIG_OF
+/* Translate dt irq specifier to linux virq for interrupt combiner controller */
+static int exynos4_irq_domain_combiner_dt_translate(struct irq_domain *d,
+			struct device_node *controller,
+			const u32 *intspec, unsigned int intsize,
+			unsigned long *out_hwirq, unsigned int *out_type)
+{
+	if (d->of_node != controller)
+		return -EINVAL;
+	if (intsize < 2)
+		return -EINVAL;
+
+	*out_hwirq = COMBINER_IRQ(intspec[0], intspec[1]);
+	*out_type = IRQ_TYPE_NONE;
+	return 0;
+}
+
+static struct irq_domain_ops exynos4_irq_domain_combiner_ops = {
+	.dt_translate = exynos4_irq_domain_combiner_dt_translate,
+};
+
+void __init combiner_init_dt(struct device_node *node,
+					struct device_node *parent)
+{
+	struct irq_domain *domain;
+
+	if (WARN(!node, "combiner_init_dt: invalid node in parameter\n"))

arch/arm/mach-exynos4/irq-combiner.c void __init combiner_init(unsigned int combiner_nr, void __iomem *base, · line 167

Quoted 10 lines

arch/arm/mach-exynos4/irq-combiner.c +10 -0

+		return;
+
+	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+	if (domain) {
+		domain->of_node = node;
+		domain->ops = &exynos4_irq_domain_combiner_ops;
+		irq_domain_add(domain);
+	} else {
+		WARN_ON(1);
+	}

I would normally expect this order for error handling :

	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
	if (!domain) {
		WARN_ON(1);
		return;
	}

	domain->of_node = node;
	domain->ops = &exynos4_irq_domain_combiner_ops;
	irq_domain_add(domain);

But having said that, I don't think this is the right approach. combiner_init_dt I would expect to call combiner_init(), and the irq_domain should become part of the combiner_chip_data structure so that it can be used for mapping back and forth from linux and hqirq numbers. (irq_data->hwirq and the mapping function). Rolling the irq_domain into the irq controller private data structure is what was done for the GIC too.