serial: samsung: rework clock lookup and add device tree support
Subsystems (5)
v2 cover serial: samsung: rework clock lookup and add device tree support
Changes since v1:
- Included the missing dt bindings documentation in the last patch.
- Rebased and tested with linux 3.1-rc9 on linux-samsung-soc tree.
- Commit messages are modified to be elaborate.
- No changes in code.
This patchset reworks the lookup of parent clocks for baud rate generator in the uart controller and adds support for device tree based discovery for the uart controller.
The Samsung uart driver was dependent on the clock names supplied in the platform data. This dependency had to be first removed to add device tree based discovery support for Samsung uart driver. In the process of reworking the clock lookup logic, several changes had to be made which in turn made parts of the driver redundant and such portions of the driver have been removed in this patchset. As a result, all the SoC specific extensions have been deleted.
Patch 1 modifies the driver to keep a copy of the location of the platform data in the driver's private data. This makes device tree support addition non-intrusive.
Patch 2 moves the complicated clock divider handling for fclk source clock for s3c2440 SoC into platform code. The fclk clock can be easily managed by representing it as a clock in the platform code. fclk clock handling was specific to s3c2440 and moving this out of the driver makes the rest of the clock handling in the driver almost identical for all SoC's supported by the driver.
Patch 3 modifies the driver to lookup source clocks for baud rate generator by using generic clock names. The generic clock name used by the driver is 'clk_uart_baud' appended with the parent number of the clock. For instance, the second parent clock source option for baud rate generator is named as 'clk_uart_baud2'.
The driver stops depending on the set_clock and get_clock callbacks in the SoC specific extensions. Instead, the driver is modified to lookup parent clock rates and decide/calculate the best parent clock source for the baud rate generator (best clock would have the least delta when compared to buad rate requested).
In this process, four new members are added in the driver's private data structure. The 'def_clk_sel' member is a platform set bit-value that specifies the possible parents that the driver is allowed to use for baud rate clock. A bit set at a particular bit position selects that parent clock source.
Example: If bit number 2 is set in 'def_clk_sel', then parent clock source '2' can be a possible parent clock for baud rate generator. The 'num_clks' is the number of possible parent clocks that the SoC supports. The 'clksel_mask' and 'clksel_shift' members are used to operate on the parent clock selection bit field int the uart controller's contol register.
Patch 4 removes all uses and instances of 'struct s3c24xx_uart_clksrc'. This structure was used to pass source clock 'names' between platform code, driver and SoC specific extensions. By moving away from using platform specified clock names in the driver, all uses and instances of 'struct s3c24xx_uart_clksrc' is removed.
Patch 5 removes all the SoC specific get_clksrc and set_clksrc callbacks. These callbacks were using SoC specific clock names to communicate the clock to be set or retrieved. These callbacks are removed as they are no longer required.
Patch 6 reworks the uart clocks in platform code of all Samsung SoC's. The driver would use generic clock names and this patch creates aliases to uart clocks with generic clock names as the alias name.
Patch 7 merges all the SoC specific port reset functions into one common port reset function and moves the common function into the common Samsung uart driver. All the SoC specific port reset functions perform the same operation allowing all of them to be converged.
Patch 8 collapses all the SoC specific probe functions and associated driver private data into the Samsung common uart driver. With get_clksrc, set_clksrc and reset_port functions removed from SoC specific extensions, all the remains in those extensions is the probe function along with SoC specific driver data. These are merged into the common Samsung uart driver and all the SoC specific extensions are deleted.
Patch 9 adds device tree based discovery support for the uart driver.
This patchset is based on the following tree
https://github.com/kgene/linux-samsung.git branch: for-next
with the following two patches applied
[PATCH] serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's [PATCH] ARM: SAMSUNG: Remove uart irq handling from plaform code
and tested on the following boards.
SMDK2440, SMDK2416, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210, SMDKV310.
This patchset has dependency on the following patchset:
[PATCH V2 0/2] Add a common macro for creating struct clk_lookup entries
Thomas Abraham (9):
serial: samsung: Keep a copy of the location of platform data in driver's private data
serial: samsung: move handling of fclk/n clock to platform code
serial: samsung: switch to clkdev based clock lookup
serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
serial: samsung: remove all uses of get_clksrc and set_clksrc
arm: samsung: register uart clocks to clock lookup list
serial: samsung: merge all SoC specific port reset functions
serial: samsung: merge probe() function from all SoC specific extensions
serial: samsung: add device tree support
.../devicetree/bindings/serial/samsung_uart.txt | 14 + arch/arm/mach-exynos4/clock.c | 106 ++-- arch/arm/mach-exynos4/init.c | 21 +- arch/arm/mach-s3c2410/mach-bast.c | 22 - arch/arm/mach-s3c2410/mach-vr1000.c | 24 - arch/arm/mach-s3c2410/s3c2410.c | 6 + arch/arm/mach-s3c2412/clock.c | 7 + arch/arm/mach-s3c2440/clock.c | 44 ++ arch/arm/mach-s3c2440/mach-anubis.c | 22 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +- arch/arm/mach-s3c2440/mach-osiris.c | 24 +- arch/arm/mach-s3c2440/mach-rx1950.c | 18 +- arch/arm/mach-s3c2440/mach-rx3715.c | 19 +- arch/arm/mach-s3c64xx/clock.c | 37 +- arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 +- arch/arm/mach-s5p64x0/clock-s5p6450.c | 32 +- arch/arm/mach-s5p64x0/init.c | 31 - arch/arm/mach-s5pc100/clock.c | 33 +- arch/arm/mach-s5pv210/clock.c | 107 ++-- arch/arm/mach-s5pv210/init.c | 19 - arch/arm/plat-s3c24xx/s3c2443-clock.c | 23 +- arch/arm/plat-samsung/include/plat/regs-serial.h | 45 +- drivers/tty/serial/Kconfig | 45 +-- drivers/tty/serial/Makefile | 5 - drivers/tty/serial/s3c2410.c | 115 ---- drivers/tty/serial/s3c2412.c | 149 ----- drivers/tty/serial/s3c2440.c | 178 ------ drivers/tty/serial/s3c6400.c | 149 ----- drivers/tty/serial/s5pv210.c | 158 ----- drivers/tty/serial/samsung.c | 639 ++++++++++++-------- drivers/tty/serial/samsung.h | 32 +- 31 files changed, 752 insertions(+), 1426 deletions(-) create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.txt delete mode 100644 drivers/tty/serial/s3c2410.c delete mode 100644 drivers/tty/serial/s3c2412.c delete mode 100644 drivers/tty/serial/s3c2440.c delete mode 100644 drivers/tty/serial/s3c6400.c delete mode 100644 drivers/tty/serial/s5pv210.c
PATCH v2 1/9 serial: samsung: Keep a copy of the location of platform data in driver's private data
Add a pointer to the location of the platform data in the driver's private data. When instantiated using device tree, pdev->dev->platform_data does not necessarily point to a valid instance of platform data. The platform data pointer in the driver's private data could be set to pdev->dev->platform_data or platform data instance created from device tree.
--- drivers/tty/serial/s5pv210.c | 12 ++++++++++-- drivers/tty/serial/samsung.c | 16 ++++++++++++---- drivers/tty/serial/samsung.h | 4 +++- 3 files changed, 25 insertions(+), 7 deletions(-)
drivers/tty/serial/s5pv210.c +10 -2
@@ -28,9 +28,13 @@static int s5pv210_serial_setsource (struct uart_port *port,struct s3c24xx_uart_clksrc *clk) { -struct s3c2410_uartcfg *cfg = port->dev->platform_data; +struct s3c24xx_uart_port *ourport; +struct s3c2410_uartcfg *cfg;unsigned long ucon =rd_regl (port,S3C2410_UCON ); + ourport = container_of(port, struct s3c24xx_uart_port, port); + cfg = ourport->cfg; +if (cfg->flags &NO_NEED_CHECK_CLKSRC )return 0 ;
@@ -51,9 +55,13 @@ static int s5pv210_serial_setsource(struct uart_port *port,static int s5pv210_serial_getsource (struct uart_port *port,struct s3c24xx_uart_clksrc *clk) { -struct s3c2410_uartcfg *cfg = port->dev->platform_data; +struct s3c24xx_uart_port *ourport; +struct s3c2410_uartcfg *cfg;u32 ucon =rd_regl (port,S3C2410_UCON ); + ourport = container_of(port, struct s3c24xx_uart_port, port); + cfg = ourport->cfg; + clk->divisor =1 ;if (cfg->flags &NO_NEED_CHECK_CLKSRC )
drivers/tty/serial/samsung.c +12 -4
@@ -190,10 +190,13 @@ static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *pstatic inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg (struct uart_port *port) { +struct s3c24xx_uart_port *ourport; +if (port->dev ==NULL )return NULL ; -return (struct s3c2410_uartcfg *)port->dev->platform_data; + ourport = container_of(port, struct s3c24xx_uart_port, port); +return ourport->cfg; } static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
@@ -1125,7 +1128,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport, struct platform_device *platdev) {struct uart_port *port = &ourport->port; -struct s3c2410_uartcfg *cfg; +struct s3c2410_uartcfg *cfg = platdev->dev.platform_data;struct resource *res;int ret;
@@ -1134,11 +1137,16 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,if (platdev ==NULL )return -ENODEV ; - cfg =s3c24xx_dev_to_cfg (&platdev->dev); -if (port->mapbase !=0 )return 0 ; +/* +* If platform data is supplied, keep a copy of the location of +* platform data in the driver's private data. +*/ +if (cfg) + ourport->cfg = cfg; +if (cfg->hwport >CONFIG_SERIAL_SAMSUNG_UARTS ) {printk (KERN_ERR "%s: port %d bigger than %d\n" , __func__, cfg->hwport,CONFIG_SERIAL_SAMSUNG_UARTS );
drivers/tty/serial/samsung.h +3 -1
@@ -48,6 +48,9 @@ struct s3c24xx_uart_port {struct clk *baudclk;struct uart_port port; +/* reference to platform data */ +struct s3c2410_uartcfg *cfg; +#ifdef CONFIG_CPU_FREQ struct notifier_block freq_transition;#endif
@@ -56,7 +59,6 @@ struct s3c24xx_uart_port {/* conversion functions */ #define s3c24xx_dev_to_port (__dev) (struct uart_port *)dev_get_drvdata(__dev) -#define s3c24xx_dev_to_cfg (__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)/* register access controls */
Signature · 1 line
1.6.6.rc2
PATCH v2 2/9 serial: samsung: move handling of fclk/n clock to platform code
In reply to Thomas Abrahams3c2440 uses fclk/n (fclk divided by n) clock as one of the possible clocks used to generate the baud rate clock. The divider 'n' in this case can be logically represented outside of the uart controller.
This patch creates a new clock by name "fclk_n" for s3c2440 based platforms to represent the fclk/n clock in the platform code. This clock provides a get_rate callback that checks the UCON0/1/2 registers to determine the clock rate. The samsung uart driver would receive the "fclk_n" clock name as one of the possible baud rate clock options and the driver need not determine clock rate of fclk/n.
--- arch/arm/mach-s3c2440/clock.c | 37 +++++++++++++++++++++++++++++++++++ arch/arm/mach-s3c2440/mach-rx1950.c | 4 +- arch/arm/mach-s3c2440/mach-rx3715.c | 4 +- drivers/tty/serial/s3c2440.c | 33 ++---------------------------- drivers/tty/serial/samsung.c | 21 ------------------- 5 files changed, 44 insertions(+), 55 deletions(-)
arch/arm/mach-s3c2440/clock.c +37 -0
@@ -34,6 +34,7 @@#include <linux/mutex.h> #include <linux/clk.h> #include <linux/io.h> +#include <linux/serial_core.h> #include <mach/hardware.h> #include <linux/atomic.h>
@@ -43,6 +44,7 @@#include <plat/clock.h> #include <plat/cpu.h> +#include <plat/regs-serial.h> /* S3C2440 extended clock support */
@@ -108,6 +110,40 @@ static struct clk s3c2440_clk_ac97 = { .ctrlbit = S3C2440_CLKCON_CAMERA, }; +static unsigned long s3c2440_fclk_n_getrate (struct clk *clk) +{ +unsigned long ucon0, ucon1, ucon2, divisor; + +/* the fun of calculating the uart divisors on the s3c2440 */ + ucon0 =__raw_readl (S3C24XX_VA_UART0 +S3C2410_UCON ); + ucon1 =__raw_readl (S3C24XX_VA_UART1 +S3C2410_UCON ); + ucon2 =__raw_readl (S3C24XX_VA_UART2 +S3C2410_UCON ); + + ucon0 &=S3C2440_UCON0_DIVMASK ; + ucon1 &=S3C2440_UCON1_DIVMASK ; + ucon2 &=S3C2440_UCON2_DIVMASK ; + +if (ucon0 !=0 ) + divisor = (ucon0 >>S3C2440_UCON_DIVSHIFT ) +6 ; +else if (ucon1 !=0 ) + divisor = (ucon1 >>S3C2440_UCON_DIVSHIFT ) +21 ; +else if (ucon2 !=0 ) + divisor = (ucon2 >>S3C2440_UCON_DIVSHIFT ) +36 ; +else +/* manual calims 44, seems to be 9 */ + divisor =9 ; + +return clk_get_rate (clk->parent) / divisor; +} + +static struct clk s3c2440_clk_fclk_n = { + .name ="fclk_n" , + .parent = &clk_f, + .ops = &(struct clk_ops ) { + .get_rate = s3c2440_fclk_n_getrate, + }, +}; +static int s3c2440_clk_add (struct sys_device *sysdev) {struct clk *clock_upll;
@@ -126,6 +162,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev) s3c2440_clk_cam.parent = clock_h; s3c2440_clk_ac97.parent = clock_p; s3c2440_clk_cam_upll.parent = clock_upll; +s3c24xx_register_clock (&s3c2440_clk_fclk_n);s3c24xx_register_clock (&s3c2440_clk_ac97);s3c24xx_register_clock (&s3c2440_clk_cam);
arch/arm/mach-s3c2440/mach-rx1950.c +2 -2
@@ -69,8 +69,8 @@ static struct map_desc rx1950_iodesc[] __initdata = {static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { [0 ] = { - .name ="fclk" , - .divisor =0x0a , + .name ="fclk_n" , + .divisor =1 , .min_baud =0 , .max_baud =0 , },
arch/arm/mach-s3c2440/mach-rx3715.c +2 -2
@@ -70,8 +70,8 @@ static struct map_desc rx3715_iodesc[] __initdata = {static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { [0 ] = { - .name ="fclk" , - .divisor =0 , + .name ="fclk_n" , + .divisor =1 , .min_baud =0 , .max_baud =0 , }
drivers/tty/serial/s3c2440.c +3 -30
@@ -39,7 +39,7 @@ static int s3c2440_serial_setsource(struct uart_port *port, ucon |=S3C2440_UCON_UCLK ; else if (strcmp(clk->name, "pclk") == 0) ucon |= S3C2440_UCON_PCLK; - else if (strcmp(clk->name, "fclk") == 0) + else if (strcmp(clk->name, "fclk_n") == 0) ucon |= S3C2440_UCON_FCLK; else {printk (KERN_ERR "unknown clock source %s\n" , clk->name);
@@ -55,7 +55,6 @@ static int s3c2440_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *clk) {unsigned long ucon =rd_regl (port,S3C2410_UCON ); -unsigned long ucon0, ucon1, ucon2;switch (ucon &S3C2440_UCON_CLKMASK ) {case S3C2440_UCON_UCLK :
@@ -70,34 +69,8 @@ static int s3c2440_serial_getsource(struct uart_port *port,break ;case S3C2440_UCON_FCLK : -/* the fun of calculating the uart divisors on -* the s3c2440 */ - - ucon0 =__raw_readl (S3C24XX_VA_UART0 +S3C2410_UCON ); - ucon1 =__raw_readl (S3C24XX_VA_UART1 +S3C2410_UCON ); - ucon2 =__raw_readl (S3C24XX_VA_UART2 +S3C2410_UCON ); - -printk ("ucons: %08lx, %08lx, %08lx\n" , ucon0, ucon1, ucon2); - - ucon0 &=S3C2440_UCON0_DIVMASK ; - ucon1 &=S3C2440_UCON1_DIVMASK ; - ucon2 &=S3C2440_UCON2_DIVMASK ; - -if (ucon0 !=0 ) { - clk->divisor = ucon0 >>S3C2440_UCON_DIVSHIFT ; - clk->divisor +=6 ; - }else if (ucon1 !=0 ) { - clk->divisor = ucon1 >>S3C2440_UCON_DIVSHIFT ; - clk->divisor +=21 ; - }else if (ucon2 !=0 ) { - clk->divisor = ucon2 >>S3C2440_UCON_DIVSHIFT ; - clk->divisor +=36 ; - }else { -/* manual calims 44, seems to be 9 */ - clk->divisor =9 ; - } - - clk->name ="fclk" ; + clk->divisor =1 ; + clk->name ="fclk_n" ;break ; }
drivers/tty/serial/samsung.c +0 -21
@@ -649,27 +649,6 @@ static unsigned int s3c24xx_serial_getclk(struct uart_port *port,if (cfg->clocks_size ==0 ) clkp = &tmp_clksrc; -/* check to see if we're sourcing fclk, and if so we're -* going to have to update the clock source -*/ - -if (strcmp (clkp->name,"fclk" ) ==0 ) { -struct s3c24xx_uart_clksrc src; - -s3c24xx_serial_getsource (port, &src); - -/* check that the port already using fclk, and if -* not, then re-select fclk -*/ - -if (strcmp (src.name, clkp->name) ==0 ) { -s3c24xx_serial_setsource (port, clkp); -s3c24xx_serial_getsource (port, &src); - } - - clkp->divisor = src.divisor; - } -s3c24xx_serial_calcbaud (res, port, clkp, baud); best = res; resptr = best +1 ;
Signature · 1 line
1.6.6.rc2
PATCH v2 3/9 serial: samsung: switch to clkdev based clock lookup
In reply to Thomas AbrahamInstead of using clock names supplied in platform data, use a generic clock name 'clk_uart_baud' to look up clocks. The platform code should register clocks with the name 'clk_uart_baud' which can be used by the baud rate generator. The clock lookup and selection of the best clock as baud rate clock is reworked.
Platform code can specify the clocks that can be used as source for the baud clock (as supported previously by passing names of clocks). A new member is added to the platform data 'clk_sel' which holds a bit-field value with each bit representing a baud source clock. If a bit at any bit position is set, that clock is looked up to participate in the selection of the baud clock source.
--- arch/arm/plat-samsung/include/plat/regs-serial.h | 5 + drivers/tty/serial/samsung.c | 207 +++++++++------------- drivers/tty/serial/samsung.h | 4 + 3 files changed, 95 insertions(+), 121 deletions(-)
arch/arm/plat-samsung/include/plat/regs-serial.h +5 -0
@@ -222,6 +222,10 @@#define S5PV210_UFSTAT_RXSHIFT (0)#define NO_NEED_CHECK_CLKSRC 1 +#define S3C2410_UCON_CLKSEL0 (1 << 0) +#define S3C2410_UCON_CLKSEL1 (1 << 1) +#define S3C2410_UCON_CLKSEL2 (1 << 2) +#define S3C2410_UCON_CLKSEL3 (1 << 3)#ifndef __ASSEMBLY__
@@ -257,6 +261,7 @@ struct s3c2410_uartcfg {unsigned char unused;unsigned short flags;upf_t uart_flags;/* default uart flags */ +unsigned int clk_sel;unsigned int has_fracval;
drivers/tty/serial/samsung.c +86 -121
289 lines not on this page · raw message
drivers/tty/serial/samsung.h +4 -0
@@ -19,6 +19,10 @@ struct s3c24xx_uart_info {unsigned long tx_fifomask;unsigned long tx_fifoshift;unsigned long tx_fifofull; +unsigned int def_clk_sel; +unsigned long num_clks; +unsigned long clksel_mask; +unsigned long clksel_shift;/* uart port features */
Signature · 1 line
1.6.6.rc2
PATCH v2 4/9 serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
In reply to Thomas AbrahamWith clkdev based clock lookup added to samsung serial driver, the use of 'struct s3c24xx_uart_clksrc' to supply clock names in platform data is removed from all the Samsung platform code.
--- arch/arm/mach-exynos4/init.c | 15 +---------- arch/arm/mach-s3c2410/mach-bast.c | 22 --------------- arch/arm/mach-s3c2410/mach-vr1000.c | 24 ----------------- arch/arm/mach-s3c2440/mach-anubis.c | 22 +-------------- arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +-------------- arch/arm/mach-s3c2440/mach-osiris.c | 24 ++--------------- arch/arm/mach-s3c2440/mach-rx1950.c | 18 ++---------- arch/arm/mach-s3c2440/mach-rx3715.c | 19 ++----------- arch/arm/mach-s5p64x0/init.c | 31 ---------------------- arch/arm/mach-s5pv210/init.c | 19 ------------- arch/arm/plat-samsung/include/plat/regs-serial.h | 23 ---------------- drivers/tty/serial/samsung.h | 1 - 12 files changed, 14 insertions(+), 226 deletions(-)
arch/arm/mach-exynos4/init.c +1 -14
@@ -14,15 +14,6 @@#include <plat/devs.h> #include <plat/regs-serial.h> -static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = { - [0 ] = { - .name ="uclk1" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, -}; -/* uart registration process */ void __init exynos4_common_init_uarts (struct s3c2410_uartcfg *cfg,int no) {
@@ -30,11 +21,7 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)u32 ucnt;for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) { -if (!tcfg->clocks) { - tcfg->has_fracval =1 ; - tcfg->clocks = exynos4_serial_clocks; - tcfg->clocks_size =ARRAY_SIZE (exynos4_serial_clocks); - } + tcfg->has_fracval =1 ; tcfg->flags |=NO_NEED_CHECK_CLKSRC ; }
arch/arm/mach-s3c2410/mach-bast.c +0 -22
@@ -164,22 +164,6 @@ static struct map_desc bast_iodesc[] __initdata = {#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc bast_serial_clocks[] = { - [0 ] = { - .name ="uclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - } -}; - -static struct s3c2410_uartcfg bast_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -187,8 +171,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), }, [1] = { .hwport = 1,
@@ -196,8 +178,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), },/* port 2 is not actually used */ [2] = {
@@ -206,8 +186,6 @@ static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = bast_serial_clocks, - .clocks_size = ARRAY_SIZE(bast_serial_clocks), } };
arch/arm/mach-s3c2410/mach-vr1000.c +0 -24
@@ -109,23 +109,6 @@ static struct map_desc vr1000_iodesc[] __initdata = {#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -/* uart clock source(s) */ - -static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = { - [0 ] = { - .name ="uclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0. - } -}; -static struct s3c2410_uartcfg vr1000_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -133,8 +116,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), }, [1] = { .hwport = 1,
@@ -142,8 +123,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), },/* port 2 is not actually used */ [2] = {
@@ -152,9 +131,6 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = vr1000_serial_clocks, - .clocks_size = ARRAY_SIZE(vr1000_serial_clocks), - } };
arch/arm/mach-s3c2440/mach-anubis.c +2 -20
@@ -96,22 +96,6 @@ static struct map_desc anubis_iodesc[] __initdata = {#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = { - [0 ] = { - .name ="uclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - } -}; - -static struct s3c2410_uartcfg anubis_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -119,8 +103,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 2,
@@ -128,8 +111,7 @@ static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = anubis_serial_clocks, - .clocks_size = ARRAY_SIZE(anubis_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, };
arch/arm/mach-s3c2440/mach-at2440evb.c +2 -20
@@ -57,22 +57,6 @@ static struct map_desc at2440evb_iodesc[] __initdata = {#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE) -static struct s3c24xx_uart_clksrc at2440evb_serial_clocks[] = { - [0 ] = { - .name ="uclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - } -}; - -static struct s3c2410_uartcfg at2440evb_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -80,8 +64,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = at2440evb_serial_clocks, - .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 1,
@@ -89,8 +72,7 @@ static struct s3c2410_uartcfg at2440evb_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = at2440evb_serial_clocks, - .clocks_size = ARRAY_SIZE(at2440evb_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, };
arch/arm/mach-s3c2440/mach-osiris.c +3 -21
@@ -100,21 +100,6 @@ static struct map_desc osiris_iodesc[] __initdata = {#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE -static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = { - [0 ] = { - .name ="uclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - } -}; -static struct s3c2410_uartcfg osiris_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -122,8 +107,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [1] = { .hwport = 1,
@@ -131,8 +115,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, }, [2] = { .hwport = 2,
@@ -140,8 +123,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = { .ucon = UCON, .ulcon = ULCON, .ufcon = UFCON, - .clocks = osiris_serial_clocks, - .clocks_size = ARRAY_SIZE(osiris_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2, } };
arch/arm/mach-s3c2440/mach-rx1950.c +3 -15
@@ -67,15 +67,6 @@static struct map_desc rx1950_iodesc[]__initdata = { }; -static struct s3c24xx_uart_clksrc rx1950_serial_clocks[] = { - [0 ] = { - .name ="fclk_n" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, -}; -static struct s3c2410_uartcfg rx1950_uartcfgs[]__initdata = { [0 ] = { .hwport =0 ,
@@ -83,8 +74,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, [1] = { .hwport = 1,
@@ -92,8 +82,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, },/* IR port */ [2] = {
@@ -102,8 +91,7 @@ static struct s3c2410_uartcfg rx1950_uartcfgs[] __initdata = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0xf1, - .clocks = rx1950_serial_clocks, - .clocks_size = ARRAY_SIZE(rx1950_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, };
arch/arm/mach-s3c2440/mach-rx3715.c +3 -16
@@ -67,16 +67,6 @@ static struct map_desc rx3715_iodesc[] __initdata = { }, }; - -static struct s3c24xx_uart_clksrc rx3715_serial_clocks[] = { - [0 ] = { - .name ="fclk_n" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - } -}; -static struct s3c2410_uartcfg rx3715_uartcfgs[] = { [0 ] = { .hwport =0 ,
@@ -84,8 +74,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, }, [1] = { .hwport = 1,
@@ -93,8 +82,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x03, .ufcon = 0x00, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, },/* IR port */ [2] = {
@@ -103,8 +91,7 @@ static struct s3c2410_uartcfg rx3715_uartcfgs[] = { .ucon = 0x3c5, .ulcon = 0x43, .ufcon = 0x51, - .clocks = rx3715_serial_clocks, - .clocks_size = ARRAY_SIZE(rx3715_serial_clocks), + .clk_sel = S3C2410_UCON_CLKSEL3, } };
arch/arm/mach-s5p64x0/init.c +0 -31
@@ -23,36 +23,7 @@#include <plat/s5p6450.h> #include <plat/regs-serial.h> -static struct s3c24xx_uart_clksrc s5p64x0_serial_clocks[] = { - [0 ] = { - .name ="pclk_low" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, - [1 ] = { - .name ="uclk1" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, -}; -/* uart registration process */ - -void __init s5p64x0_common_init_uarts (struct s3c2410_uartcfg *cfg,int no) -{ -struct s3c2410_uartcfg *tcfg = cfg; -u32 ucnt; - -for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) { -if (!tcfg->clocks) { - tcfg->clocks = s5p64x0_serial_clocks; - tcfg->clocks_size =ARRAY_SIZE (s5p64x0_serial_clocks); - } - } -} -void __init s5p6440_init_uarts (struct s3c2410_uartcfg *cfg,int no) {int uart;
@@ -62,12 +33,10 @@ void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) s5p_uart_resources[uart].resources->end =S5P6440_PA_UART (uart) +S5P_SZ_UART ; } -s5p64x0_common_init_uarts (cfg, no);s3c24xx_init_uartdevs ("s3c6400-uart" , s5p_uart_resources, cfg, no); }void __init s5p6450_init_uarts (struct s3c2410_uartcfg *cfg,int no) { -s5p64x0_common_init_uarts (cfg, no);s3c24xx_init_uartdevs ("s3c6400-uart" , s5p_uart_resources, cfg, no); }
arch/arm/mach-s5pv210/init.c +0 -19
@@ -18,27 +18,8 @@#include <plat/s5pv210.h> #include <plat/regs-serial.h> -static struct s3c24xx_uart_clksrc s5pv210_serial_clocks[] = { - [0 ] = { - .name ="pclk" , - .divisor =1 , - .min_baud =0 , - .max_baud =0 , - }, -}; -/* uart registration process */ void __init s5pv210_common_init_uarts (struct s3c2410_uartcfg *cfg,int no) { -struct s3c2410_uartcfg *tcfg = cfg; -u32 ucnt; - -for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) { -if (!tcfg->clocks) { - tcfg->clocks = s5pv210_serial_clocks; - tcfg->clocks_size =ARRAY_SIZE (s5pv210_serial_clocks); - } - } -s3c24xx_init_uartdevs ("s5pv210-uart" , s5p_uart_resources, cfg, no); }
arch/arm/plat-samsung/include/plat/regs-serial.h +0 -23
@@ -229,26 +229,6 @@#ifndef __ASSEMBLY__ -/* struct s3c24xx_uart_clksrc -* -* this structure defines a named clock source that can be used for the -* uart, so that the best clock can be selected for the requested baud -* rate. -* -* min_baud and max_baud define the range of baud-rates this clock is -* acceptable for, if they are both zero, it is assumed any baud rate that -* can be generated from this clock will be used. -* -* divisor gives the divisor from the clock to the one seen by the uart -*/ - -struct s3c24xx_uart_clksrc { -const char *name; -unsigned int divisor; -unsigned int min_baud; -unsigned int max_baud; -}; -/* configuration structure for per-machine configurations for the * serial port *
@@ -268,9 +248,6 @@ struct s3c2410_uartcfg {unsigned long ucon;/* value of ucon for port */ unsigned long ulcon;/* value of ulcon for port */ unsigned long ufcon;/* value of ufcon for port */ - -struct s3c24xx_uart_clksrc *clocks; -unsigned int clocks_size; };/* s3c24xx_uart_devs
drivers/tty/serial/samsung.h +0 -1
@@ -47,7 +47,6 @@ struct s3c24xx_uart_port {unsigned int tx_irq;struct s3c24xx_uart_info *info; -struct s3c24xx_uart_clksrc *clksrc;struct clk *clk;struct clk *baudclk;struct uart_port port;
Signature · 1 line
1.6.6.rc2
PATCH v2 4/9 serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
Quoted 8 lines · Thomas Abraham
With clkdev based clock lookup added to samsung serial driver, the use of 'struct
s3c24xx_uart_clksrc' to supply clock names in platform data is removed from all the Samsung platform code.Cc Ben Dooks <[email protected]>Cc Ramax Lo <[email protected]>Cc Vasily Khoruzhick <[email protected]>Signed-off-by Thomas Abraham <[email protected]>
Quoted 14 lines
--- arch/arm/mach-exynos4/init.c | 15 +---------- arch/arm/mach-s3c2410/mach-bast.c | 22 --------------- arch/arm/mach-s3c2410/mach-vr1000.c | 24 ----------------- arch/arm/mach-s3c2440/mach-anubis.c | 22 +-------------- arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +-------------- arch/arm/mach-s3c2440/mach-osiris.c | 24 ++--------------- arch/arm/mach-s3c2440/mach-rx1950.c | 18 ++---------- arch/arm/mach-s3c2440/mach-rx3715.c | 19 ++----------- arch/arm/mach-s5p64x0/init.c | 31 ---------------------- arch/arm/mach-s5pv210/init.c | 19 ------------- arch/arm/plat-samsung/include/plat/regs-serial.h | 23 ---------------- drivers/tty/serial/samsung.h | 1 - 12 files changed, 14 insertions(+), 226 deletions(-)
Nice diffstat. :-)
g.
PATCH v2 5/9 serial: samsung: remove all uses of get_clksrc and set_clksrc
In reply to Thomas AbrahamWith clkdev based clock lookup support, the clock set and get operation using clock names communicated between the samsung uart driver and the SoC specific extension can be removed.
In addition to that, for each platform specific extension, add the default clock selection, number of clock options for uart baud generator, clock selection bit mask and shift values which is required by the clkdev support in samsung uart driver.
The default clock selection value 'def_clk_sel' specifies the default clock to be used as the source clock for baud rate generator in case the platform code does not specify the same.
--- arch/arm/mach-exynos4/init.c | 4 +- arch/arm/plat-samsung/include/plat/regs-serial.h | 7 ++- drivers/tty/serial/s3c2410.c | 31 ++---------- drivers/tty/serial/s3c2412.c | 55 ++------------------ drivers/tty/serial/s3c2440.c | 58 ++------------------- drivers/tty/serial/s3c6400.c | 54 ++------------------ drivers/tty/serial/s5pv210.c | 60 ++-------------------- drivers/tty/serial/samsung.h | 5 -- 8 files changed, 27 insertions(+), 247 deletions(-)
arch/arm/mach-exynos4/init.c +1 -3
@@ -20,10 +20,8 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)struct s3c2410_uartcfg *tcfg = cfg;u32 ucnt; -for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) { +for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) tcfg->has_fracval =1 ; - tcfg->flags |=NO_NEED_CHECK_CLKSRC ; - }s3c24xx_init_uartdevs ("s5pv210-uart" , s5p_uart_resources, cfg, no); }
arch/arm/plat-samsung/include/plat/regs-serial.h +6 -1
@@ -71,6 +71,7 @@#define S3C2410_LCON_IRM (1<<6)#define S3C2440_UCON_CLKMASK (3<<10) +#define S3C2440_UCON_CLKSHIFT (10)#define S3C2440_UCON_PCLK (0<<10)#define S3C2440_UCON_UCLK (1<<10)#define S3C2440_UCON_PCLK2 (2<<10)
@@ -78,6 +79,7 @@#define S3C2443_UCON_EPLL (3<<10)#define S3C6400_UCON_CLKMASK (3<<10) +#define S3C6400_UCON_CLKSHIFT (10)#define S3C6400_UCON_PCLK (0<<10)#define S3C6400_UCON_PCLK2 (2<<10)#define S3C6400_UCON_UCLK0 (1<<10)
@@ -90,11 +92,14 @@#define S3C2440_UCON_DIVSHIFT (12)#define S3C2412_UCON_CLKMASK (3<<10) +#define S3C2412_UCON_CLKSHIFT (10)#define S3C2412_UCON_UCLK (1<<10)#define S3C2412_UCON_USYSCLK (3<<10)#define S3C2412_UCON_PCLK (0<<10)#define S3C2412_UCON_PCLK2 (2<<10) +#define S3C2410_UCON_CLKMASK (1 << 10) +#define S3C2410_UCON_CLKSHIFT (10)#define S3C2410_UCON_UCLK (1<<10)#define S3C2410_UCON_SBREAK (1<<4)
@@ -193,6 +198,7 @@/* Following are specific to S5PV210 */ #define S5PV210_UCON_CLKMASK (1<<10) +#define S5PV210_UCON_CLKSHIFT (10)#define S5PV210_UCON_PCLK (0<<10)#define S5PV210_UCON_UCLK (1<<10)
@@ -221,7 +227,6 @@#define S5PV210_UFSTAT_RXMASK (255<<0)#define S5PV210_UFSTAT_RXSHIFT (0) -#define NO_NEED_CHECK_CLKSRC 1#define S3C2410_UCON_CLKSEL0 (1 << 0)#define S3C2410_UCON_CLKSEL1 (1 << 1)#define S3C2410_UCON_CLKSEL2 (1 << 2)
drivers/tty/serial/s3c2410.c +4 -27
@@ -25,31 +25,6 @@#include "samsung.h" -static int s3c2410_serial_setsource (struct uart_port *port, -struct s3c24xx_uart_clksrc *clk) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - -if (strcmp (clk->name,"uclk" ) ==0 ) - ucon |=S3C2410_UCON_UCLK ; -else - ucon &= ~S3C2410_UCON_UCLK ; - -wr_regl (port,S3C2410_UCON , ucon); -return 0 ; -} - -static int s3c2410_serial_getsource (struct uart_port *port, -struct s3c24xx_uart_clksrc *clk) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - - clk->divisor =1 ; - clk->name = (ucon &S3C2410_UCON_UCLK ) ?"uclk" :"pclk" ; - -return 0 ; -} -static int s3c2410_serial_resetport (struct uart_port *port,struct s3c2410_uartcfg *cfg) {
@@ -77,8 +52,10 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = { .tx_fifofull = S3C2410_UFSTAT_TXFULL, .tx_fifomask = S3C2410_UFSTAT_TXMASK, .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT, - .get_clksrc = s3c2410_serial_getsource, - .set_clksrc = s3c2410_serial_setsource, + .def_clk_sel = S3C2410_UCON_CLKSEL0, + .num_clks = 2, + .clksel_mask = S3C2410_UCON_CLKMASK, + .clksel_shift = S3C2410_UCON_CLKSHIFT, .reset_port = s3c2410_serial_resetport, };
drivers/tty/serial/s3c2412.c +4 -51
67 lines not on this page · raw message
drivers/tty/serial/s3c2440.c +4 -54
70 lines not on this page · raw message
drivers/tty/serial/s3c6400.c +4 -50
66 lines not on this page · raw message
drivers/tty/serial/s5pv210.c +4 -56
72 lines not on this page · raw message
drivers/tty/serial/samsung.h +0 -5
@@ -28,11 +28,6 @@ struct s3c24xx_uart_info { unsigned int has_divslot:1; -/* clock source control */ - -int (*get_clksrc)(struct uart_port *,struct s3c24xx_uart_clksrc *clk); -int (*set_clksrc)(struct uart_port *,struct s3c24xx_uart_clksrc *clk); -/* uart controls */ int (*reset_port)(struct uart_port *,struct s3c2410_uartcfg *); };
Signature · 1 line
1.6.6.rc2
PATCH v2 6/9 arm: samsung: register uart clocks to clock lookup list
In reply to Thomas AbrahamSamsung uart driver lookups the clock using the connection id 'clk_uart_baud'. The uart clocks for all Samsung platforms are reorganized to register them with the lookup name as required by the uart driver.
--- arch/arm/mach-exynos4/clock.c | 106 ++++++++++++++++++++------------ arch/arm/mach-exynos4/init.c | 2 +- arch/arm/mach-s3c2410/s3c2410.c | 6 ++ arch/arm/mach-s3c2412/clock.c | 7 ++ arch/arm/mach-s3c2440/clock.c | 7 ++ arch/arm/mach-s3c64xx/clock.c | 37 ++++++++--- arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 +++++++--- arch/arm/mach-s5p64x0/clock-s5p6450.c | 32 +++++++--- arch/arm/mach-s5pc100/clock.c | 33 +++++++--- arch/arm/mach-s5pv210/clock.c | 107 ++++++++++++++++++++------------ arch/arm/plat-s3c24xx/s3c2443-clock.c | 23 +++++-- 11 files changed, 266 insertions(+), 126 deletions(-)
arch/arm/mach-exynos4/clock.c +66 -40
@@ -1014,46 +1014,6 @@ static struct clksrc_clk clk_dout_mmc4 = {static struct clksrc_clk clksrcs[] = { { - .clk = { - .name ="uclk1" , - .devname ="s5pv210-uart.0" , - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 <<0 ), - }, - .sources = &clkset_group, - .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =0 , .size =4 }, - .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =0 , .size =4 }, - }, { - .clk = { - .name ="uclk1" , - .devname ="s5pv210-uart.1" , - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 <<4 ), - }, - .sources = &clkset_group, - .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =4 , .size =4 }, - .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =4 , .size =4 }, - }, { - .clk = { - .name ="uclk1" , - .devname ="s5pv210-uart.2" , - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 <<8 ), - }, - .sources = &clkset_group, - .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =8 , .size =4 }, - .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =8 , .size =4 }, - }, { - .clk = { - .name ="uclk1" , - .devname ="s5pv210-uart.3" , - .enable = exynos4_clksrc_mask_peril0_ctrl, - .ctrlbit = (1 <<12 ), - }, - .sources = &clkset_group, - .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =12 , .size =4 }, - .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =12 , .size =4 }, - }, { .clk = { .name ="sclk_pwm" , .enable = exynos4_clksrc_mask_peril0_ctrl,
@@ -1242,6 +1202,54 @@ static struct clksrc_clk clksrcs[] = { } }; +static struct clksrc_clk clk_sclk_uart0 = { + .clk = { + .name ="uclk1" , + .devname ="exynos4210-uart.0" , + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 <<0 ), + }, + .sources = &clkset_group, + .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =0 , .size =4 }, + .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =0 , .size =4 }, +}; + +static struct clksrc_clk clk_sclk_uart1 = { + .clk = { + .name ="uclk1" , + .devname ="exynos4210-uart.1" , + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 <<4 ), + }, + .sources = &clkset_group, + .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =4 , .size =4 }, + .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =4 , .size =4 }, +}; + +static struct clksrc_clk clk_sclk_uart2 = { + .clk = { + .name ="uclk1" , + .devname ="exynos4210-uart.2" , + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 <<8 ), + }, + .sources = &clkset_group, + .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =8 , .size =4 }, + .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =8 , .size =4 }, +}; + +static struct clksrc_clk clk_sclk_uart3 = { + .clk = { + .name ="uclk1" , + .devname ="exynos4210-uart.3" , + .enable = exynos4_clksrc_mask_peril0_ctrl, + .ctrlbit = (1 <<12 ), + }, + .sources = &clkset_group, + .reg_src = { .reg =S5P_CLKSRC_PERIL0 , .shift =12 , .size =4 }, + .reg_div = { .reg =S5P_CLKDIV_PERIL0 , .shift =12 , .size =4 }, +}; +/* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll,
@@ -1276,6 +1284,20 @@ static struct clksrc_clk *sysclks[] = { &clk_mout_mfc1, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart0, + &clk_sclk_uart1, + &clk_sclk_uart2, + &clk_sclk_uart3, +}; + +static struct clk_lookup exynos4_clk_lookup[] = { +CLKDEV_INIT ("exynos4210-uart.0" ,"clk_uart_baud0" , &clk_sclk_uart0.clk), +CLKDEV_INIT ("exynos4210-uart.1" ,"clk_uart_baud0" , &clk_sclk_uart1.clk), +CLKDEV_INIT ("exynos4210-uart.2" ,"clk_uart_baud0" , &clk_sclk_uart2.clk), +CLKDEV_INIT ("exynos4210-uart.3" ,"clk_uart_baud0" , &clk_sclk_uart3.clk), +}; +static int xtal_rate;static unsigned long exynos4_fout_apll_get_rate (struct clk *clk)
@@ -1483,11 +1505,15 @@ void __init exynos4_register_clocks(void)for (ptr =0 ; ptr <ARRAY_SIZE (sclk_tv); ptr++)s3c_register_clksrc (sclk_tv[ptr],1 ); +for (ptr =0 ; ptr <ARRAY_SIZE (clksrc_cdev); ptr++) +s3c_register_clksrc (clksrc_cdev[ptr],1 ); +s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs));s3c_register_clocks (init_clocks,ARRAY_SIZE (init_clocks));s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off));s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); +clkdev_add_table (exynos4_clk_lookup,ARRAY_SIZE (exynos4_clk_lookup));register_syscore_ops (&exynos4_clock_syscore_ops);s3c24xx_register_clock (&dummy_apb_pclk);
arch/arm/mach-exynos4/init.c +1 -1
@@ -23,5 +23,5 @@ void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)for (ucnt =0 ; ucnt < no; ucnt++, tcfg++) tcfg->has_fracval =1 ; -s3c24xx_init_uartdevs ("s5pv210-uart" , s5p_uart_resources, cfg, no); +s3c24xx_init_uartdevs ("exynos4210-uart" , s5p_uart_resources, cfg, no); }
arch/arm/mach-s3c2410/s3c2410.c +6 -0
@@ -123,12 +123,18 @@ static struct clk s3c2410_armclk = { .id = -1, }; +static struct clk_lookup s3c2410_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud0" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud1" , &s3c24xx_uclk), +}; +void __init s3c2410_init_clocks (int xtal) {s3c24xx_register_baseclocks (xtal);s3c2410_setup_clocks ();s3c2410_baseclk_add ();s3c24xx_register_clock (&s3c2410_armclk); +clkdev_add_table (s3c2410_clk_lookup,ARRAY_SIZE (s3c2410_clk_lookup)); }struct sysdev_class s3c2410_sysclass = {
arch/arm/mach-s3c2412/clock.c +7 -0
@@ -659,6 +659,12 @@ static struct clk *clks[] __initdata = { &clk_armclk, }; +static struct clk_lookup s3c2412_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud1" , &s3c24xx_uclk), +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_usysclk), +}; +int __init s3c2412_baseclk_add (void ) {unsigned long clkcon =__raw_readl (S3C2410_CLKCON );
@@ -751,6 +757,7 @@ int __init s3c2412_baseclk_add(void)s3c2412_clkcon_enable (clkp,0 ); } +clkdev_add_table (s3c2412_clk_lookup,ARRAY_SIZE (s3c2412_clk_lookup));s3c_pwmclk_init ();return 0 ; }
arch/arm/mach-s3c2440/clock.c +7 -0
@@ -144,6 +144,12 @@ static struct clk s3c2440_clk_fclk_n = { }, }; +static struct clk_lookup s3c2440_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud1" , &s3c24xx_uclk), +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &s3c2440_clk_fclk_n), +}; +static int s3c2440_clk_add (struct sys_device *sysdev) {struct clk *clock_upll;
@@ -167,6 +173,7 @@ static int s3c2440_clk_add(struct sys_device *sysdev)s3c24xx_register_clock (&s3c2440_clk_ac97);s3c24xx_register_clock (&s3c2440_clk_cam);s3c24xx_register_clock (&s3c2440_clk_cam_upll); +clkdev_add_table (s3c2440_clk_lookup,ARRAY_SIZE (s3c2440_clk_lookup));clk_disable (&s3c2440_clk_ac97);clk_disable (&s3c2440_clk_cam);
arch/arm/mach-s3c64xx/clock.c +27 -10
@@ -617,16 +617,6 @@ static struct clksrc_clk clksrcs[] = { .sources = &clkset_uhost, }, { .clk = { - .name = "uclk1", - .ctrlbit = S3C_CLKCON_SCLK_UART, - .enable = s3c64xx_sclk_ctrl, - }, - .reg_src = { .reg = S3C_CLK_SRC, .shift = 13, .size = 1 }, - .reg_div = { .reg = S3C_CLK_DIV2, .shift = 16, .size = 4 }, - .sources = &clkset_uart, - }, { -/* Where does UCLK0 come from? */ - .clk = { .name = "spi-bus", .devname = "s3c64xx-spi.0", .ctrlbit = S3C_CLKCON_SCLK_SPI0,
@@ -695,6 +685,18 @@ static struct clksrc_clk clksrcs[] = { }, }; +/* Where does UCLK0 come from? */ +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name ="uclk1" , + .ctrlbit =S3C_CLKCON_SCLK_UART , + .enable = s3c64xx_sclk_ctrl, + }, + .reg_src = { .reg =S3C_CLK_SRC , .shift =13 , .size =1 }, + .reg_div = { .reg =S3C_CLK_DIV2 , .shift =16 , .size =4 }, + .sources = &clkset_uart, +}; +/* Clock initialisation code */ static struct clksrc_clk *init_parents[] = {
@@ -703,6 +705,15 @@ static struct clksrc_clk *init_parents[] = { &clk_mout_mpll, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, +}; + +static struct clk_lookup s3c64xx_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_sclk_uclk.clk), +}; +#define GET_DIV (clk, field) ((((clk) & field##_MASK) >> field##_SHIFT) + 1) void __init_or_cpufreq s3c6400_setup_clocks(void)
@@ -811,6 +822,8 @@ static struct clk *clks[] __initdata = {void __init s3c64xx_register_clocks (unsigned long xtal,unsigned armclk_divlimit) { +unsigned int cnt; + armclk_mask = armclk_divlimit;s3c24xx_register_baseclocks (xtal);
@@ -823,5 +836,9 @@ void __init s3c64xx_register_clocks(unsigned long xtal,s3c24xx_register_clocks (clks1,ARRAY_SIZE (clks1));s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs)); +for (cnt =0 ; cnt <ARRAY_SIZE (clksrc_cdev); cnt++) +s3c_register_clksrc (clksrc_cdev[cnt],1 ); +clkdev_add_table (s3c64xx_clk_lookup,ARRAY_SIZE (s3c64xx_clk_lookup)); +s3c_pwmclk_init (); }
arch/arm/mach-s5p64x0/clock-s5p6440.c +23 -9
@@ -421,15 +421,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, }, { .clk = { - .name = "uclk1", - .ctrlbit = (1 << 5), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, - }, { - .clk = { .name = "sclk_spi", .devname = "s3c64xx-spi.0", .ctrlbit = (1 << 20),
@@ -487,6 +478,17 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name ="uclk1" , + .ctrlbit = (1 <<5 ), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg =S5P64X0_CLK_SRC0 , .shift =13 , .size =1 }, + .reg_div = { .reg =S5P64X0_CLK_DIV2 , .shift =16 , .size =4 }, +}; +/* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll,
@@ -505,6 +507,15 @@ static struct clk dummy_apb_pclk = { .id = -1, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, +}; + +static struct clk_lookup s5p6440_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_pclk_low.clk), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_sclk_uclk.clk), +}; + void __init_or_cpufreq s5p6440_setup_clocks(void) {struct clk *xtal_clk;
@@ -583,9 +594,12 @@ void __init s5p6440_register_clocks(void)s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs));s3c_register_clocks (init_clocks,ARRAY_SIZE (init_clocks)); +for (ptr =0 ; ptr <ARRAY_SIZE (clksrc_cdev); ptr++) +s3c_register_clksrc (clksrc_cdev[ptr],1 );s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off));s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); +clkdev_add_table (s5p6440_clk_lookup,ARRAY_SIZE (s5p6440_clk_lookup));s3c24xx_register_clock (&dummy_apb_pclk);
arch/arm/mach-s5p64x0/clock-s5p6450.c +23 -9
@@ -443,15 +443,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, }, { .clk = { - .name = "uclk1", - .ctrlbit = (1 << 5), - .enable = s5p64x0_sclk_ctrl, - }, - .sources = &clkset_uart, - .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, - .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, - }, { - .clk = { .name = "sclk_spi", .devname = "s3c64xx-spi.0", .ctrlbit = (1 << 20),
@@ -536,6 +527,26 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uclk = { + .clk = { + .name ="uclk1" , + .ctrlbit = (1 <<5 ), + .enable = s5p64x0_sclk_ctrl, + }, + .sources = &clkset_uart, + .reg_src = { .reg =S5P64X0_CLK_SRC0 , .shift =13 , .size =1 }, + .reg_div = { .reg =S5P64X0_CLK_DIV2 , .shift =16 , .size =4 }, +}; + +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uclk, +}; + +static struct clk_lookup s5p6450_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_pclk_low.clk), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_sclk_uclk.clk), +}; +/* Clock initialization code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll,
@@ -634,9 +645,12 @@ void __init s5p6450_register_clocks(void)s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs));s3c_register_clocks (init_clocks,ARRAY_SIZE (init_clocks)); +for (ptr =0 ; ptr <ARRAY_SIZE (clksrc_cdev); ptr++) +s3c_register_clksrc (clksrc_cdev[ptr],1 );s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off));s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); +clkdev_add_table (s5p6450_clk_lookup,ARRAY_SIZE (s5p6450_clk_lookup));s3c24xx_register_clock (&dummy_apb_pclk);
arch/arm/mach-s5pc100/clock.c +23 -10
@@ -962,16 +962,6 @@ static struct clksrc_clk clksrcs[] = { .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, }, { .clk = { - .name = "uclk1", - .ctrlbit = (1 << 3), - .enable = s5pc100_sclk0_ctrl, - - }, - .sources = &clk_src_group2, - .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, - .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, - }, { - .clk = { .name = "sclk_mixer", .ctrlbit = (1 << 6), .enable = s5pc100_sclk0_ctrl,
@@ -1098,6 +1088,17 @@ static struct clksrc_clk clksrcs[] = { }, }; +static struct clksrc_clk clk_sclk_uart = { + .clk = { + .name ="uclk1" , + .ctrlbit = (1 <<3 ), + .enable = s5pc100_sclk0_ctrl, + }, + .sources = &clk_src_group2, + .reg_src = { .reg =S5P_CLK_SRC1 , .shift =0 , .size =1 }, + .reg_div = { .reg =S5P_CLK_DIV2 , .shift =0 , .size =4 }, +}; +/* Clock initialisation code */ static struct clksrc_clk *sysclks[] = { &clk_mout_apll,
@@ -1127,6 +1128,10 @@ static struct clksrc_clk *sysclks[] = { &clk_sclk_spdif, }; +static struct clksrc_clk *clksrc_cdev[] = { + &clk_sclk_uart, +}; + void __init_or_cpufreq s5pc100_setup_clocks(void) {unsigned long xtal;
@@ -1266,6 +1271,11 @@ static struct clk *clks[] __initdata = { &clk_pcmcdclk1, }; +static struct clk_lookup s5pc100_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_sclk_uart.clk), +}; +void __init s5pc100_register_clocks (void ) {int ptr;
@@ -1277,9 +1287,12 @@ void __init s5pc100_register_clocks(void)s3c_register_clksrc (clksrcs,ARRAY_SIZE (clksrcs));s3c_register_clocks (init_clocks,ARRAY_SIZE (init_clocks)); +for (ptr =0 ; ptr <ARRAY_SIZE (clksrc_cdev); ptr++) +s3c_register_clksrc (clksrc_cdev[ptr],1 );s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off));s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); +clkdev_add_table (s5pc100_clk_lookup,ARRAY_SIZE (s5pc100_clk_lookup));s3c24xx_register_clock (&dummy_apb_pclk);
arch/arm/mach-s5pv210/clock.c +67 -40
136 lines not on this page · raw message
arch/arm/plat-s3c24xx/s3c2443-clock.c +16 -7
@@ -179,13 +179,6 @@ static struct clksrc_clk clk_usb_bus_host = {static struct clksrc_clk clksrc_clks[] = { { -/* ART baud-rate clock sourced from esysclk via a divisor */ - .clk = { - .name ="uartclk" , - .parent = &clk_esysclk.clk, - }, - .reg_div = { .reg =S3C2443_CLKDIV1 , .size =4 , .shift =8 }, - }, {/* camera interface bus-clock, divided down from esysclk */ .clk = { .name ="camif-upll" ,/* same as 2440 name */
@@ -205,6 +198,15 @@ static struct clksrc_clk clksrc_clks[] = { }, }; +static struct clksrc_clk clk_esys_uart = { +/* ART baud-rate clock sourced from esysclk via a divisor */ + .clk = { + .name ="uartclk" , + .parent = &clk_esysclk.clk, + }, + .reg_div = { .reg =S3C2443_CLKDIV1 , .size =4 , .shift =8 }, +}; +static struct clk clk_i2s_ext = { .name ="i2s-ext" , };
@@ -469,6 +471,12 @@ static struct clksrc_clk *clksrcs[] __initdata = { &clk_msysclk, }; +static struct clk_lookup s3c2443_clk_lookup[] = { +CLKDEV_INIT (NULL ,"clk_uart_baud1" , &s3c24xx_uclk), +CLKDEV_INIT (NULL ,"clk_uart_baud2" , &clk_p), +CLKDEV_INIT (NULL ,"clk_uart_baud3" , &clk_esys_uart.clk), +}; +void __init s3c2443_common_init_clocks (int xtal,pll_fn get_mpll,fdiv_fn get_fdiv) {
@@ -493,6 +501,7 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll,/* See s3c2443/etc notes on disabling clocks at init time */ s3c_register_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off));s3c_disable_clocks (init_clocks_off,ARRAY_SIZE (init_clocks_off)); +clkdev_add_table (s3c2443_clk_lookup,ARRAY_SIZE (s3c2443_clk_lookup));s3c2443_common_setup_clocks (get_mpll, get_fdiv); }
Signature · 1 line
1.6.6.rc2
PATCH v2 7/9 serial: samsung: merge all SoC specific port reset functions
In reply to Thomas AbrahamThe port reset function in each of the platform specific extension performs the same operations and hence all the reset port functions can be merged into one and moved into the common samsung uart driver. The SoC specific port reset functions are removed from SoC extensions.
--- drivers/tty/serial/s3c2410.c | 18 ------------------ drivers/tty/serial/s3c2412.c | 24 ------------------------ drivers/tty/serial/s3c2440.c | 24 ------------------------ drivers/tty/serial/s3c6400.c | 24 ------------------------ drivers/tty/serial/s5pv210.c | 22 +--------------------- drivers/tty/serial/samsung.c | 23 ++++++++++++++++++----- 6 files changed, 19 insertions(+), 116 deletions(-)
drivers/tty/serial/s3c2410.c +0 -18
@@ -25,23 +25,6 @@#include "samsung.h" -static int s3c2410_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) -{ -dbg ("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n" , - port, port->mapbase, cfg); - -wr_regl (port,S3C2410_UCON , cfg->ucon); -wr_regl (port,S3C2410_ULCON , cfg->ulcon); - -/* reset both fifos */ - -wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); -wr_regl (port,S3C2410_UFCON , cfg->ufcon); - -return 0 ; -} -static struct s3c24xx_uart_info s3c2410_uart_inf = { .name ="Samsung S3C2410 UART" , .type =PORT_S3C2410 ,
@@ -56,7 +39,6 @@ static struct s3c24xx_uart_info s3c2410_uart_inf = { .num_clks = 2, .clksel_mask = S3C2410_UCON_CLKMASK, .clksel_shift = S3C2410_UCON_CLKSHIFT, - .reset_port = s3c2410_serial_resetport, };static int s3c2410_serial_probe (struct platform_device *dev)
drivers/tty/serial/s3c2412.c +0 -24
@@ -25,29 +25,6 @@#include "samsung.h" -static int s3c2412_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - -dbg ("%s: port=%p (%08lx), cfg=%p\n" , - __func__, port, port->mapbase, cfg); - -/* ensure we don't change the clock settings... */ - - ucon &=S3C2412_UCON_CLKMASK ; - -wr_regl (port,S3C2410_UCON , ucon | cfg->ucon); -wr_regl (port,S3C2410_ULCON , cfg->ulcon); - -/* reset both fifos */ - -wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); -wr_regl (port,S3C2410_UFCON , cfg->ufcon); - -return 0 ; -} -static struct s3c24xx_uart_info s3c2412_uart_inf = { .name ="Samsung S3C2412 UART" , .type =PORT_S3C2412 ,
@@ -63,7 +40,6 @@ static struct s3c24xx_uart_info s3c2412_uart_inf = { .num_clks = 4, .clksel_mask = S3C2412_UCON_CLKMASK, .clksel_shift = S3C2412_UCON_CLKSHIFT, - .reset_port = s3c2412_serial_resetport, };/* device management */
drivers/tty/serial/s3c2440.c +0 -24
@@ -25,29 +25,6 @@#include "samsung.h" -static int s3c2440_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - -dbg ("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n" , - port, port->mapbase, cfg); - -/* ensure we don't change the clock settings... */ - - ucon &= (S3C2440_UCON0_DIVMASK | (3 <<10 )); - -wr_regl (port,S3C2410_UCON , ucon | cfg->ucon); -wr_regl (port,S3C2410_ULCON , cfg->ulcon); - -/* reset both fifos */ - -wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); -wr_regl (port,S3C2410_UFCON , cfg->ufcon); - -return 0 ; -} -static struct s3c24xx_uart_info s3c2440_uart_inf = { .name ="Samsung S3C2440 UART" , .type =PORT_S3C2440 ,
@@ -62,7 +39,6 @@ static struct s3c24xx_uart_info s3c2440_uart_inf = { .num_clks = 4, .clksel_mask = S3C2440_UCON_CLKMASK, .clksel_shift = S3C2440_UCON_CLKSHIFT, - .reset_port = s3c2440_serial_resetport, };/* device management */
drivers/tty/serial/s3c6400.c +0 -24
@@ -26,29 +26,6 @@#include "samsung.h" -static int s3c6400_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - -dbg ("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n" , - port, port->mapbase, cfg); - -/* ensure we don't change the clock settings... */ - - ucon &=S3C6400_UCON_CLKMASK ; - -wr_regl (port,S3C2410_UCON , ucon | cfg->ucon); -wr_regl (port,S3C2410_ULCON , cfg->ulcon); - -/* reset both fifos */ - -wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); -wr_regl (port,S3C2410_UFCON , cfg->ufcon); - -return 0 ; -} -static struct s3c24xx_uart_info s3c6400_uart_inf = { .name ="Samsung S3C6400 UART" , .type =PORT_S3C6400 ,
@@ -64,7 +41,6 @@ static struct s3c24xx_uart_info s3c6400_uart_inf = { .num_clks = 4, .clksel_mask = S3C6400_UCON_CLKMASK, .clksel_shift = S3C6400_UCON_CLKSHIFT, - .reset_port = s3c6400_serial_resetport, };/* device management */
drivers/tty/serial/s5pv210.c +1 -21
@@ -25,25 +25,6 @@#include <plat/regs-serial.h> #include "samsung.h" -static int s5pv210_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) -{ -unsigned long ucon =rd_regl (port,S3C2410_UCON ); - - ucon &=S5PV210_UCON_CLKMASK ; -wr_regl (port,S3C2410_UCON , ucon | cfg->ucon); -wr_regl (port,S3C2410_ULCON , cfg->ulcon); - -/* reset both fifos */ -wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); -wr_regl (port,S3C2410_UFCON , cfg->ufcon); - -/* It is need to delay When reset FIFO register */ -udelay (1 ); - -return 0 ; -} -#define S5PV210_UART_DEFAULT_INFO (fifo_size) \ .name = "Samsung S5PV210 UART0", \ .type = PORT_S3C6400, \
@@ -58,8 +39,7 @@ static int s5pv210_serial_resetport(struct uart_port *port, .def_clk_sel = S3C2410_UCON_CLKSEL0, \ .num_clks = 2, \ .clksel_mask = S5PV210_UCON_CLKMASK, \ - .clksel_shift = S5PV210_UCON_CLKSHIFT, \ - .reset_port = s5pv210_serial_resetport + .clksel_shift = S5PV210_UCON_CLKSHIFT static struct s3c24xx_uart_info s5p_port_fifo256 = {S5PV210_UART_DEFAULT_INFO (256 ),
drivers/tty/serial/samsung.c +18 -5
@@ -965,16 +965,29 @@ static struct s3c24xx_uart_port s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS/* s3c24xx_serial_resetport * -* wrapper to call the specific reset for this port (reset the fifos -* and the settings) +* reset the fifos and other the settings. */ -static inline int s3c24xx_serial_resetport (struct uart_port *port, -struct s3c2410_uartcfg *cfg) +static void s3c24xx_serial_resetport (struct uart_port *port, +struct s3c2410_uartcfg *cfg) {struct s3c24xx_uart_info *info =s3c24xx_port_to_info (port); +unsigned long ucon =rd_regl (port,S3C2410_UCON ); +unsigned int ucon_mask; -return (info->reset_port)(port, cfg); + ucon_mask = info->clksel_mask; +if (info->type ==PORT_S3C2440 ) + ucon_mask |=S3C2440_UCON0_DIVMASK ; + + ucon &= ucon_mask; +wr_regl (port,S3C2410_UCON , ucon | cfg->ucon); + +/* reset both fifos */ +wr_regl (port,S3C2410_UFCON , cfg->ufcon |S3C2410_UFCON_RESETBOTH ); +wr_regl (port,S3C2410_UFCON , cfg->ufcon); + +/* some delay is required after fifo reset */ +udelay (1 ); }
Signature · 1 line
1.6.6.rc2
PATCH v2 8/9 serial: samsung: merge probe() function from all SoC specific extensions
In reply to Thomas AbrahamWith reset port, set clock and get clock functions in SoC specific extentions being removed, only the driver probe is left over in these extensions. The probe function itself can be merged into one and moved into the samsung common serial driver. With driver probe also moved, all the SoC specific extentions are no longer required and they are deleted.
--- arch/arm/plat-samsung/include/plat/regs-serial.h | 12 + drivers/tty/serial/Kconfig | 45 +--- drivers/tty/serial/Makefile | 5 - drivers/tty/serial/s3c2410.c | 74 ----- drivers/tty/serial/s3c2412.c | 78 ----- drivers/tty/serial/s3c2440.c | 77 ----- drivers/tty/serial/s3c6400.c | 79 ----- drivers/tty/serial/s5pv210.c | 94 ------ drivers/tty/serial/samsung.c | 360 +++++++++++++++------- drivers/tty/serial/samsung.h | 18 +- 10 files changed, 265 insertions(+), 577 deletions(-) delete mode 100644 drivers/tty/serial/s3c2410.c delete mode 100644 drivers/tty/serial/s3c2412.c delete mode 100644 drivers/tty/serial/s3c2440.c delete mode 100644 drivers/tty/serial/s3c6400.c delete mode 100644 drivers/tty/serial/s5pv210.c
arch/arm/plat-samsung/include/plat/regs-serial.h +12 -0
@@ -232,6 +232,18 @@#define S3C2410_UCON_CLKSEL2 (1 << 2)#define S3C2410_UCON_CLKSEL3 (1 << 3) +/* Default values for s5pv210 UCON and UFCON uart registers */ +#define S5PV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ + S3C2410_UCON_RXILEVEL | \ + S3C2410_UCON_TXIRQMODE | \ + S3C2410_UCON_RXIRQMODE | \ + S3C2410_UCON_RXFIFO_TOI | \ + S3C2443_UCON_RXERR_IRQEN) + +#define S5PV210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ + S5PV210_UFCON_TXTRIG4 | \ + S5PV210_UFCON_RXTRIG4) +#ifndef __ASSEMBLY__/* configuration structure for per-machine configurations for the
drivers/tty/serial/Kconfig +2 -43
63 lines not on this page · raw message
drivers/tty/serial/Makefile +0 -5
@@ -38,11 +38,6 @@ obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o -obj-$(CONFIG_SERIAL_S3C2410) += s3c2410.o -obj-$(CONFIG_SERIAL_S3C2412) += s3c2412.o -obj-$(CONFIG_SERIAL_S3C2440) += s3c2440.o -obj-$(CONFIG_SERIAL_S3C6400) += s3c6400.o -obj-$(CONFIG_SERIAL_S5PV210) += s5pv210.o obj-$(CONFIG_SERIAL_MAX3100) += max3100.o obj-$(CONFIG_SERIAL_MAX3107) += max3107.o obj-$(CONFIG_SERIAL_MAX3107_AAVA) += max3107-aava.o
drivers/tty/serial/s3c2410.c deleted +0 -74
74 lines not on this page · raw message
drivers/tty/serial/s3c2412.c deleted +0 -78
78 lines not on this page · raw message
drivers/tty/serial/s3c2440.c deleted +0 -77
77 lines not on this page · raw message
drivers/tty/serial/s3c6400.c deleted +0 -79
79 lines not on this page · raw message
drivers/tty/serial/s5pv210.c deleted +0 -94
94 lines not on this page · raw message
drivers/tty/serial/samsung.c +244 -116
467 lines not on this page · raw message
drivers/tty/serial/samsung.h +7 -11
@@ -32,6 +32,12 @@ struct s3c24xx_uart_info {int (*reset_port)(struct uart_port *,struct s3c2410_uartcfg *); }; +struct s3c24xx_serial_drv_data { +struct s3c24xx_uart_info *info; +struct s3c2410_uartcfg *def_cfg; +unsigned int fifosize[CONFIG_SERIAL_SAMSUNG_UARTS ]; +}; +struct s3c24xx_uart_port {unsigned char rx_claimed;unsigned char tx_claimed;
@@ -45,6 +51,7 @@ struct s3c24xx_uart_port {struct clk *clk;struct clk *baudclk;struct uart_port port; +struct s3c24xx_serial_drv_data *drv_data;/* reference to platform data */ struct s3c2410_uartcfg *cfg;
@@ -69,17 +76,6 @@ struct s3c24xx_uart_port {#define wr_regb (port, reg, val) __raw_writeb(val, portaddr(port, reg))#define wr_regl (port, reg, val) __raw_writel(val, portaddr(port, reg)) -extern int s3c24xx_serial_probe (struct platform_device *dev, -struct s3c24xx_uart_info *uart); - -extern int __devexit s3c24xx_serial_remove(struct platform_device *dev); - -extern int s3c24xx_serial_initconsole (struct platform_driver *drv, -struct s3c24xx_uart_info **uart); - -extern int s3c24xx_serial_init (struct platform_driver *drv, -struct s3c24xx_uart_info *info); -#ifdef CONFIG_SERIAL_SAMSUNG_DEBUG extern void printascii (const char *);
Signature · 1 line
1.6.6.rc2
PATCH v2 9/9 serial: samsung: add device tree support
In reply to Thomas AbrahamAdd device tree based discovery support for Samsung's uart controller.
--- .../devicetree/bindings/serial/samsung_uart.txt | 14 ++++++++ drivers/tty/serial/samsung.c | 36 ++++++++++++++++++- 2 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.txt
Documentation/devicetree/bindings/serial/samsung_uart.txt new file +14 -0
@@ -0,0 +1,14 @@ +* Samsung's UART Controller + +The Samsung's UART controller is used for interfacing SoC with serial communicaion +devices. + +Required properties: +- compatible: should be + - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports. + +- reg: base physical address of the controller and length of memory mapped + region. + +- interrupts: interrupt number to the cpu. The interrupt specifier format depends + on the interrupt controller parent.
drivers/tty/serial/samsung.c +34 -2
@@ -42,6 +42,7 @@#include <linux/delay.h> #include <linux/clk.h> #include <linux/cpufreq.h> +#include <linux/of.h> #include <asm/irq.h>
@@ -1163,10 +1164,26 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); +/* Device driver serial port probe */ +static const struct of_device_id s3c24xx_uart_dt_match[];static int probe_index; +static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data ( +struct platform_device *pdev) +{ +#ifdef CONFIG_OF +if (pdev->dev.of_node) { +const struct of_device_id *match; + match =of_match_node (s3c24xx_uart_dt_match, pdev->dev.of_node); +return (struct s3c24xx_serial_drv_data *)match->data; + } +#endif +return (struct s3c24xx_serial_drv_data *) +platform_get_device_id (pdev)->driver_data; +} +static int s3c24xx_serial_probe (struct platform_device *pdev) {struct s3c24xx_uart_port *ourport;
@@ -1176,8 +1193,11 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) ourport = &s3c24xx_serial_ports[probe_index]; - ourport->drv_data = (struct s3c24xx_serial_drv_data *) -platform_get_device_id (pdev)->driver_data; + ourport->drv_data =s3c24xx_get_driver_data (pdev); +if (!ourport->drv_data) { +dev_err (&pdev->dev,"could not find driver data\n" ); +return -ENODEV ; + } ourport->info = ourport->drv_data->info; ourport->cfg = (pdev->dev.platform_data) ?
@@ -1626,6 +1646,17 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = { };MODULE_DEVICE_TABLE (platform, s3c24xx_serial_driver_ids); +#ifdef CONFIG_OF +static const struct of_device_id s3c24xx_uart_dt_match[] = { + { .compatible ="samsung,exynos4210-uart" , + .data = &exynos4210_serial_drv_data }, + {}, +}; +MODULE_DEVICE_TABLE (of, s3c24xx_uart_dt_match); +#else +#define s3c24xx_uart_dt_match NULL +#endif +static struct platform_driver samsung_serial_driver = { .probe = s3c24xx_serial_probe, .remove =__devexit_p (s3c24xx_serial_remove),
@@ -1634,6 +1665,7 @@ static struct platform_driver samsung_serial_driver = { .name = "samsung-uart", .owner = THIS_MODULE, .pm = SERIAL_SAMSUNG_PM_OPS, + .of_match_table = s3c24xx_uart_dt_match, }, };
Signature · 1 line
1.6.6.rc2
PATCH v2 9/9 serial: samsung: add device tree support
Quoted 5 lines · Thomas Abraham
Add device tree based discovery support for Samsung's uart controller.
Cc Ben Dooks <[email protected]>Cc Grant Likely <[email protected]>Signed-off-by Thomas Abraham <[email protected]>
Quoted 108 lines
--- .../devicetree/bindings/serial/samsung_uart.txt | 14 ++++++++ drivers/tty/serial/samsung.c | 36 ++++++++++++++++++- 2 files changed, 48 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.txtDocumentation/devicetree/bindings/serial/samsung_uart.txt new file +14
-0@@ -0,0 +1,14 @@ +* Samsung's UART Controller + +The Samsung's UART controller is used for interfacing SoC with serial communicaion +devices. + +Required properties: +- compatible: should be + - "samsung,exynos4210-uart", for UART's compatible with Exynos4210 uart ports. + +- reg: base physical address of the controller and length of memory mapped + region. + +- interrupts: interrupt number to the cpu. The interrupt specifier format depends + on the interrupt controller parent.drivers/tty/serial/samsung.c +34
-2@@ -42,6 +42,7 @@#include <linux/delay.h> #include <linux/clk.h> #include <linux/cpufreq.h> +#include <linux/of.h> #include <asm/irq.h> @@ -1163,10 +1164,26 @@ static ssize_t s3c24xx_serial_show_clksrc(struct device *dev, static DEVICE_ATTR(clock_source, S_IRUGO, s3c24xx_serial_show_clksrc, NULL); +/* Device driver serial port probe */ +static const struct of_device_id s3c24xx_uart_dt_match[];static int probe_index; +static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data ( +struct platform_device *pdev) +{ +#ifdef CONFIG_OF +if (pdev->dev.of_node) { +const struct of_device_id *match; + match =of_match_node (s3c24xx_uart_dt_match, pdev->dev.of_node); +return (struct s3c24xx_serial_drv_data *)match->data; + } +#endif +return (struct s3c24xx_serial_drv_data *) +platform_get_device_id (pdev)->driver_data; +} +static int s3c24xx_serial_probe (struct platform_device *pdev) {struct s3c24xx_uart_port *ourport;@@ -1176,8 +1193,11 @@ static int s3c24xx_serial_probe(struct platform_device *pdev) ourport = &s3c24xx_serial_ports[probe_index]; - ourport->drv_data = (struct s3c24xx_serial_drv_data *) -platform_get_device_id (pdev)->driver_data; + ourport->drv_data =s3c24xx_get_driver_data (pdev); +if (!ourport->drv_data) { +dev_err (&pdev->dev,"could not find driver data\n" ); +return -ENODEV ; + } ourport->info = ourport->drv_data->info; ourport->cfg = (pdev->dev.platform_data) ?@@ -1626,6 +1646,17 @@ static struct platform_device_id s3c24xx_serial_driver_ids[] = { };MODULE_DEVICE_TABLE (platform, s3c24xx_serial_driver_ids); +#ifdef CONFIG_OF +static const struct of_device_id s3c24xx_uart_dt_match[] = { + { .compatible ="samsung,exynos4210-uart" , + .data = &exynos4210_serial_drv_data }, + {}, +}; +MODULE_DEVICE_TABLE (of, s3c24xx_uart_dt_match); +#else +#define s3c24xx_uart_dt_match NULL +#endif +static struct platform_driver samsung_serial_driver = { .probe = s3c24xx_serial_probe, .remove =__devexit_p (s3c24xx_serial_remove),@@ -1634,6 +1665,7 @@ static struct platform_driver samsung_serial_driver = { .name = "samsung-uart", .owner = THIS_MODULE, .pm = SERIAL_SAMSUNG_PM_OPS, + .of_match_table = s3c24xx_uart_dt_match, }, };Signature · 1 line
1.6.6.rc2
v2 cover serial: samsung: rework clock lookup and add device tree support
In reply to Thomas AbrahamQuoted 137 lines · Thomas Abraham
Changes since v1:
- Included the missing dt bindings documentation in the last patch.
- Rebased and tested with linux 3.1-rc9 on linux-samsung-soc tree.
- Commit messages are modified to be elaborate.
- No changes in code.This patchset reworks the lookup of parent clocks for baud rate generator in the uart controller and adds support for device tree based discovery for the uart controller.
The Samsung uart driver was dependent on the clock names supplied in the platform data. This dependency had to be first removed to add device tree based discovery support for Samsung uart driver. In the process of reworking the clock lookup logic, several changes had to be made which in turn made parts of the driver redundant and such portions of the driver have been removed in this patchset. As a result, all the SoC specific extensions have been deleted.
Patch 1 modifies the driver to keep a copy of the location of the platform data in the driver's private data. This makes device tree support addition non-intrusive.
Patch 2 moves the complicated clock divider handling for fclk source clock for s3c2440 SoC into platform code. The fclk clock can be easily managed by representing it as a clock in the platform code. fclk clock handling was specific to s3c2440 and moving this out of the driver makes the rest of the clock handling in the driver almost identical for all SoC's supported by the driver.
Patch 3 modifies the driver to lookup source clocks for baud rate generator by using generic clock names. The generic clock name used by the driver is '
clk_uart_baud' appended with the parent number of the clock. For instance, the second parent clock source option for baud rate generator is named as 'clk_uart_baud2'.The driver stops depending on the
set_clockandget_clockcallbacks in the SoC specific extensions. Instead, the driver is modified to lookup parent clock rates and decide/calculate the best parent clock source for the baud rate generator (best clock would have the least delta when compared to buad rate requested).In this process, four new members are added in the driver's private data structure. The '
def_clk_sel' member is a platform set bit-value that specifies the possible parents that the driver is allowed to use for baud rate clock. A bit set at a particular bit position selects that parent clock source.
Example: If bit number 2 is set in 'def_clk_sel', then parent clock source '2' can be a possible parent clock for baud rate generator. The 'num_clks' is the number of possible parent clocks that the SoC supports. The 'clksel_mask' and 'clksel_shift' members are used to operate on the parent clock selection bit field int the uart controller's contol register.Patch 4 removes all uses and instances of 'struct
s3c24xx_uart_clksrc'. This structure was used to pass source clock 'names' between platform code, driver and SoC specific extensions. By moving away from using platform specified clock names in the driver, all uses and instances of 'structs3c24xx_uart_clksrc' is removed.Patch 5 removes all the SoC specific
get_clksrcandset_clksrccallbacks. These callbacks were using SoC specific clock names to communicate the clock to be set or retrieved. These callbacks are removed as they are no longer required.Patch 6 reworks the uart clocks in platform code of all Samsung SoC's. The driver would use generic clock names and this patch creates aliases to uart clocks with generic clock names as the alias name.
Patch 7 merges all the SoC specific port reset functions into one common port reset function and moves the common function into the common Samsung uart driver. All the SoC specific port reset functions perform the same operation allowing all of them to be converged.
Patch 8 collapses all the SoC specific probe functions and associated driver private data into the Samsung common uart driver. With
get_clksrc,set_clksrcandreset_portfunctions removed from SoC specific extensions, all the remains in those extensions is the probe function along with SoC specific driver data. These are merged into the common Samsung uart driver and all the SoC specific extensions are deleted.Patch 9 adds device tree based discovery support for the uart driver.
This patchset is based on the following tree
https://github.com/kgene/linux-samsung.git branch: for-nextwith the following two patches applied
[PATCH] serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's [PATCH] ARM: SAMSUNG: Remove uart irq handling from plaform codeand tested on the following boards.
SMDK2440, SMDK2416, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210, SMDKV310.This patchset has dependency on the following patchset:
[PATCH V2 0/2] Add a common macro for creating structclk_lookupentriesThomas Abraham (9):
serial: samsung: Keep a copy of the location of platform data in driver's private data
serial: samsung: move handling of fclk/n clock to platform code
serial: samsung: switch to clkdev based clock lookup
serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
serial: samsung: remove all uses ofget_clksrcandset_clksrc
arm: samsung: register uart clocks to clock lookup list
serial: samsung: merge all SoC specific port reset functions
serial: samsung: mergeprobe()function from all SoC specific extensions
serial: samsung: add device tree support.../devicetree/bindings/serial/samsung_uart.txt | 14 + arch/arm/mach-exynos4/clock.c | 106 ++-- arch/arm/mach-exynos4/init.c | 21 +- arch/arm/mach-s3c2410/mach-bast.c | 22 - arch/arm/mach-s3c2410/mach-vr1000.c | 24 - arch/arm/mach-s3c2410/s3c2410.c | 6 + arch/arm/mach-s3c2412/clock.c | 7 + arch/arm/mach-s3c2440/clock.c | 44 ++ arch/arm/mach-s3c2440/mach-anubis.c | 22 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +- arch/arm/mach-s3c2440/mach-osiris.c | 24 +- arch/arm/mach-s3c2440/mach-rx1950.c | 18 +- arch/arm/mach-s3c2440/mach-rx3715.c | 19 +- arch/arm/mach-s3c64xx/clock.c | 37 +- arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 +- arch/arm/mach-s5p64x0/clock-s5p6450.c | 32 +- arch/arm/mach-s5p64x0/init.c | 31 - arch/arm/mach-s5pc100/clock.c | 33 +- arch/arm/mach-s5pv210/clock.c | 107 ++-- arch/arm/mach-s5pv210/init.c | 19 - arch/arm/plat-s3c24xx/s3c2443-clock.c | 23 +- arch/arm/plat-samsung/include/plat/regs-serial.h | 45 +- drivers/tty/serial/Kconfig | 45 +-- drivers/tty/serial/Makefile | 5 - drivers/tty/serial/s3c2410.c | 115 ---- drivers/tty/serial/s3c2412.c | 149 ----- drivers/tty/serial/s3c2440.c | 178 ------ drivers/tty/serial/s3c6400.c | 149 ----- drivers/tty/serial/s5pv210.c | 158 ----- drivers/tty/serial/samsung.c | 639 ++++++++++++-------- drivers/tty/serial/samsung.h | 32 +- 31 files changed, 752 insertions(+), 1426 deletions(-)
Quoted 6 lines
create mode 100644
Documentation/devicetree/bindings/serial/samsung_uart.txtdelete mode 100644drivers/tty/serial/s3c2410.c
delete mode 100644drivers/tty/serial/s3c2412.c
delete mode 100644drivers/tty/serial/s3c2440.c
delete mode 100644drivers/tty/serial/s3c6400.c
delete mode 100644drivers/tty/serial/s5pv210.c
(Cc'ed Greg KH)
Looks good for me, and I need to get the ack from Greg before applying.
Greg, if you're ok, I'd like to send this series to upstream via Samsung tree for supporting device tree because this touches a lot of arch/arm/ Samsung stuff. If any problems, please let me know.
Thanks.
Best regards,
Kgene.
--
Kukjin Kim <[email protected]>, Senior Engineer, SW Solution Development Team, Samsung Electronics Co., Ltd.
v2 cover serial: samsung: rework clock lookup and add device tree support
Quoted 145 lines · Kukjin Kim
Quoted 135 lines · Thomas Abraham
Changes since v1:
- Included the missing dt bindings documentation in the last patch.
- Rebased and tested with linux 3.1-rc9 on linux-samsung-soc tree.
- Commit messages are modified to be elaborate.
- No changes in code.This patchset reworks the lookup of parent clocks for baud rate generator in the uart controller and adds support for device tree based discovery for the uart controller.
The Samsung uart driver was dependent on the clock names supplied in the platform data. This dependency had to be first removed to add device tree based discovery support for Samsung uart driver. In the process of reworking the clock lookup logic, several changes had to be made which in turn made parts of the driver redundant and such portions of the driver have been removed in this patchset. As a result, all the SoC specific extensions have been deleted.
Patch 1 modifies the driver to keep a copy of the location of the platform data in the driver's private data. This makes device tree support addition non-intrusive.
Patch 2 moves the complicated clock divider handling for fclk source clock for s3c2440 SoC into platform code. The fclk clock can be easily managed by representing it as a clock in the platform code. fclk clock handling was specific to s3c2440 and moving this out of the driver makes the rest of the clock handling in the driver almost identical for all SoC's supported by the driver.
Patch 3 modifies the driver to lookup source clocks for baud rate generator by using generic clock names. The generic clock name used by the driver is '
clk_uart_baud' appended with the parent number of the clock. For instance, the second parent clock source option for baud rate generator is named as 'clk_uart_baud2'.The driver stops depending on the
set_clockandget_clockcallbacks in the SoC specific extensions. Instead, the driver is modified to lookup parent clock rates and decide/calculate the best parent clock source for the baud rate generator (best clock would have the least delta when compared to buad rate requested).In this process, four new members are added in the driver's private data structure. The '
def_clk_sel' member is a platform set bit-value that specifies the possible parents that the driver is allowed to use for baud rate clock. A bit set at a particular bit position selects that parent clock source.
Example: If bit number 2 is set in 'def_clk_sel', then parent clock source '2' can be a possible parent clock for baud rate generator. The 'num_clks' is the number of possible parent clocks that the SoC supports. The 'clksel_mask' and 'clksel_shift' members are used to operate on the parent clock selection bit field int the uart controller's contol register.Patch 4 removes all uses and instances of 'struct
s3c24xx_uart_clksrc'. This structure was used to pass source clock 'names' between platform code, driver and SoC specific extensions. By moving away from using platform specified clock names in the driver, all uses and instances of 'structs3c24xx_uart_clksrc' is removed.Patch 5 removes all the SoC specific
get_clksrcandset_clksrccallbacks. These callbacks were using SoC specific clock names to communicate the clock to be set or retrieved. These callbacks are removed as they are no longer required.Patch 6 reworks the uart clocks in platform code of all Samsung SoC's. The driver would use generic clock names and this patch creates aliases to uart clocks with generic clock names as the alias name.
Patch 7 merges all the SoC specific port reset functions into one common port reset function and moves the common function into the common Samsung uart driver. All the SoC specific port reset functions perform the same operation allowing all of them to be converged.
Patch 8 collapses all the SoC specific probe functions and associated driver private data into the Samsung common uart driver. With
get_clksrc,set_clksrcandreset_portfunctions removed from SoC specific extensions, all the remains in those extensions is the probe function along with SoC specific driver data. These are merged into the common Samsung uart driver and all the SoC specific extensions are deleted.Patch 9 adds device tree based discovery support for the uart driver.
This patchset is based on the following tree
https://github.com/kgene/linux-samsung.git branch: for-nextwith the following two patches applied
[PATCH] serial: samsung: Add unified interrupt handler for s3c64xx and later SoC's [PATCH] ARM: SAMSUNG: Remove uart irq handling from plaform codeand tested on the following boards.
SMDK2440, SMDK2416, SMDK6410, SMDK6440, SMDK6450, SMDKC100, SMDKV210, SMDKV310.This patchset has dependency on the following patchset:
[PATCH V2 0/2] Add a common macro for creating structclk_lookupentriesThomas Abraham (9):
serial: samsung: Keep a copy of the location of platform data in driver's private data
serial: samsung: move handling of fclk/n clock to platform code
serial: samsung: switch to clkdev based clock lookup
serial: samsung: remove struct 's3c24xx_uart_clksrc' and all uses of it
serial: samsung: remove all uses ofget_clksrcandset_clksrc
arm: samsung: register uart clocks to clock lookup list
serial: samsung: merge all SoC specific port reset functions
serial: samsung: mergeprobe()function from all SoC specific extensions
serial: samsung: add device tree support.../devicetree/bindings/serial/samsung_uart.txt | 14 + arch/arm/mach-exynos4/clock.c | 106 ++-- arch/arm/mach-exynos4/init.c | 21 +- arch/arm/mach-s3c2410/mach-bast.c | 22 - arch/arm/mach-s3c2410/mach-vr1000.c | 24 - arch/arm/mach-s3c2410/s3c2410.c | 6 + arch/arm/mach-s3c2412/clock.c | 7 + arch/arm/mach-s3c2440/clock.c | 44 ++ arch/arm/mach-s3c2440/mach-anubis.c | 22 +- arch/arm/mach-s3c2440/mach-at2440evb.c | 22 +- arch/arm/mach-s3c2440/mach-osiris.c | 24 +- arch/arm/mach-s3c2440/mach-rx1950.c | 18 +- arch/arm/mach-s3c2440/mach-rx3715.c | 19 +- arch/arm/mach-s3c64xx/clock.c | 37 +- arch/arm/mach-s5p64x0/clock-s5p6440.c | 32 +- arch/arm/mach-s5p64x0/clock-s5p6450.c | 32 +- arch/arm/mach-s5p64x0/init.c | 31 - arch/arm/mach-s5pc100/clock.c | 33 +- arch/arm/mach-s5pv210/clock.c | 107 ++-- arch/arm/mach-s5pv210/init.c | 19 - arch/arm/plat-s3c24xx/s3c2443-clock.c | 23 +- arch/arm/plat-samsung/include/plat/regs-serial.h | 45 +- drivers/tty/serial/Kconfig | 45 +-- drivers/tty/serial/Makefile | 5 - drivers/tty/serial/s3c2410.c | 115 ---- drivers/tty/serial/s3c2412.c | 149 ----- drivers/tty/serial/s3c2440.c | 178 ------ drivers/tty/serial/s3c6400.c | 149 ----- drivers/tty/serial/s5pv210.c | 158 ----- drivers/tty/serial/samsung.c | 639 ++++++++++++--------Quoted 8 lines
drivers/tty/serial/samsung.h | 32 +- 31 files changed, 752 insertions(+), 1426 deletions(-) create mode 100644 Documentation/devicetree/bindings/serial/samsung_uart.txt delete mode 100644 drivers/tty/serial/s3c2410.c delete mode 100644 drivers/tty/serial/s3c2412.c delete mode 100644 drivers/tty/serial/s3c2440.c delete mode 100644 drivers/tty/serial/s3c6400.c delete mode 100644 drivers/tty/serial/s5pv210.c
Quoted 7 lines
(Cc'ed Greg KH)
Looks good for me, and I need to get the ack from Greg before applying.
Greg, if you're ok, I'd like to send this series to upstream via Samsung tree for supporting device tree because this touches a lot of
arch/arm/Samsung stuff. If any problems, please let me know.
No objection from me, feel free to take this through your tree.
greg k-h