mx31: Introduce mx31_set_gpr function

PATCH New Fabio Estevam 2 participants 6 messages Oct 21, 2011 – Oct 25, 2011

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Arm (32-bit) Arm i.MX and Layerscape

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Fabio Estevam

author reviewer

2011-10-21 02:01 UTC #0 lore raw

PATCH 1/3 mx31: Introduce mx31_set_gpr function

Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31.

This function can be useful for setting a group of pins into tied to some specific peripherals.

Reuse this function from the linux kernel.

Signed-off-by Fabio Estevam <[email protected]>

---
 arch/arm/cpu/arm1136/mx31/generic.c       |   15 +++++++++++
 arch/arm/include/asm/arch-mx31/clock.h    |    1 +
 arch/arm/include/asm/arch-mx31/imx-regs.h |   38 +++++++++++++++++++++++++++++
 3 files changed, 54 insertions(+), 0 deletions(-)

arch/arm/cpu/arm1136/mx31/generic.c +15 -0

index 78df7b9..4f27e25 100644
@@ -27,6 +27,8 @@
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 
+#define IOMUXGPR	(IOMUXC_BASE + 0x008)
+
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = GET_PLL_MFI(reg);

@@ -141,6 +143,19 @@ void mx31_set_pad(enum iomux_pins pin, u32 config)
 
 }
 
+void mx31_set_gpr(enum iomux_gp_func gp, char en)
+{
+	u32 l;
+
+	l = readl(IOMUXGPR);
+	if (en)
+		l |= gp;
+	else
+		l &= ~gp;
+
+	writel(l, IOMUXGPR);
+}
+
 void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
 {
 	struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;

arch/arm/include/asm/arch-mx31/clock.h +1 -0

index 2e3bce2..3e22d9a 100644
@@ -37,6 +37,7 @@ unsigned int mxc_get_clock(enum mxc_clock clk);
 extern u32 imx_get_uartclk(void);
 extern void mx31_gpio_mux(unsigned long mode);
 extern void mx31_set_pad(enum iomux_pins pin, u32 config);
+extern void mx31_set_gpr(enum iomux_gp_func gp, char en);
 
 void mx31_uart1_hw_init(void);
 void mx31_spi2_hw_init(void);

arch/arm/include/asm/arch-mx31/imx-regs.h +38 -0

index 552c821..6ce008d 100644
@@ -468,6 +468,44 @@ enum iomux_pins {
 	MX31_PIN_CAPTURE	= IOMUX_PIN(7,    327),
 };
 
+/*
+ * various IOMUX general purpose functions
+ */
+enum iomux_gp_func {
+	MUX_PGP_FIRI			= 1 << 0,
+	MUX_DDR_MODE			= 1 << 1,
+	MUX_PGP_CSPI_BB			= 1 << 2,
+	MUX_PGP_ATA_1			= 1 << 3,
+	MUX_PGP_ATA_2			= 1 << 4,
+	MUX_PGP_ATA_3			= 1 << 5,
+	MUX_PGP_ATA_4			= 1 << 6,
+	MUX_PGP_ATA_5			= 1 << 7,
+	MUX_PGP_ATA_6			= 1 << 8,
+	MUX_PGP_ATA_7			= 1 << 9,
+	MUX_PGP_ATA_8			= 1 << 10,
+	MUX_PGP_UH2			= 1 << 11,
+	MUX_SDCTL_CSD0_SEL		= 1 << 12,
+	MUX_SDCTL_CSD1_SEL		= 1 << 13,
+	MUX_CSPI1_UART3			= 1 << 14,
+	MUX_EXTDMAREQ2_MBX_SEL		= 1 << 15,
+	MUX_TAMPER_DETECT_EN		= 1 << 16,
+	MUX_PGP_USB_4WIRE		= 1 << 17,
+	MUX_PGP_USB_COMMON		= 1 << 18,
+	MUX_SDHC_MEMSTICK1		= 1 << 19,
+	MUX_SDHC_MEMSTICK2		= 1 << 20,
+	MUX_PGP_SPLL_BYP		= 1 << 21,
+	MUX_PGP_UPLL_BYP		= 1 << 22,
+	MUX_PGP_MSHC1_CLK_SEL		= 1 << 23,
+	MUX_PGP_MSHC2_CLK_SEL		= 1 << 24,
+	MUX_CSPI3_UART5_SEL		= 1 << 25,
+	MUX_PGP_ATA_9			= 1 << 26,
+	MUX_PGP_USB_SUSPEND		= 1 << 27,
+	MUX_PGP_USB_OTG_LOOPBACK	= 1 << 28,
+	MUX_PGP_USB_HS1_LOOPBACK	= 1 << 29,
+	MUX_PGP_USB_HS2_LOOPBACK	= 1 << 30,
+	MUX_CLKO_DDR_MODE		= 1 << 31,
+};
+
 /* Bit definitions for RCSR register in CCM */
 #define CCM_RCSR_NF16B	(1 << 31)
 #define CCM_RCSR_NFMS	(1 << 30)

Signature · 1 line

1.7.1

Fabio Estevam

author reviewer

2011-10-21 02:01 UTC #1 lore raw

PATCH 2/3 qong: Use mx31_set_gpr to setup USBH2 pins

Instead of writing directly to the GPR register, use mx31_set_gpr to setup USBH2 pins.

Signed-off-by Fabio Estevam <[email protected]>

---
 board/davedenx/qong/qong.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

board/davedenx/qong/qong.c +2 -2

index 5b2830c..de32fb5 100644
@@ -142,8 +142,8 @@ int board_early_init_f(void)
 	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
 	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
 	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
-
-	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
+	mx31_set_gpr(MUX_PGP_UH2, 1);
 
 	return 0;

Signature · 1 line

1.7.1

Stefano Babic

2011-10-25 08:08 UTC #2 lore raw

PATCH 2/3 qong: Use mx31_set_gpr to setup USBH2 pins

Quoted 12 lines · Fabio Estevam

Instead of writing directly to the GPR register, use mx31_set_gpr to setup USBH2 pins.
Signed-off-by Fabio Estevam <[email protected]>
---
 board/davedenx/qong/qong.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)
board/davedenx/qong/qong.c +0 -0
index 5b2830c..de32fb5 100644

board/davedenx/qong/qong.c int board_early_init_f(void) · line 149

Quoted 10 lines

board/davedenx/qong/qong.c +2 -2

@@ -142,8 +142,8 @@ int board_early_init_f(void)
 	mx31_set_pad(MX31_PIN_SCK3, H2_PAD_CFG);	/* USBH2_DATA5 */
 	mx31_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG);	/* USBH2_DATA6 */
 	mx31_set_pad(MX31_PIN_STXD3, H2_PAD_CFG);	/* USBH2_DATA7 */
-
-	writel(readl((IOMUXC_BASE + 0x8)) | (1 << 11), IOMUXC_BASE + 0x8);
+
+	mx31_set_gpr(MUX_PGP_UH2, 1);
 
 	return 0;

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Fabio Estevam

author reviewer

2011-10-21 02:01 UTC #3 lore raw

PATCH 3/3 qong: remove unneeded IOMUX settings

In reply to Fabio Estevam

On qong board some of the USBH2 pins are set via GPR register, so don need to setup the IOMUX for each pin individually.

Other than that, these pins should not be configured as primary function because the primary function selects SSI functionality.

Let GPR register do the work and remove the unneeded IOMUX setup.

Signed-off-by Fabio Estevam <[email protected]>

---

Stefano,

I don't have access to the qong board to test this, but I believe this is the right thing to do here.

 board/davedenx/qong/qong.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

board/davedenx/qong/qong.c +0 -6

index de32fb5..70af593 100644
@@ -120,12 +120,6 @@ int board_early_init_f(void)
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 
 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

Signature · 1 line

1.7.1

Stefano Babic

2011-10-24 07:56 UTC #4 lore raw

PATCH 3/3 qong: remove unneeded IOMUX settings

Quoted 11 lines · Fabio Estevam

On qong board some of the USBH2 pins are set via GPR register, so don need to setup the IOMUX for each pin individually.
Other than that, these pins should not be configured as primary function because the primary function selects SSI functionality.
Let GPR register do the work and remove the unneeded IOMUX setup.
Signed-off-by Fabio Estevam <[email protected]>
---

Hi Fabio,

Quoted 3 lines

Stefano,
I don't have access to the qong board to test this, but I believe this is the right thing to do here.

I have not written this code and I do not know the history, but reading the manual I agree with you. The setup of the iomux is ininfluent, because the pins are already set in "Hardware mode 2" in the GPR register (GPR[11]).

Quoted 11 lines

 board/davedenx/qong/qong.c |    6 ------
 1 files changed, 0 insertions(+), 6 deletions(-)

board/davedenx/qong/qong.c +0 -0

index de32fb5..70af593 100644
@@ -120,12 +120,6 @@ int board_early_init_f(void)
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_STP, MUX_CTL_FUNC));
 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA0, MUX_CTL_FUNC));

board/davedenx/qong/qong.c int board_early_init_f(void) · line 125

Quoted 10 lines

board/davedenx/qong/qong.c +0 -6

 	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_USBH2_DATA1, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SCK3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SFS3, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_STXD6, MUX_CTL_FUNC));
-	mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SRXD6, MUX_CTL_FUNC));
 
 #define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
 			PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)

Acked-by Stefano Babic <[email protected]>

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

Stefano Babic

2011-10-25 08:07 UTC #5 lore raw

PATCH 1/3 mx31: Introduce mx31_set_gpr function

In reply to Fabio Estevam

arch/arm/cpu/arm1136/mx31/generic.c

Quoted 15 lines · Fabio Estevam

Introduce mx31_set_gpr function for setting the GPR (General Purpose Register) on MX31.
This function can be useful for setting a group of pins into tied to some specific peripherals.
Reuse this function from the linux kernel.
Signed-off-by Fabio Estevam <[email protected]>
---
 arch/arm/cpu/arm1136/mx31/generic.c       |   15 +++++++++++
 arch/arm/include/asm/arch-mx31/clock.h    |    1 +
 arch/arm/include/asm/arch-mx31/imx-regs.h |   38 +++++++++++++++++++++++++++++
 3 files changed, 54 insertions(+), 0 deletions(-)
arch/arm/cpu/arm1136/mx31/generic.c +0 -0
index 78df7b9..4f27e25 100644

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================