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mx31pdk: Enable D and I caches

PATCH New Fabio Estevam 4 participants 5 messages Nov 1, 2011 – Nov 4, 2011

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#0 lore raw

PATCH 1/1 mx31pdk: Enable D and I caches

Enable D and I caches on mx31pdk.

---
Stefano,

You explained that enabling cache may cause some drivers like FEC and MMC not to work properly. As mx31pdk does not have FEC or MMC driver I thought this should be OK.

Tested by booting Linux kernel via TFTP and mounting a NFS rootfs.

 board/freescale/mx31pdk/mx31pdk.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
board/freescale/mx31pdk/mx31pdk.c +8 -0
index 9f8bc53..1d7b4f6 100644
@@ -71,11 +71,19 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	enable_caches();
+
 	return 0;
 }
 
Signature · 1 line
1.6.0.4
#1 lore raw

PATCH 1/1 mx31pdk: Enable D and I caches

Quoted 8 lines · Fabio Estevam

Enable D and I caches on mx31pdk.

---
Stefano,

You explained that enabling cache may cause some drivers like FEC and MMC not to work properly. As mx31pdk does not have FEC or MMC driver I thought this should be OK.

Ok, understood.

Quoted 2 lines

Tested by booting Linux kernel via TFTP and mounting a NFS rootfs.

Good. To be sure, do you have also tested NAND in u-boot ? I do not expect problems, but...

Quoted 18 lines
 board/freescale/mx31pdk/mx31pdk.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
board/freescale/mx31pdk/mx31pdk.c +6 -0
index 9f8bc53..1d7b4f6 100644
@@ -71,11 +71,19 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+

board/freescale/mx31pdk/mx31pdk.c int board_early_init_f(void) · line 89

Quoted 10 lines
board/freescale/mx31pdk/mx31pdk.c +2 -0
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	enable_caches();
+
 	return 0;
 }
 

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================
#2 lore raw

PATCH 1/1 mx31pdk: Enable D and I caches

Hi Stefano,

Quoted 2 lines · Stefano Babic

Good. To be sure, do you have also tested NAND in u-boot ? I do not expect problems, but...

Yes, I confirmed that NAND works with the caches enabled by doing the following tests:

1. Save environment variables in NAND
2. Reprogram U-boot in NAND using "run prg_uboot" script.

I would like to investigate the FEC issue when caches are enabled when I have a chance.

Would you have any pointers as to where to start investigating why the FEC driver is buggy when caches are enabled?

Thanks,

Fabio Estevam

#3 lore raw

PATCH 1/1 mx31pdk: Enable D and I caches

Fabio,

2011/11/3 Fabio Estevam <[email protected]>:

Quoted 10 lines

Hi Stefano,

Quoted 2 lines · Stefano Babic

Good. To be sure, do you have also tested NAND in u-boot ? I do not expect problems, but...

Yes, I confirmed that NAND works with the caches enabled by doing the following tests:

Quoted 8 lines

1. Save environment variables in NAND
2. Reprogram U-boot in NAND using "run prg_uboot" script.

I would like to investigate the FEC issue when caches are enabled when I have a chance.

Would you have any pointers as to where to start investigating why the FEC driver is buggy when caches are enabled?

you can search the tread: [U-Boot] i.MX51: FEC: Cache coherency problem?

Jason Liu

Quoted 9 lines

Thanks,

Fabio Estevam
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot

#4 lore raw

PATCH 1/1 mx31pdk: Enable D and I caches

In reply to Fabio Estevam
Quoted 28 lines · Fabio Estevam

Enable D and I caches on mx31pdk.

---
Stefano,

You explained that enabling cache may cause some drivers like FEC and MMC not to work properly. As mx31pdk does not have FEC or MMC driver I thought this should be OK.

Tested by booting Linux kernel via TFTP and mounting a NFS rootfs.

 board/freescale/mx31pdk/mx31pdk.c |    8 ++++++++
 1 files changed, 8 insertions(+), 0 deletions(-)
board/freescale/mx31pdk/mx31pdk.c +6 -0
index 9f8bc53..1d7b4f6 100644
@@ -71,11 +71,19 @@ int board_early_init_f(void)
 	return 0;
 }
 
+void enable_caches(void)
+{
+	icache_enable();
+	dcache_enable();
+}
+

board/freescale/mx31pdk/mx31pdk.c int board_early_init_f(void) · line 89

Quoted 10 lines
board/freescale/mx31pdk/mx31pdk.c +2 -0
 int board_init(void)
 {
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 
+	enable_caches();
+
 	return 0;
 }
 

Applied to u-boot-imx, thanks.

Best regards,
Stefano Babic

Signature · 5 lines
=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================