Support for HTKW mcx board
Subsystems (7)
cover Support for HTKW mcx board
Hello All,
these patches introduce support for HTKW mcx board (AM3517-based).
Previously posted DaVinci EMAC patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 ) and NAND SPL patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112890 ) are also included as long as EHCI host support (moved from Beagle board code).
Signed-off-by Ilya Yanok <[email protected]>
PATCH 1/14 davinci_emac: compilation fix, phy is array now
Fix compilation issues introduced by recent multiply PHY patch.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/net/davinci_emac.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
drivers/net/davinci_emac.c +1 -1
@@ -809,7 +809,7 @@ int davinci_emac_initialize(void) phy[i].auto_negotiate = gen_auto_negotiate; } -debug ("Ethernet PHY: %s\n" , phy.name); +debug ("Ethernet PHY: %s\n" , phy[i].name);miiphy_register (phy[i].name, davinci_mii_phy_read, davinci_mii_phy_write);
Signature · 1 line
1.7.6.4
PATCH 2/14 davinci_emac: move arch-independent defines to separate header
In reply to Ilya YanokDaVinci EMAC is found not only on DaVinci SoCs but on some OMAP3 SoCs also. This patch moves common defines from arch-davinci/emac_defs.h to drivers/net/davinci_emac.h
Signed-off-by Ilya Yanok <[email protected]>
--- arch/arm/include/asm/arch-davinci/emac_defs.h | 289 ----------------------- drivers/net/davinci_emac.c | 1 + drivers/net/davinci_emac.h | 314 +++++++++++++++++++++++++ 3 files changed, 315 insertions(+), 289 deletions(-) create mode 100644 drivers/net/davinci_emac.h
arch/arm/include/asm/arch-davinci/emac_defs.h +0 -289
@@ -84,295 +84,6 @@#define EMAC_MDIO_CLOCK_FREQ 2000000/* 2.0 MHz */ #endif -/* Ethernet Min/Max packet size */ -#define EMAC_MIN_ETHERNET_PKT_SIZE 60 -#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -#define EMAC_PKT_ALIGN 18/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ - -/* Number of RX packet buffers -* NOTE: Only 1 buffer supported as of now -*/ -#define EMAC_MAX_RX_BUFFERS 10 - - -/*********************************************** -******** Internally used macros *************** -***********************************************/ - -#define EMAC_CH_TX 1 -#define EMAC_CH_RX 0 - -/* Each descriptor occupies 4 words, lets start RX desc's at 0 and -* reserve space for 64 descriptors max -*/ -#define EMAC_RX_DESC_BASE 0x0 -#define EMAC_TX_DESC_BASE 0x1000 - -/* EMAC Teardown value */ -#define EMAC_TEARDOWN_VALUE 0xfffffffc - -/* MII Status Register */ -#define MII_STATUS_REG 1 - -/* Number of statistics registers */ -#define EMAC_NUM_STATS 36 - - -/* EMAC Descriptor */ -typedef volatile struct _emac_desc -{ -u_int32_t next;/* Pointer to next descriptor in chain */ -u_int8_t *buffer;/* Pointer to data buffer */ -u_int32_t buff_off_len;/* Buffer Offset(MSW) and Length(LSW) */ -u_int32_t pkt_flag_len;/* Packet Flags(MSW) and Length(LSW) */ -}emac_desc ; - -/* CPPI bit positions */ -#define EMAC_CPPI_SOP_BIT (0x80000000) -#define EMAC_CPPI_EOP_BIT (0x40000000) -#define EMAC_CPPI_OWNERSHIP_BIT (0x20000000) -#define EMAC_CPPI_EOQ_BIT (0x10000000) -#define EMAC_CPPI_TEARDOWN_COMPLETE_BIT (0x08000000) -#define EMAC_CPPI_PASS_CRC_BIT (0x04000000) - -#define EMAC_CPPI_RX_ERROR_FRAME (0x03fc0000) - -#define EMAC_MACCONTROL_MIIEN_ENABLE (0x20) -#define EMAC_MACCONTROL_FULLDUPLEX_ENABLE (0x1) -#define EMAC_MACCONTROL_GIGABIT_ENABLE (1 << 7) -#define EMAC_MACCONTROL_GIGFORCE (1 << 17) -#define EMAC_MACCONTROL_RMIISPEED_100 (1 << 15) - -#define EMAC_MAC_ADDR_MATCH (1 << 19) -#define EMAC_MAC_ADDR_IS_VALID (1 << 20) - -#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000) -#define EMAC_RXMBPENABLE_RXBROADEN (0x2000) - - -#define MDIO_CONTROL_IDLE (0x80000000) -#define MDIO_CONTROL_ENABLE (0x40000000) -#define MDIO_CONTROL_FAULT_ENABLE (0x40000) -#define MDIO_CONTROL_FAULT (0x80000) -#define MDIO_USERACCESS0_GO (0x80000000) -#define MDIO_USERACCESS0_WRITE_READ (0x0) -#define MDIO_USERACCESS0_WRITE_WRITE (0x40000000) -#define MDIO_USERACCESS0_ACK (0x20000000) - -/* Ethernet MAC Registers Structure */ -typedef struct { -dv_reg TXIDVER; -dv_reg TXCONTROL; -dv_reg TXTEARDOWN; -u_int8_t RSVD0[4 ]; -dv_reg RXIDVER; -dv_reg RXCONTROL; -dv_reg RXTEARDOWN; -u_int8_t RSVD1[100 ]; -dv_reg TXINTSTATRAW; -dv_reg TXINTSTATMASKED; -dv_reg TXINTMASKSET; -dv_reg TXINTMASKCLEAR; -dv_reg MACINVECTOR; -u_int8_t RSVD2[12 ]; -dv_reg RXINTSTATRAW; -dv_reg RXINTSTATMASKED; -dv_reg RXINTMASKSET; -dv_reg RXINTMASKCLEAR; -dv_reg MACINTSTATRAW; -dv_reg MACINTSTATMASKED; -dv_reg MACINTMASKSET; -dv_reg MACINTMASKCLEAR; -u_int8_t RSVD3[64 ]; -dv_reg RXMBPENABLE; -dv_reg RXUNICASTSET; -dv_reg RXUNICASTCLEAR; -dv_reg RXMAXLEN; -dv_reg RXBUFFEROFFSET; -dv_reg RXFILTERLOWTHRESH; -u_int8_t RSVD4[8 ]; -dv_reg RX0FLOWTHRESH; -dv_reg RX1FLOWTHRESH; -dv_reg RX2FLOWTHRESH; -dv_reg RX3FLOWTHRESH; -dv_reg RX4FLOWTHRESH; -dv_reg RX5FLOWTHRESH; -dv_reg RX6FLOWTHRESH; -dv_reg RX7FLOWTHRESH; -dv_reg RX0FREEBUFFER; -dv_reg RX1FREEBUFFER; -dv_reg RX2FREEBUFFER; -dv_reg RX3FREEBUFFER; -dv_reg RX4FREEBUFFER; -dv_reg RX5FREEBUFFER; -dv_reg RX6FREEBUFFER; -dv_reg RX7FREEBUFFER; -dv_reg MACCONTROL; -dv_reg MACSTATUS; -dv_reg EMCONTROL; -dv_reg FIFOCONTROL; -dv_reg MACCONFIG; -dv_reg SOFTRESET; -u_int8_t RSVD5[88 ]; -dv_reg MACSRCADDRLO; -dv_reg MACSRCADDRHI; -dv_reg MACHASH1; -dv_reg MACHASH2; -dv_reg BOFFTEST; -dv_reg TPACETEST; -dv_reg RXPAUSE; -dv_reg TXPAUSE; -u_int8_t RSVD6[16 ]; -dv_reg RXGOODFRAMES; -dv_reg RXBCASTFRAMES; -dv_reg RXMCASTFRAMES; -dv_reg RXPAUSEFRAMES; -dv_reg RXCRCERRORS; -dv_reg RXALIGNCODEERRORS; -dv_reg RXOVERSIZED; -dv_reg RXJABBER; -dv_reg RXUNDERSIZED; -dv_reg RXFRAGMENTS; -dv_reg RXFILTERED; -dv_reg RXQOSFILTERED; -dv_reg RXOCTETS; -dv_reg TXGOODFRAMES; -dv_reg TXBCASTFRAMES; -dv_reg TXMCASTFRAMES; -dv_reg TXPAUSEFRAMES; -dv_reg TXDEFERRED; -dv_reg TXCOLLISION; -dv_reg TXSINGLECOLL; -dv_reg TXMULTICOLL; -dv_reg TXEXCESSIVECOLL; -dv_reg TXLATECOLL; -dv_reg TXUNDERRUN; -dv_reg TXCARRIERSENSE; -dv_reg TXOCTETS; -dv_reg FRAME64; -dv_reg FRAME65T127; -dv_reg FRAME128T255; -dv_reg FRAME256T511; -dv_reg FRAME512T1023; -dv_reg FRAME1024TUP; -dv_reg NETOCTETS; -dv_reg RXSOFOVERRUNS; -dv_reg RXMOFOVERRUNS; -dv_reg RXDMAOVERRUNS; -u_int8_t RSVD7[624 ]; -dv_reg MACADDRLO; -dv_reg MACADDRHI; -dv_reg MACINDEX; -u_int8_t RSVD8[244 ]; -dv_reg TX0HDP; -dv_reg TX1HDP; -dv_reg TX2HDP; -dv_reg TX3HDP; -dv_reg TX4HDP; -dv_reg TX5HDP; -dv_reg TX6HDP; -dv_reg TX7HDP; -dv_reg RX0HDP; -dv_reg RX1HDP; -dv_reg RX2HDP; -dv_reg RX3HDP; -dv_reg RX4HDP; -dv_reg RX5HDP; -dv_reg RX6HDP; -dv_reg RX7HDP; -dv_reg TX0CP; -dv_reg TX1CP; -dv_reg TX2CP; -dv_reg TX3CP; -dv_reg TX4CP; -dv_reg TX5CP; -dv_reg TX6CP; -dv_reg TX7CP; -dv_reg RX0CP; -dv_reg RX1CP; -dv_reg RX2CP; -dv_reg RX3CP; -dv_reg RX4CP; -dv_reg RX5CP; -dv_reg RX6CP; -dv_reg RX7CP; -}emac_regs ; - -/* EMAC Wrapper Registers Structure */ -typedef struct { -#ifdef DAVINCI_EMAC_VERSION2 -dv_reg idver; -dv_reg softrst; -dv_reg emctrl; -dv_reg c0rxthreshen; -dv_reg c0rxen; -dv_reg c0txen; -dv_reg c0miscen; -dv_reg c1rxthreshen; -dv_reg c1rxen; -dv_reg c1txen; -dv_reg c1miscen; -dv_reg c2rxthreshen; -dv_reg c2rxen; -dv_reg c2txen; -dv_reg c2miscen; -dv_reg c0rxthreshstat; -dv_reg c0rxstat; -dv_reg c0txstat; -dv_reg c0miscstat; -dv_reg c1rxthreshstat; -dv_reg c1rxstat; -dv_reg c1txstat; -dv_reg c1miscstat; -dv_reg c2rxthreshstat; -dv_reg c2rxstat; -dv_reg c2txstat; -dv_reg c2miscstat; -dv_reg c0rximax; -dv_reg c0tximax; -dv_reg c1rximax; -dv_reg c1tximax; -dv_reg c2rximax; -dv_reg c2tximax; -#else -u_int8_t RSVD0[4100 ]; -dv_reg EWCTL; -dv_reg EWINTTCNT; -#endif -}ewrap_regs ; - -/* EMAC MDIO Registers Structure */ -typedef struct { -dv_reg VERSION; -dv_reg CONTROL; -dv_reg ALIVE; -dv_reg LINK; -dv_reg LINKINTRAW; -dv_reg LINKINTMASKED; -u_int8_t RSVD0[8 ]; -dv_reg USERINTRAW; -dv_reg USERINTMASKED; -dv_reg USERINTMASKSET; -dv_reg USERINTMASKCLEAR; -u_int8_t RSVD1[80 ]; -dv_reg USERACCESS0; -dv_reg USERPHYSEL0; -dv_reg USERACCESS1; -dv_reg USERPHYSEL1; -}mdio_regs ; - -int davinci_eth_phy_read (u_int8_t phy_addr,u_int8_t reg_num,u_int16_t *data); -int davinci_eth_phy_write (u_int8_t phy_addr,u_int8_t reg_num,u_int16_t data); - -typedef struct -{ -char name[64 ]; -int (*init)(int phy_addr); -int (*is_phy_connected)(int phy_addr); -int (*get_link_speed)(int phy_addr); -int (*auto_negotiate)(int phy_addr); -}phy_t ; -#define PHY_KSZ8873 (0x00221450)int ksz8873_is_phy_connected (int phy_addr);int ksz8873_get_link_speed (int phy_addr);
drivers/net/davinci_emac.c +1 -0
@@ -43,6 +43,7 @@#include <malloc.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> +#include "davinci_emac.h" unsigned int emac_dbg =0 ; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args)
drivers/net/davinci_emac.h new file +314 -0
314 lines not on this page · raw message
Signature · 1 line
1.7.6.4
PATCH 3/14 davinci_emac: use internal addresses in buffer descriptors
In reply to Ilya YanokOn AM35xx CPPI RAM had different addresses when accessed from the CPU and from the EMAC. We need to account this to deal with the buffer descriptors correctly.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/net/davinci_emac.c | 39 ++++++++++++++++++++++++++++++--------- 1 files changed, 30 insertions(+), 9 deletions(-)
drivers/net/davinci_emac.c +30 -9
@@ -48,6 +48,27 @@unsigned int emac_dbg =0 ; #define debug_emac(fmt,args...) if (emac_dbg) printf(fmt,##args) +#ifdef EMAC_HW_RAM_ADDR +static inline unsigned long BD_TO_HW (unsigned long x) +{ +if (x ==0 ) +return 0 ; + +return x -EMAC_WRAPPER_RAM_ADDR +EMAC_HW_RAM_ADDR ; +} + +static inline unsigned long HW_TO_BD (unsigned long x) +{ +if (x ==0 ) +return 0 ; + +return x -EMAC_HW_RAM_ADDR +EMAC_WRAPPER_RAM_ADDR ; +} +#else +#define BD_TO_HW (x) (x) +#define HW_TO_BD (x) (x) +#endif +#ifdef DAVINCI_EMAC_GIG_ENABLE #define emac_gigabit_enable (phy_addr) davinci_eth_gigabit_enable(phy_addr)#else
@@ -435,7 +456,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)/* Create RX queue and set receive process in place */ emac_rx_active_head = emac_rx_desc;for (cnt =0 ; cnt <EMAC_MAX_RX_BUFFERS ; cnt++) { - rx_desc->next = (u_int32_t)(rx_desc +1 ); + rx_desc->next =BD_TO_HW ((u_int32_t)(rx_desc +1 )); rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE +EMAC_PKT_ALIGN )]; rx_desc->buff_off_len =EMAC_MAX_ETHERNET_PKT_SIZE ; rx_desc->pkt_flag_len =EMAC_CPPI_OWNERSHIP_BIT ;
@@ -488,7 +509,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)emac_gigabit_enable (active_phy_addr[index]);/* Start receive process */ -writel ((u_int32_t )emac_rx_desc, &adap_emac->RX0HDP); +writel (BD_TO_HW ((u_int32_t )emac_rx_desc), &adap_emac->RX0HDP);debug_emac ("- emac_open\n" );
@@ -606,7 +627,7 @@ static int davinci_eth_send_packet (struct eth_device *dev,EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT);/* Send the packet */ -writel ((unsigned long )emac_tx_desc, &adap_emac->TX0HDP); +writel (BD_TO_HW ((unsigned long )emac_tx_desc), &adap_emac->TX0HDP);/* Wait for packet to complete or link down */ while (1 ) {
@@ -650,14 +671,14 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) }/* Ack received packet descriptor */ -writel ((unsigned long )rx_curr_desc, &adap_emac->RX0CP); +writel (BD_TO_HW ((ulong )rx_curr_desc), &adap_emac->RX0CP); curr_desc = rx_curr_desc; emac_rx_active_head = - (volatile emac_desc *) rx_curr_desc->next; + (volatile emac_desc *) (HW_TO_BD (rx_curr_desc->next));if (status &EMAC_CPPI_EOQ_BIT ) {if (emac_rx_active_head) { -writel ((unsigned long )emac_rx_active_head, +writel (BD_TO_HW ((ulong )emac_rx_active_head), &adap_emac->RX0HDP); }else { emac_rx_queue_active =0 ;
@@ -675,7 +696,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) emac_rx_active_head = curr_desc; emac_rx_active_tail = curr_desc;if (emac_rx_queue_active !=0 ) { -writel ((unsigned long )emac_rx_active_head, +writel (BD_TO_HW ((ulong )emac_rx_active_head), &adap_emac->RX0HDP);printf ("INFO: emac_rcv_pkt: active queue head = 0, HDP fired\n" ); emac_rx_queue_active =1 ;
@@ -683,10 +704,10 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) }else { tail_desc = emac_rx_active_tail; emac_rx_active_tail = curr_desc; - tail_desc->next = (unsigned int ) curr_desc; + tail_desc->next =BD_TO_HW ((ulong ) curr_desc); status = tail_desc->pkt_flag_len;if (status &EMAC_CPPI_EOQ_BIT ) { -writel ((unsigned long )curr_desc, +writel (BD_TO_HW ((ulong )curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT ; tail_desc->pkt_flag_len = status;
Signature · 1 line
1.7.6.4
PATCH 4/14 davinci_emac: conditionally compile specific PHY support
In reply to Ilya YanokSigned-off-by Ilya Yanok <[email protected]>
--- drivers/net/davinci_emac.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-)
drivers/net/davinci_emac.c +8 -0
@@ -790,6 +790,7 @@ int davinci_emac_initialize(void) phy_id |= tmp &0x0000ffff ;switch (phy_id) { +#ifdef PHY_KSZ8873 case PHY_KSZ8873 :sprintf (phy[i].name,"KSZ8873 @ 0x%02x" , active_phy_addr[i]);
@@ -798,6 +799,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = ksz8873_get_link_speed; phy[i].auto_negotiate = ksz8873_auto_negotiate;break ; +#endif +#ifdef PHY_LXT972 case PHY_LXT972 :sprintf (phy[i].name,"LXT972 @ 0x%02x" , active_phy_addr[i]);
@@ -806,6 +809,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = lxt972_get_link_speed; phy[i].auto_negotiate = lxt972_auto_negotiate;break ; +#endif +#ifdef PHY_DP83848 case PHY_DP83848 :sprintf (phy[i].name,"DP83848 @ 0x%02x" , active_phy_addr[i]);
@@ -814,6 +819,8 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = dp83848_get_link_speed; phy[i].auto_negotiate = dp83848_auto_negotiate;break ; +#endif +#ifdef PHY_ET1011C case PHY_ET1011C :sprintf (phy[i].name,"ET1011C @ 0x%02x" , active_phy_addr[i]);
@@ -822,6 +829,7 @@ int davinci_emac_initialize(void) phy[i].get_link_speed = et1011c_get_link_speed; phy[i].auto_negotiate = gen_auto_negotiate;break ; +#endif default :sprintf (phy[i].name,"GENERIC @ 0x%02x" , active_phy_addr[i]);
Signature · 1 line
1.7.6.4
PATCH 5/14 davinci_emac: fix for running with dcache enabled
In reply to Ilya YanokDaVinci EMAC is present on TI AM35xx SoCs (ARMv7) which run with D-Cache enabled by default. So we have to take care and flush/invalidate the cache before/after the DMA operations.
Please note that the receive buffer alignment to 32 byte boundary comes from the old driver version I don't know if it is really needed or alignment to cache line size is enough.
!!!NOTE!!! This actually breaks builds for all DaVinci boards that use this driver (as there is no {invalidate,flush}_dcache_range for ARM926EJS).
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/net/davinci_emac.c | 41 +++++++++++++++++++++++++++++++++++++++-- drivers/net/davinci_emac.h | 5 +++-- 2 files changed, 42 insertions(+), 4 deletions(-)
drivers/net/davinci_emac.c +39 -2
@@ -41,6 +41,7 @@#include <net.h> #include <miiphy.h> #include <malloc.h> +#include <linux/compiler.h> #include <asm/arch/emac_defs.h> #include <asm/io.h> #include "davinci_emac.h"
@@ -100,7 +101,8 @@ static volatile emac_desc *emac_rx_active_tail = 0;static int emac_rx_queue_active =0 ;/* Receive packet buffers */ -static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS * (EMAC_MAX_ETHERNET_PKT_SIZE +EMAC_PKT_ALIGN )]; +static unsigned char emac_rx_buffers[EMAC_MAX_RX_BUFFERS *EMAC_RXBUF_SIZE ] +__aligned(CONFIG_SYS_CACHELINE_SIZE) ;#define MAX_PHY 3
@@ -112,6 +114,26 @@ static u_int8_t num_phy;phy_t phy[MAX_PHY ]; +static inline void davinci_flush_rx_descs (void ) +{ +/* flush the whole RX descs area */ +flush_dcache_range (EMAC_WRAPPER_RAM_ADDR +EMAC_RX_DESC_BASE , +EMAC_WRAPPER_RAM_ADDR +EMAC_TX_DESC_BASE ); +} + +static inline void davinci_invalidate_rx_descs (void ) +{ +/* invalidate the whole RX descs area */ +invalidate_dcache_range (EMAC_WRAPPER_RAM_ADDR +EMAC_RX_DESC_BASE , +EMAC_WRAPPER_RAM_ADDR +EMAC_TX_DESC_BASE ); +} + +static inline void davinci_flush_desc (emac_desc *desc) +{ +flush_dcache_range ((unsigned long )desc, + (unsigned long )desc +sizeof (*desc)); +} +static int davinci_eth_set_mac_addr (struct eth_device *dev) {unsigned long mac_hi;
@@ -457,7 +479,7 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_head = emac_rx_desc;for (cnt =0 ; cnt <EMAC_MAX_RX_BUFFERS ; cnt++) { rx_desc->next =BD_TO_HW ((u_int32_t)(rx_desc +1 )); - rx_desc->buffer = &emac_rx_buffers[cnt * (EMAC_MAX_ETHERNET_PKT_SIZE +EMAC_PKT_ALIGN )]; + rx_desc->buffer = &emac_rx_buffers[cnt *EMAC_RXBUF_SIZE ]; rx_desc->buff_off_len =EMAC_MAX_ETHERNET_PKT_SIZE ; rx_desc->pkt_flag_len =EMAC_CPPI_OWNERSHIP_BIT ; rx_desc++;
@@ -469,6 +491,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis) emac_rx_active_tail = rx_desc; emac_rx_queue_active =1 ; +davinci_flush_rx_descs (); +/* Enable TX/RX */ writel (EMAC_MAX_ETHERNET_PKT_SIZE , &adap_emac->RXMAXLEN);writel (0 , &adap_emac->RXBUFFEROFFSET);
@@ -626,6 +650,11 @@ static int davinci_eth_send_packet (struct eth_device *dev,EMAC_CPPI_SOP_BIT |EMAC_CPPI_OWNERSHIP_BIT | EMAC_CPPI_EOP_BIT); + +flush_dcache_range ((unsigned long )packet, + (unsigned long )packet + length); +davinci_flush_desc (emac_tx_desc); +/* Send the packet */ writel (BD_TO_HW ((unsigned long )emac_tx_desc), &adap_emac->TX0HDP);
@@ -658,6 +687,8 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)volatile emac_desc *tail_desc;int status, ret =-1 ; +davinci_invalidate_rx_descs (); + rx_curr_desc = emac_rx_active_head; status = rx_curr_desc->pkt_flag_len;if ((rx_curr_desc) && ((status &EMAC_CPPI_OWNERSHIP_BIT ) ==0 )) {
@@ -665,6 +696,9 @@ static int davinci_eth_rcv_packet (struct eth_device *dev)/* Error in packet - discard it and requeue desc */ printf ("WARN: emac_rcv_pkt: Error in packet\n" ); }else { +unsigned long tmp = (unsigned long )rx_curr_desc->buffer; + +invalidate_dcache_range (tmp, tmp +EMAC_RXBUF_SIZE );NetReceive (rx_curr_desc->buffer, (rx_curr_desc->buff_off_len &0xffff )); ret = rx_curr_desc->buff_off_len &0xffff ;
@@ -690,6 +724,7 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) rx_curr_desc->buff_off_len =EMAC_MAX_ETHERNET_PKT_SIZE ; rx_curr_desc->pkt_flag_len =EMAC_CPPI_OWNERSHIP_BIT ; rx_curr_desc->next =0 ; +davinci_flush_desc (rx_curr_desc);if (emac_rx_active_head ==0 ) {printf ("INFO: emac_rcv_pkt: active queue head = 0\n" );
@@ -707,11 +742,13 @@ static int davinci_eth_rcv_packet (struct eth_device *dev) tail_desc->next =BD_TO_HW ((ulong ) curr_desc); status = tail_desc->pkt_flag_len;if (status &EMAC_CPPI_EOQ_BIT ) { +davinci_flush_desc (tail_desc);writel (BD_TO_HW ((ulong )curr_desc), &adap_emac->RX0HDP); status &= ~EMAC_CPPI_EOQ_BIT ; tail_desc->pkt_flag_len = status; } +davinci_flush_desc (tail_desc); }return (ret); }
drivers/net/davinci_emac.h +3 -2
@@ -24,8 +24,9 @@/* Ethernet Min/Max packet size */ #define EMAC_MIN_ETHERNET_PKT_SIZE 60#define EMAC_MAX_ETHERNET_PKT_SIZE 1518 -/* 1518 + 18 = 1536 (packet aligned on 32 byte boundry) */ -#define EMAC_PKT_ALIGN 18 +/* Buffer size (should be aligned on 32 byte and cache line) */ +#define EMAC_RXBUF_SIZE ALIGN(ALIGN(EMAC_MAX_ETHERNET_PKT_SIZE, 32),\ + CONFIG_SYS_CACHELINE_SIZE)/* Number of RX packet buffers * NOTE: Only 1 buffer supported as of now
Signature · 1 line
1.7.6.4
PATCH 6/14 davinci_emac: hardcode 100Mbps for AM35xx and RMII
In reply to Ilya YanokFor some reason code setting the speed based on the PHY feedback causes troubles on AM3517 so hardcode 100Mbps for now.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/net/davinci_emac.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-)
drivers/net/davinci_emac.c +2 -1
@@ -507,7 +507,8 @@ static int davinci_eth_open(struct eth_device *dev, bd_t *bis)writel (1 , &adap_emac->RXUNICASTSET);/* Enable MII interface and Full duplex mode */ -#ifdef CONFIG_SOC_DA8XX +#if defined(CONFIG_SOC_DA8XX ) || \ + (defined(CONFIG_OMAP34XX ) && defined(CONFIG_DRIVER_TI_EMAC_USE_RMII )) writel((EMAC_MACCONTROL_MIIEN_ENABLE | EMAC_MACCONTROL_FULLDUPLEX_ENABLE | EMAC_MACCONTROL_RMIISPEED_100),
Signature · 1 line
1.7.6.4
PATCH 7/14 AM35xx: add EMAC support
In reply to Ilya YanokAM35xx has DaVinci-compatible EMAC.
Signed-off-by Ilya Yanok <[email protected]>
--- arch/arm/cpu/armv7/omap3/Makefile | 1 + arch/arm/cpu/armv7/omap3/emac.c | 44 +++++++++++++++++++++ arch/arm/include/asm/arch-omap3/am35x_def.h | 3 + arch/arm/include/asm/arch-omap3/emac_defs.h | 56 +++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 0 deletions(-) create mode 100644 arch/arm/cpu/armv7/omap3/emac.c create mode 100644 arch/arm/include/asm/arch-omap3/emac_defs.h
arch/arm/cpu/armv7/omap3/Makefile +1 -0
@@ -32,6 +32,7 @@ COBJS += clock.o COBJS += mem.o COBJS += sys_info.o +COBJS-$(CONFIG_DRIVER_TI_EMAC) += emac.o COBJS-$(CONFIG_EMIF4) += emif4.o COBJS-$(CONFIG_SDRC) += sdrc.o
arch/arm/cpu/armv7/omap3/emac.c new file +44 -0
44 lines not on this page · raw message
arch/arm/include/asm/arch-omap3/am35x_def.h +3 -0
@@ -32,6 +32,9 @@#ifndef __KERNEL_STRICT_NAMES#ifndef __ASSEMBLY__ +/* IP_SW_RESET bits */ +#define CPGMACSS_SW_RST (1 << 1)/* reset CPGMAC */ +/* General register mappings of system control module */ #define AM35X_SCM_GEN_BASE 0x48002270 struct am35x_scm_general {
arch/arm/include/asm/arch-omap3/emac_defs.h new file +56 -0
56 lines not on this page · raw message
Signature · 1 line
1.7.6.4
PATCH 8/14 AM3517: move AM3517 specific mux defines to generic header
In reply to Ilya YanokAM3517 specific CONTROL_PADCONF_* defines moved from board-specific files to <asm/arch-omap3/mux.h>
Signed-off-by Ilya Yanok <[email protected]>
--- arch/arm/include/asm/arch-omap3/mux.h | 41 +++++++++++++++++++++++++++++++++ board/logicpd/am3517evm/am3517evm.h | 40 -------------------------------- board/ti/am3517crane/am3517crane.h | 39 ------------------------------- 3 files changed, 41 insertions(+), 79 deletions(-)
arch/arm/include/asm/arch-omap3/mux.h +41 -0
@@ -404,6 +404,47 @@#define CONTROL_PADCONF_SDRC_CKE0 0x0262#define CONTROL_PADCONF_SDRC_CKE1 0x0264 +/* AM3517 specific mux configuration */ +#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 +/* CCDC */ +#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 +#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 +#define CONTROL_PADCONF_CCDC_HD 0x01E8 +#define CONTROL_PADCONF_CCDC_VD 0x01EA +#define CONTROL_PADCONF_CCDC_WEN 0x01EC +#define CONTROL_PADCONF_CCDC_DATA0 0x01EE +#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 +#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 +#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 +#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 +#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 +#define CONTROL_PADCONF_CCDC_DATA6 0x01FA +#define CONTROL_PADCONF_CCDC_DATA7 0x01FC +/* RMII */ +#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE +#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 +#define CONTROL_PADCONF_RMII_RXD0 0x0202 +#define CONTROL_PADCONF_RMII_RXD1 0x0204 +#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 +#define CONTROL_PADCONF_RMII_RXER 0x0208 +#define CONTROL_PADCONF_RMII_TXD0 0x020A +#define CONTROL_PADCONF_RMII_TXD1 0x020C +#define CONTROL_PADCONF_RMII_TXEN 0x020E +#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 +#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 +/* CAN */ +#define CONTROL_PADCONF_HECC1_TXD 0x0214 +#define CONTROL_PADCONF_HECC1_RXD 0x0216 + +#define CONTROL_PADCONF_SYS_BOOT7 0x0218 +#define CONTROL_PADCONF_SDRC_DQS0N 0x021A +#define CONTROL_PADCONF_SDRC_DQS1N 0x021C +#define CONTROL_PADCONF_SDRC_DQS2N 0x021E +#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 +#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 +#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 +#define CONTROL_PADCONF_SYS_BOOT8 0x0226 +#define MUX_VAL (OFFSET ,VALUE )\ writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
board/logicpd/am3517evm/am3517evm.h +0 -40
@@ -31,46 +31,6 @@ const omap3_sysinfo sysinfo = {"AM3517EVM Board" , "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 - -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226/* * IEN - Input Enable
board/ti/am3517crane/am3517crane.h +0 -39
@@ -30,45 +30,6 @@ const omap3_sysinfo sysinfo = {"CraneBoard" , "NAND", }; -/* AM3517 specific mux configuration */ -#define CONTROL_PADCONF_SYS_NRESWARM 0x0A08 -/* CCDC */ -#define CONTROL_PADCONF_CCDC_PCLK 0x01E4 -#define CONTROL_PADCONF_CCDC_FIELD 0x01E6 -#define CONTROL_PADCONF_CCDC_HD 0x01E8 -#define CONTROL_PADCONF_CCDC_VD 0x01EA -#define CONTROL_PADCONF_CCDC_WEN 0x01EC -#define CONTROL_PADCONF_CCDC_DATA0 0x01EE -#define CONTROL_PADCONF_CCDC_DATA1 0x01F0 -#define CONTROL_PADCONF_CCDC_DATA2 0x01F2 -#define CONTROL_PADCONF_CCDC_DATA3 0x01F4 -#define CONTROL_PADCONF_CCDC_DATA4 0x01F6 -#define CONTROL_PADCONF_CCDC_DATA5 0x01F8 -#define CONTROL_PADCONF_CCDC_DATA6 0x01FA -#define CONTROL_PADCONF_CCDC_DATA7 0x01FC -/* RMII */ -#define CONTROL_PADCONF_RMII_MDIO_DATA 0x01FE -#define CONTROL_PADCONF_RMII_MDIO_CLK 0x0200 -#define CONTROL_PADCONF_RMII_RXD0 0x0202 -#define CONTROL_PADCONF_RMII_RXD1 0x0204 -#define CONTROL_PADCONF_RMII_CRS_DV 0x0206 -#define CONTROL_PADCONF_RMII_RXER 0x0208 -#define CONTROL_PADCONF_RMII_TXD0 0x020A -#define CONTROL_PADCONF_RMII_TXD1 0x020C -#define CONTROL_PADCONF_RMII_TXEN 0x020E -#define CONTROL_PADCONF_RMII_50MHZ_CLK 0x0210 -#define CONTROL_PADCONF_USB0_DRVBUS 0x0212 -/* CAN */ -#define CONTROL_PADCONF_HECC1_TXD 0x0214 -#define CONTROL_PADCONF_HECC1_RXD 0x0216 -#define CONTROL_PADCONF_SYS_BOOT7 0x0218 -#define CONTROL_PADCONF_SDRC_DQS0N 0x021A -#define CONTROL_PADCONF_SDRC_DQS1N 0x021C -#define CONTROL_PADCONF_SDRC_DQS2N 0x021E -#define CONTROL_PADCONF_SDRC_DQS3N 0x0220 -#define CONTROL_PADCONF_STRBEN_DLY0 0x0222 -#define CONTROL_PADCONF_STRBEN_DLY1 0x0224 -#define CONTROL_PADCONF_SYS_BOOT8 0x0226/* * IEN - Input Enable
Signature · 1 line
1.7.6.4
PATCH 9/14 omap/spl: actually enable the console
In reply to Ilya YanokCurrently OMAP SPL code does all the initialization but does not set the gd->have_console value so no output is actually performed. This patch sets gd->have_console to 1.
Signed-off-by Ilya Yanok <[email protected]>
--- arch/arm/cpu/armv7/omap-common/spl.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)
arch/arm/cpu/armv7/omap-common/spl.c +2 -0
@@ -156,6 +156,8 @@ void preloader_console_init(void)serial_init ();/* serial communications setup */ + gd->have_console =1 ; +/* Avoid a second "U-Boot" coming from this string */ u_boot_rev = &u_boot_rev[7 ];
Signature · 1 line
1.7.6.4
PATCH 10/14 nand_spl_simple: add support for software ECC
In reply to Ilya YanokThis patch adds support for software ECC to the nand_spl_simple driver. To enable this one have to define CONFIG_SPL_NAND_SOFTECC.
Tested on OMAP3.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/mtd/nand/nand_ecc.c | 2 +- drivers/mtd/nand/nand_spl_simple.c | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-)
drivers/mtd/nand/nand_ecc.c +1 -1
@@ -50,7 +50,7 @@* only nand_correct_data() is needed */ -#ifndef CONFIG_NAND_SPL +#if !defined(CONFIG_NAND_SPL ) || defined(CONFIG_SPL_NAND_SOFTECC )/* * Pre-calculated 256-way 1 byte column parity */
drivers/mtd/nand/nand_spl_simple.c +10 -1
@@ -21,6 +21,7 @@#include <common.h> #include <nand.h> #include <asm/io.h> +#include <linux/mtd/nand_ecc.h> static int nand_ecc_pos[] =CONFIG_SYS_NAND_ECCPOS ;static nand_info_t mtd;
@@ -163,7 +164,8 @@ static int nand_read_page(int block, int page, void *dst) oob_data = ecc_calc +0x200 ;for (i =0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) { - this->ecc.hwctl (&mtd,NAND_ECC_READ ); +if (this->ecc.mode !=NAND_ECC_SOFT ) + this->ecc.hwctl (&mtd,NAND_ECC_READ ); this->read_buf (&mtd, p, eccsize); this->ecc.calculate (&mtd, p, &ecc_calc[i]); }
@@ -233,6 +235,13 @@ void nand_init(void) nand_chip.options =0 ;board_nand_init (&nand_chip); +#ifdef CONFIG_SPL_NAND_SOFTECC +if (nand_chip.ecc.mode ==NAND_ECC_SOFT ) { + nand_chip.ecc.calculate = nand_calculate_ecc; + nand_chip.ecc.correct = nand_correct_data; + } +#endif +if (nand_chip.select_chip) nand_chip.select_chip (&mtd,0 ); }
Signature · 1 line
1.7.6.4
PATCH 11/14 omap_gpmc: use SOFTECC in SPL if it's enabled
In reply to Ilya YanokUse software ECC for the SPL build if support for software ECC in SPL is enabled.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/mtd/nand/omap_gpmc.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)
drivers/mtd/nand/omap_gpmc.c +3 -1
@@ -348,7 +348,7 @@ int board_nand_init(struct nand_chip *nand) nand->chip_delay =100 ;/* Default ECC mode */ -#ifndef CONFIG_SPL_BUILD +#if !defined(CONFIG_SPL_BUILD ) || defined(CONFIG_SPL_NAND_SOFTECC ) nand->ecc.mode =NAND_ECC_SOFT ;#else nand->ecc.mode =NAND_ECC_HW ;
@@ -359,7 +359,9 @@ int board_nand_init(struct nand_chip *nand) nand->ecc.correct = omap_correct_data; nand->ecc.calculate = omap_calculate_ecc;omap_hwecc_init (nand); +#endif +#ifdef CONFIG_SPL_BUILD if (nand->options &NAND_BUSWIDTH_16 ) nand->read_buf = nand_read_buf16;else
Signature · 1 line
1.7.6.4
PATCH 12/14 nand_spl_simple: store temp data at CONFIG_SPL_NAND_WORKSPACE
In reply to Ilya YanokCurrently nand_spl_simple puts it's temp data at 0x10000 offset in SDRAM which is likely to contain already loaded data. I can't see any way to determine some safe address automagically so make it up to board porter to provide the safe-to-use address via CONFIG_SPL_NAND_WORKSPACE value.
Signed-off-by Ilya Yanok <[email protected]>
--- drivers/mtd/nand/nand_spl_simple.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-)
drivers/mtd/nand/nand_spl_simple.c +6 -1
@@ -158,8 +158,13 @@ static int nand_read_page(int block, int page, void *dst)/* No malloc available for now, just use some temporary locations * in SDRAM +* Please provide some safe value for CONFIG_SPL_NAND_WORKSPACE in +* your board configuration, this is just a guess!! */ - ecc_calc = (u_char *)(CONFIG_SYS_SDRAM_BASE +0x10000 ); +#ifndef CONFIG_SPL_NAND_WORKSPACE +#define CONFIG_SPL_NAND_WORKSPACE (CONFIG_SYS_SDRAM_BASE + 0x10000) +#endif + ecc_calc = (u_char *)CONFIG_SPL_NAND_WORKSPACE ; ecc_code = ecc_calc +0x100 ; oob_data = ecc_calc +0x200 ;
Signature · 1 line
1.7.6.4
PATCH 13/14 ehci-omap: driver for EHCI host on OMAP3
In reply to Ilya YanokTaken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by Ilya Yanok <[email protected]>
---
Please note that I wasn't able to test this patch on Beagle. Testers are welcome! Also we have one strange bug in our setup (mcx board, USB storage device, keyboard, mouse and BT stick connected through several hubs): while scanning the bus U-Boot fails to detect the keyboard (stalled endpoint while first 64-byte descriptor read) and after that the keyboard can't be detected even in Linux until power off/on.
Enabling DEBUG in common/usb.c makes this bug go away.
board/ti/beagle/beagle.c | 101 ------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 161 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 165 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.c
board/ti/beagle/beagle.c +0 -101
@@ -40,15 +40,6 @@#include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h>
@@ -376,104 +367,12 @@ int board_mmc_init(bd_t *bis)#endif #ifdef CONFIG_USB_EHCI - -#define GPIO_PHY_RESET 147 - -/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop (void ) -{ -pr_debug ("Resetting OMAP3 EHCI\n" ); -gpio_set_value (GPIO_PHY_RESET ,0 ); -writel (OMAP_UHH_SYSCONFIG_SOFTRESET ,OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); -/* disable USB clocks */ -struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; -sr32 (&prcm_base->iclken_usbhost,0 ,1 ,0 ); -sr32 (&prcm_base->fclken_usbhost,0 ,2 ,0 ); -sr32 (&prcm_base->iclken3_core,2 ,1 ,0 ); -sr32 (&prcm_base->fclken3_core,2 ,1 ,0 ); -return 0 ; -} -/* Call usb_stop() before starting the kernel */ void show_boot_progress (int val) {if (val ==15 )usb_stop (); } - -/* -* Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard. -* Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. -* See there for additional Copyrights. -*/ -int ehci_hcd_init (void ) -{ -pr_debug ("Initializing OMAP3 ECHI\n" ); - -/* Put the PHY in RESET */ -gpio_request (GPIO_PHY_RESET ,"" ); -gpio_direction_output (GPIO_PHY_RESET ,0 ); -gpio_set_value (GPIO_PHY_RESET ,0 ); - -/* Hold the PHY in RESET for enough time till DIR is high */ -/* Refer: ISSUE1 */ -udelay (10 ); - -struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; -/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ -sr32 (&prcm_base->iclken_usbhost,0 ,1 ,1 ); -/* -* Enable USBHOST_48M_FCLK (USBHOST_FCLK1) -* and USBHOST_120M_FCLK (USBHOST_FCLK2) -*/ -sr32 (&prcm_base->fclken_usbhost,0 ,2 ,3 ); -/* Enable USBTTL_ICLK */ -sr32 (&prcm_base->iclken3_core,2 ,1 ,1 ); -/* Enable USBTTL_FCLK */ -sr32 (&prcm_base->fclken3_core,2 ,1 ,1 ); -pr_debug ("USB clocks enabled\n" ); - -/* perform TLL soft reset, and wait until reset is complete */ -writel (OMAP_USBTLL_SYSCONFIG_SOFTRESET , -OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); -/* Wait for TLL reset to complete */ -while (!(readl (OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSSTATUS ) - &OMAP_USBTLL_SYSSTATUS_RESETDONE )); -pr_debug ("TLL reset done\n" ); - -writel (OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | -OMAP_USBTLL_SYSCONFIG_SIDLEMODE | -OMAP_USBTLL_SYSCONFIG_CACTIVITY , -OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); - -/* Put UHH in NoIdle/NoStandby mode */ -writel (OMAP_UHH_SYSCONFIG_ENAWAKEUP - |OMAP_UHH_SYSCONFIG_SIDLEMODE - |OMAP_UHH_SYSCONFIG_CACTIVITY - |OMAP_UHH_SYSCONFIG_MIDLEMODE , -OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); - -/* setup burst configurations */ -writel (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN - |OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN - |OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN , -OMAP3_UHH_BASE +OMAP_UHH_HOSTCONFIG ); - -/* -* Refer ISSUE1: -* Hold the PHY in RESET for enough time till -* PHY is settled and ready -*/ -udelay (10 ); -gpio_set_value (GPIO_PHY_RESET ,1 ); - - hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE ); - hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE +0x10 ); - -pr_debug ("OMAP3 EHCI init done\n" ); -return 0 ; -} -#endif /* CONFIG_USB_EHCI */ /*
drivers/usb/host/Makefile +1 -0
@@ -41,6 +41,7 @@ else COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.o
drivers/usb/host/ehci-omap.c new file +161 -0
161 lines not on this page · raw message
include/configs/omap3_beagle.h +3 -0
@@ -133,6 +133,9 @@/* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET 147#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX
Signature · 1 line
1.7.6.4
PATCH 13/14 ehci-omap: driver for EHCI host on OMAP3
Hi Ilya,
This is great! Thanks.
Couple of comments below
Quoted 5 lines · Ilya Yanok
Taken from Beagle code. Tested on mcx board (AM3517-based).
Signed-off-by Ilya Yanok <[email protected]>---
Quoted 8 lines
Please note that I wasn't able to test this patch on Beagle. Testers are welcome! Also we have one strange bug in our setup (mcx board, USB storage device, keyboard, mouse and BT stick connected through several hubs): while scanning the bus U-Boot fails to detect the keyboard (stalled endpoint while first 64-byte descriptor read) and after that the keyboard can't be detected even in Linux until power off/on.
Enabling DEBUG in
common/usb.cmakes this bug go away.
Sounds like kind of timing problem?
Have you tried using a delay in places where debug is used?
Quoted 193 lines
board/ti/beagle/beagle.c | 101 ------------------------- drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-omap.c | 161 ++++++++++++++++++++++++++++++++++++++++ include/configs/omap3_beagle.h | 3 + 4 files changed, 165 insertions(+), 101 deletions(-) create mode 100644 drivers/usb/host/ehci-omap.cboard/ti/beagle/beagle.c +0
-101@@ -40,15 +40,6 @@#include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> -#ifdef CONFIG_USB_EHCI -#include <usb.h> -#include <asm/arch/clocks.h> -#include <asm/arch/clocks_omap3.h> -#include <asm/arch/ehci_omap3.h> -/* from drivers/usb/host/ehci-core.h */ -extern struct ehci_hccr *hccr; -extern volatile struct ehci_hcor *hcor; -#endif #include "beagle.h" #include <command.h> @@ -376,104 +367,12 @@ int board_mmc_init(bd_t *bis)#endif #ifdef CONFIG_USB_EHCI - -#define GPIO_PHY_RESET 147 - -/* Reset is needed otherwise the kernel-driver will throw an error. */ -int ehci_hcd_stop (void ) -{ -pr_debug ("Resetting OMAP3 EHCI\n" ); -gpio_set_value (GPIO_PHY_RESET ,0 ); -writel (OMAP_UHH_SYSCONFIG_SOFTRESET ,OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); -/* disable USB clocks */ -struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; -sr32 (&prcm_base->iclken_usbhost,0 ,1 ,0 ); -sr32 (&prcm_base->fclken_usbhost,0 ,2 ,0 ); -sr32 (&prcm_base->iclken3_core,2 ,1 ,0 ); -sr32 (&prcm_base->fclken3_core,2 ,1 ,0 ); -return 0 ; -} -/* Call usb_stop() before starting the kernel */ void show_boot_progress (int val) {if (val ==15 )usb_stop (); } - -/* -* Initialize the OMAP3 EHCI controller and PHY on the BeagleBoard. -* Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. -* See there for additional Copyrights. -*/ -int ehci_hcd_init (void ) -{ -pr_debug ("Initializing OMAP3 ECHI\n" ); - -/* Put the PHY in RESET */ -gpio_request (GPIO_PHY_RESET ,"" ); -gpio_direction_output (GPIO_PHY_RESET ,0 ); -gpio_set_value (GPIO_PHY_RESET ,0 ); - -/* Hold the PHY in RESET for enough time till DIR is high */ -/* Refer: ISSUE1 */ -udelay (10 ); - -struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; -/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ -sr32 (&prcm_base->iclken_usbhost,0 ,1 ,1 ); -/* -* Enable USBHOST_48M_FCLK (USBHOST_FCLK1) -* and USBHOST_120M_FCLK (USBHOST_FCLK2) -*/ -sr32 (&prcm_base->fclken_usbhost,0 ,2 ,3 ); -/* Enable USBTTL_ICLK */ -sr32 (&prcm_base->iclken3_core,2 ,1 ,1 ); -/* Enable USBTTL_FCLK */ -sr32 (&prcm_base->fclken3_core,2 ,1 ,1 ); -pr_debug ("USB clocks enabled\n" ); - -/* perform TLL soft reset, and wait until reset is complete */ -writel (OMAP_USBTLL_SYSCONFIG_SOFTRESET , -OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); -/* Wait for TLL reset to complete */ -while (!(readl (OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSSTATUS ) - &OMAP_USBTLL_SYSSTATUS_RESETDONE )); -pr_debug ("TLL reset done\n" ); - -writel (OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | -OMAP_USBTLL_SYSCONFIG_SIDLEMODE | -OMAP_USBTLL_SYSCONFIG_CACTIVITY , -OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); - -/* Put UHH in NoIdle/NoStandby mode */ -writel (OMAP_UHH_SYSCONFIG_ENAWAKEUP - |OMAP_UHH_SYSCONFIG_SIDLEMODE - |OMAP_UHH_SYSCONFIG_CACTIVITY - |OMAP_UHH_SYSCONFIG_MIDLEMODE , -OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); - -/* setup burst configurations */ -writel (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN - |OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN - |OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN , -OMAP3_UHH_BASE +OMAP_UHH_HOSTCONFIG ); - -/* -* Refer ISSUE1: -* Hold the PHY in RESET for enough time till -* PHY is settled and ready -*/ -udelay (10 ); -gpio_set_value (GPIO_PHY_RESET ,1 ); - - hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE ); - hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE +0x10 ); - -pr_debug ("OMAP3 EHCI init done\n" ); -return 0 ; -} -#endif /* CONFIG_USB_EHCI */ /* drivers/usb/host/Makefile +1
-0@@ -41,6 +41,7 @@ else COBJS-$(CONFIG_USB_EHCI_FSL) += ehci-fsl.o endif COBJS-$(CONFIG_USB_EHCI_MXC) += ehci-mxc.o +COBJS-$(CONFIG_USB_EHCI_OMAP) += ehci-omap.o COBJS-$(CONFIG_USB_EHCI_PPC4XX) += ehci-ppc4xx.o COBJS-$(CONFIG_USB_EHCI_IXP4XX) += ehci-ixp.o COBJS-$(CONFIG_USB_EHCI_KIRKWOOD) += ehci-kirkwood.odrivers/usb/host/ehci-omap.c new file +42
-0@@ -0,0 +1,161 @@ +/* +* (C) Copyright 2011 Ilya Yanok, Emcraft Systems +* (C) Copyright 2004-2008 +* Texas Instruments, <www.ti.com> +* +* Derived from Beagle Board code by +* Sunil Kumar <[email protected]> +* Shashi Ranjan <[email protected]> +* +* +* See file CREDITS for list of people who contributed to this +* project. +* +* This program is free software; you can redistribute it and/or +* modify it under the terms of the GNU General Public License as +* published by the Free Software Foundation; either version 2 of +* the License, or (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc. +*/ +#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/gpio.h> +#include <asm/arch/clocks.h> +#include <asm/arch/clocks_omap3.h> +#include <asm/arch/ehci_omap3.h> +#include <asm/arch/sys_proto.h> +#include "ehci-core.h" + +inline int __board_usb_init (void ) +{ +return 0 ; +} +int board_usb_init (void ) __attribute__((weak,alias ("__board_usb_init" )));
drivers/usb/host/ehci-omap.c line 52
Quoted 10 lines
drivers/usb/host/ehci-omap.c new file +10
-0+ +/* Reset is needed otherwise the kernel-driver will throw an error. */ +int ehci_hcd_stop (void ) +{ +debug ("Resetting OMAP3 EHCI\n" ); +#ifdef CONFIG_OMAP_EHCI_PHY1_RESET +gpio_set_value (CONFIG_OMAP_EHCI_PHY1_RESET ,0 ); +#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET +gpio_set_value (CONFIG_OMAP_EHCI_PHY2_RESET ,0 );
The CONFIG_OMAP_EHCI_PHYx_RESET name is confusing - it does not say that it should be a GPIO number.
Quoted 35 lines
drivers/usb/host/ehci-omap.c new file +35
-0+#endif +writel (OMAP_UHH_SYSCONFIG_SOFTRESET , +OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); +/* disable USB clocks */ +struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; +sr32 (&prcm_base->iclken_usbhost,0 ,1 ,0 ); +sr32 (&prcm_base->fclken_usbhost,0 ,2 ,0 ); +sr32 (&prcm_base->iclken3_core,2 ,1 ,0 ); +sr32 (&prcm_base->fclken3_core,2 ,1 ,0 ); +return 0 ; +} + +/* +* Initialize the OMAP3 EHCI controller and PHY. +* Based on "drivers/usb/host/ehci-omap.c" from Linux 2.6.37. +* See there for additional Copyrights. +*/ +int ehci_hcd_init (void ) +{ +int ret; + +debug ("Initializing OMAP3 EHCI\n" ); + + ret =board_usb_init (); +if (ret <0 ) +return ret; + +#if defined(CONFIG_OMAP_EHCI_PHY1_RESET ) || \ + defined(CONFIG_OMAP_EHCI_PHY2_RESET ) +/* Put the PHY in RESET */ +#ifdef CONFIG_OMAP_EHCI_PHY1_RESET +gpio_request (CONFIG_OMAP_EHCI_PHY1_RESET ,"USB PHY1 reset" ); +gpio_direction_output (CONFIG_OMAP_EHCI_PHY1_RESET ,0 ); +gpio_set_value (CONFIG_OMAP_EHCI_PHY1_RESET ,0 ); +#endif
drivers/usb/host/ehci-omap.c line 97
Quoted 10 lines
drivers/usb/host/ehci-omap.c new file +10
-0+#ifdef CONFIG_OMAP_EHCI_PHY2_RESET +gpio_request (CONFIG_OMAP_EHCI_PHY2_RESET ,"USB PHY2 reset" ); +gpio_direction_output (CONFIG_OMAP_EHCI_PHY2_RESET ,0 ); +gpio_set_value (CONFIG_OMAP_EHCI_PHY2_RESET ,0 ); +#endif + +/* Hold the PHY in RESET for enough time till DIR is high */ +/* Refer: ISSUE1 */ +udelay (10 ); +#endif
The above does not look good...
May be extract the above to an additional function(s) and add a stub(s) if the relevant config option is not present?
Quoted 47 lines
drivers/usb/host/ehci-omap.c new file +47
-0+ +struct prcm *prcm_base = (struct prcm *)PRCM_BASE ; +/* Enable USBHOST_L3_ICLK (USBHOST_MICLK) */ +sr32 (&prcm_base->iclken_usbhost,0 ,1 ,1 ); +/* +* Enable USBHOST_48M_FCLK (USBHOST_FCLK1) +* and USBHOST_120M_FCLK (USBHOST_FCLK2) +*/ +sr32 (&prcm_base->fclken_usbhost,0 ,2 ,3 ); +/* Enable USBTTL_ICLK */ +sr32 (&prcm_base->iclken3_core,2 ,1 ,1 ); +/* Enable USBTTL_FCLK */ +sr32 (&prcm_base->fclken3_core,2 ,1 ,1 ); +debug ("USB clocks enabled\n" ); + +/* perform TLL soft reset, and wait until reset is complete */ +writel (OMAP_USBTLL_SYSCONFIG_SOFTRESET , +OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); +/* Wait for TLL reset to complete */ +while (!(readl (OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSSTATUS ) + &OMAP_USBTLL_SYSSTATUS_RESETDONE )) + ; +debug ("TLL reset done\n" ); + +writel (OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | +OMAP_USBTLL_SYSCONFIG_SIDLEMODE | +OMAP_USBTLL_SYSCONFIG_CACTIVITY , +OMAP3_USBTLL_BASE +OMAP_USBTLL_SYSCONFIG ); + +/* Put UHH in NoIdle/NoStandby mode */ +writel (OMAP_UHH_SYSCONFIG_ENAWAKEUP + |OMAP_UHH_SYSCONFIG_SIDLEMODE + |OMAP_UHH_SYSCONFIG_CACTIVITY + |OMAP_UHH_SYSCONFIG_MIDLEMODE , +OMAP3_UHH_BASE +OMAP_UHH_SYSCONFIG ); + +/* setup burst configurations */ +writel (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN + |OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN + |OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN , +OMAP3_UHH_BASE +OMAP_UHH_HOSTCONFIG ); + +#if defined(CONFIG_OMAP_EHCI_PHY1_RESET ) || \ + defined(CONFIG_OMAP_EHCI_PHY2_RESET ) +/* +* Refer ISSUE1: +* Hold the PHY in RESET for enough time till
drivers/usb/host/ehci-omap.c line 154
Quoted 10 lines
drivers/usb/host/ehci-omap.c new file +10
-0+* PHY is settled and ready +*/ +udelay (10 ); +#ifdef CONFIG_OMAP_EHCI_PHY1_RESET +gpio_set_value (CONFIG_OMAP_EHCI_PHY1_RESET ,1 ); +#endif +#ifdef CONFIG_OMAP_EHCI_PHY2_RESET +gpio_set_value (CONFIG_OMAP_EHCI_PHY2_RESET ,1 ); +#endif +#endif
same here?
Quoted 21 lines
drivers/usb/host/ehci-omap.c new file +7
-0+ + hccr = (struct ehci_hccr *)(OMAP3_EHCI_BASE ); + hcor = (struct ehci_hcor *)(OMAP3_EHCI_BASE +0x10 ); + +debug ("OMAP3 EHCI init done\n" ); +return 0 ; +}include/configs/omap3_beagle.h +3
-0@@ -133,6 +133,9 @@/* USB EHCI */ #define CONFIG_CMD_USB #define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET 147#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3#define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_SMSC95XX
Signature · 2 lines
Regards, Igor.
PATCH 13/14 ehci-omap: driver for EHCI host on OMAP3
Hi Igor,
Quoted 10 lines · Igor Grinberg
Quoted 8 lines
Please note that I wasn't able to test this patch on Beagle. Testers are welcome! Also we have one strange bug in our setup (mcx board, USB storage device, keyboard, mouse and BT stick connected through several hubs): while scanning the bus U-Boot fails to detect the keyboard (stalled endpoint while first 64-byte descriptor read) and after that the keyboard can't be detected even in Linux until power off/on.
Enabling DEBUG in
common/usb.cmakes this bug go away.Sounds like kind of timing problem?
Have you tried using a delay in places where debug is used?
Yes, increasing the delay after port reset from 200ms to 260ms does help.
Thanks for your comments, I've addressed them and just posted the updated version.
Regards, Ilya.
PATCH 14/14 mcx: support for HTKW mcx board
In reply to Ilya YanokThis patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Requires updated mach-types file.
Signed-off-by Ilya Yanok <[email protected]>
--- MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 89 ++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 918 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.h
MAINTAINERS +4 -0
@@ -886,6 +886,10 @@ Richard Woodruff <[email protected]> omap2420h4 ARM1136EJS +Ilya Yanok <[email protected]> + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim <[email protected]> Sughosh Ganu <[email protected]>
board/htkw/mcx/Makefile new file +38 -0
@@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend
board/htkw/mcx/mcx.c new file +89 -0
89 lines not on this page · raw message
board/htkw/mcx/mcx.h new file +408 -0
408 lines not on this page · raw message
boards.cfg +1 -0
@@ -185,6 +185,7 @@ omap3_beagle arm armv7 beagle ti omap3_evm arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsung s5pc1xx
include/configs/mcx.h new file +378 -0
378 lines not on this page · raw message
Signature · 1 line
1.7.6.4
PATCH 14/14 mcx: support for HTKW mcx board
Hi Ilya,
Quoted 160 lines · Ilya Yanok
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported.
Requires updated mach-types file.
Signed-off-by Ilya Yanok <[email protected]>--- MAINTAINERS | 4 + board/htkw/mcx/Makefile | 38 +++++ board/htkw/mcx/mcx.c | 89 ++++++++++ board/htkw/mcx/mcx.h | 408 +++++++++++++++++++++++++++++++++++++++++++++++ boards.cfg | 1 + include/configs/mcx.h | 378 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 918 insertions(+), 0 deletions(-) create mode 100644 board/htkw/mcx/Makefile create mode 100644 board/htkw/mcx/mcx.c create mode 100644 board/htkw/mcx/mcx.h create mode 100644 include/configs/mcx.hMAINTAINERS +4
-0@@ -886,6 +886,10 @@ Richard Woodruff <[email protected]> omap2420h4 ARM1136EJS +Ilya Yanok <[email protected]> + + mcx ARM ARMV7 (AM35x SoC) + Syed Mohammed Khasim <[email protected]> Sughosh Ganu <[email protected]>board/htkw/mcx/Makefile new file +38
-0@@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Ilya Yanok, Emcraft Systems +# +# Based on ti/evm/Makefile +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).dependboard/htkw/mcx/mcx.c new file +75
-0@@ -0,0 +1,89 @@ +/* +* Copyright (C) 2011 Ilya Yanok, Emcraft Systems +* +* Based on ti/evm/evm.c +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc. +*/ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mem.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-types.h> +#include <asm/gpio.h> +#include <asm/omap_gpio.h> +#include <i2c.h> +#include "mcx.h" + +DECLARE_GLOBAL_DATA_PTR ; + +/* +* Routine: board_init +* Description: Early hardware init. +*/ +int board_init (void ) +{ +gpmc_init ();/* in SRAM or SDRAM, finish GPMC */ +/* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 +0x100 ); + +return 0 ; +} + +/* +* Routine: misc_init_r +* Description: Init i2c, ethernet, etc... (done here so udelay works) +*/ +int misc_init_r (void ) +{ +dieid_num_r (); + +return 0 ; +} + +/* +* Routine: set_muxconf_regs +* Description: Setting up the configuration Mux registers specific to the +* hardware. Many pins need to be moved from protect to primary +* mode. +*/ +void set_muxconf_regs (void ) +{ +MUX_MCX (); +} + +#if defined(CONFIG_GENERIC_MMC ) && defined(CONFIG_OMAP_HSMMC ) && \ + !defined(CONFIG_SPL_BUILD ) +int board_mmc_init (bd_t *bis) +{ +omap_mmc_init (0 ); +return 0 ;
board/htkw/mcx/mcx.c line 85
Quoted 10 lines
board/htkw/mcx/mcx.c new file +10
-0+} +#endif + +#ifdef CONFIG_USB_EHCI_OMAP +#define USB_HOST_PWR_EN 132 +int board_usb_init (void ) +{ +gpio_request (USB_HOST_PWR_EN ,"USB_HOST_PWR_EN" ); +gpio_direction_output (USB_HOST_PWR_EN ,1 ); +gpio_set_value (USB_HOST_PWR_EN ,1 );
gpio_direction_output(x, y) already sets a value, you don't need to call gpio_set_value() afterwards. This also holds for 13/14 patch.
Quoted 797 lines
board/htkw/mcx/mcx.c new file +4
-0+ + return 0; +} +#endif board/htkw/mcx/mcx.h new file +408
-0@@ -0,0 +1,408 @@ +/* +* Copyright (C) 2011 Ilya Yanok, Emcraft Systems +* +* Based on ti/evm/evm.h +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc. +*/ + +#ifndef _AM3517EVM_H_ +#define _AM3517EVM_H_ + +const omap3_sysinfo sysinfo = { +DDR_DISCRETE , +"HTKW mcx Board" , +"NAND" , +}; + +/* +* IEN - Input Enable +* IDIS - Input Disable +* PTD - Pull type Down +* PTU - Pull type Up +* DIS - Pull type selection is inactive +* EN - Pull type selection is active +* M0 - Mode 0 +* The commented string gives the final mux configuration for that pin +*/ +#define MUX_MCX () \ +/* SDRC */ \ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SDRC_DQS0N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS1N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS2N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_DQS3N), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(SDRC_CKE0), (M0)) \ + MUX_VAL(CP(SDRC_CKE1), (M0)) \ + MUX_VAL(CP(STRBEN_DLY0), (IEN | PTD | EN | M0)) \ +/*sdrc_strben_dly0*/ \ +MUX_VAL (CP (STRBEN_DLY1 ), (IEN |PTD |EN |M0 )) \ +/*sdrc_strben_dly1*/ \ + /* GPMC */\ + MUX_VAL(CP(GPMC_A1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A7), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_A9), (IEN | PTU | EN | M4)) \ +MUX_VAL (CP (GPMC_A10 ), (IDIS |PTU |DIS |M4 )) \ + /* GPIO_43 LCD buffer enable */ \ + MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_NCS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS3), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_NCS5), (IEN | PTU | EN | M4)) \ +MUX_VAL (CP (GPMC_NCS6 ), (IEN |PTU |EN |M4 )) \ + /* GPIO_57 TS_PenIRQn */\ +MUX_VAL (CP (GPMC_NCS7 ), (IEN |PTU |EN |M4 )) \ + /* GPIO_58 ETHERNET RESET */\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0)) \ +MUX_VAL (CP (GPMC_NBE1 ), (IEN |PTU |DIS |M4 )) \ + /* GPIO_61 SD-CARD CD */ \ +MUX_VAL (CP (GPMC_NWP ), (IDIS |PTU |EN |M4 )) \ + /* GPIO_62 Nand write protect, keep enabled */ \ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4))\ +MUX_VAL (CP (GPMC_WAIT3 ), (IEN |PTU |EN |M4 )) \ +/* GPIO_65 SD-CARD WP */ \ + /* DSS */\ + MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA0), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(DSS_DATA1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA8), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA9), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA17), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA18), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0)) \ +MUX_VAL (CP (DSS_DATA23 ), (IDIS |PTD |DIS |M0 )) \ + /* CAMERA */\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_PCLK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(CAM_FLD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D6), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D7), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D8), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D9), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D10), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_D11), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_XCLKB), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CAM_STROBE), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DY0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CSI2_DX1), (IEN | PTD | EN | M4)) \ +MUX_VAL (CP (CSI2_DY1 ), (IEN |PTD |EN |M4 )) \ + /* MMC */\ + MUX_VAL(CP(MMC1_CLK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MMC1_DAT4), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT5), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT6), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MMC1_DAT7), (IEN | PTU | EN | M4)) \ + \ + MUX_VAL(CP(MMC2_CLK), (IEN | PTD | EN | M4)) \ +MUX_VAL (CP (MMC2_CMD ), (IDIS |PTD |DIS |M4 )) \ + /* GPIO_131 LCD Enable */ \ +MUX_VAL (CP (MMC2_DAT0 ), (IDIS |PTD |DIS |M4 )) \ + /* GPIO_132 USB host Enable */\ +MUX_VAL (CP (MMC2_DAT1 ), (IDIS |PTD |DIS |M4 )) \ + /* GPIO_133 HDMI PD */\ + MUX_VAL(CP(MMC2_DAT2), (IEN | PTU | EN | M4)) \ +MUX_VAL (CP (MMC2_DAT3 ), (IEN |PTU |EN |M4 ))\ + /* McBSP */\ + MUX_VAL(CP(MCBSP_CLKS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_FSX), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(MCBSP2_FSX), (IEN | PTU | EN | M4))\ + MUX_VAL(CP(MCBSP2_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP2_DX), (IEN | PTU | EN | M4))\ + \ + MUX_VAL(CP(MCBSP3_DX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_DR), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_CLKX), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCBSP3_FSX), (IEN | PTU | EN | M4))\ + \ +MUX_VAL (CP (MCBSP4_CLKX ), (IDIS |PTD |DIS |M4 )) \ + /* GPIO_152 USB phy2 reset */\ +MUX_VAL (CP (MCBSP4_DR ), (IEN |PTU |EN |M4 )) \ + /* GPIO_153 */\ +MUX_VAL (CP (MCBSP4_DX ), (IDIS |PTD |DIS |M4 )) \ + /* GPIO_154 USB phy1 reset */\ +MUX_VAL (CP (MCBSP4_FSX ), (IEN |PTU |EN |M4 )) \ +/* GPIO_155 TS_BUSY */ \ + /* UART */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART2_RX), (IEN | PTD | DIS | M0)) \ + \ + MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | DIS | M0)) \ + MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTD | DIS | M0)) \ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) \ +MUX_VAL (CP (UART3_TX_IRTX ), (IDIS |PTD |DIS |M0 )) \ + /* I2C */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0)) \ +MUX_VAL (CP (I2C4_SDA ), (IEN |PTU |EN |M0 )) \ + /* McSPI */\ + MUX_VAL(CP(MCSPI1_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SIMO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_SOMI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(MCSPI1_CS0), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(MCSPI1_CS1), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS2), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(MCSPI1_CS3), (IEN | PTU | EN | M4)) \ +MUX_VAL (CP (MCSPI2_CLK ), (IEN |PTD |DIS |M3 )) \ + /* HSUSB2_dat7 */\ +MUX_VAL (CP (MCSPI2_SIMO ), (IEN |PTD |DIS |M3 )) \ + /* HSUSB2_dat4 */\ +MUX_VAL (CP (MCSPI2_SOMI ), (IEN |PTD |DIS |M3 )) \ + /* HSUSB2_dat5 */\ +MUX_VAL (CP (MCSPI2_CS0 ), (IEN |PTD |DIS |M3 )) \ + /* HSUSB2_dat6 */\ +MUX_VAL (CP (MCSPI2_CS1 ), (IEN |PTD |DIS |M3 )) \ +/* HSUSB2_dat3 */ \ + /* CCDC */\ + MUX_VAL(CP(CCDC_PCLK), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_FIELD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_HD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_VD), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_WEN), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA0), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA1), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA2), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA3), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA4), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA5), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(CCDC_DATA6), (IEN | PTD | EN | M4)) \ +MUX_VAL (CP (CCDC_DATA7 ), (IEN |PTD |EN |M4 )) \ + /* RMII */\ + MUX_VAL(CP(RMII_MDIO_DATA), (IEN | M0)) \ + MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \ + MUX_VAL(CP(RMII_RXD0), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXD1), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | M0)) \ + MUX_VAL(CP(RMII_RXER), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD0), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXD1), (PTD | M0)) \ + MUX_VAL(CP(RMII_TXEN), (PTD | M0)) \ +MUX_VAL (CP (RMII_50MHZ_CLK ), (IEN |PTD |EN |M0 )) \ + /* HECC */\ + MUX_VAL(CP(HECC1_TXD), (IEN | PTD | EN | M4)) \ +MUX_VAL (CP (HECC1_RXD ), (IEN |PTD |EN |M4 )) \ + /* HSUSB */\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) \ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) \ +MUX_VAL (CP (USB0_DRVBUS ), (IEN |PTD |EN |M0 )) \ + /* HDQ */\ +MUX_VAL (CP (HDQ_SIO ), (IEN |PTD |EN |M4 )) \ + /* Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | EN | M4)) \ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_NIRQ), (IEN | PTD | EN | M4)) \ +MUX_VAL (CP (SYS_NRESWARM ), (IEN |PTU |DIS |M4 )) \ + /* SYS_nRESWARM */\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4))\ + MUX_VAL(CP(SYS_BOOT7), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(SYS_BOOT8), (IEN | PTD | DIS | M4)) \ + \ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M4))\ +MUX_VAL (CP (SYS_CLKOUT2 ), (IDIS |PTU |DIS |M4 ))\ + /* JTAG */\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TCK), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TMS), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_TDI), (IEN | PTU | EN | M4)) \ + MUX_VAL(CP(JTAG_EMU0), (IEN | PTU | EN | M4)) \ +MUX_VAL (CP (JTAG_EMU1 ), (IEN |PTU |EN |M4 ))\ + /* ETK (ES2 onwards) */\ +MUX_VAL (CP (ETK_CLK_ES2 ), (IDIS |PTD |DIS |M3 )) \ + /* hsusb1_stp */ \ +MUX_VAL (CP (ETK_CTL_ES2 ), (IDIS |PTD |DIS |M3 )) \ + /* hsusb1_clk */\ + MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)) \ + MUX_VAL(CP(ETK_D10_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D11_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | DIS | M4)) \ + MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | DIS | M4)) \ +MUX_VAL (CP (ETK_D15_ES2 ), (IEN |PTD |DIS |M4 )) \ + /* Die to Die */\ + MUX_VAL(CP(D2D_MCAD34), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD35), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_MCAD36), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_CLK26MI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_NRESPWRON), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_NRESWARM), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_ARM9NIRQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SPINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_FRINT), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_DMAREQ0), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ1), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ2), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_DMAREQ3), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTRST), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDI), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTDO), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTMS), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_N3GRTCK), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MSTDBY), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0)) \ + MUX_VAL(CP(D2D_IDLEREQ), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_IDLEACK), (IEN | PTU | EN | M0)) \ + MUX_VAL(CP(D2D_MWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SWRITE), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SREAD), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_MBUSFLAG), (IEN | PTD | DIS | M0)) \ + MUX_VAL(CP(D2D_SBUSFLAG), (IEN | PTD | DIS | M0)) \ + +#endif boards.cfg +1
-0@@ -185,6 +185,7 @@ omap3_beagle arm armv7 beagle ti omap3_evm arm armv7 evm ti omap3 omap3_sdp3430 arm armv7 sdp3430 ti omap3 devkit8000 arm armv7 devkit8000 timll omap3 +mcx arm armv7 mcx htkw omap3 omap4_panda arm armv7 panda ti omap4 omap4_sdp4430 arm armv7 sdp4430 ti omap4 s5p_goni arm armv7 goni samsung s5pc1xxinclude/configs/mcx.h new file +361
-0@@ -0,0 +1,378 @@ +/* +* Copyright (C) 2011 Ilya Yanok, Emcraft Systems +* +* Based on omap3_evm_config.h +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License as published by +* the Free Software Foundation; either version 2 of the License, or +* (at your option) any later version. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc. +*/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* +* High Level Configuration Options +*/ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_MCX /* working with mcx */ + +#define CONFIG_MACH_TYPE MACH_TYPE_MCX + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#define CONFIG_EMIF4 /* The chip has EMIF4 controller */ + +#include <asm/arch/cpu.h> /* get chip and board defs */ +#include <asm/arch/omap3.h> + +#define CONFIG_OF_LIBFDT +#define CONFIG_FIT + +#define CONFIG_SYS_TEXT_BASE 0x80008000 + +/* +* Display CPU and Board information +*/ +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* Clock Defines */ +#define V_OSCK 26000000/* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ/* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* +* Size of malloc() pool +*/ +#define CONFIG_ENV_SIZE (128 << 10)/* 128 KiB sector */ +#define CONFIG_SYS_MALLOC_LEN (1024 << 10) +/* +* DDR related +*/ +#define CONFIG_OMAP3_MICRON_DDR /* Micron DDR */ +#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) + +/* +* Hardware drivers +*/ + +/* +* NS16550 Configuration +*/ +#define V_NS16550_CLK 48000000/* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* +* select serial console configuration +*/ +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3/* UART3 */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_GENERIC_MMC +#define CONFIG_DOS_PARTITION + +/* EHCI */ +#define CONFIG_USB_STORAGE +#define CONFIG_OMAP3_GPIO_5 +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_OMAP +/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */ +#define CONFIG_OMAP_EHCI_PHY1_RESET 154 +#define CONFIG_OMAP_EHCI_PHY2_RESET 152 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 + +/* commands to include */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ + +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_NAND /* NAND support */ +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_RBTREE +#define CONFIG_LZO +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_MTDPARTS + +#undef CONFIG_CMD_FLASH/* flinfo, erase, protect */ +#undef CONFIG_CMD_FPGA/* FPGA configuration Support */ +#undef CONFIG_CMD_IMI/* iminfo */ +#undef CONFIG_CMD_IMLS/* List all found images */ + +#define CONFIG_SYS_NO_FLASH +#define CONFIG_HARD_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_DRIVER_OMAP34XX_I2C + +/* RTC */ +#define CONFIG_RTC_DS1337 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 + +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +/* +* Board NAND Info. +*/ +#define CONFIG_SYS_NAND_ADDR NAND_BASE/* physical address */ +/* to access nand */ +#define CONFIG_SYS_NAND_BASE NAND_BASE/* physical address */ +/* to access */ +/* nand at CS0 */ + +#define CONFIG_SYS_MAX_NAND_DEVICE 1/* Max number of */ +/* NAND devices */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ + +#define CONFIG_JFFS2_NAND +/* nand device jffs2 lives on */ +#define CONFIG_JFFS2_DEV "nand0" +/* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_OFFSET 0x680000 +#define CONFIG_JFFS2_PART_SIZE 0xf980000/* sz of jffs2 part */ + +/* Environment information */ +#define CONFIG_BOOTDELAY 10 + +#define CONFIG_BOOTFILE "uImage" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyO2,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "nandargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock4 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "nandboot=echo Booting from nand ...; " \ + "run nandargs; " \ + "nand read ${loadaddr} 280000 400000; " \ + "bootm ${loadaddr}\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmc init; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run nandboot; " \ + "fi; " \ + "fi; " \ + "else run nandboot; fi" + +#define CONFIG_AUTO_COMPLETE +/* +* Miscellaneous configurable options +*/ +#define V_PROMPT "mcx # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 512/* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 32/* max number of command */ +/* args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) +/* memtest works on */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ + 0x01F00000)/* 31MB */ + +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)/* default load */ +/* address */ + +/* +* AM3517 has 12 GP timers, they can be driven by the system clock +* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). +* This rate is divided by a local divisor. +*/ +#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 +#define CONFIG_SYS_PTV 2/* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/*----------------------------------------------------------------------- +* Stack sizes +* +* The stack sizes are set up in start.S using the settings below +*/ +#define CONFIG_STACKSIZE (128 << 10)/* regular stack 128 KiB */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10)/* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10)/* FIQ stack 4 KiB */ +#endif + +/*----------------------------------------------------------------------- +* Physical Memory Map +*/ +#define CONFIG_NR_DRAM_BANKS 2/* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20)/*@least 32 MiB */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/*----------------------------------------------------------------------- +* FLASH and environment organization +*/ + +/* **** PISMO SUPPORT *** */ + +/* Configure the PISMO */ +#define PISMO1_NAND_SIZE GPMC_SIZE_128M + +#define CONFIG_NAND_OMAP_GPMC +#define GPMC_NAND_ECC_LP_x16_LAYOUT +#define CONFIG_ENV_IS_IN_NAND +#define SMNAND_ENV_OFFSET 0x260000/* environment starts here */ + +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)/* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET +#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET + +/*----------------------------------------------------------------------- +* CFI FLASH driver setup +*/ +/* timeout values are in ticks */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* Flash banks JFFS2 should use */ +#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ + CONFIG_SYS_MAX_NAND_DEVICE) +#define CONFIG_SYS_JFFS2_MEM_NAND +/* use flash_info[2] */ +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_NAND_SOFTECC +#define CONFIG_SPL_NAND_WORKSPACE 0x8f07f000/* below malloc */ + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +#define CONFIG_SPL_TEXT_BASE 0x40200000/*CONFIG_SYS_SRAM_START*/ +#define CONFIG_SPL_MAX_SIZE 0xB400/* 45 K */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x8f080000/* end of RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300/* address 0x60000 */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 +#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\ + 48, 49, 50, 51, 52, 53, 54, 55,\ + 56, 57, 58, 59, 60, 61, 62, 63} +#define CONFIG_SYS_NAND_ECCSIZE 256 +#define CONFIG_SYS_NAND_ECCBYTES 3 + +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) + +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE + +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
include/configs/mcx.h line 371
Quoted 10 lines
include/configs/mcx.h new file +10
-0+ +/* +* ethernet support +* +*/ +#if defined(CONFIG_CMD_NET ) +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_DRIVER_TI_EMAC_USE_RMII +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT
alignment?
Quoted 7 lines
include/configs/mcx.h new file +7
-0+#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#endif + +#endif /* __CONFIG_H */
Signature · 2 lines
Regards, Igor.
cover Support for HTKW mcx board
In reply to Ilya YanokQuoted 4 lines · Ilya Yanok
Hello All,
these patches introduce support for HTKW mcx board (AM3517-based).
Quoted 8 lines
Previously posted DaVinci EMAC patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 ) and NAND SPL patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112890 ) are also included as long as EHCI host support (moved from Beagle board code).Signed-off-by Ilya Yanok <[email protected]>
As a note, these patches, along with the board specific enablement work on am3517evm and I'll be posting those patches soon.
Signature · 1 line
Tom
cover Support for HTKW mcx board
In reply to Ilya YanokQuoted 4 lines · Ilya Yanok
Hello All,
these patches introduce support for HTKW mcx board (AM3517-based).
Quoted 8 lines
Previously posted DaVinci EMAC patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 ) and NAND SPL patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112890 ) are also included as long as EHCI host support (moved from Beagle board code).Signed-off-by Ilya Yanok <[email protected]>
I'm not sure what we should do about this series right now. Aside from some "easily" fixable things like all of the PHY files needing an ugly #include "../../../../../drivers/net/davinci_emac.h" to compile again and a CONFIG_SYS_CACHELINE_SIZE 32 in all of the platforms, the lack of flush functions means that MAKEALL -s davinci fails for almost every board now. I'm not sure what we should do, at this point...
Signature · 1 line
Tom
cover Support for HTKW mcx board
Hi Tom,
Quoted 9 lines · Tom Rini
Quoted 9 lines
these patches introduce support for HTKW mcx board (AM3517-based).
Previously posted DaVinci EMAC patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 ) and NAND SPL patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112890 ) are also included as long as EHCI host support (moved from Beagle board code).
Quoted 5 lines
Quoted 1 line
Signed-off-by Ilya Yanok<[email protected]>I'm not sure what we should do about this series right now. Aside from some "easily" fixable things like all of the PHY files needing an ugly #include "
../../../../../drivers/net/davinci_emac.h" to compile
Shouldn't we use generic PHY layer and move all PHY files to drivers/net/phy?
Quoted 1 line
again and a
CONFIG_SYS_CACHELINE_SIZE32 in all of the platforms, the
s/CONFIG_SYS_CACHELINE_SIZE/ARCH_DMA_MINALIGN/ should solve this problem. I'll fix this.
Quoted 2 lines
lack of flush functions means that MAKEALL -s davinci fails for almost every board now. I'm not sure what we should do, at this point...
Argh.. Actually my initial version had a workaround for this, only using {flush,invalidate}_dcache_range under #ifdef DAVINCI_EMAC_DCACHE clause... But Mike told me that I should remove this...
Maybe we can just add empty functions for CONFIG_DCACHE_OFF case to fix the compilation?
Regards, Ilya.
cover Support for HTKW mcx board
Quoted 13 lines · Ilya Yanok
Hi Tom,
Quoted 10 lines · Tom Rini
Quoted 10 lines
these patches introduce support for HTKW mcx board (AM3517-based).
Previously posted DaVinci EMAC patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 ) and NAND SPL patches
( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112890 ) are also included as long as EHCI host support (moved from Beagle board code).
Quoted 7 lines
Quoted 5 lines
Quoted 1 line
Signed-off-by Ilya Yanok<[email protected]>I'm not sure what we should do about this series right now. Aside from some "easily" fixable things like all of the PHY files needing an ugly #include "
../../../../../drivers/net/davinci_emac.h" to compileShouldn't we use generic PHY layer and move all PHY files to
drivers/net/phy?
I'd love to see a switch to phylib (which the kernel version uses) but don't see that as a blocker to merging the series.
Quoted 4 lines
Quoted 2 lines
again and a
CONFIG_SYS_CACHELINE_SIZE32 in all of the platforms, thes/CONFIG_SYS_CACHELINE_SIZE/ARCH_DMA_MINALIGN/ should solve this problem.
I'll fix this.
Thanks.
Quoted 4 lines
Quoted 2 lines
lack of flush functions means that MAKEALL -s davinci fails for almost every board now. I'm not sure what we should do, at this point...
Argh.. Actually my initial version had a workaround for this, only using
{flush,invalidate}_dcache_range under #ifdef DAVINCI_EMAC_DCACHE clause... But Mike told me that I should remove this...
Quoted 2 lines
Maybe we can just add empty functions for
CONFIG_DCACHE_OFFcase to fix
the compilation?
Let me think about this more...
Signature · 4 lines
Tom -- Tom
cover Support for HTKW mcx board
Hi Tom,
I've just posted the updated patches, please consider merging them. ( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/116535 )
Quoted 3 lines · Tom Rini
Quoted 3 lines
Quoted 3 lines
I'm not sure what we should do about this series right now. Aside from some "easily" fixable things like all of the PHY files needing an ugly #include "
../../../../../drivers/net/davinci_emac.h" to compile
I've fixed PHY files to include this.
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
again and a
CONFIG_SYS_CACHELINE_SIZE32 in all of the platforms, thes/CONFIG_SYS_CACHELINE_SIZE/ARCH_DMA_MINALIGN/ should solve this
problem. I'll fix this.
Thanks.
Fixed.
Quoted 9 lines
Quoted 4 lines
Quoted 2 lines
lack of flush functions means that MAKEALL -s davinci fails for almost every board now. I'm not sure what we should do, at this point...
Argh.. Actually my initial version had a workaround for this, only
using {flush,invalidate}_dcache_range under #ifdef
DAVINCI_EMAC_DCACHEclause... But Mike told me that I should remove this...Quoted 2 lines
Maybe we can just add empty functions for
CONFIG_DCACHE_OFFcase tofix the compilation?
Added no-op cache functions for arm926ejs. However many DaVinci boards are still broken as suprisingly they have D-Cache enabled (I wonder if EMAC works on these boards).
Regards, Ilya.
cover Support for HTKW mcx board
Quoted 28 lines · Ilya Yanok
Hi Tom,
I've just posted the updated patches, please consider merging them. ( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/116535 )
Quoted 3 lines · Tom Rini
Quoted 3 lines
Quoted 3 lines
I'm not sure what we should do about this series right now. ?Aside from some "easily" fixable things like all of the PHY files needing an ugly #include "
../../../../../drivers/net/davinci_emac.h" to compileI've fixed PHY files to include this.
Quoted 6 lines
Quoted 3 lines
Quoted 1 line
again and a
CONFIG_SYS_CACHELINE_SIZE32 in all of the platforms, thes/CONFIG_SYS_CACHELINE_SIZE/ARCH_DMA_MINALIGN/ should solve this
problem. I'll fix this.
Thanks.
Fixed.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
lack of flush functions means that MAKEALL -s davinci fails for almost every board now. ?I'm not sure what we should do, at this point...
Argh.. Actually my initial version had a workaround for this, only
using {flush,invalidate}_dcache_range under #ifdef
DAVINCI_EMAC_DCACHEclause... But Mike told me that I should remove this...Quoted 1 line
Quoted 6 lines
Quoted 2 lines
Quoted 1 line
Maybe we can just add empty functions for
CONFIG_DCACHE_OFFcase tofix the compilation?
Added no-op cache functions for arm926ejs. However many DaVinci boards are still broken as suprisingly they have D-Cache enabled (I wonder if EMAC works on these boards).
Given how quick builds are now, what's MAKEALL -s davinci look like, before/after? Or did you mean EMAC functions not just builds? That's another question which I've had a few conversations with people about (and I've got a TODO list item to poke the kernel about how it does cache flushing/etc here, but it also probably relies on page stuff we don't do..). Thanks!
Signature · 1 line
Tom
cover Support for HTKW mcx board
Hi Tom,
Quoted 5 lines · Tom Rini
Quoted 3 lines
Added no-op cache functions for arm926ejs. However many DaVinci boards are still broken as suprisingly they have D-Cache enabled (I wonder if EMAC works on these boards).
Given how quick builds are now, what's MAKEALL -s davinci look like, before/after? Or did you mean EMAC functions not just builds? That's
MAKEALL logs are attached. Things are significantly worse after merging the series. That's because of DaVinci boards using EMAC driver and D-Cache enabled (I think this comes from times when D-Cache was disabled by default on ARM9). With this
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/116671 patch applied the results are almost the same as with master branch (see after+patch.log).
Quoted 4 lines
another question which I've had a few conversations with people about (and I've got a TODO list item to poke the kernel about how it does cache flushing/etc here, but it also probably relies on page stuff we don't do..). Thanks!
Well, kernel uses coherent memory for descriptors and do dma_map/dma_unmap on buffers. We don't have coherent memory support in U-Boot so I just perform flush/invalidate for both descriptors and buffers.
Regards, Ilya.
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