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Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

PATCH New Marc Zyngier 8 participants 30 messages Nov 4, 2011 – Nov 7, 2011

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Marc Zyngier

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#0 lore raw

v3 cover Switch GIC users (and omap2plus) to CONFIG_MULTI_IRQ_HANDLER

In order to support multiple primary interrupt controllers in the same image, it is necessary to use the MULTI_IRQ_HANDLER config option.

This patch series makes a first step in that direction by:
- having the GIC code to provides a global handler,
- make GIC users to provide this handler from their machine descriptor.

A side effect of this is that it forces OMAP2/3 platforms to be converted too in order to preserve the MULTI_OMAP feature. This leads to a certain simplification of the interrupt handling for the OMAP2/3/4 platforms.

This series has been tested by myself on VE (A9, A5, A15), PB11MP, Panda, IGEPv2, Harmony and Origen, as well as on other platforms by people who tested it. Patches against next-20111104 plus my "ARM: gic:
allow GIC to support non-banked setups" patch.

author
#1 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback.

It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S.

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S.

Cc Eric Miao <[email protected]>
Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/kernel/entry-armv.S                      |    7 ++--
 arch/arm/mach-pxa/include/mach/entry-macro.S      |   36 ---------------------
 arch/arm/mach-shmobile/include/mach/entry-macro.S |    9 -----
 3 files changed, 3 insertions(+), 49 deletions(-)
arch/arm/kernel/entry-armv.S +3 -4
index 9ad50c4..bd49a6a 100644
@@ -36,12 +36,11 @@
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	ldr	r1, =handle_arch_irq
 	mov	r0, sp
-	ldr	r1, [r1]
 	adr	lr, BSYM(9997f)
-	teq	r1, #0
-	movne	pc, r1
-#endif
+	ldr	pc, [r1]
+#else
 	arch_irq_handler_default
+#endif
 9997:
 	.endm
arch/arm/mach-pxa/include/mach/entry-macro.S +0 -36
index a73bc86..260c0c1 100644
@@ -7,45 +7,9 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 		.macro	disable_fiq
 		.endm
 
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
-
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
-		mov	\tmp, \tmp, lsr #13
-		and	\tmp, \tmp, #0x7		@ Core G
-		cmp	\tmp, #1
-		bhi	1002f
-
-		@ Core Generation 1 (PXA25x)
-		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
-		add	\base, \base, #0x00d00000
-		ldr	\irqstat, [\base, #0]		@ ICIP
-		ldr	\irqnr, [\base, #4]		@ ICMR
-
-		ands	\irqnr, \irqstat, \irqnr
-		beq	1001f
-		rsb	\irqstat, \irqnr, #0
-		and	\irqstat, \irqstat, \irqnr
-		clz	\irqnr, \irqstat
-		rsb	\irqnr, \irqnr, #(31 + PXA_IRQ(0))
-		b	1001f
-1002:
-		@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
-		mrc	p6, 0, \irqstat, c5, c0, 0	@ ICHP
-		tst	\irqstat, #0x80000000
-		beq	1001f
-		bic	\irqstat, \irqstat, #0x80000000
-		mov	\irqnr, \irqstat, lsr #16
-		add	\irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
-		.endm
arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -9
index 8d4a416..2a57b29 100644
@@ -18,14 +18,5 @@
 	.macro  disable_fiq
 	.endm
 
-	.macro  get_irqnr_preamble, base, tmp
-	.endm
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-	.endm
-
-	.macro  test_for_ipi, irqnr, irqstat, base, tmp
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
Signature · 1 line
1.7.0.4
#2 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Quoted 9 lines · Marc Zyngier

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback.

It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S.

Quoted 7 lines

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S.

Cc Eric Miao <[email protected]>
Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>

I like the look of it.

Acked-by Nicolas Pitre <[email protected]>
Quoted 105 lines
---
 arch/arm/kernel/entry-armv.S                      |    7 ++--
 arch/arm/mach-pxa/include/mach/entry-macro.S      |   36 ---------------------
 arch/arm/mach-shmobile/include/mach/entry-macro.S |    9 -----
 3 files changed, 3 insertions(+), 49 deletions(-)
arch/arm/kernel/entry-armv.S +3 -4
index 9ad50c4..bd49a6a 100644
@@ -36,12 +36,11 @@
 #ifdef CONFIG_MULTI_IRQ_HANDLER
 	ldr	r1, =handle_arch_irq
 	mov	r0, sp
-	ldr	r1, [r1]
 	adr	lr, BSYM(9997f)
-	teq	r1, #0
-	movne	pc, r1
-#endif
+	ldr	pc, [r1]
+#else
 	arch_irq_handler_default
+#endif
 9997:
 	.endm
arch/arm/mach-pxa/include/mach/entry-macro.S +0 -36
index a73bc86..260c0c1 100644
@@ -7,45 +7,9 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <mach/irqs.h>
 
 		.macro	disable_fiq
 		.endm
 
-		.macro  get_irqnr_preamble, base, tmp
-		.endm
-
 		.macro  arch_ret_to_user, tmp1, tmp2
 		.endm
-
-		.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-		mrc	p15, 0, \tmp, c0, c0, 0		@ CPUID
-		mov	\tmp, \tmp, lsr #13
-		and	\tmp, \tmp, #0x7		@ Core G
-		cmp	\tmp, #1
-		bhi	1002f
-
-		@ Core Generation 1 (PXA25x)
-		mov	\base, #io_p2v(0x40000000)	@ IIR Ctl = 0x40d00000
-		add	\base, \base, #0x00d00000
-		ldr	\irqstat, [\base, #0]		@ ICIP
-		ldr	\irqnr, [\base, #4]		@ ICMR
-
-		ands	\irqnr, \irqstat, \irqnr
-		beq	1001f
-		rsb	\irqstat, \irqnr, #0
-		and	\irqstat, \irqstat, \irqnr
-		clz	\irqnr, \irqstat
-		rsb	\irqnr, \irqnr, #(31 + PXA_IRQ(0))
-		b	1001f
-1002:
-		@ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
-		mrc	p6, 0, \irqstat, c5, c0, 0	@ ICHP
-		tst	\irqstat, #0x80000000
-		beq	1001f
-		bic	\irqstat, \irqstat, #0x80000000
-		mov	\irqnr, \irqstat, lsr #16
-		add	\irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
-		.endm
arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -9
index 8d4a416..2a57b29 100644
@@ -18,14 +18,5 @@
 	.macro  disable_fiq
 	.endm
 
-	.macro  get_irqnr_preamble, base, tmp
-	.endm
-
-	.macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-	.endm
-
-	.macro  test_for_ipi, irqnr, irqstat, base, tmp
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
Signature · 8 lines
1.7.0.4



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linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
#3 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

In reply to Marc Zyngier
Quoted 9 lines · Marc Zyngier

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback.

It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S.

Quoted 7 lines

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S.

Cc Eric Miao <[email protected]>
Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
Acked-by Eric Miao <[email protected]>
Quoted 100 lines

---

?arch/arm/kernel/entry-armv.S ? ? ? ? ? ? ? ? ? ? ?| ? ?7 ++--
?arch/arm/mach-pxa/include/mach/entry-macro.S ? ? ?| ? 36 ---------------------
?arch/arm/mach-shmobile/include/mach/entry-macro.S | ? ?9 -----

?3 files changed, 3 insertions(+), 49 deletions(-)

arch/arm/kernel/entry-armv.S +0 -0
index 9ad50c4..bd49a6a 100644
@@ -36,12 +36,11 @@

?#ifdef CONFIG_MULTI_IRQ_HANDLER
? ? ? ?ldr ? ? r1, =handle_arch_irq
? ? ? ?mov ? ? r0, sp
- ? ? ? ldr ? ? r1, [r1]
? ? ? ?adr ? ? lr, BSYM(9997f)
- ? ? ? teq ? ? r1, #0
- ? ? ? movne ? pc, r1

arch/arm/kernel/entry-armv.S +2 -1
-#endif
+ ? ? ? ldr ? ? pc, [r1]
+#else

? ? ? ?arch_irq_handler_default
+#endif
?9997:
? ? ? ?.endm

arch/arm/mach-pxa/include/mach/entry-macro.S +0 -0
index a73bc86..260c0c1 100644
@@ -7,45 +7,9 @@

?* License version 2. This program is licensed "as is" without any ?* warranty of any kind, whether express or implied. ?*/

arch/arm/mach-pxa/include/mach/entry-macro.S +0 -2
-#include <mach/hardware.h>
-#include <mach/irqs.h>

? ? ? ? ? ? ? ?.macro ?disable_fiq
? ? ? ? ? ? ? ?.endm

- ? ? ? ? ? ? ? .macro ?get_irqnr_preamble, base, tmp
- ? ? ? ? ? ? ? .endm
-
? ? ? ? ? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2 ? ? ? ? ? ? ? ?.endm

arch/arm/mach-pxa/include/mach/entry-macro.S +0 -31
-
- ? ? ? ? ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
- ? ? ? ? ? ? ? mrc ? ? p15, 0, \tmp, c0, c0, 0 ? ? ? ? @ CPUID
- ? ? ? ? ? ? ? mov ? ? \tmp, \tmp, lsr #13
- ? ? ? ? ? ? ? and ? ? \tmp, \tmp, #0x7 ? ? ? ? ? ? ? ?@ Core G
- ? ? ? ? ? ? ? cmp ? ? \tmp, #1
- ? ? ? ? ? ? ? bhi ? ? 1002f
-
- ? ? ? ? ? ? ? @ Core Generation 1 (PXA25x)
- ? ? ? ? ? ? ? mov ? ? \base, #io_p2v(0x40000000) ? ? ?@ IIR Ctl = 0x40d00000
- ? ? ? ? ? ? ? add ? ? \base, \base, #0x00d00000
- ? ? ? ? ? ? ? ldr ? ? \irqstat, [\base, #0] ? ? ? ? ? @ ICIP
- ? ? ? ? ? ? ? ldr ? ? \irqnr, [\base, #4] ? ? ? ? ? ? @ ICMR
-
- ? ? ? ? ? ? ? ands ? ?\irqnr, \irqstat, \irqnr
- ? ? ? ? ? ? ? beq ? ? 1001f
- ? ? ? ? ? ? ? rsb ? ? \irqstat, \irqnr, #0
- ? ? ? ? ? ? ? and ? ? \irqstat, \irqstat, \irqnr
- ? ? ? ? ? ? ? clz ? ? \irqnr, \irqstat
- ? ? ? ? ? ? ? rsb ? ? \irqnr, \irqnr, #(31 + PXA_IRQ(0))
- ? ? ? ? ? ? ? b ? ? ? 1001f
-1002:
- ? ? ? ? ? ? ? @ Core Generation 2 (PXA27x) or Core Generation 3 (PXA3xx)
- ? ? ? ? ? ? ? mrc ? ? p6, 0, \irqstat, c5, c0, 0 ? ? ?@ ICHP
- ? ? ? ? ? ? ? tst ? ? \irqstat, #0x80000000
- ? ? ? ? ? ? ? beq ? ? 1001f
- ? ? ? ? ? ? ? bic ? ? \irqstat, \irqstat, #0x80000000
- ? ? ? ? ? ? ? mov ? ? \irqnr, \irqstat, lsr #16
- ? ? ? ? ? ? ? add ? ? \irqnr, \irqnr, #(PXA_IRQ(0))
-1001:
- ? ? ? ? ? ? ? .endm
arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -0
index 8d4a416..2a57b29 100644
@@ -18,14 +18,5 @@

? ? ? ?.macro ?disable_fiq
? ? ? ?.endm

- ? ? ? .macro ?get_irqnr_preamble, base, tmp
- ? ? ? .endm

arch/arm/mach-shmobile/include/mach/entry-macro.S +0 -7
-
- ? ? ? .macro ?get_irqnr_and_base, irqnr, irqstat, base, tmp
- ? ? ? .endm
-
- ? ? ? .macro ?test_for_ipi, irqnr, irqstat, base, tmp
- ? ? ? .endm
-

? ? ? ?.macro ?arch_ret_to_user, tmp1, tmp2
? ? ? ?.endm
--
1.7.0.4

#4 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

In reply to Marc Zyngier

Hi Marc,

Quoted 9 lines · Marc Zyngier

Even when CONFIG_MULTI_IRQ_HANDLER is selected, the core code requires the arch_irq_handler_default macro to be defined as a fallback.

It turns out nobody is using that particular feature as both PXA and shmobile have all their machine descriptors populated with the interrupt handler, leaving unused code (or empty macros) in their entry-macro.S file just to be able to compile entry-armv.S.

Quoted 7 lines

Make CONFIG_MULTI_IRQ_HANDLER exclusive wrt arch_irq_handler_default, which allows to remove one test from the hot path. Also cleanup both PXA and shmobile entry-macro.S.

Cc Eric Miao <[email protected]>
Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
Tested-by Jamie Iles <[email protected]>

My VIC patches are using this so if it goes in through the GIC patches first then that would be great!

Thanks,

Jamie

#5 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Quoted 2 lines · Jamie Iles

My VIC patches are using this so if it goes in through the GIC patches first then that would be great!

That sounds like you should create some common irqchip-consolidation topic branch in ARM SoC or Russell's tree to get this properly stacked up?

Linus Walleij

author
#6 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Quoted 7 lines · Linus Walleij
Quoted 2 lines · Jamie Iles

My VIC patches are using this so if it goes in through the GIC patches first then that would be great!

That sounds like you should create some common irqchip-consolidation topic branch in ARM SoC or Russell's tree to get this properly stacked up?

Sounds like a good idea to me. I'm willing to gather such patches if nobody else steps up.

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
#7 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Quoted 11 lines · Marc Zyngier
Quoted 7 lines · Linus Walleij
Quoted 2 lines · Jamie Iles

My VIC patches are using this so if it goes in through the GIC patches first then that would be great!

That sounds like you should create some common irqchip-consolidation topic branch in ARM SoC or Russell's tree to get this properly stacked up?

Sounds like a good idea to me. I'm willing to gather such patches if nobody else steps up.

Great, thanks Marc! I'm happy to rebase my branch onto any point so you can easily pull if that makes things easier.

Thanks,

Jamie

author
#8 lore raw

PATCH v3 1/17 ARM: Make global handler and CONFIG_MULTI_IRQ_HANDLER mutually exclusive

Quoted 7 lines · Jamie Iles
Quoted 6 lines · Marc Zyngier
Quoted 5 lines · Linus Walleij
Quoted 2 lines · Jamie Iles

My VIC patches are using this so if it goes in through the GIC patches first then that would be great!

Quoted 8 lines
Quoted 5 lines
Quoted 2 lines

That sounds like you should create some common irqchip-consolidation topic branch in ARM SoC or Russell's tree to get this properly stacked up?

Sounds like a good idea to me. I'm willing to gather such patches if nobody else steps up.

Great, thanks Marc! I'm happy to rebase my branch onto any point so you can easily pull if that makes things easier.

Thanks Jamie. I'll create a branch based on -rc1 as soon as it is tagged (shouldn't be long now).

Cheers,

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
author
#9 lore raw

PATCH v3 2/17 ARM: mxc: rename gic_handle_irq to avoid name clash

In reply to Marc Zyngier

Before introducing a global gic_handle_irq(), rename MXC's version to mcx_gic_handle_irq(). This function will be removed altogether in a later patch.

Cc Shawn Guo <[email protected]>
Cc Sascha Hauer <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/plat-mxc/gic.c                 |    2 +-
 arch/arm/plat-mxc/include/mach/common.h |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/plat-mxc/gic.c +1 -1
index 12f8f81..ea51ea4 100644
@@ -18,7 +18,7 @@
 #include <asm/smp.h>
 #endif
 
-asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry mxc_gic_handle_irq(struct pt_regs *regs)
 {
 	u32 irqstat, irqnr;
arch/arm/plat-mxc/include/mach/common.h +2 -2
index 83b745a..f6c13ab 100644
@@ -90,7 +90,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
-void gic_handle_irq(struct pt_regs *);
+void mxc_gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq

@@ -101,7 +101,7 @@ void gic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq gic_handle_irq
+#define imx6q_handle_irq mcx_gic_handle_irq
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
Signature · 1 line
1.7.0.4
#10 lore raw

PATCH v3 2/17 ARM: mxc: rename gic_handle_irq to avoid name clash

Hi Marc,

Thanks for the patch. Minor comment below.

Quoted 2 lines · Marc Zyngier

Before introducing a global gic_handle_irq(), rename MXC's version to mcx_gic_handle_irq(). This function will be

s/mcx_gic_handle_irq/mxc_gic_handle_irq

Quoted 37 lines

removed altogether in a later patch.

Cc Shawn Guo <[email protected]>
Cc Sascha Hauer <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/plat-mxc/gic.c                 |    2 +-
 arch/arm/plat-mxc/include/mach/common.h |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/plat-mxc/gic.c +1 -1
index 12f8f81..ea51ea4 100644
@@ -18,7 +18,7 @@
 #include <asm/smp.h>
 #endif
 
-asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+asmlinkage void __exception_irq_entry mxc_gic_handle_irq(struct pt_regs *regs)
 {
 	u32 irqstat, irqnr;
arch/arm/plat-mxc/include/mach/common.h +1 -1
index 83b745a..f6c13ab 100644
@@ -90,7 +90,7 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
-void gic_handle_irq(struct pt_regs *);
+void mxc_gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq

arch/arm/plat-mxc/include/mach/common.h void gic_handle_irq(struct pt_regs *); · line 105

Quoted 6 lines
arch/arm/plat-mxc/include/mach/common.h +1 -1
@@ -101,7 +101,7 @@ void gic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq gic_handle_irq
+#define imx6q_handle_irq mcx_gic_handle_irq

s/mcx_gic_handle_irq/mxc_gic_handle_irq

Regards,
Shawn

Quoted 4 lines
arch/arm/plat-mxc/include/mach/common.h +0 -0
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
Signature · 1 line
1.7.0.4
author
#11 lore raw

PATCH v3 3/17 ARM: GIC: Add global gic_handle_irq() function

In reply to Marc Zyngier

Provide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/common/gic.c               |   27 +++++++++++++++++++++++++++
 arch/arm/include/asm/hardware/gic.h |    1 +
 2 files changed, 28 insertions(+), 0 deletions(-)
arch/arm/common/gic.c +27 -0
index 1565fca..2d29d86 100644
@@ -40,6 +40,7 @@
 #include <linux/slab.h>
 
 #include <asm/irq.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 #include <asm/hardware/gic.h>
 

@@ -242,6 +243,32 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
 #define gic_set_wake	NULL
 #endif
 
+asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
+{
+	u32 irqstat, irqnr;
+	struct gic_chip_data *gic = &gic_data[0];
+	void __iomem *cpu_base = gic_data_cpu_base(gic);
+
+	do {
+		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
+		irqnr = irqstat & ~0x1c00;
+
+		if (likely(irqnr > 15 && irqnr < 1021)) {
+			irqnr = irq_domain_to_irq(&gic->domain, irqnr);
+			handle_IRQ(irqnr, regs);
+			continue;
+		}
+		if (irqnr < 16) {
+			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
+#ifdef CONFIG_SMP
+			handle_IPI(irqnr, regs);
+#endif
+			continue;
+		}
+		break;
+	} while (1);
+}
+
 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 {
 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
arch/arm/include/asm/hardware/gic.h +1 -0
index 729e00b..a38eee2 100644
@@ -42,6 +42,7 @@ extern struct irq_chip gic_arch_extn;
 void gic_init(unsigned int, int, void __iomem *, void __iomem *);
 int gic_of_init(struct device_node *node, struct device_node *parent);
 void gic_secondary_init_base(unsigned int, void __iomem *, void __iomem *);
+void gic_handle_irq(struct pt_regs *regs);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
Signature · 1 line
1.7.0.4
author
#12 lore raw

PATCH v3 4/17 ARM: mxc: convert smp platforms to global gic_handle_irq()

In reply to Marc Zyngier

Convert the SMP shmobile platforms to use the global gic_handle_irq() function instead a private function.

Cc Shawn Guo <[email protected]>
Cc Sascha Hauer <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/plat-mxc/Makefile                   |    1 -
 arch/arm/plat-mxc/gic.c                      |   41 --------------------------
 arch/arm/plat-mxc/include/mach/common.h      |    3 +-
 arch/arm/plat-mxc/include/mach/entry-macro.S |   14 ---------
 4 files changed, 1 insertions(+), 58 deletions(-)
 delete mode 100644 arch/arm/plat-mxc/gic.c
arch/arm/plat-mxc/Makefile +0 -1
index b9f0f5f..076db84 100644
@@ -5,7 +5,6 @@
 # Common support
 obj-y := clock.o time.o devices.o cpu.o system.o irq-common.o
 
-obj-$(CONFIG_ARM_GIC) += gic.o
 obj-$(CONFIG_MXC_TZIC) += tzic.o
 obj-$(CONFIG_MXC_AVIC) += avic.o
arch/arm/plat-mxc/gic.c deleted +0 -41

41 lines not on this page · raw message

arch/arm/plat-mxc/include/mach/common.h +1 -2
index f6c13ab..14b4703 100644
@@ -90,7 +90,6 @@ extern void imx_print_silicon_rev(const char *cpu, int srev);
 
 void avic_handle_irq(struct pt_regs *);
 void tzic_handle_irq(struct pt_regs *);
-void mxc_gic_handle_irq(struct pt_regs *);
 
 #define imx1_handle_irq avic_handle_irq
 #define imx21_handle_irq avic_handle_irq

@@ -101,7 +100,7 @@ void mxc_gic_handle_irq(struct pt_regs *);
 #define imx50_handle_irq tzic_handle_irq
 #define imx51_handle_irq tzic_handle_irq
 #define imx53_handle_irq tzic_handle_irq
-#define imx6q_handle_irq mcx_gic_handle_irq
+#define imx6q_handle_irq gic_handle_irq
 
 extern void imx_enable_cpu(int cpu, bool enable);
 extern void imx_set_cpu_jump(int cpu, void *jump_addr);
arch/arm/plat-mxc/include/mach/entry-macro.S +0 -14
index 9fe0dfc..def5d30 100644
@@ -9,22 +9,8 @@
  * published by the Free Software Foundation.
  */
 
-/* Unused, we use CONFIG_MULTI_IRQ_HANDLER */
-
 	.macro	disable_fiq
 	.endm
 
-	.macro  get_irqnr_preamble, base, tmp
-	.endm
-
 	.macro  arch_ret_to_user, tmp1, tmp2
 	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	.endm
-
-	.macro test_for_ipi, irqnr, irqstat, base, tmp
-	.endm
-
-	.macro test_for_ltirq, irqnr, irqstat, base, tmp
-	.endm
Signature · 1 line
1.7.0.4
author
#14 lore raw

PATCH v3 4/17 ARM: mxc: convert smp platforms to global gic_handle_irq()

Quoted 10 lines · Shawn Guo
Quoted 1 line · Marc Zyngier

Convert the SMP shmobile platforms to use the global gic_handle_irq()

s/shmobile/imx

Other than the typo there, for patches #2 and #4:

Acked-by Shawn Guo <[email protected]>
Quoted 1 line

function instead a private function.

Can't believe I made that many typo in so few patches... ;-) Thanks for reviewing!

	M.
Signature · 1 line
Jazz is not dead. It just smells funny...
author
#15 lore raw

PATCH v3 5/17 ARM: highbank: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the highbank platform to be using the gic_handle_irq function as its primary interrupt handler.

Cc Rob Herring <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-highbank/highbank.c                 |    1 +
 arch/arm/mach-highbank/include/mach/entry-macro.S |    2 --
 3 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index c4f13c3..503daf0 100644
@@ -345,6 +345,7 @@ config ARCH_HIGHBANK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
 	select USE_OF
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for the Calxeda Highbank SoC based boards.
arch/arm/mach-highbank/highbank.c +1 -0
index b82dcf0..89bdf00 100644
@@ -140,6 +140,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
 	.map_io		= highbank_map_io,
 	.init_irq	= highbank_init_irq,
 	.timer		= &highbank_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= highbank_init,
 	.dt_compat	= highbank_match,
 MACHINE_END
arch/arm/mach-highbank/include/mach/entry-macro.S +0 -2
index 73c1129..a14f9e6 100644
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
 	.macro	disable_fiq
 	.endm
Signature · 1 line
1.7.0.4
#16 lore raw

PATCH v3 5/17 ARM: highbank: convert to CONFIG_MULTI_IRQ_HANDLER

Quoted 5 lines · Marc Zyngier

Convert the highbank platform to be using the gic_handle_irq function as its primary interrupt handler.

Cc Rob Herring <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
Acked-by Rob Herring <[email protected]>

Rob

Quoted 40 lines
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-highbank/highbank.c                 |    1 +
 arch/arm/mach-highbank/include/mach/entry-macro.S |    2 --
 3 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index c4f13c3..503daf0 100644
@@ -345,6 +345,7 @@ config ARCH_HIGHBANK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
 	select USE_OF
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for the Calxeda Highbank SoC based boards.
arch/arm/mach-highbank/highbank.c +1 -0
index b82dcf0..89bdf00 100644
@@ -140,6 +140,7 @@ DT_MACHINE_START(HIGHBANK, "Highbank")
 	.map_io		= highbank_map_io,
 	.init_irq	= highbank_init_irq,
 	.timer		= &highbank_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= highbank_init,
 	.dt_compat	= highbank_match,
 MACHINE_END
arch/arm/mach-highbank/include/mach/entry-macro.S +0 -2
index 73c1129..a14f9e6 100644
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
 	.macro	disable_fiq
 	.endm
author
#17 lore raw

PATCH v3 6/17 ARM: RealView: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the RealView platforms to be using the gic_handle_irq function as their primary interrupt handler.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-realview/include/mach/entry-macro.S |    2 --
 arch/arm/mach-realview/realview_eb.c              |    1 +
 arch/arm/mach-realview/realview_pb1176.c          |    1 +
 arch/arm/mach-realview/realview_pb11mp.c          |    1 +
 arch/arm/mach-realview/realview_pba8.c            |    1 +
 arch/arm/mach-realview/realview_pbx.c             |    1 +
 7 files changed, 6 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index 503daf0..918d466 100644
@@ -278,6 +278,7 @@ config ARCH_REALVIEW
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
 	select NEED_MACH_MEMORY_H
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for ARM Ltd RealView boards.
arch/arm/mach-realview/include/mach/entry-macro.S +0 -2
index 4071164..e8a5179 100644
@@ -7,8 +7,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
arch/arm/mach-realview/realview_eb.c +1 -0
index 427e44e..f01e332 100644
@@ -470,6 +470,7 @@ MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_eb_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_eb_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pb1176.c +1 -0
index ad227c4..d329b37 100644
@@ -393,6 +393,7 @@ MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb1176_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb1176_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pb11mp.c +1 -0
index 6cb8318..32d18e5 100644
@@ -367,6 +367,7 @@ MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pb11mp_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pb11mp_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pba8.c +1 -0
index 3db72c5..0896cc4 100644
@@ -317,6 +317,7 @@ MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pba8_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pba8_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
arch/arm/mach-realview/realview_pbx.c +1 -0
index bea4212..cac0b69 100644
@@ -400,6 +400,7 @@ MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
 	.init_early	= realview_init_early,
 	.init_irq	= gic_init_irq,
 	.timer		= &realview_pbx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= realview_pbx_init,
 #ifdef CONFIG_ZONE_DMA
 	.dma_zone_size	= SZ_256M,
Signature · 1 line
1.7.0.4
author
#18 lore raw

PATCH v3 7/17 ARM: VExpress: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the VExpress platform to be using the gic_handle_irq function as its primary interrupt handler.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                  |    1 +
 arch/arm/mach-vexpress/include/mach/entry-macro.S |    2 --
 arch/arm/mach-vexpress/v2m.c                      |    2 ++
 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index 918d466..af6e59d 100644
@@ -311,6 +311,7 @@ config ARCH_VEXPRESS
 	select ICST
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLCD
+	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
arch/arm/mach-vexpress/include/mach/entry-macro.S +0 -2
index 73c1129..a14f9e6 100644
@@ -1,5 +1,3 @@
-#include <asm/hardware/entry-macro-gic.S>
-
 	.macro	disable_fiq
 	.endm
arch/arm/mach-vexpress/v2m.c +2 -0
index 47bca2a..d540a1b 100644
@@ -24,6 +24,7 @@
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/sp810.h>
+#include <asm/hardware/gic.h>
 
 #include <mach/ct-ca9x4.h>
 #include <mach/motherboard.h>

@@ -457,5 +458,6 @@ MACHINE_START(VEXPRESS, "ARM-Versatile Express")
 	.init_early	= v2m_init_early,
 	.init_irq	= v2m_init_irq,
 	.timer		= &v2m_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= v2m_init,
 MACHINE_END
Signature · 1 line
1.7.0.4
author
#19 lore raw

PATCH v3 8/17 ARM: msm: convert SMP platforms to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the SMP msm platforms to be using the gic_handle_irq function as their primary interrupt handler.

Tested-by David Brown <[email protected]>
Acked-by David Brown <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-msm/Kconfig                         |    2 +
 arch/arm/mach-msm/board-msm8960.c                 |    2 +
 arch/arm/mach-msm/board-msm8x60.c                 |    4 ++
 arch/arm/mach-msm/include/mach/entry-macro-qgic.S |   17 ---------
 arch/arm/mach-msm/include/mach/entry-macro-vic.S  |   37 ---------------------
 arch/arm/mach-msm/include/mach/entry-macro.S      |   27 +++++++++++++--
 6 files changed, 31 insertions(+), 58 deletions(-)
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-qgic.S
 delete mode 100644 arch/arm/mach-msm/include/mach/entry-macro-vic.S
arch/arm/mach-msm/Kconfig +2 -0
index ebde97f..ba36b74 100644
@@ -50,6 +50,7 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"

@@ -60,6 +61,7 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
+	select MULTI_IRQ_HANDLER
 
 endchoice
arch/arm/mach-msm/board-msm8960.c +2 -0
index c811e29..7af9a6d 100644
@@ -101,6 +101,7 @@ MACHINE_START(MSM8960_SIM, "QCT MSM8960 SIMULATOR")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_sim_init,
 MACHINE_END
 

@@ -111,6 +112,7 @@ MACHINE_START(MSM8960_RUMI3, "QCT MSM8960 RUMI3")
 	.map_io = msm8960_map_io,
 	.init_irq = msm8960_init_irq,
 	.timer = &msm_timer,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8960_rumi3_init,
 MACHINE_END
arch/arm/mach-msm/board-msm8x60.c +4 -0
index fdc8a34..bf5b04d 100644
@@ -111,6 +111,7 @@ MACHINE_START(MSM8X60_RUMI3, "QCT MSM8X60 RUMI3")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -121,6 +122,7 @@ MACHINE_START(MSM8X60_SURF, "QCT MSM8X60 SURF")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -131,6 +133,7 @@ MACHINE_START(MSM8X60_SIM, "QCT MSM8X60 SIMULATOR")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END

@@ -141,6 +144,7 @@ MACHINE_START(MSM8X60_FFA, "QCT MSM8X60 FFA")
 	.reserve = msm8x60_reserve,
 	.map_io = msm8x60_map_io,
 	.init_irq = msm8x60_init_irq,
+	.handle_irq = gic_handle_irq,
 	.init_machine = msm8x60_init,
 	.timer = &msm_timer,
 MACHINE_END
arch/arm/mach-msm/include/mach/entry-macro-qgic.S deleted +0 -17
deleted file mode 100644
index 717076f..0000000
@@ -1,17 +0,0 @@
-/*
- * Low-level IRQ helper macros
- *
- * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/hardware/entry-macro-gic.S>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
arch/arm/mach-msm/include/mach/entry-macro-vic.S deleted +0 -37
deleted file mode 100644
index 70563ed..0000000
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <[email protected]>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <mach/msm_iomap.h>
-
-	.macro	disable_fiq
-	.endm
-
-	.macro	get_irqnr_preamble, base, tmp
-	@ enable imprecise aborts
-	cpsie	a
-	mov	\base, #MSM_VIC_BASE
-	.endm
-
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
-	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
-	@ 0xD0 has irq# or old irq# if the irq has been handled
-	@ 0xD4 has irq# or -1 if none pending *but* if you just
-	@ read 0xD4 you never get the first irq for some reason
-	ldr	\irqnr, [\base, #0xD0]
-	ldr	\irqnr, [\base, #0xD4]
-	cmp	\irqnr, #0xffffffff
-	.endm
arch/arm/mach-msm/include/mach/entry-macro.S +23 -4
index b16f082..41f7003 100644
@@ -16,8 +16,27 @@
  *
  */
 
-#if defined(CONFIG_ARM_GIC)
-#include <mach/entry-macro-qgic.S>
-#else
-#include <mach/entry-macro-vic.S>
+	.macro	disable_fiq
+	.endm
+
+	.macro	arch_ret_to_user, tmp1, tmp2
+	.endm
+
+#if !defined(CONFIG_ARM_GIC)
+#include <mach/msm_iomap.h>
+
+	.macro	get_irqnr_preamble, base, tmp
+	@ enable imprecise aborts
+	cpsie	a
+	mov	\base, #MSM_VIC_BASE
+	.endm
+
+	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
+	@ 0xD0 has irq# or old irq# if the irq has been handled
+	@ 0xD4 has irq# or -1 if none pending *but* if you just
+	@ read 0xD4 you never get the first irq for some reason
+	ldr	\irqnr, [\base, #0xD0]
+	ldr	\irqnr, [\base, #0xD4]
+	cmp	\irqnr, #0xffffffff
+	.endm
 #endif
Signature · 1 line
1.7.0.4
author
#20 lore raw

PATCH v3 9/17 ARM: exynos4: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the Exynos4 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Cc Ben Dooks <[email protected]>
Cc Kukjin Kim <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-exynos4/cpu.c                      |    1 +
 arch/arm/mach-exynos4/include/mach/entry-macro.S |   74 ----------------------
 arch/arm/mach-exynos4/mach-armlex4210.c          |    2 +
 arch/arm/mach-exynos4/mach-nuri.c                |    2 +
 arch/arm/mach-exynos4/mach-origen.c              |    2 +
 arch/arm/mach-exynos4/mach-smdk4x12.c            |    3 +
 arch/arm/mach-exynos4/mach-smdkv310.c            |    3 +
 arch/arm/mach-exynos4/mach-universal_c210.c      |    2 +
 9 files changed, 16 insertions(+), 74 deletions(-)
arch/arm/Kconfig +1 -0
index af6e59d..605e897 100644
@@ -855,6 +855,7 @@ config ARCH_EXYNOS4
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 	select NEED_MACH_MEMORY_H
+	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
arch/arm/mach-exynos4/cpu.c +1 -0
index b57b905..567a4c1 100644
@@ -17,6 +17,7 @@
 #include <asm/mach/irq.h>
 
 #include <asm/proc-fns.h>
+#include <asm/exception.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/hardware/gic.h>
arch/arm/mach-exynos4/include/mach/entry-macro.S +0 -74

82 lines not on this page · raw message

arch/arm/mach-exynos4/mach-armlex4210.c +2 -0
index 8c82c6b..2fdcc9d 100644
@@ -16,6 +16,7 @@
 #include <linux/smsc911x.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <plat/cpu.h>

@@ -213,6 +214,7 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= armlex4210_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= armlex4210_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-nuri.c +2 -0
index f6eb7a4..6fddafa 100644
@@ -32,6 +32,7 @@
 #include <media/v4l2-mediabus.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <plat/adc.h>

@@ -1336,6 +1337,7 @@ MACHINE_START(NURI, "NURI")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= nuri_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= nuri_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &nuri_reserve,
arch/arm/mach-exynos4/mach-origen.c +2 -0
index b643584..192bffd 100644
@@ -22,6 +22,7 @@
 #include <linux/lcd.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>

@@ -697,6 +698,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= origen_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= origen_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve	= &origen_reserve,
arch/arm/mach-exynos4/mach-smdk4x12.c +3 -0
index 052b2cb..9e7e8a2 100644
@@ -21,6 +21,7 @@
 #include <linux/serial_core.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <plat/backlight.h>

@@ -290,6 +291,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdk4x12_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= smdk4x12_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END

@@ -302,5 +304,6 @@ MACHINE_START(SMDK4412, "SMDK4412")
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdk4x12_map_io,
 	.init_machine	= smdk4x12_machine_init,
+	.handle_irq	= gic_handle_irq,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-smdkv310.c +3 -0
index 525b042..6b49dbe 100644
@@ -21,6 +21,7 @@
 #include <linux/pwm_backlight.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <video/platform_lcd.h>

@@ -378,6 +379,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdkv310_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= smdkv310_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve	= &smdkv310_reserve,

@@ -389,6 +391,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= smdkv310_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= smdkv310_machine_init,
 	.timer		= &exynos4_timer,
 MACHINE_END
arch/arm/mach-exynos4/mach-universal_c210.c +2 -0
index 1bdb4c2..4e50b13 100644
@@ -24,6 +24,7 @@
 #include <linux/i2c/atmel_mxt_ts.h>
 
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 
 #include <plat/regs-serial.h>

@@ -1061,6 +1062,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
 	.soc		= &exynos4_soc_desc,
 	.init_irq	= exynos4_init_irq,
 	.map_io		= universal_map_io,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= universal_machine_init,
 	.timer		= &exynos4_timer,
 	.reserve        = &universal_reserve,
Signature · 1 line
1.7.0.4
author
#21 lore raw

PATCH v3 10/17 ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Tested on harmony.

Cc Colin Cross <[email protected]>
Acked-by Stephen Warren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-tegra/Kconfig                    |    1 +
 arch/arm/mach-tegra/board-dt.c                 |    2 ++
 arch/arm/mach-tegra/board-harmony.c            |    2 ++
 arch/arm/mach-tegra/board-paz00.c              |    2 ++
 arch/arm/mach-tegra/board-seaboard.c           |    4 ++++
 arch/arm/mach-tegra/board-trimslice.c          |    2 ++
 arch/arm/mach-tegra/include/mach/entry-macro.S |   22 ++--------------------
 7 files changed, 15 insertions(+), 20 deletions(-)
arch/arm/mach-tegra/Kconfig +1 -0
index 91aff7c..a6faa50 100644
@@ -13,6 +13,7 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-tegra/board-dt.c +2 -0
index 580dd73..c001e96 100644
@@ -32,6 +32,7 @@
 #include <linux/i2c.h>
 #include <linux/i2c-tegra.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -131,6 +132,7 @@ DT_MACHINE_START(TEGRA_DT, "nVidia Tegra (Flattened Device Tree)")
 	.soc		= &tegra_soc_desc,
 	.init_early	= tegra_init_early,
 	.init_irq	= tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer		= &tegra_timer,
 	.init_machine	= tegra_dt_init,
 	.dt_compat	= tegra_dt_board_compat,
arch/arm/mach-tegra/board-harmony.c +2 -0
index f2ef94f..eb65d68 100644
@@ -31,6 +31,7 @@
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
+#include <asm/hardware/gic.h>
 #include <asm/setup.h>
 
 #include <mach/tegra_wm8903_pdata.h>

@@ -189,6 +190,7 @@ MACHINE_START(HARMONY, "harmony")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_harmony_init,
 MACHINE_END
arch/arm/mach-tegra/board-paz00.c +2 -0
index 8d1f7bf..bece14a 100644
@@ -29,6 +29,7 @@
 #include <linux/gpio.h>
 #include <linux/rfkill-gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>

@@ -192,6 +193,7 @@ MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_paz00_init,
 MACHINE_END
arch/arm/mach-tegra/board-seaboard.c +4 -0
index dfd9c95..7fd71cf 100644
@@ -34,6 +34,7 @@
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include "board.h"
 #include "board-seaboard.h"

@@ -286,6 +287,7 @@ MACHINE_START(SEABOARD, "seaboard")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_seaboard_init,
 MACHINE_END

@@ -296,6 +298,7 @@ MACHINE_START(KAEN, "kaen")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_kaen_init,
 MACHINE_END

@@ -306,6 +309,7 @@ MACHINE_START(WARIO, "wario")
 	.map_io         = tegra_map_common_io,
 	.init_early     = tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_wario_init,
 MACHINE_END
arch/arm/mach-tegra/board-trimslice.c +2 -0
index 3e76f4a..74c4dea 100644
@@ -26,6 +26,7 @@
 #include <linux/i2c.h>
 #include <linux/gpio.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/setup.h>

@@ -178,6 +179,7 @@ MACHINE_START(TRIMSLICE, "trimslice")
 	.map_io         = tegra_map_common_io,
 	.init_early	= tegra_init_early,
 	.init_irq       = tegra_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.timer          = &tegra_timer,
 	.init_machine   = tegra_trimslice_init,
 MACHINE_END
arch/arm/mach-tegra/include/mach/entry-macro.S +2 -20
index dd165c5..ac11262 100644
@@ -12,30 +12,15 @@
  * GNU General Public License for more details.
  *
  */
-#include <mach/iomap.h>
-#include <mach/io.h>
-
-#if defined(CONFIG_ARM_GIC)
-#define HAVE_GET_IRQNR_PREAMBLE
-#include <asm/hardware/entry-macro-gic.S>
-
-	/* Uses the GIC interrupt controller built into the cpu */
-#define ICTRL_BASE (IO_CPU_VIRT + 0x100)
 
 	.macro	disable_fiq
 	.endm
 
-	.macro	get_irqnr_preamble, base, tmp
-	movw \base, #(ICTRL_BASE & 0x0000ffff)
-	movt \base, #((ICTRL_BASE & 0xffff0000) >> 16)
+	.macro	arch_ret_to_user, tmp1, tmp2
 	.endm
 
-	.macro  arch_ret_to_user, tmp1, tmp2
-	.endm
-#else
+#if !defined(CONFIG_ARM_GIC)
 	/* legacy interrupt controller for AP16 */
-	.macro	disable_fiq
-	.endm
 
 	.macro	get_irqnr_preamble, base, tmp
 	@ enable imprecise aborts

@@ -46,9 +31,6 @@
 	orr \base, #0x0000f000
 	.endm
 
-	.macro	arch_ret_to_user, tmp1, tmp2
-	.endm
-
 	.macro	get_irqnr_and_base, irqnr, irqstat, base, tmp
 	ldr \irqnr, [\base, #0x20]	@ EVT_IRQ_STS
 	cmp \irqnr, #0x80
Signature · 1 line
1.7.0.4
#22 lore raw

PATCH v3 10/17 ARM: tegra2: convert to CONFIG_MULTI_IRQ_HANDLER

Quoted 8 lines · Marc Zyngier

Convert the tegra2 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Tested on harmony.

Cc Colin Cross <[email protected]>
Acked-by Stephen Warren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>

Hm, the series did require some manual touch up on top of last night's linux-next, mostly due to fuzz and some exynos changes. That being said, the tegra parts are still:

Acked-by Olof Johansson <[email protected]>

(I acked 0/x of the last patch set instead of the individual patch)

-Olof

author
#23 lore raw

PATCH v3 11/17 ARM: ux500: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the ux500 platforms to be using the gic_handle_irq function as their primary interrupt handler.

Acked-by Linus Walleij <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-ux500/Kconfig                    |    1 +
 arch/arm/mach-ux500/board-mop500.c             |    4 ++++
 arch/arm/mach-ux500/board-u5500.c              |    2 ++
 arch/arm/mach-ux500/include/mach/entry-macro.S |    2 --
 4 files changed, 7 insertions(+), 2 deletions(-)
arch/arm/mach-ux500/Kconfig +1 -0
index a3e0c86..bb2b52b 100644
@@ -7,6 +7,7 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
+	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
arch/arm/mach-ux500/board-mop500.c +4 -0
index f0b1a00..2539b0b 100644
@@ -33,6 +33,7 @@
 #include <linux/leds.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
+#include <asm/hardware/gic.h>
 
 #include <plat/i2c.h>
 #include <plat/ste_dma40.h>

@@ -696,6 +697,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= mop500_init_machine,
 MACHINE_END
 

@@ -705,6 +707,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
 	.map_io		= u8500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= hrefv60_init_machine,
 MACHINE_END
 

@@ -715,5 +718,6 @@ MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
 	.init_irq	= ux500_init_irq,
 	/* we re-use nomadik timer here */
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= snowball_init_machine,
 MACHINE_END
arch/arm/mach-ux500/board-u5500.c +2 -0
index aeb125a..2141658 100644
@@ -12,6 +12,7 @@
 #include <linux/i2c.h>
 #include <linux/mfd/ab5500/ab5500.h>
 
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
 

@@ -150,5 +151,6 @@ MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
 	.map_io		= u5500_map_io,
 	.init_irq	= ux500_init_irq,
 	.timer		= &ux500_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= u5500_init_machine,
 MACHINE_END
arch/arm/mach-ux500/include/mach/entry-macro.S +0 -2
index 071bba9..e16299e 100644
@@ -10,8 +10,6 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
 
 		.macro	disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
author
#24 lore raw

PATCH v3 12/17 ARM: shmobile: convert smp platforms to gic_handle_irq()

In reply to Marc Zyngier

Convert the SMP shmobile platforms to use gic_handle_irq() instead of the assembly macro.

Cc Paul Mundt <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-shmobile/Makefile              |    1 -
 arch/arm/mach-shmobile/board-ag5evm.c        |    2 +-
 arch/arm/mach-shmobile/entry-gic.S           |   18 ------------------
 arch/arm/mach-shmobile/include/mach/common.h |    1 -
 4 files changed, 1 insertions(+), 21 deletions(-)
 delete mode 100644 arch/arm/mach-shmobile/entry-gic.S
arch/arm/mach-shmobile/Makefile +0 -1
index 43754f3..38fdbf2 100644
@@ -28,7 +28,6 @@ pfc-$(CONFIG_ARCH_SH73A0)	+= pfc-sh73a0.o
 obj-$(CONFIG_ARCH_SH7367)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7377)	+= entry-intc.o
 obj-$(CONFIG_ARCH_SH7372)	+= entry-intc.o
-obj-$(CONFIG_ARCH_SH73A0)	+= entry-gic.o
 
 # PM objects
 obj-$(CONFIG_SUSPEND)		+= suspend.o
arch/arm/mach-shmobile/board-ag5evm.c +1 -1
index 448f51a..06483e4 100644
@@ -603,7 +603,7 @@ MACHINE_START(AG5EVM, "ag5evm")
 	.map_io		= ag5evm_map_io,
 	.soc		= &sh73a0_soc_desc,
 	.init_irq	= ag5evm_init_irq,
-	.handle_irq	= shmobile_handle_irq_gic,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= ag5evm_init,
 	.timer		= &ag5evm_timer,
 MACHINE_END
arch/arm/mach-shmobile/entry-gic.S deleted +0 -18
deleted file mode 100644
index e20239b..0000000
@@ -1,18 +0,0 @@
-/*
- * ARM Interrupt demux handler using GIC
- *
- * Copyright (C) 2010 Magnus Damm
- * Copyright (C) 2011 Paul Mundt
- * Copyright (C) 2010 - 2011 Renesas Solutions Corp.
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <asm/assembler.h>
-#include <asm/entry-macro-multi.S>
-#include <asm/hardware/gic.h>
-#include <asm/hardware/entry-macro-gic.S>
-
-	arch_irq_handler shmobile_handle_irq_gic
arch/arm/mach-shmobile/include/mach/common.h +0 -1
index 2283521..04856a3 100644
@@ -7,7 +7,6 @@ extern void shmobile_secondary_vector(void);
 struct clk;
 extern int clk_init(void);
 extern void shmobile_handle_irq_intc(struct pt_regs *);
-extern void shmobile_handle_irq_gic(struct pt_regs *);
 extern struct platform_suspend_ops shmobile_suspend_ops;
 struct cpuidle_device;
 extern void (*shmobile_cpuidle_modes[])(void);
Signature · 1 line
1.7.0.4
author
#25 lore raw

PATCH v3 13/17 ARM: cns3xxx: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the cns3xxx platform to be using the gic_handle_irq function as its primary interrupt handler.

Acked-by Anton Vorontsov <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                 |    1 +
 arch/arm/mach-cns3xxx/cns3420vb.c                |    2 ++
 arch/arm/mach-cns3xxx/include/mach/entry-macro.S |    2 --
 3 files changed, 3 insertions(+), 2 deletions(-)
arch/arm/Kconfig +1 -0
index 605e897..e38be77 100644
@@ -366,6 +366,7 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
arch/arm/mach-cns3xxx/cns3420vb.c +2 -0
index 55f7b4b..594852f 100644
@@ -26,6 +26,7 @@
 #include <linux/mtd/partitions.h>
 #include <asm/setup.h>
 #include <asm/mach-types.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>

@@ -201,5 +202,6 @@ MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
 	.map_io		= cns3420_map_io,
 	.init_irq	= cns3xxx_init_irq,
 	.timer		= &cns3xxx_timer,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= cns3420_init,
 MACHINE_END
arch/arm/mach-cns3xxx/include/mach/entry-macro.S +0 -2
index d87bfc3..01c57df 100644
@@ -8,8 +8,6 @@
  * published by the Free Software Foundation.
  */
 
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro	disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
author
#26 lore raw

PATCH v3 14/17 ARM: zynq: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the zynq platform to be using the gic_handle_irq function as its primary interrupt handler.

Acked-by John Linn <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                              |    1 +
 arch/arm/mach-zynq/common.c                   |    1 +
 arch/arm/mach-zynq/include/mach/entry-macro.S |    3 ---
 3 files changed, 2 insertions(+), 3 deletions(-)
arch/arm/Kconfig +1 -0
index e38be77..a3bcccc 100644
@@ -980,6 +980,7 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
+	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
arch/arm/mach-zynq/common.c +1 -0
index 73e9368..ab5cfdd 100644
@@ -112,6 +112,7 @@ static const char *xilinx_dt_match[] = {
 MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
 	.map_io		= xilinx_map_io,
 	.init_irq	= xilinx_irq_init,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= xilinx_init_machine,
 	.timer		= &xttcpss_sys_timer,
 	.dt_compat	= xilinx_dt_match,
arch/arm/mach-zynq/include/mach/entry-macro.S +0 -3
index 3cfc01b..d621fb7 100644
@@ -20,9 +20,6 @@
  * GNU General Public License for more details.
  */
 
-#include <mach/hardware.h>
-#include <asm/hardware/entry-macro-gic.S>
-
 		.macro  disable_fiq
 		.endm
Signature · 1 line
1.7.0.4
author
#27 lore raw

PATCH v3 15/17 ARM: omap2/3: Add global omap2/3_intc_handle_irq() functions

In reply to Marc Zyngier

Provide the OMAP2/3 IRQ code with low level handlers that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Though the handlers are written in C, the compiled code looks very similar to its assembly counterpart (at least with my gcc 4.4.1).

Tested-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-omap2/irq.c              |   50 ++++++++++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/irqs.h |    2 +
 2 files changed, 52 insertions(+), 0 deletions(-)
arch/arm/mach-omap2/irq.c +50 -0
index 65f1be6..ec52bee 100644
@@ -15,6 +15,7 @@
 #include <linux/interrupt.h>
 #include <linux/io.h>
 #include <mach/hardware.h>
+#include <asm/exception.h>
 #include <asm/mach/irq.h>
 
 

@@ -35,6 +36,11 @@
 /* Number of IRQ state bits in each MIR register */
 #define IRQ_BITS_PER_REG	32
 
+#define OMAP2_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE)
+#define OMAP3_IRQ_BASE		OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE)
+#define INTCPS_SIR_IRQ_OFFSET	0x0040	/* omap2/3 active interrupt offset */
+#define ACTIVEIRQ_MASK		0x7f	/* omap2/3 active interrupt bits */
+
 /*
  * OMAP2 has a number of different interrupt controllers, each interrupt
  * controller is identified as its own "bank". Register definitions are

@@ -191,6 +197,44 @@ void __init ti816x_init_irq(void)
 	omap_init_irq(OMAP34XX_IC_BASE, 128);
 }
 
+static inline void omap_intc_handle_irq(void __iomem *base_addr, struct pt_regs *regs)
+{
+	u32 irqnr;
+
+	do {
+		irqnr = readl_relaxed(base_addr + 0x98);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xb8);
+		if (irqnr)
+			goto out;
+
+		irqnr = readl_relaxed(base_addr + 0xd8);
+#ifdef CONFIG_SOC_OMAPTI816X
+		if (irqnr)
+			goto out;
+		irqnr = readl_relaxed(base_addr + 0xf8);
+#endif
+
+out:
+		if (!irqnr)
+			break;
+
+		irqnr = readl_relaxed(base_addr + INTCPS_SIR_IRQ_OFFSET);
+		irqnr &= ACTIVEIRQ_MASK;
+
+		if (irqnr)
+			handle_IRQ(irqnr, regs);
+	} while (irqnr);
+}
+
+asmlinkage void __exception_irq_entry omap2_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP2_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
+
 #ifdef CONFIG_ARCH_OMAP3
 static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
 

@@ -263,4 +307,10 @@ void omap3_intc_resume_idle(void)
 	/* Re-enable autoidle */
 	intc_bank_write_reg(1, &irq_banks[0], INTC_SYSCONFIG);
 }
+
+asmlinkage void __exception_irq_entry omap3_intc_handle_irq(struct pt_regs *regs)
+{
+	void __iomem *base_addr = OMAP3_IRQ_BASE;
+	omap_intc_handle_irq(base_addr, regs);
+}
 #endif /* CONFIG_ARCH_OMAP3 */
arch/arm/plat-omap/include/plat/irqs.h +2 -0
index 30e1071..8b19a63 100644
@@ -448,6 +448,8 @@ void omap_intc_restore_context(void);
 void omap3_intc_suspend(void);
 void omap3_intc_prepare_idle(void);
 void omap3_intc_resume_idle(void);
+void omap2_intc_handle_irq(struct pt_regs *regs);
+void omap3_intc_handle_irq(struct pt_regs *regs);
 #endif
 
 #include <mach/hardware.h>
Signature · 1 line
1.7.0.4
author
#28 lore raw

PATCH v3 16/17 ARM: omap2plus: convert to CONFIG_MULTI_IRQ_HANDLER

In reply to Marc Zyngier

Convert the omap2plus platforms to be using CONFIG_MULTI_IRQ_HANDLER. Each machine is modified to provide either omap2_intc_handle_irq(), omap3_intc_handle_irq() or gic_handle_irq().

This allows for a major cleanup, removing the MULTI_OMAP setup from the interrupt path.

Tested on both Panda and IGEPv2 (single kernel image)

Tested-by Tony Lindgren <[email protected]>
Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/mach-omap2/Kconfig                    |    1 +
 arch/arm/mach-omap2/board-2430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3430sdp.c            |    1 +
 arch/arm/mach-omap2/board-3630sdp.c            |    1 +
 arch/arm/mach-omap2/board-4430sdp.c            |    2 +
 arch/arm/mach-omap2/board-am3517crane.c        |    1 +
 arch/arm/mach-omap2/board-am3517evm.c          |    1 +
 arch/arm/mach-omap2/board-apollon.c            |    1 +
 arch/arm/mach-omap2/board-cm-t35.c             |    2 +
 arch/arm/mach-omap2/board-cm-t3517.c           |    1 +
 arch/arm/mach-omap2/board-devkit8000.c         |    1 +
 arch/arm/mach-omap2/board-generic.c            |    1 +
 arch/arm/mach-omap2/board-h4.c                 |    1 +
 arch/arm/mach-omap2/board-igep0020.c           |    2 +
 arch/arm/mach-omap2/board-ldp.c                |    1 +
 arch/arm/mach-omap2/board-n8x0.c               |    3 +
 arch/arm/mach-omap2/board-omap3beagle.c        |    1 +
 arch/arm/mach-omap2/board-omap3evm.c           |    1 +
 arch/arm/mach-omap2/board-omap3logic.c         |    2 +
 arch/arm/mach-omap2/board-omap3pandora.c       |    1 +
 arch/arm/mach-omap2/board-omap3stalker.c       |    1 +
 arch/arm/mach-omap2/board-omap3touchbook.c     |    1 +
 arch/arm/mach-omap2/board-omap4panda.c         |    2 +
 arch/arm/mach-omap2/board-overo.c              |    1 +
 arch/arm/mach-omap2/board-rm680.c              |    1 +
 arch/arm/mach-omap2/board-rx51.c               |    1 +
 arch/arm/mach-omap2/board-zoom.c               |    2 +
 arch/arm/mach-omap2/include/mach/entry-macro.S |  137 ------------------------
 arch/arm/plat-omap/Kconfig                     |    1 +
 29 files changed, 36 insertions(+), 137 deletions(-)
arch/arm/mach-omap2/Kconfig +1 -0
index 5034147..9a6d818 100644
@@ -25,6 +25,7 @@ config ARCH_OMAP2
 	depends on ARCH_OMAP2PLUS
 	default y
 	select CPU_V6
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP3
 	bool "TI OMAP3"
arch/arm/mach-omap2/board-2430sdp.c +1 -0
index d704f0a..d33821b 100644
@@ -301,6 +301,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_2430sdp_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-3430sdp.c +1 -0
index 77142c1..1c17bd8 100644
@@ -728,6 +728,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_3430sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-3630sdp.c +1 -0
index f552305..b27aa85 100644
@@ -215,6 +215,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_sdp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-4430sdp.c +2 -0
index 9db9ddb..1d21d3f 100644
@@ -28,6 +28,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -985,6 +986,7 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap_4430sdp_init,
 	.timer		= &omap4_timer,
 MACHINE_END
arch/arm/mach-omap2/board-am3517crane.c +1 -0
index 7834536..0166f4e 100644
@@ -98,6 +98,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_crane_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-am3517evm.c +1 -0
index d314f03..18cf2ce 100644
@@ -491,6 +491,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= am3517_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-apollon.c +1 -0
index de8134b..cf4f2c5 100644
@@ -354,6 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_apollon_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-cm-t35.c +2 -0
index bd1bcac..21a2436 100644
@@ -634,6 +634,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t35_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -644,6 +645,7 @@ MACHINE_START(CM_T3730, "Compulab CM-T3730")
 	.map_io         = omap3_map_io,
 	.init_early     = omap3630_init_early,
 	.init_irq       = omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine   = cm_t3730_init,
 	.timer          = &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-cm-t3517.c +1 -0
index 3f4dc66..1e2c52b 100644
@@ -299,6 +299,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
 	.map_io		= omap3_map_io,
 	.init_early	= am35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= cm_t3517_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-devkit8000.c +1 -0
index 4291894..31dda68 100644
@@ -661,6 +661,7 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= devkit8000_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-generic.c +1 -0
index 06941d1..67b821f 100644
@@ -112,6 +112,7 @@ DT_MACHINE_START(OMAP243X_DT, "Generic OMAP2430 (Flattened Device Tree)")
 	.map_io		= omap243x_map_io,
 	.init_early	= omap2430_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_generic_init,
 	.timer		= &omap2_timer,
 	.dt_compat	= omap243x_boards_compat,
arch/arm/mach-omap2/board-h4.c +1 -0
index c12666e..58a029f 100644
@@ -380,6 +380,7 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= omap_h4_init,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-igep0020.c +2 -0
index d0a3f78..b45d48d 100644
@@ -672,6 +672,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -682,6 +683,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= igep_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-ldp.c +1 -0
index e179da0..72b2d86 100644
@@ -434,6 +434,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_ldp_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-n8x0.c +3 -0
index e9d5f4a..fa04052 100644
@@ -689,6 +689,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END

@@ -699,6 +700,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END

@@ -709,6 +711,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
 	.map_io		= omap242x_map_io,
 	.init_early	= omap2420_init_early,
 	.init_irq	= omap2_init_irq,
+	.handle_irq	= omap2_intc_handle_irq,
 	.init_machine	= n8x0_init_machine,
 	.timer		= &omap2_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3beagle.c +1 -0
index 4a71cb7..b77fd3b 100644
@@ -559,6 +559,7 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_beagle_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3evm.c +1 -0
index ec00b2e..f86c1e8 100644
@@ -681,6 +681,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_evm_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3logic.c +2 -0
index 7c0f193..bd65196 100644
@@ -208,6 +208,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -217,6 +218,7 @@ MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3logic_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3pandora.c +1 -0
index f7811f4..caf607c 100644
@@ -606,6 +606,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3pandora_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3stalker.c +1 -0
index ddb7d66..4328ec8 100644
@@ -454,6 +454,7 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
 	.map_io			= omap3_map_io,
 	.init_early		= omap35xx_init_early,
 	.init_irq		= omap3_init_irq,
+	.handle_irq		= omap3_intc_handle_irq,
 	.init_machine		= omap3_stalker_init,
 	.timer			= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap3touchbook.c +1 -0
index a2d0d19..2b7bc4e 100644
@@ -381,6 +381,7 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap3_touchbook_init,
 	.timer		= &omap3_secure_timer,
 MACHINE_END
arch/arm/mach-omap2/board-omap4panda.c +2 -0
index 42a42da..828efcb 100644
@@ -31,6 +31,7 @@
 
 #include <mach/hardware.h>
 #include <mach/omap4-common.h>
+#include <asm/hardware/gic.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>

@@ -578,6 +579,7 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
 	.map_io		= omap4_map_io,
 	.init_early	= omap4430_init_early,
 	.init_irq	= gic_init_irq,
+	.handle_irq	= gic_handle_irq,
 	.init_machine	= omap4_panda_init,
 	.timer		= &omap4_timer,
 MACHINE_END
arch/arm/mach-omap2/board-overo.c +1 -0
index 4cf7aea..9865d8d 100644
@@ -562,6 +562,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
 	.map_io		= omap3_map_io,
 	.init_early	= omap35xx_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= overo_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-rm680.c +1 -0
index 616fb39..e0f5fd5 100644
@@ -149,6 +149,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rm680_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-rx51.c +1 -0
index 4af7c4b..5e52af5 100644
@@ -127,6 +127,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= rx51_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/board-zoom.c +2 -0
index be6684d..011b2e3 100644
@@ -135,6 +135,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3430_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END

@@ -145,6 +146,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
 	.map_io		= omap3_map_io,
 	.init_early	= omap3630_init_early,
 	.init_irq	= omap3_init_irq,
+	.handle_irq	= omap3_intc_handle_irq,
 	.init_machine	= omap_zoom_init,
 	.timer		= &omap3_timer,
 MACHINE_END
arch/arm/mach-omap2/include/mach/entry-macro.S +0 -137

146 lines not on this page · raw message

arch/arm/plat-omap/Kconfig +1 -0
index aa59f42..4a1cc58 100644
@@ -24,6 +24,7 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
+	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4
author
#29 lore raw

PATCH v3 17/17 ARM: GIC: Make MULTI_IRQ_HANDLER mandatory

In reply to Marc Zyngier

Now that MULTI_IRQ_HANDLER is selected by all the in-tree GIC users, make it mandatory and remove the unused macros.

Signed-off-by Marc Zyngier <[email protected]>
---
 arch/arm/Kconfig                                |    6 --
 arch/arm/common/Kconfig                         |    1 +
 arch/arm/common/gic.c                           |    4 --
 arch/arm/include/asm/hardware/entry-macro-gic.S |   60 -----------------------
 arch/arm/include/asm/hardware/gic.h             |    1 -
 arch/arm/mach-msm/Kconfig                       |    2 -
 arch/arm/mach-omap2/Kconfig                     |    1 +
 arch/arm/mach-tegra/Kconfig                     |    1 -
 arch/arm/mach-ux500/Kconfig                     |    1 -
 arch/arm/plat-omap/Kconfig                      |    1 -
 10 files changed, 2 insertions(+), 76 deletions(-)
 delete mode 100644 arch/arm/include/asm/hardware/entry-macro-gic.S
arch/arm/Kconfig +0 -6
index a3bcccc..c4f13c3 100644
@@ -278,7 +278,6 @@ config ARCH_REALVIEW
 	select ARM_TIMER_SP804
 	select GPIO_PL061 if GPIOLIB
 	select NEED_MACH_MEMORY_H
-	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for ARM Ltd RealView boards.
 

@@ -311,7 +310,6 @@ config ARCH_VEXPRESS
 	select ICST
 	select PLAT_VERSATILE
 	select PLAT_VERSATILE_CLCD
-	select MULTI_IRQ_HANDLER
 	help
 	  This enables support for the ARM Ltd Versatile Express boards.
 

@@ -347,7 +345,6 @@ config ARCH_HIGHBANK
 	select GENERIC_CLOCKEVENTS
 	select HAVE_ARM_SCU
 	select USE_OF
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for the Calxeda Highbank SoC based boards.
 

@@ -366,7 +363,6 @@ config ARCH_CNS3XXX
 	select ARM_GIC
 	select MIGHT_HAVE_PCI
 	select PCI_DOMAINS if PCI
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Cavium Networks CNS3XXX platform.
 

@@ -856,7 +852,6 @@ config ARCH_EXYNOS4
 	select HAVE_S3C2410_I2C if I2C
 	select HAVE_S3C2410_WATCHDOG if WATCHDOG
 	select NEED_MACH_MEMORY_H
-	select MULTI_IRQ_HANDLER
 	help
 	  Samsung EXYNOS4 series based systems
 

@@ -980,7 +975,6 @@ config ARCH_ZYNQ
 	select ARM_AMBA
 	select ICST
 	select USE_OF
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for Xilinx Zynq ARM Cortex A9 Platform
 endchoice
arch/arm/common/Kconfig +1 -0
index 74df9ca..8b8dfba 100644
@@ -1,5 +1,6 @@
 config ARM_GIC
 	select IRQ_DOMAIN
+	select MULTI_IRQ_HANDLER
 	bool
 
 config ARM_VIC
arch/arm/common/gic.c +0 -4
index 2d29d86..e3d1cf6 100644
@@ -63,9 +63,6 @@ struct gic_chip_data {
 
 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
 
-/* Address of GIC 0 CPU interface */
-void __iomem *gic_cpu_base_addr __read_mostly;
-
 /*
  * Supported arch specific GIC irq extension.
  * Default make them NULL.

@@ -647,7 +644,6 @@ void __init gic_init(unsigned int gic_nr, int irq_start,
 	 * For secondary GICs, skip over PPIs, too.
 	 */
 	if (gic_nr == 0) {
-		gic_cpu_base_addr = cpu_base;
 		domain->hwirq_base = 16;
 		if (irq_start > 0)
 			irq_start = (irq_start & ~31) + 16;
arch/arm/include/asm/hardware/entry-macro-gic.S deleted +0 -60

60 lines not on this page · raw message

arch/arm/include/asm/hardware/gic.h +0 -1
index a38eee2..b54a5b0 100644
@@ -36,7 +36,6 @@
 #include <linux/irqdomain.h>
 struct device_node;
 
-extern void __iomem *gic_cpu_base_addr;
 extern struct irq_chip gic_arch_extn;
 
 void gic_init(unsigned int, int, void __iomem *, void __iomem *);
arch/arm/mach-msm/Kconfig +0 -2
index ba36b74..ebde97f 100644
@@ -50,7 +50,6 @@ config ARCH_MSM8X60
 	select GPIO_MSM_V2
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 config ARCH_MSM8960
 	bool "MSM8960"

@@ -61,7 +60,6 @@ config ARCH_MSM8960
 	select MSM_V2_TLMM
 	select MSM_GPIOMUX
 	select MSM_SCM if SMP
-	select MULTI_IRQ_HANDLER
 
 endchoice
arch/arm/mach-omap2/Kconfig +1 -0
index 9a6d818..22f7c97 100644
@@ -37,6 +37,7 @@ config ARCH_OMAP3
 	select ARCH_HAS_OPP
 	select PM_OPP if PM
 	select ARM_CPU_SUSPEND if PM
+	select MULTI_IRQ_HANDLER
 
 config ARCH_OMAP4
 	bool "TI OMAP4"
arch/arm/mach-tegra/Kconfig +0 -1
index a6faa50..91aff7c 100644
@@ -13,7 +13,6 @@ config ARCH_TEGRA_2x_SOC
 	select USB_ARCH_HAS_EHCI if USB_SUPPORT
 	select USB_ULPI if USB_SUPPORT
 	select USB_ULPI_VIEWPORT if USB_SUPPORT
-	select MULTI_IRQ_HANDLER
 	help
 	  Support for NVIDIA Tegra AP20 and T20 processors, based on the
 	  ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
arch/arm/mach-ux500/Kconfig +0 -1
index bb2b52b..a3e0c86 100644
@@ -7,7 +7,6 @@ config UX500_SOC_COMMON
 	select HAS_MTU
 	select ARM_ERRATA_753970
 	select ARM_ERRATA_754322
-	select MULTI_IRQ_HANDLER
 
 menu "Ux500 SoC"
arch/arm/plat-omap/Kconfig +0 -1
index 4a1cc58..aa59f42 100644
@@ -24,7 +24,6 @@ config ARCH_OMAP2PLUS
 	select CLKDEV_LOOKUP
 	select GENERIC_IRQ_CHIP
 	select OMAP_DM_TIMER
-	select MULTI_IRQ_HANDLER
 	help
 	  "Systems based on OMAP2, OMAP3 or OMAP4"
Signature · 1 line
1.7.0.4